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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/dma-mapping.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28
29/**
30 * amdgpu_ih_ring_init - initialize the IH state
31 *
32 * @adev: amdgpu_device pointer
33 * @ih: ih ring to initialize
34 * @ring_size: ring size to allocate
35 * @use_bus_addr: true when we can use dma_alloc_coherent
36 *
37 * Initializes the IH state and allocates a buffer
38 * for the IH ring buffer.
39 * Returns 0 for success, errors for failure.
40 */
41int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
42 unsigned ring_size, bool use_bus_addr)
43{
44 u32 rb_bufsz;
45 int r;
46
47 /* Align ring size */
48 rb_bufsz = order_base_2(ring_size / 4);
49 ring_size = (1 << rb_bufsz) * 4;
50 ih->ring_size = ring_size;
51 ih->ptr_mask = ih->ring_size - 1;
52 ih->rptr = 0;
53 ih->use_bus_addr = use_bus_addr;
54
55 if (use_bus_addr) {
56 dma_addr_t dma_addr;
57
58 if (ih->ring)
59 return 0;
60
61 /* add 8 bytes for the rptr/wptr shadows and
62 * add them to the end of the ring allocation.
63 */
64 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
65 &dma_addr, GFP_KERNEL);
66 if (ih->ring == NULL)
67 return -ENOMEM;
68
69 ih->gpu_addr = dma_addr;
70 ih->wptr_addr = dma_addr + ih->ring_size;
71 ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
72 ih->rptr_addr = dma_addr + ih->ring_size + 4;
73 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
74 } else {
75 unsigned wptr_offs, rptr_offs;
76
77 r = amdgpu_device_wb_get(adev, &wptr_offs);
78 if (r)
79 return r;
80
81 r = amdgpu_device_wb_get(adev, &rptr_offs);
82 if (r) {
83 amdgpu_device_wb_free(adev, wptr_offs);
84 return r;
85 }
86
87 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
88 AMDGPU_GEM_DOMAIN_GTT,
89 &ih->ring_obj, &ih->gpu_addr,
90 (void **)&ih->ring);
91 if (r) {
92 amdgpu_device_wb_free(adev, rptr_offs);
93 amdgpu_device_wb_free(adev, wptr_offs);
94 return r;
95 }
96
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs];
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
100 ih->rptr_cpu = &adev->wb.wb[rptr_offs];
101 }
102 return 0;
103}
104
105/**
106 * amdgpu_ih_ring_fini - tear down the IH state
107 *
108 * @adev: amdgpu_device pointer
109 * @ih: ih ring to tear down
110 *
111 * Tears down the IH state and frees buffer
112 * used for the IH ring buffer.
113 */
114void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
115{
116 if (ih->use_bus_addr) {
117 if (!ih->ring)
118 return;
119
120 /* add 8 bytes for the rptr/wptr shadows and
121 * add them to the end of the ring allocation.
122 */
123 dma_free_coherent(adev->dev, ih->ring_size + 8,
124 (void *)ih->ring, ih->gpu_addr);
125 ih->ring = NULL;
126 } else {
127 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
128 (void **)&ih->ring);
129 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
130 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
131 }
132}
133
134/**
135 * amdgpu_ih_process - interrupt handler
136 *
137 * @adev: amdgpu_device pointer
138 * @ih: ih ring to process
139 *
140 * Interrupt hander (VI), walk the IH ring.
141 * Returns irq process return code.
142 */
143int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
144{
145 unsigned int count = AMDGPU_IH_MAX_NUM_IVS;
146 u32 wptr;
147
148 if (!ih->enabled || adev->shutdown)
149 return IRQ_NONE;
150
151 wptr = amdgpu_ih_get_wptr(adev, ih);
152
153restart_ih:
154 /* is somebody else already processing irqs? */
155 if (atomic_xchg(&ih->lock, 1))
156 return IRQ_NONE;
157
158 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
159
160 /* Order reading of wptr vs. reading of IH ring data */
161 rmb();
162
163 while (ih->rptr != wptr && --count) {
164 amdgpu_irq_dispatch(adev, ih);
165 ih->rptr &= ih->ptr_mask;
166 }
167
168 amdgpu_ih_set_rptr(adev, ih);
169 atomic_set(&ih->lock, 0);
170
171 /* make sure wptr hasn't changed while processing */
172 wptr = amdgpu_ih_get_wptr(adev, ih);
173 if (wptr != ih->rptr)
174 goto restart_ih;
175
176 return IRQ_HANDLED;
177}
178
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drmP.h>
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_amdkfd.h"
28
29/**
30 * amdgpu_ih_ring_alloc - allocate memory for the IH ring
31 *
32 * @adev: amdgpu_device pointer
33 *
34 * Allocate a ring buffer for the interrupt controller.
35 * Returns 0 for success, errors for failure.
36 */
37static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
38{
39 int r;
40
41 /* Allocate ring buffer */
42 if (adev->irq.ih.ring_obj == NULL) {
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
44 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
45 &adev->irq.ih.ring_obj,
46 &adev->irq.ih.gpu_addr,
47 (void **)&adev->irq.ih.ring);
48 if (r) {
49 DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
50 return r;
51 }
52 }
53 return 0;
54}
55
56/**
57 * amdgpu_ih_ring_init - initialize the IH state
58 *
59 * @adev: amdgpu_device pointer
60 *
61 * Initializes the IH state and allocates a buffer
62 * for the IH ring buffer.
63 * Returns 0 for success, errors for failure.
64 */
65int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
66 bool use_bus_addr)
67{
68 u32 rb_bufsz;
69 int r;
70
71 /* Align ring size */
72 rb_bufsz = order_base_2(ring_size / 4);
73 ring_size = (1 << rb_bufsz) * 4;
74 adev->irq.ih.ring_size = ring_size;
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
76 adev->irq.ih.rptr = 0;
77 adev->irq.ih.use_bus_addr = use_bus_addr;
78
79 if (adev->irq.ih.use_bus_addr) {
80 if (!adev->irq.ih.ring) {
81 /* add 8 bytes for the rptr/wptr shadows and
82 * add them to the end of the ring allocation.
83 */
84 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
85 adev->irq.ih.ring_size + 8,
86 &adev->irq.ih.rb_dma_addr);
87 if (adev->irq.ih.ring == NULL)
88 return -ENOMEM;
89 memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
90 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
91 adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
92 }
93 return 0;
94 } else {
95 r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
96 if (r) {
97 dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
98 return r;
99 }
100
101 r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
102 if (r) {
103 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
104 dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
105 return r;
106 }
107
108 return amdgpu_ih_ring_alloc(adev);
109 }
110}
111
112/**
113 * amdgpu_ih_ring_fini - tear down the IH state
114 *
115 * @adev: amdgpu_device pointer
116 *
117 * Tears down the IH state and frees buffer
118 * used for the IH ring buffer.
119 */
120void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
121{
122 if (adev->irq.ih.use_bus_addr) {
123 if (adev->irq.ih.ring) {
124 /* add 8 bytes for the rptr/wptr shadows and
125 * add them to the end of the ring allocation.
126 */
127 pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
128 (void *)adev->irq.ih.ring,
129 adev->irq.ih.rb_dma_addr);
130 adev->irq.ih.ring = NULL;
131 }
132 } else {
133 amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
134 &adev->irq.ih.gpu_addr,
135 (void **)&adev->irq.ih.ring);
136 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
137 amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
138 }
139}
140
141/**
142 * amdgpu_ih_process - interrupt handler
143 *
144 * @adev: amdgpu_device pointer
145 *
146 * Interrupt hander (VI), walk the IH ring.
147 * Returns irq process return code.
148 */
149int amdgpu_ih_process(struct amdgpu_device *adev)
150{
151 struct amdgpu_iv_entry entry;
152 u32 wptr;
153
154 if (!adev->irq.ih.enabled || adev->shutdown)
155 return IRQ_NONE;
156
157 wptr = amdgpu_ih_get_wptr(adev);
158
159restart_ih:
160 /* is somebody else already processing irqs? */
161 if (atomic_xchg(&adev->irq.ih.lock, 1))
162 return IRQ_NONE;
163
164 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
165
166 /* Order reading of wptr vs. reading of IH ring data */
167 rmb();
168
169 while (adev->irq.ih.rptr != wptr) {
170 u32 ring_index = adev->irq.ih.rptr >> 2;
171
172 /* Before dispatching irq to IP blocks, send it to amdkfd */
173 amdgpu_amdkfd_interrupt(adev,
174 (const void *) &adev->irq.ih.ring[ring_index]);
175
176 entry.iv_entry = (const uint32_t *)
177 &adev->irq.ih.ring[ring_index];
178 amdgpu_ih_decode_iv(adev, &entry);
179 adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
180
181 amdgpu_irq_dispatch(adev, &entry);
182 }
183 amdgpu_ih_set_rptr(adev);
184 atomic_set(&adev->irq.ih.lock, 0);
185
186 /* make sure wptr hasn't changed while processing */
187 wptr = amdgpu_ih_get_wptr(adev);
188 if (wptr != adev->irq.ih.rptr)
189 goto restart_ih;
190
191 return IRQ_HANDLED;
192}