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1/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/vga_switcheroo.h>
31
32#include <drm/amdgpu_drm.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_fourcc.h>
37
38#include "amdgpu.h"
39#include "cikd.h"
40#include "amdgpu_gem.h"
41
42#include "amdgpu_display.h"
43
44/* object hierarchy -
45 this contains a helper + a amdgpu fb
46 the helper contains a pointer to amdgpu framebuffer baseclass.
47*/
48
49static int
50amdgpufb_open(struct fb_info *info, int user)
51{
52 struct drm_fb_helper *fb_helper = info->par;
53 int ret = pm_runtime_get_sync(fb_helper->dev->dev);
54 if (ret < 0 && ret != -EACCES) {
55 pm_runtime_mark_last_busy(fb_helper->dev->dev);
56 pm_runtime_put_autosuspend(fb_helper->dev->dev);
57 return ret;
58 }
59 return 0;
60}
61
62static int
63amdgpufb_release(struct fb_info *info, int user)
64{
65 struct drm_fb_helper *fb_helper = info->par;
66
67 pm_runtime_mark_last_busy(fb_helper->dev->dev);
68 pm_runtime_put_autosuspend(fb_helper->dev->dev);
69 return 0;
70}
71
72static const struct fb_ops amdgpufb_ops = {
73 .owner = THIS_MODULE,
74 DRM_FB_HELPER_DEFAULT_OPS,
75 .fb_open = amdgpufb_open,
76 .fb_release = amdgpufb_release,
77 .fb_fillrect = drm_fb_helper_cfb_fillrect,
78 .fb_copyarea = drm_fb_helper_cfb_copyarea,
79 .fb_imageblit = drm_fb_helper_cfb_imageblit,
80};
81
82
83int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
84{
85 int aligned = width;
86 int pitch_mask = 0;
87
88 switch (cpp) {
89 case 1:
90 pitch_mask = 255;
91 break;
92 case 2:
93 pitch_mask = 127;
94 break;
95 case 3:
96 case 4:
97 pitch_mask = 63;
98 break;
99 }
100
101 aligned += pitch_mask;
102 aligned &= ~pitch_mask;
103 return aligned * cpp;
104}
105
106static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
107{
108 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
109 int ret;
110
111 ret = amdgpu_bo_reserve(abo, true);
112 if (likely(ret == 0)) {
113 amdgpu_bo_kunmap(abo);
114 amdgpu_bo_unpin(abo);
115 amdgpu_bo_unreserve(abo);
116 }
117 drm_gem_object_put(gobj);
118}
119
120static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
121 struct drm_mode_fb_cmd2 *mode_cmd,
122 struct drm_gem_object **gobj_p)
123{
124 const struct drm_format_info *info;
125 struct amdgpu_device *adev = rfbdev->adev;
126 struct drm_gem_object *gobj = NULL;
127 struct amdgpu_bo *abo = NULL;
128 bool fb_tiled = false; /* useful for testing */
129 u32 tiling_flags = 0, domain;
130 int ret;
131 int aligned_size, size;
132 int height = mode_cmd->height;
133 u32 cpp;
134 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
135 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
136 AMDGPU_GEM_CREATE_VRAM_CLEARED;
137
138 info = drm_get_format_info(adev->ddev, mode_cmd);
139 cpp = info->cpp[0];
140
141 /* need to align pitch with crtc limits */
142 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
143 fb_tiled);
144 domain = amdgpu_display_supported_domains(adev, flags);
145 height = ALIGN(mode_cmd->height, 8);
146 size = mode_cmd->pitches[0] * height;
147 aligned_size = ALIGN(size, PAGE_SIZE);
148 ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
149 ttm_bo_type_kernel, NULL, &gobj);
150 if (ret) {
151 pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
152 return -ENOMEM;
153 }
154 abo = gem_to_amdgpu_bo(gobj);
155
156 if (fb_tiled)
157 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
158
159 ret = amdgpu_bo_reserve(abo, false);
160 if (unlikely(ret != 0))
161 goto out_unref;
162
163 if (tiling_flags) {
164 ret = amdgpu_bo_set_tiling_flags(abo,
165 tiling_flags);
166 if (ret)
167 dev_err(adev->dev, "FB failed to set tiling flags\n");
168 }
169
170 ret = amdgpu_bo_pin(abo, domain);
171 if (ret) {
172 amdgpu_bo_unreserve(abo);
173 goto out_unref;
174 }
175
176 ret = amdgpu_ttm_alloc_gart(&abo->tbo);
177 if (ret) {
178 amdgpu_bo_unreserve(abo);
179 dev_err(adev->dev, "%p bind failed\n", abo);
180 goto out_unref;
181 }
182
183 ret = amdgpu_bo_kmap(abo, NULL);
184 amdgpu_bo_unreserve(abo);
185 if (ret) {
186 goto out_unref;
187 }
188
189 *gobj_p = gobj;
190 return 0;
191out_unref:
192 amdgpufb_destroy_pinned_object(gobj);
193 *gobj_p = NULL;
194 return ret;
195}
196
197static int amdgpufb_create(struct drm_fb_helper *helper,
198 struct drm_fb_helper_surface_size *sizes)
199{
200 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
201 struct amdgpu_device *adev = rfbdev->adev;
202 struct fb_info *info;
203 struct drm_framebuffer *fb = NULL;
204 struct drm_mode_fb_cmd2 mode_cmd;
205 struct drm_gem_object *gobj = NULL;
206 struct amdgpu_bo *abo = NULL;
207 int ret;
208 unsigned long tmp;
209
210 mode_cmd.width = sizes->surface_width;
211 mode_cmd.height = sizes->surface_height;
212
213 if (sizes->surface_bpp == 24)
214 sizes->surface_bpp = 32;
215
216 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
217 sizes->surface_depth);
218
219 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
220 if (ret) {
221 DRM_ERROR("failed to create fbcon object %d\n", ret);
222 return ret;
223 }
224
225 abo = gem_to_amdgpu_bo(gobj);
226
227 /* okay we have an object now allocate the framebuffer */
228 info = drm_fb_helper_alloc_fbi(helper);
229 if (IS_ERR(info)) {
230 ret = PTR_ERR(info);
231 goto out;
232 }
233
234 ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
235 &mode_cmd, gobj);
236 if (ret) {
237 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
238 goto out;
239 }
240
241 fb = &rfbdev->rfb.base;
242
243 /* setup helper */
244 rfbdev->helper.fb = fb;
245
246 info->fbops = &amdgpufb_ops;
247
248 tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
249 info->fix.smem_start = adev->gmc.aper_base + tmp;
250 info->fix.smem_len = amdgpu_bo_size(abo);
251 info->screen_base = amdgpu_bo_kptr(abo);
252 info->screen_size = amdgpu_bo_size(abo);
253
254 drm_fb_helper_fill_info(info, &rfbdev->helper, sizes);
255
256 /* setup aperture base/size for vesafb takeover */
257 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
258 info->apertures->ranges[0].size = adev->gmc.aper_size;
259
260 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
261
262 if (info->screen_base == NULL) {
263 ret = -ENOSPC;
264 goto out;
265 }
266
267 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
268 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
269 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
270 DRM_INFO("fb depth is %d\n", fb->format->depth);
271 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
272
273 vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
274 return 0;
275
276out:
277 if (abo) {
278
279 }
280 if (fb && ret) {
281 drm_gem_object_put(gobj);
282 drm_framebuffer_unregister_private(fb);
283 drm_framebuffer_cleanup(fb);
284 kfree(fb);
285 }
286 return ret;
287}
288
289static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
290{
291 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
292
293 drm_fb_helper_unregister_fbi(&rfbdev->helper);
294
295 if (rfb->base.obj[0]) {
296 amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
297 rfb->base.obj[0] = NULL;
298 drm_framebuffer_unregister_private(&rfb->base);
299 drm_framebuffer_cleanup(&rfb->base);
300 }
301 drm_fb_helper_fini(&rfbdev->helper);
302
303 return 0;
304}
305
306static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
307 .fb_probe = amdgpufb_create,
308};
309
310int amdgpu_fbdev_init(struct amdgpu_device *adev)
311{
312 struct amdgpu_fbdev *rfbdev;
313 int bpp_sel = 32;
314 int ret;
315
316 /* don't init fbdev on hw without DCE */
317 if (!adev->mode_info.mode_config_initialized)
318 return 0;
319
320 /* don't init fbdev if there are no connectors */
321 if (list_empty(&adev->ddev->mode_config.connector_list))
322 return 0;
323
324 /* select 8 bpp console on low vram cards */
325 if (adev->gmc.real_vram_size <= (32*1024*1024))
326 bpp_sel = 8;
327
328 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
329 if (!rfbdev)
330 return -ENOMEM;
331
332 rfbdev->adev = adev;
333 adev->mode_info.rfbdev = rfbdev;
334
335 drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
336 &amdgpu_fb_helper_funcs);
337
338 ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper);
339 if (ret) {
340 kfree(rfbdev);
341 return ret;
342 }
343
344 /* disable all the possible outputs/crtcs before entering KMS mode */
345 if (!amdgpu_device_has_dc_support(adev))
346 drm_helper_disable_unused_functions(adev->ddev);
347
348 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
349 return 0;
350}
351
352void amdgpu_fbdev_fini(struct amdgpu_device *adev)
353{
354 if (!adev->mode_info.rfbdev)
355 return;
356
357 amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
358 kfree(adev->mode_info.rfbdev);
359 adev->mode_info.rfbdev = NULL;
360}
361
362void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
363{
364 if (adev->mode_info.rfbdev)
365 drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
366 state);
367}
368
369int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
370{
371 struct amdgpu_bo *robj;
372 int size = 0;
373
374 if (!adev->mode_info.rfbdev)
375 return 0;
376
377 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
378 size += amdgpu_bo_size(robj);
379 return size;
380}
381
382bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
383{
384 if (!adev->mode_info.rfbdev)
385 return false;
386 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
387 return true;
388 return false;
389}
1/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26#include <linux/module.h>
27#include <linux/slab.h>
28#include <linux/pm_runtime.h>
29
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/amdgpu_drm.h>
34#include "amdgpu.h"
35#include "cikd.h"
36
37#include <drm/drm_fb_helper.h>
38
39#include <linux/vga_switcheroo.h>
40
41/* object hierarchy -
42 this contains a helper + a amdgpu fb
43 the helper contains a pointer to amdgpu framebuffer baseclass.
44*/
45struct amdgpu_fbdev {
46 struct drm_fb_helper helper;
47 struct amdgpu_framebuffer rfb;
48 struct amdgpu_device *adev;
49};
50
51static int
52amdgpufb_open(struct fb_info *info, int user)
53{
54 struct amdgpu_fbdev *rfbdev = info->par;
55 struct amdgpu_device *adev = rfbdev->adev;
56 int ret = pm_runtime_get_sync(adev->ddev->dev);
57 if (ret < 0 && ret != -EACCES) {
58 pm_runtime_mark_last_busy(adev->ddev->dev);
59 pm_runtime_put_autosuspend(adev->ddev->dev);
60 return ret;
61 }
62 return 0;
63}
64
65static int
66amdgpufb_release(struct fb_info *info, int user)
67{
68 struct amdgpu_fbdev *rfbdev = info->par;
69 struct amdgpu_device *adev = rfbdev->adev;
70
71 pm_runtime_mark_last_busy(adev->ddev->dev);
72 pm_runtime_put_autosuspend(adev->ddev->dev);
73 return 0;
74}
75
76static struct fb_ops amdgpufb_ops = {
77 .owner = THIS_MODULE,
78 DRM_FB_HELPER_DEFAULT_OPS,
79 .fb_open = amdgpufb_open,
80 .fb_release = amdgpufb_release,
81 .fb_fillrect = drm_fb_helper_cfb_fillrect,
82 .fb_copyarea = drm_fb_helper_cfb_copyarea,
83 .fb_imageblit = drm_fb_helper_cfb_imageblit,
84};
85
86
87int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
88{
89 int aligned = width;
90 int pitch_mask = 0;
91
92 switch (cpp) {
93 case 1:
94 pitch_mask = 255;
95 break;
96 case 2:
97 pitch_mask = 127;
98 break;
99 case 3:
100 case 4:
101 pitch_mask = 63;
102 break;
103 }
104
105 aligned += pitch_mask;
106 aligned &= ~pitch_mask;
107 return aligned * cpp;
108}
109
110static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
111{
112 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
113 int ret;
114
115 ret = amdgpu_bo_reserve(abo, false);
116 if (likely(ret == 0)) {
117 amdgpu_bo_kunmap(abo);
118 amdgpu_bo_unpin(abo);
119 amdgpu_bo_unreserve(abo);
120 }
121 drm_gem_object_unreference_unlocked(gobj);
122}
123
124static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
125 struct drm_mode_fb_cmd2 *mode_cmd,
126 struct drm_gem_object **gobj_p)
127{
128 struct amdgpu_device *adev = rfbdev->adev;
129 struct drm_gem_object *gobj = NULL;
130 struct amdgpu_bo *abo = NULL;
131 bool fb_tiled = false; /* useful for testing */
132 u32 tiling_flags = 0;
133 int ret;
134 int aligned_size, size;
135 int height = mode_cmd->height;
136 u32 cpp;
137
138 cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
139
140 /* need to align pitch with crtc limits */
141 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
142 fb_tiled);
143
144 height = ALIGN(mode_cmd->height, 8);
145 size = mode_cmd->pitches[0] * height;
146 aligned_size = ALIGN(size, PAGE_SIZE);
147 ret = amdgpu_gem_object_create(adev, aligned_size, 0,
148 AMDGPU_GEM_DOMAIN_VRAM,
149 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
150 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
151 true, &gobj);
152 if (ret) {
153 printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
154 aligned_size);
155 return -ENOMEM;
156 }
157 abo = gem_to_amdgpu_bo(gobj);
158
159 if (fb_tiled)
160 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
161
162 ret = amdgpu_bo_reserve(abo, false);
163 if (unlikely(ret != 0))
164 goto out_unref;
165
166 if (tiling_flags) {
167 ret = amdgpu_bo_set_tiling_flags(abo,
168 tiling_flags);
169 if (ret)
170 dev_err(adev->dev, "FB failed to set tiling flags\n");
171 }
172
173
174 ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
175 if (ret) {
176 amdgpu_bo_unreserve(abo);
177 goto out_unref;
178 }
179 ret = amdgpu_bo_kmap(abo, NULL);
180 amdgpu_bo_unreserve(abo);
181 if (ret) {
182 goto out_unref;
183 }
184
185 *gobj_p = gobj;
186 return 0;
187out_unref:
188 amdgpufb_destroy_pinned_object(gobj);
189 *gobj_p = NULL;
190 return ret;
191}
192
193static int amdgpufb_create(struct drm_fb_helper *helper,
194 struct drm_fb_helper_surface_size *sizes)
195{
196 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
197 struct amdgpu_device *adev = rfbdev->adev;
198 struct fb_info *info;
199 struct drm_framebuffer *fb = NULL;
200 struct drm_mode_fb_cmd2 mode_cmd;
201 struct drm_gem_object *gobj = NULL;
202 struct amdgpu_bo *abo = NULL;
203 int ret;
204 unsigned long tmp;
205
206 mode_cmd.width = sizes->surface_width;
207 mode_cmd.height = sizes->surface_height;
208
209 if (sizes->surface_bpp == 24)
210 sizes->surface_bpp = 32;
211
212 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
213 sizes->surface_depth);
214
215 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
216 if (ret) {
217 DRM_ERROR("failed to create fbcon object %d\n", ret);
218 return ret;
219 }
220
221 abo = gem_to_amdgpu_bo(gobj);
222
223 /* okay we have an object now allocate the framebuffer */
224 info = drm_fb_helper_alloc_fbi(helper);
225 if (IS_ERR(info)) {
226 ret = PTR_ERR(info);
227 goto out_unref;
228 }
229
230 info->par = rfbdev;
231 info->skip_vt_switch = true;
232
233 ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
234 if (ret) {
235 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
236 goto out_destroy_fbi;
237 }
238
239 fb = &rfbdev->rfb.base;
240
241 /* setup helper */
242 rfbdev->helper.fb = fb;
243
244 memset_io(abo->kptr, 0x0, amdgpu_bo_size(abo));
245
246 strcpy(info->fix.id, "amdgpudrmfb");
247
248 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
249
250 info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
251 info->fbops = &amdgpufb_ops;
252
253 tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
254 info->fix.smem_start = adev->mc.aper_base + tmp;
255 info->fix.smem_len = amdgpu_bo_size(abo);
256 info->screen_base = abo->kptr;
257 info->screen_size = amdgpu_bo_size(abo);
258
259 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
260
261 /* setup aperture base/size for vesafb takeover */
262 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
263 info->apertures->ranges[0].size = adev->mc.aper_size;
264
265 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
266
267 if (info->screen_base == NULL) {
268 ret = -ENOSPC;
269 goto out_destroy_fbi;
270 }
271
272 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
273 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
274 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
275 DRM_INFO("fb depth is %d\n", fb->depth);
276 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
277
278 vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
279 return 0;
280
281out_destroy_fbi:
282 drm_fb_helper_release_fbi(helper);
283out_unref:
284 if (abo) {
285
286 }
287 if (fb && ret) {
288 drm_gem_object_unreference_unlocked(gobj);
289 drm_framebuffer_unregister_private(fb);
290 drm_framebuffer_cleanup(fb);
291 kfree(fb);
292 }
293 return ret;
294}
295
296void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
297{
298 if (adev->mode_info.rfbdev)
299 drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
300}
301
302static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
303{
304 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
305
306 drm_fb_helper_unregister_fbi(&rfbdev->helper);
307 drm_fb_helper_release_fbi(&rfbdev->helper);
308
309 if (rfb->obj) {
310 amdgpufb_destroy_pinned_object(rfb->obj);
311 rfb->obj = NULL;
312 }
313 drm_fb_helper_fini(&rfbdev->helper);
314 drm_framebuffer_unregister_private(&rfb->base);
315 drm_framebuffer_cleanup(&rfb->base);
316
317 return 0;
318}
319
320/** Sets the color ramps on behalf of fbcon */
321static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
322 u16 blue, int regno)
323{
324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
325
326 amdgpu_crtc->lut_r[regno] = red >> 6;
327 amdgpu_crtc->lut_g[regno] = green >> 6;
328 amdgpu_crtc->lut_b[regno] = blue >> 6;
329}
330
331/** Gets the color ramps on behalf of fbcon */
332static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
333 u16 *blue, int regno)
334{
335 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
336
337 *red = amdgpu_crtc->lut_r[regno] << 6;
338 *green = amdgpu_crtc->lut_g[regno] << 6;
339 *blue = amdgpu_crtc->lut_b[regno] << 6;
340}
341
342static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
343 .gamma_set = amdgpu_crtc_fb_gamma_set,
344 .gamma_get = amdgpu_crtc_fb_gamma_get,
345 .fb_probe = amdgpufb_create,
346};
347
348int amdgpu_fbdev_init(struct amdgpu_device *adev)
349{
350 struct amdgpu_fbdev *rfbdev;
351 int bpp_sel = 32;
352 int ret;
353
354 /* don't init fbdev on hw without DCE */
355 if (!adev->mode_info.mode_config_initialized)
356 return 0;
357
358 /* don't init fbdev if there are no connectors */
359 if (list_empty(&adev->ddev->mode_config.connector_list))
360 return 0;
361
362 /* select 8 bpp console on low vram cards */
363 if (adev->mc.real_vram_size <= (32*1024*1024))
364 bpp_sel = 8;
365
366 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
367 if (!rfbdev)
368 return -ENOMEM;
369
370 rfbdev->adev = adev;
371 adev->mode_info.rfbdev = rfbdev;
372
373 drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
374 &amdgpu_fb_helper_funcs);
375
376 ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
377 adev->mode_info.num_crtc,
378 AMDGPUFB_CONN_LIMIT);
379 if (ret) {
380 kfree(rfbdev);
381 return ret;
382 }
383
384 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
385
386 /* disable all the possible outputs/crtcs before entering KMS mode */
387 drm_helper_disable_unused_functions(adev->ddev);
388
389 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
390 return 0;
391}
392
393void amdgpu_fbdev_fini(struct amdgpu_device *adev)
394{
395 if (!adev->mode_info.rfbdev)
396 return;
397
398 amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
399 kfree(adev->mode_info.rfbdev);
400 adev->mode_info.rfbdev = NULL;
401}
402
403void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
404{
405 if (adev->mode_info.rfbdev)
406 drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
407 state);
408}
409
410int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
411{
412 struct amdgpu_bo *robj;
413 int size = 0;
414
415 if (!adev->mode_info.rfbdev)
416 return 0;
417
418 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
419 size += amdgpu_bo_size(robj);
420 return size;
421}
422
423bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
424{
425 if (!adev->mode_info.rfbdev)
426 return false;
427 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
428 return true;
429 return false;
430}
431
432void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
433{
434 struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev;
435 struct drm_fb_helper *fb_helper;
436 int ret;
437
438 if (!afbdev)
439 return;
440
441 fb_helper = &afbdev->helper;
442
443 ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
444 if (ret)
445 DRM_DEBUG("failed to restore crtc mode\n");
446}