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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7enum qcom_scm_convention {
8 SMC_CONVENTION_UNKNOWN,
9 SMC_CONVENTION_LEGACY,
10 SMC_CONVENTION_ARM_32,
11 SMC_CONVENTION_ARM_64,
12};
13
14extern enum qcom_scm_convention qcom_scm_convention;
15
16#define MAX_QCOM_SCM_ARGS 10
17#define MAX_QCOM_SCM_RETS 3
18
19enum qcom_scm_arg_types {
20 QCOM_SCM_VAL,
21 QCOM_SCM_RO,
22 QCOM_SCM_RW,
23 QCOM_SCM_BUFVAL,
24};
25
26#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
27 (((a) & 0x3) << 4) | \
28 (((b) & 0x3) << 6) | \
29 (((c) & 0x3) << 8) | \
30 (((d) & 0x3) << 10) | \
31 (((e) & 0x3) << 12) | \
32 (((f) & 0x3) << 14) | \
33 (((g) & 0x3) << 16) | \
34 (((h) & 0x3) << 18) | \
35 (((i) & 0x3) << 20) | \
36 (((j) & 0x3) << 22) | \
37 ((num) & 0xf))
38
39#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
40
41
42/**
43 * struct qcom_scm_desc
44 * @arginfo: Metadata describing the arguments in args[]
45 * @args: The array of arguments for the secure syscall
46 */
47struct qcom_scm_desc {
48 u32 svc;
49 u32 cmd;
50 u32 arginfo;
51 u64 args[MAX_QCOM_SCM_ARGS];
52 u32 owner;
53};
54
55/**
56 * struct qcom_scm_res
57 * @result: The values returned by the secure syscall
58 */
59struct qcom_scm_res {
60 u64 result[MAX_QCOM_SCM_RETS];
61};
62
63#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
64extern int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
65 struct qcom_scm_res *res, bool atomic);
66
67#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
68extern int scm_legacy_call_atomic(struct device *dev,
69 const struct qcom_scm_desc *desc,
70 struct qcom_scm_res *res);
71extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
72 struct qcom_scm_res *res);
73
74#define QCOM_SCM_SVC_BOOT 0x01
75#define QCOM_SCM_BOOT_SET_ADDR 0x01
76#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
77#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
78#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
79#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
80
81#define QCOM_SCM_SVC_PIL 0x02
82#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
83#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
84#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
85#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
86#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
87#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
88
89#define QCOM_SCM_SVC_IO 0x05
90#define QCOM_SCM_IO_READ 0x01
91#define QCOM_SCM_IO_WRITE 0x02
92
93#define QCOM_SCM_SVC_INFO 0x06
94#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
95
96#define QCOM_SCM_SVC_MP 0x0c
97#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
98#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
99#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
100#define QCOM_SCM_MP_ASSIGN 0x16
101
102#define QCOM_SCM_SVC_OCMEM 0x0f
103#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
104#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
105
106#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
107#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
108#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
109
110#define QCOM_SCM_SVC_HDCP 0x11
111#define QCOM_SCM_HDCP_INVOKE 0x01
112
113#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
114#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
115#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
116
117extern void __qcom_scm_init(void);
118
119/* common error codes */
120#define QCOM_SCM_V2_EBUSY -12
121#define QCOM_SCM_ENOMEM -5
122#define QCOM_SCM_EOPNOTSUPP -4
123#define QCOM_SCM_EINVAL_ADDR -3
124#define QCOM_SCM_EINVAL_ARG -2
125#define QCOM_SCM_ERROR -1
126#define QCOM_SCM_INTERRUPTED 1
127
128static inline int qcom_scm_remap_error(int err)
129{
130 switch (err) {
131 case QCOM_SCM_ERROR:
132 return -EIO;
133 case QCOM_SCM_EINVAL_ADDR:
134 case QCOM_SCM_EINVAL_ARG:
135 return -EINVAL;
136 case QCOM_SCM_EOPNOTSUPP:
137 return -EOPNOTSUPP;
138 case QCOM_SCM_ENOMEM:
139 return -ENOMEM;
140 case QCOM_SCM_V2_EBUSY:
141 return -EBUSY;
142 }
143 return -EINVAL;
144}
145
146#endif
1/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __QCOM_SCM_INT_H
13#define __QCOM_SCM_INT_H
14
15#define QCOM_SCM_SVC_BOOT 0x1
16#define QCOM_SCM_BOOT_ADDR 0x1
17#define QCOM_SCM_BOOT_ADDR_MC 0x11
18
19#define QCOM_SCM_FLAG_HLOS 0x01
20#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
21#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
22extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
23 const cpumask_t *cpus);
24extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
25
26#define QCOM_SCM_CMD_TERMINATE_PC 0x2
27#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
28#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
29extern void __qcom_scm_cpu_power_down(u32 flags);
30
31#define QCOM_SCM_SVC_INFO 0x6
32#define QCOM_IS_CALL_AVAIL_CMD 0x1
33extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
34 u32 cmd_id);
35
36#define QCOM_SCM_SVC_HDCP 0x11
37#define QCOM_SCM_CMD_HDCP 0x01
38extern int __qcom_scm_hdcp_req(struct device *dev,
39 struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
40
41extern void __qcom_scm_init(void);
42
43#define QCOM_SCM_SVC_PIL 0x2
44#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
45#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
46#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
47#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
48#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
49#define QCOM_SCM_PAS_MSS_RESET 0xa
50extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
51extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
52 dma_addr_t metadata_phys);
53extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
54 phys_addr_t addr, phys_addr_t size);
55extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
56extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
57extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
58
59/* common error codes */
60#define QCOM_SCM_V2_EBUSY -12
61#define QCOM_SCM_ENOMEM -5
62#define QCOM_SCM_EOPNOTSUPP -4
63#define QCOM_SCM_EINVAL_ADDR -3
64#define QCOM_SCM_EINVAL_ARG -2
65#define QCOM_SCM_ERROR -1
66#define QCOM_SCM_INTERRUPTED 1
67
68static inline int qcom_scm_remap_error(int err)
69{
70 switch (err) {
71 case QCOM_SCM_ERROR:
72 return -EIO;
73 case QCOM_SCM_EINVAL_ADDR:
74 case QCOM_SCM_EINVAL_ARG:
75 return -EINVAL;
76 case QCOM_SCM_EOPNOTSUPP:
77 return -EOPNOTSUPP;
78 case QCOM_SCM_ENOMEM:
79 return -ENOMEM;
80 case QCOM_SCM_V2_EBUSY:
81 return -EBUSY;
82 }
83 return -EINVAL;
84}
85
86#endif