1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Platform data for the chipidea USB dual role controller
  4 */
  5
  6#ifndef __LINUX_USB_CHIPIDEA_H
  7#define __LINUX_USB_CHIPIDEA_H
  8
  9#include <linux/extcon.h>
 10#include <linux/usb/otg.h>
 11
 12struct ci_hdrc;
 13
 14/**
 15 * struct ci_hdrc_cable - structure for external connector cable state tracking
 16 * @connected: true if cable is connected, false otherwise
 17 * @changed: set to true when extcon event happen
 18 * @enabled: set to true if we've enabled the vbus or id interrupt
 19 * @edev: device which generate events
 20 * @ci: driver state of the chipidea device
 21 * @nb: hold event notification callback
 22 * @conn: used for notification registration
 23 */
 24struct ci_hdrc_cable {
 25	bool				connected;
 26	bool				changed;
 27	bool				enabled;
 28	struct extcon_dev		*edev;
 29	struct ci_hdrc			*ci;
 30	struct notifier_block		nb;
 31};
 32
 33struct ci_hdrc_platform_data {
 34	const char	*name;
 35	/* offset of the capability registers */
 36	uintptr_t	 capoffset;
 37	unsigned	 power_budget;
 38	struct phy	*phy;
 39	/* old usb_phy interface */
 40	struct usb_phy	*usb_phy;
 41	enum usb_phy_interface phy_mode;
 42	unsigned long	 flags;
 43#define CI_HDRC_REGS_SHARED		BIT(0)
 44#define CI_HDRC_DISABLE_DEVICE_STREAMING	BIT(1)
 45#define CI_HDRC_SUPPORTS_RUNTIME_PM	BIT(2)
 46#define CI_HDRC_DISABLE_HOST_STREAMING	BIT(3)
 47#define CI_HDRC_DISABLE_STREAMING (CI_HDRC_DISABLE_DEVICE_STREAMING |	\
 48		CI_HDRC_DISABLE_HOST_STREAMING)
 49	/*
 50	 * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
 51	 * but otg is not supported (no register otgsc).
 52	 */
 53#define CI_HDRC_DUAL_ROLE_NOT_OTG	BIT(4)
 54#define CI_HDRC_IMX28_WRITE_FIX		BIT(5)
 55#define CI_HDRC_FORCE_FULLSPEED		BIT(6)
 56#define CI_HDRC_TURN_VBUS_EARLY_ON	BIT(7)
 57#define CI_HDRC_SET_NON_ZERO_TTHA	BIT(8)
 58#define CI_HDRC_OVERRIDE_AHB_BURST	BIT(9)
 59#define CI_HDRC_OVERRIDE_TX_BURST	BIT(10)
 60#define CI_HDRC_OVERRIDE_RX_BURST	BIT(11)
 61#define CI_HDRC_OVERRIDE_PHY_CONTROL	BIT(12) /* Glue layer manages phy */
 62#define CI_HDRC_REQUIRES_ALIGNED_DMA	BIT(13)
 63#define CI_HDRC_IMX_IS_HSIC		BIT(14)
 64#define CI_HDRC_PMQOS			BIT(15)
 65	enum usb_dr_mode	dr_mode;
 66#define CI_HDRC_CONTROLLER_RESET_EVENT		0
 67#define CI_HDRC_CONTROLLER_STOPPED_EVENT	1
 68#define CI_HDRC_IMX_HSIC_ACTIVE_EVENT		2
 69#define CI_HDRC_IMX_HSIC_SUSPEND_EVENT		3
 70#define CI_HDRC_CONTROLLER_VBUS_EVENT		4
 71	int	(*notify_event) (struct ci_hdrc *ci, unsigned event);
 72	struct regulator	*reg_vbus;
 73	struct usb_otg_caps	ci_otg_caps;
 74	bool			tpl_support;
 75	/* interrupt threshold setting */
 76	u32			itc_setting;
 77	u32			ahb_burst_config;
 78	u32			tx_burst_size;
 79	u32			rx_burst_size;
 80
 81	/* VBUS and ID signal state tracking, using extcon framework */
 82	struct ci_hdrc_cable		vbus_extcon;
 83	struct ci_hdrc_cable		id_extcon;
 84	u32			phy_clkgate_delay_us;
 85
 86	/* pins */
 87	struct pinctrl *pctl;
 88	struct pinctrl_state *pins_default;
 89	struct pinctrl_state *pins_host;
 90	struct pinctrl_state *pins_device;
 91};
 92
 93/* Default offset of capability registers */
 94#define DEF_CAPOFFSET		0x100
 95
 96/* Add ci hdrc device */
 97struct platform_device *ci_hdrc_add_device(struct device *dev,
 98			struct resource *res, int nres,
 99			struct ci_hdrc_platform_data *platdata);
100/* Remove ci hdrc device */
101void ci_hdrc_remove_device(struct platform_device *pdev);
102/* Get current available role */
103enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev);
104
105#endif

 
 1/*
 2 * Platform data for the chipidea USB dual role controller
 3 */
 4
 5#ifndef __LINUX_USB_CHIPIDEA_H
 6#define __LINUX_USB_CHIPIDEA_H
 7
 8struct ci13xxx;
 9struct ci13xxx_udc_driver {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
10	const char	*name;
11	/* offset of the capability registers */
12	uintptr_t	 capoffset;
13	unsigned	 power_budget;
 
 
 
 
14	unsigned long	 flags;
15#define CI13XXX_REGS_SHARED		BIT(0)
16#define CI13XXX_REQUIRE_TRANSCEIVER	BIT(1)
17#define CI13XXX_PULLUP_ON_VBUS		BIT(2)
18#define CI13XXX_DISABLE_STREAMING	BIT(3)
19
20#define CI13XXX_CONTROLLER_RESET_EVENT		0
21#define CI13XXX_CONTROLLER_STOPPED_EVENT	1
22	void	(*notify_event) (struct ci13xxx *udc, unsigned event);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
23};
24
25/* Default offset of capability registers */
26#define DEF_CAPOFFSET		0x100
 
 
 
 
 
 
 
 
 
27
28#endif