Loading...
1// SPDX-License-Identifier: GPL-2.0+
2//
3// wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC
4//
5// Copyright 2007, 2008 Wolfson Microelectronics PLC.
6//
7// Author: Liam Girdwood
8// linux@wolfsonmicro.com
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/bitops.h>
14#include <linux/err.h>
15#include <linux/i2c.h>
16#include <linux/mfd/wm8350/core.h>
17#include <linux/mfd/wm8350/pmic.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/driver.h>
20#include <linux/regulator/machine.h>
21
22/* Maximum value possible for VSEL */
23#define WM8350_DCDC_MAX_VSEL 0x66
24
25/* Microamps */
26static const unsigned int isink_cur[] = {
27 4,
28 5,
29 6,
30 7,
31 8,
32 10,
33 11,
34 14,
35 16,
36 19,
37 23,
38 27,
39 32,
40 39,
41 46,
42 54,
43 65,
44 77,
45 92,
46 109,
47 130,
48 154,
49 183,
50 218,
51 259,
52 308,
53 367,
54 436,
55 518,
56 616,
57 733,
58 872,
59 1037,
60 1233,
61 1466,
62 1744,
63 2073,
64 2466,
65 2933,
66 3487,
67 4147,
68 4932,
69 5865,
70 6975,
71 8294,
72 9864,
73 11730,
74 13949,
75 16589,
76 19728,
77 23460,
78 27899,
79 33178,
80 39455,
81 46920,
82 55798,
83 66355,
84 78910,
85 93840,
86 111596,
87 132710,
88 157820,
89 187681,
90 223191
91};
92
93/* turn on ISINK followed by DCDC */
94static int wm8350_isink_enable(struct regulator_dev *rdev)
95{
96 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
97 int isink = rdev_get_id(rdev);
98
99 switch (isink) {
100 case WM8350_ISINK_A:
101 switch (wm8350->pmic.isink_A_dcdc) {
102 case WM8350_DCDC_2:
103 case WM8350_DCDC_5:
104 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
105 WM8350_CS1_ENA);
106 wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
107 WM8350_CS1_DRIVE);
108 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
109 1 << (wm8350->pmic.isink_A_dcdc -
110 WM8350_DCDC_1));
111 break;
112 default:
113 return -EINVAL;
114 }
115 break;
116 case WM8350_ISINK_B:
117 switch (wm8350->pmic.isink_B_dcdc) {
118 case WM8350_DCDC_2:
119 case WM8350_DCDC_5:
120 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
121 WM8350_CS2_ENA);
122 wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
123 WM8350_CS2_DRIVE);
124 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
125 1 << (wm8350->pmic.isink_B_dcdc -
126 WM8350_DCDC_1));
127 break;
128 default:
129 return -EINVAL;
130 }
131 break;
132 default:
133 return -EINVAL;
134 }
135 return 0;
136}
137
138static int wm8350_isink_disable(struct regulator_dev *rdev)
139{
140 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
141 int isink = rdev_get_id(rdev);
142
143 switch (isink) {
144 case WM8350_ISINK_A:
145 switch (wm8350->pmic.isink_A_dcdc) {
146 case WM8350_DCDC_2:
147 case WM8350_DCDC_5:
148 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
149 1 << (wm8350->pmic.isink_A_dcdc -
150 WM8350_DCDC_1));
151 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
152 WM8350_CS1_ENA);
153 break;
154 default:
155 return -EINVAL;
156 }
157 break;
158 case WM8350_ISINK_B:
159 switch (wm8350->pmic.isink_B_dcdc) {
160 case WM8350_DCDC_2:
161 case WM8350_DCDC_5:
162 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
163 1 << (wm8350->pmic.isink_B_dcdc -
164 WM8350_DCDC_1));
165 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
166 WM8350_CS2_ENA);
167 break;
168 default:
169 return -EINVAL;
170 }
171 break;
172 default:
173 return -EINVAL;
174 }
175 return 0;
176}
177
178static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
179{
180 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
181 int isink = rdev_get_id(rdev);
182
183 switch (isink) {
184 case WM8350_ISINK_A:
185 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
186 0x8000;
187 case WM8350_ISINK_B:
188 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
189 0x8000;
190 }
191 return -EINVAL;
192}
193
194static int wm8350_isink_enable_time(struct regulator_dev *rdev)
195{
196 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
197 int isink = rdev_get_id(rdev);
198 int reg;
199
200 switch (isink) {
201 case WM8350_ISINK_A:
202 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
203 break;
204 case WM8350_ISINK_B:
205 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 if (reg & WM8350_CS1_FLASH_MODE) {
212 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
213 case 0:
214 return 0;
215 case 1:
216 return 1950;
217 case 2:
218 return 3910;
219 case 3:
220 return 7800;
221 }
222 } else {
223 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
224 case 0:
225 return 0;
226 case 1:
227 return 250000;
228 case 2:
229 return 500000;
230 case 3:
231 return 1000000;
232 }
233 }
234
235 return -EINVAL;
236}
237
238
239int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
240 u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
241 u16 drive)
242{
243 switch (isink) {
244 case WM8350_ISINK_A:
245 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
246 (mode ? WM8350_CS1_FLASH_MODE : 0) |
247 (trigger ? WM8350_CS1_TRIGSRC : 0) |
248 duration | on_ramp | off_ramp | drive);
249 break;
250 case WM8350_ISINK_B:
251 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
252 (mode ? WM8350_CS2_FLASH_MODE : 0) |
253 (trigger ? WM8350_CS2_TRIGSRC : 0) |
254 duration | on_ramp | off_ramp | drive);
255 break;
256 default:
257 return -EINVAL;
258 }
259 return 0;
260}
261EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
262
263static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
264{
265 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
266 int sel, volt_reg, dcdc = rdev_get_id(rdev);
267 u16 val;
268
269 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
270
271 switch (dcdc) {
272 case WM8350_DCDC_1:
273 volt_reg = WM8350_DCDC1_LOW_POWER;
274 break;
275 case WM8350_DCDC_3:
276 volt_reg = WM8350_DCDC3_LOW_POWER;
277 break;
278 case WM8350_DCDC_4:
279 volt_reg = WM8350_DCDC4_LOW_POWER;
280 break;
281 case WM8350_DCDC_6:
282 volt_reg = WM8350_DCDC6_LOW_POWER;
283 break;
284 case WM8350_DCDC_2:
285 case WM8350_DCDC_5:
286 default:
287 return -EINVAL;
288 }
289
290 sel = regulator_map_voltage_linear(rdev, uV, uV);
291 if (sel < 0)
292 return sel;
293
294 /* all DCDCs have same mV bits */
295 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
296 wm8350_reg_write(wm8350, volt_reg, val | sel);
297 return 0;
298}
299
300static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
301{
302 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
303 int dcdc = rdev_get_id(rdev);
304 u16 val;
305
306 switch (dcdc) {
307 case WM8350_DCDC_1:
308 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
309 & ~WM8350_DCDC_HIB_MODE_MASK;
310 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
311 val | wm8350->pmic.dcdc1_hib_mode);
312 break;
313 case WM8350_DCDC_3:
314 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
315 & ~WM8350_DCDC_HIB_MODE_MASK;
316 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
317 val | wm8350->pmic.dcdc3_hib_mode);
318 break;
319 case WM8350_DCDC_4:
320 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
321 & ~WM8350_DCDC_HIB_MODE_MASK;
322 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
323 val | wm8350->pmic.dcdc4_hib_mode);
324 break;
325 case WM8350_DCDC_6:
326 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
327 & ~WM8350_DCDC_HIB_MODE_MASK;
328 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
329 val | wm8350->pmic.dcdc6_hib_mode);
330 break;
331 case WM8350_DCDC_2:
332 case WM8350_DCDC_5:
333 default:
334 return -EINVAL;
335 }
336
337 return 0;
338}
339
340static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
341{
342 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
343 int dcdc = rdev_get_id(rdev);
344 u16 val;
345
346 switch (dcdc) {
347 case WM8350_DCDC_1:
348 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
349 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
350 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
351 val | WM8350_DCDC_HIB_MODE_DIS);
352 break;
353 case WM8350_DCDC_3:
354 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
355 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
356 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
357 val | WM8350_DCDC_HIB_MODE_DIS);
358 break;
359 case WM8350_DCDC_4:
360 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
361 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
362 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
363 val | WM8350_DCDC_HIB_MODE_DIS);
364 break;
365 case WM8350_DCDC_6:
366 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
367 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
368 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
369 val | WM8350_DCDC_HIB_MODE_DIS);
370 break;
371 case WM8350_DCDC_2:
372 case WM8350_DCDC_5:
373 default:
374 return -EINVAL;
375 }
376
377 return 0;
378}
379
380static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
381{
382 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
383 int dcdc = rdev_get_id(rdev);
384 u16 val;
385
386 switch (dcdc) {
387 case WM8350_DCDC_2:
388 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
389 & ~WM8350_DC2_HIB_MODE_MASK;
390 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
391 (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
392 break;
393 case WM8350_DCDC_5:
394 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
395 & ~WM8350_DC5_HIB_MODE_MASK;
396 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
397 (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
398 break;
399 default:
400 return -EINVAL;
401 }
402 return 0;
403}
404
405static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
406{
407 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
408 int dcdc = rdev_get_id(rdev);
409 u16 val;
410
411 switch (dcdc) {
412 case WM8350_DCDC_2:
413 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
414 & ~WM8350_DC2_HIB_MODE_MASK;
415 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
416 (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
417 break;
418 case WM8350_DCDC_5:
419 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
420 & ~WM8350_DC5_HIB_MODE_MASK;
421 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
422 (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
423 break;
424 default:
425 return -EINVAL;
426 }
427 return 0;
428}
429
430static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
431 unsigned int mode)
432{
433 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
434 int dcdc = rdev_get_id(rdev);
435 u16 *hib_mode;
436
437 switch (dcdc) {
438 case WM8350_DCDC_1:
439 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
440 break;
441 case WM8350_DCDC_3:
442 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
443 break;
444 case WM8350_DCDC_4:
445 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
446 break;
447 case WM8350_DCDC_6:
448 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
449 break;
450 case WM8350_DCDC_2:
451 case WM8350_DCDC_5:
452 default:
453 return -EINVAL;
454 }
455
456 switch (mode) {
457 case REGULATOR_MODE_NORMAL:
458 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
459 break;
460 case REGULATOR_MODE_IDLE:
461 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
462 break;
463 case REGULATOR_MODE_STANDBY:
464 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 return 0;
471}
472
473static const struct linear_range wm8350_ldo_ranges[] = {
474 REGULATOR_LINEAR_RANGE(900000, 0, 15, 50000),
475 REGULATOR_LINEAR_RANGE(1800000, 16, 31, 100000),
476};
477
478static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
479{
480 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
481 int sel, volt_reg, ldo = rdev_get_id(rdev);
482 u16 val;
483
484 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, uV / 1000);
485
486 switch (ldo) {
487 case WM8350_LDO_1:
488 volt_reg = WM8350_LDO1_LOW_POWER;
489 break;
490 case WM8350_LDO_2:
491 volt_reg = WM8350_LDO2_LOW_POWER;
492 break;
493 case WM8350_LDO_3:
494 volt_reg = WM8350_LDO3_LOW_POWER;
495 break;
496 case WM8350_LDO_4:
497 volt_reg = WM8350_LDO4_LOW_POWER;
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 sel = regulator_map_voltage_linear_range(rdev, uV, uV);
504 if (sel < 0)
505 return sel;
506
507 /* all LDOs have same mV bits */
508 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
509 wm8350_reg_write(wm8350, volt_reg, val | sel);
510 return 0;
511}
512
513static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
514{
515 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
516 int volt_reg, ldo = rdev_get_id(rdev);
517 u16 val;
518
519 switch (ldo) {
520 case WM8350_LDO_1:
521 volt_reg = WM8350_LDO1_LOW_POWER;
522 break;
523 case WM8350_LDO_2:
524 volt_reg = WM8350_LDO2_LOW_POWER;
525 break;
526 case WM8350_LDO_3:
527 volt_reg = WM8350_LDO3_LOW_POWER;
528 break;
529 case WM8350_LDO_4:
530 volt_reg = WM8350_LDO4_LOW_POWER;
531 break;
532 default:
533 return -EINVAL;
534 }
535
536 /* all LDOs have same mV bits */
537 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
538 wm8350_reg_write(wm8350, volt_reg, val);
539 return 0;
540}
541
542static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
543{
544 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
545 int volt_reg, ldo = rdev_get_id(rdev);
546 u16 val;
547
548 switch (ldo) {
549 case WM8350_LDO_1:
550 volt_reg = WM8350_LDO1_LOW_POWER;
551 break;
552 case WM8350_LDO_2:
553 volt_reg = WM8350_LDO2_LOW_POWER;
554 break;
555 case WM8350_LDO_3:
556 volt_reg = WM8350_LDO3_LOW_POWER;
557 break;
558 case WM8350_LDO_4:
559 volt_reg = WM8350_LDO4_LOW_POWER;
560 break;
561 default:
562 return -EINVAL;
563 }
564
565 /* all LDOs have same mV bits */
566 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
567 wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
568 return 0;
569}
570
571int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
572 u16 stop, u16 fault)
573{
574 int slot_reg;
575 u16 val;
576
577 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
578 __func__, dcdc, start, stop);
579
580 /* slot valid ? */
581 if (start > 15 || stop > 15)
582 return -EINVAL;
583
584 switch (dcdc) {
585 case WM8350_DCDC_1:
586 slot_reg = WM8350_DCDC1_TIMEOUTS;
587 break;
588 case WM8350_DCDC_2:
589 slot_reg = WM8350_DCDC2_TIMEOUTS;
590 break;
591 case WM8350_DCDC_3:
592 slot_reg = WM8350_DCDC3_TIMEOUTS;
593 break;
594 case WM8350_DCDC_4:
595 slot_reg = WM8350_DCDC4_TIMEOUTS;
596 break;
597 case WM8350_DCDC_5:
598 slot_reg = WM8350_DCDC5_TIMEOUTS;
599 break;
600 case WM8350_DCDC_6:
601 slot_reg = WM8350_DCDC6_TIMEOUTS;
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 val = wm8350_reg_read(wm8350, slot_reg) &
608 ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
609 WM8350_DC1_ERRACT_MASK);
610 wm8350_reg_write(wm8350, slot_reg,
611 val | (start << WM8350_DC1_ENSLOT_SHIFT) |
612 (stop << WM8350_DC1_SDSLOT_SHIFT) |
613 (fault << WM8350_DC1_ERRACT_SHIFT));
614
615 return 0;
616}
617EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
618
619int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
620{
621 int slot_reg;
622 u16 val;
623
624 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
625 __func__, ldo, start, stop);
626
627 /* slot valid ? */
628 if (start > 15 || stop > 15)
629 return -EINVAL;
630
631 switch (ldo) {
632 case WM8350_LDO_1:
633 slot_reg = WM8350_LDO1_TIMEOUTS;
634 break;
635 case WM8350_LDO_2:
636 slot_reg = WM8350_LDO2_TIMEOUTS;
637 break;
638 case WM8350_LDO_3:
639 slot_reg = WM8350_LDO3_TIMEOUTS;
640 break;
641 case WM8350_LDO_4:
642 slot_reg = WM8350_LDO4_TIMEOUTS;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
649 wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
650 return 0;
651}
652EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
653
654int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
655 u16 ilim, u16 ramp, u16 feedback)
656{
657 u16 val;
658
659 dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
660 mode ? "normal" : "boost", ilim ? "low" : "normal");
661
662 switch (dcdc) {
663 case WM8350_DCDC_2:
664 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
665 & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
666 WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
667 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
668 (mode << WM8350_DC2_MODE_SHIFT) |
669 (ilim << WM8350_DC2_ILIM_SHIFT) |
670 (ramp << WM8350_DC2_RMP_SHIFT) |
671 (feedback << WM8350_DC2_FBSRC_SHIFT));
672 break;
673 case WM8350_DCDC_5:
674 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
675 & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
676 WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
677 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
678 (mode << WM8350_DC5_MODE_SHIFT) |
679 (ilim << WM8350_DC5_ILIM_SHIFT) |
680 (ramp << WM8350_DC5_RMP_SHIFT) |
681 (feedback << WM8350_DC5_FBSRC_SHIFT));
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 return 0;
688}
689EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
690
691static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
692{
693 int reg = 0, ret;
694
695 switch (dcdc) {
696 case WM8350_DCDC_1:
697 reg = WM8350_DCDC1_FORCE_PWM;
698 break;
699 case WM8350_DCDC_3:
700 reg = WM8350_DCDC3_FORCE_PWM;
701 break;
702 case WM8350_DCDC_4:
703 reg = WM8350_DCDC4_FORCE_PWM;
704 break;
705 case WM8350_DCDC_6:
706 reg = WM8350_DCDC6_FORCE_PWM;
707 break;
708 default:
709 return -EINVAL;
710 }
711
712 if (enable)
713 ret = wm8350_set_bits(wm8350, reg,
714 WM8350_DCDC1_FORCE_PWM_ENA);
715 else
716 ret = wm8350_clear_bits(wm8350, reg,
717 WM8350_DCDC1_FORCE_PWM_ENA);
718 return ret;
719}
720
721static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
722{
723 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
724 int dcdc = rdev_get_id(rdev);
725 u16 val;
726
727 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
728 return -EINVAL;
729
730 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
731 return -EINVAL;
732
733 val = 1 << (dcdc - WM8350_DCDC_1);
734
735 switch (mode) {
736 case REGULATOR_MODE_FAST:
737 /* force continuous mode */
738 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
739 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
740 force_continuous_enable(wm8350, dcdc, 1);
741 break;
742 case REGULATOR_MODE_NORMAL:
743 /* active / pulse skipping */
744 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
745 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
746 force_continuous_enable(wm8350, dcdc, 0);
747 break;
748 case REGULATOR_MODE_IDLE:
749 /* standby mode */
750 force_continuous_enable(wm8350, dcdc, 0);
751 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
752 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
753 break;
754 case REGULATOR_MODE_STANDBY:
755 /* LDO mode */
756 force_continuous_enable(wm8350, dcdc, 0);
757 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
758 break;
759 }
760
761 return 0;
762}
763
764static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
765{
766 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
767 int dcdc = rdev_get_id(rdev);
768 u16 mask, sleep, active, force;
769 int mode = REGULATOR_MODE_NORMAL;
770 int reg;
771
772 switch (dcdc) {
773 case WM8350_DCDC_1:
774 reg = WM8350_DCDC1_FORCE_PWM;
775 break;
776 case WM8350_DCDC_3:
777 reg = WM8350_DCDC3_FORCE_PWM;
778 break;
779 case WM8350_DCDC_4:
780 reg = WM8350_DCDC4_FORCE_PWM;
781 break;
782 case WM8350_DCDC_6:
783 reg = WM8350_DCDC6_FORCE_PWM;
784 break;
785 default:
786 return -EINVAL;
787 }
788
789 mask = 1 << (dcdc - WM8350_DCDC_1);
790 active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
791 force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
792 sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
793
794 dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
795 mask, active, sleep, force);
796
797 if (active && !sleep) {
798 if (force)
799 mode = REGULATOR_MODE_FAST;
800 else
801 mode = REGULATOR_MODE_NORMAL;
802 } else if (!active && !sleep)
803 mode = REGULATOR_MODE_IDLE;
804 else if (sleep)
805 mode = REGULATOR_MODE_STANDBY;
806
807 return mode;
808}
809
810static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
811{
812 return REGULATOR_MODE_NORMAL;
813}
814
815struct wm8350_dcdc_efficiency {
816 int uA_load_min;
817 int uA_load_max;
818 unsigned int mode;
819};
820
821static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
822 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
823 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
824 {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
825 {-1, -1, REGULATOR_MODE_NORMAL},
826};
827
828static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
829 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
830 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
831 {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
832 {-1, -1, REGULATOR_MODE_NORMAL},
833};
834
835static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
836{
837 int i = 0;
838
839 while (eff[i].uA_load_min != -1) {
840 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
841 return eff[i].mode;
842 i++;
843 }
844 return REGULATOR_MODE_NORMAL;
845}
846
847/* Query the regulator for it's most efficient mode @ uV,uA
848 * WM8350 regulator efficiency is pretty similar over
849 * different input and output uV.
850 */
851static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
852 int input_uV, int output_uV,
853 int output_uA)
854{
855 int dcdc = rdev_get_id(rdev), mode;
856
857 switch (dcdc) {
858 case WM8350_DCDC_1:
859 case WM8350_DCDC_6:
860 mode = get_mode(output_uA, dcdc1_6_efficiency);
861 break;
862 case WM8350_DCDC_3:
863 case WM8350_DCDC_4:
864 mode = get_mode(output_uA, dcdc3_4_efficiency);
865 break;
866 default:
867 mode = REGULATOR_MODE_NORMAL;
868 break;
869 }
870 return mode;
871}
872
873static const struct regulator_ops wm8350_dcdc_ops = {
874 .set_voltage_sel = regulator_set_voltage_sel_regmap,
875 .get_voltage_sel = regulator_get_voltage_sel_regmap,
876 .list_voltage = regulator_list_voltage_linear,
877 .map_voltage = regulator_map_voltage_linear,
878 .enable = regulator_enable_regmap,
879 .disable = regulator_disable_regmap,
880 .is_enabled = regulator_is_enabled_regmap,
881 .get_mode = wm8350_dcdc_get_mode,
882 .set_mode = wm8350_dcdc_set_mode,
883 .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
884 .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
885 .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
886 .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
887 .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
888};
889
890static const struct regulator_ops wm8350_dcdc2_5_ops = {
891 .enable = regulator_enable_regmap,
892 .disable = regulator_disable_regmap,
893 .is_enabled = regulator_is_enabled_regmap,
894 .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
895 .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
896};
897
898static const struct regulator_ops wm8350_ldo_ops = {
899 .map_voltage = regulator_map_voltage_linear_range,
900 .set_voltage_sel = regulator_set_voltage_sel_regmap,
901 .get_voltage_sel = regulator_get_voltage_sel_regmap,
902 .list_voltage = regulator_list_voltage_linear_range,
903 .enable = regulator_enable_regmap,
904 .disable = regulator_disable_regmap,
905 .is_enabled = regulator_is_enabled_regmap,
906 .get_mode = wm8350_ldo_get_mode,
907 .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
908 .set_suspend_enable = wm8350_ldo_set_suspend_enable,
909 .set_suspend_disable = wm8350_ldo_set_suspend_disable,
910};
911
912static const struct regulator_ops wm8350_isink_ops = {
913 .set_current_limit = regulator_set_current_limit_regmap,
914 .get_current_limit = regulator_get_current_limit_regmap,
915 .enable = wm8350_isink_enable,
916 .disable = wm8350_isink_disable,
917 .is_enabled = wm8350_isink_is_enabled,
918 .enable_time = wm8350_isink_enable_time,
919};
920
921static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
922 {
923 .name = "DCDC1",
924 .id = WM8350_DCDC_1,
925 .ops = &wm8350_dcdc_ops,
926 .irq = WM8350_IRQ_UV_DC1,
927 .type = REGULATOR_VOLTAGE,
928 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
929 .min_uV = 850000,
930 .uV_step = 25000,
931 .vsel_reg = WM8350_DCDC1_CONTROL,
932 .vsel_mask = WM8350_DC1_VSEL_MASK,
933 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
934 .enable_mask = WM8350_DC1_ENA,
935 .owner = THIS_MODULE,
936 },
937 {
938 .name = "DCDC2",
939 .id = WM8350_DCDC_2,
940 .ops = &wm8350_dcdc2_5_ops,
941 .irq = WM8350_IRQ_UV_DC2,
942 .type = REGULATOR_VOLTAGE,
943 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
944 .enable_mask = WM8350_DC2_ENA,
945 .owner = THIS_MODULE,
946 },
947 {
948 .name = "DCDC3",
949 .id = WM8350_DCDC_3,
950 .ops = &wm8350_dcdc_ops,
951 .irq = WM8350_IRQ_UV_DC3,
952 .type = REGULATOR_VOLTAGE,
953 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
954 .min_uV = 850000,
955 .uV_step = 25000,
956 .vsel_reg = WM8350_DCDC3_CONTROL,
957 .vsel_mask = WM8350_DC3_VSEL_MASK,
958 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
959 .enable_mask = WM8350_DC3_ENA,
960 .owner = THIS_MODULE,
961 },
962 {
963 .name = "DCDC4",
964 .id = WM8350_DCDC_4,
965 .ops = &wm8350_dcdc_ops,
966 .irq = WM8350_IRQ_UV_DC4,
967 .type = REGULATOR_VOLTAGE,
968 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
969 .min_uV = 850000,
970 .uV_step = 25000,
971 .vsel_reg = WM8350_DCDC4_CONTROL,
972 .vsel_mask = WM8350_DC4_VSEL_MASK,
973 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
974 .enable_mask = WM8350_DC4_ENA,
975 .owner = THIS_MODULE,
976 },
977 {
978 .name = "DCDC5",
979 .id = WM8350_DCDC_5,
980 .ops = &wm8350_dcdc2_5_ops,
981 .irq = WM8350_IRQ_UV_DC5,
982 .type = REGULATOR_VOLTAGE,
983 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
984 .enable_mask = WM8350_DC5_ENA,
985 .owner = THIS_MODULE,
986 },
987 {
988 .name = "DCDC6",
989 .id = WM8350_DCDC_6,
990 .ops = &wm8350_dcdc_ops,
991 .irq = WM8350_IRQ_UV_DC6,
992 .type = REGULATOR_VOLTAGE,
993 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
994 .min_uV = 850000,
995 .uV_step = 25000,
996 .vsel_reg = WM8350_DCDC6_CONTROL,
997 .vsel_mask = WM8350_DC6_VSEL_MASK,
998 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
999 .enable_mask = WM8350_DC6_ENA,
1000 .owner = THIS_MODULE,
1001 },
1002 {
1003 .name = "LDO1",
1004 .id = WM8350_LDO_1,
1005 .ops = &wm8350_ldo_ops,
1006 .irq = WM8350_IRQ_UV_LDO1,
1007 .type = REGULATOR_VOLTAGE,
1008 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1009 .linear_ranges = wm8350_ldo_ranges,
1010 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1011 .vsel_reg = WM8350_LDO1_CONTROL,
1012 .vsel_mask = WM8350_LDO1_VSEL_MASK,
1013 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1014 .enable_mask = WM8350_LDO1_ENA,
1015 .owner = THIS_MODULE,
1016 },
1017 {
1018 .name = "LDO2",
1019 .id = WM8350_LDO_2,
1020 .ops = &wm8350_ldo_ops,
1021 .irq = WM8350_IRQ_UV_LDO2,
1022 .type = REGULATOR_VOLTAGE,
1023 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1024 .linear_ranges = wm8350_ldo_ranges,
1025 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1026 .vsel_reg = WM8350_LDO2_CONTROL,
1027 .vsel_mask = WM8350_LDO2_VSEL_MASK,
1028 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1029 .enable_mask = WM8350_LDO2_ENA,
1030 .owner = THIS_MODULE,
1031 },
1032 {
1033 .name = "LDO3",
1034 .id = WM8350_LDO_3,
1035 .ops = &wm8350_ldo_ops,
1036 .irq = WM8350_IRQ_UV_LDO3,
1037 .type = REGULATOR_VOLTAGE,
1038 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1039 .linear_ranges = wm8350_ldo_ranges,
1040 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1041 .vsel_reg = WM8350_LDO3_CONTROL,
1042 .vsel_mask = WM8350_LDO3_VSEL_MASK,
1043 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1044 .enable_mask = WM8350_LDO3_ENA,
1045 .owner = THIS_MODULE,
1046 },
1047 {
1048 .name = "LDO4",
1049 .id = WM8350_LDO_4,
1050 .ops = &wm8350_ldo_ops,
1051 .irq = WM8350_IRQ_UV_LDO4,
1052 .type = REGULATOR_VOLTAGE,
1053 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1054 .linear_ranges = wm8350_ldo_ranges,
1055 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1056 .vsel_reg = WM8350_LDO4_CONTROL,
1057 .vsel_mask = WM8350_LDO4_VSEL_MASK,
1058 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1059 .enable_mask = WM8350_LDO4_ENA,
1060 .owner = THIS_MODULE,
1061 },
1062 {
1063 .name = "ISINKA",
1064 .id = WM8350_ISINK_A,
1065 .ops = &wm8350_isink_ops,
1066 .irq = WM8350_IRQ_CS1,
1067 .type = REGULATOR_CURRENT,
1068 .owner = THIS_MODULE,
1069 .curr_table = isink_cur,
1070 .n_current_limits = ARRAY_SIZE(isink_cur),
1071 .csel_reg = WM8350_CURRENT_SINK_DRIVER_A,
1072 .csel_mask = WM8350_CS1_ISEL_MASK,
1073 },
1074 {
1075 .name = "ISINKB",
1076 .id = WM8350_ISINK_B,
1077 .ops = &wm8350_isink_ops,
1078 .irq = WM8350_IRQ_CS2,
1079 .type = REGULATOR_CURRENT,
1080 .owner = THIS_MODULE,
1081 .curr_table = isink_cur,
1082 .n_current_limits = ARRAY_SIZE(isink_cur),
1083 .csel_reg = WM8350_CURRENT_SINK_DRIVER_B,
1084 .csel_mask = WM8350_CS2_ISEL_MASK,
1085 },
1086};
1087
1088static irqreturn_t pmic_uv_handler(int irq, void *data)
1089{
1090 struct regulator_dev *rdev = (struct regulator_dev *)data;
1091
1092 regulator_lock(rdev);
1093 if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1094 regulator_notifier_call_chain(rdev,
1095 REGULATOR_EVENT_REGULATION_OUT,
1096 NULL);
1097 else
1098 regulator_notifier_call_chain(rdev,
1099 REGULATOR_EVENT_UNDER_VOLTAGE,
1100 NULL);
1101 regulator_unlock(rdev);
1102
1103 return IRQ_HANDLED;
1104}
1105
1106static int wm8350_regulator_probe(struct platform_device *pdev)
1107{
1108 struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1109 struct regulator_config config = { };
1110 struct regulator_dev *rdev;
1111 int ret;
1112 u16 val;
1113
1114 if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1115 return -ENODEV;
1116
1117 /* do any regulatior specific init */
1118 switch (pdev->id) {
1119 case WM8350_DCDC_1:
1120 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1121 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1122 break;
1123 case WM8350_DCDC_3:
1124 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1125 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1126 break;
1127 case WM8350_DCDC_4:
1128 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1129 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1130 break;
1131 case WM8350_DCDC_6:
1132 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1133 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1134 break;
1135 }
1136
1137 config.dev = &pdev->dev;
1138 config.init_data = dev_get_platdata(&pdev->dev);
1139 config.driver_data = dev_get_drvdata(&pdev->dev);
1140 config.regmap = wm8350->regmap;
1141
1142 /* register regulator */
1143 rdev = devm_regulator_register(&pdev->dev, &wm8350_reg[pdev->id],
1144 &config);
1145 if (IS_ERR(rdev)) {
1146 dev_err(&pdev->dev, "failed to register %s\n",
1147 wm8350_reg[pdev->id].name);
1148 return PTR_ERR(rdev);
1149 }
1150
1151 /* register regulator IRQ */
1152 ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1153 pmic_uv_handler, 0, "UV", rdev);
1154 if (ret < 0) {
1155 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1156 wm8350_reg[pdev->id].name);
1157 return ret;
1158 }
1159
1160 return 0;
1161}
1162
1163static int wm8350_regulator_remove(struct platform_device *pdev)
1164{
1165 struct regulator_dev *rdev = platform_get_drvdata(pdev);
1166 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1167
1168 wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1169
1170 return 0;
1171}
1172
1173int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1174 struct regulator_init_data *initdata)
1175{
1176 struct platform_device *pdev;
1177 int ret;
1178 if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1179 return -EINVAL;
1180
1181 if (wm8350->pmic.pdev[reg])
1182 return -EBUSY;
1183
1184 if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1185 reg > wm8350->pmic.max_dcdc)
1186 return -ENODEV;
1187 if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1188 reg > wm8350->pmic.max_isink)
1189 return -ENODEV;
1190
1191 pdev = platform_device_alloc("wm8350-regulator", reg);
1192 if (!pdev)
1193 return -ENOMEM;
1194
1195 wm8350->pmic.pdev[reg] = pdev;
1196
1197 initdata->driver_data = wm8350;
1198
1199 pdev->dev.platform_data = initdata;
1200 pdev->dev.parent = wm8350->dev;
1201 platform_set_drvdata(pdev, wm8350);
1202
1203 ret = platform_device_add(pdev);
1204
1205 if (ret != 0) {
1206 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1207 reg, ret);
1208 platform_device_put(pdev);
1209 wm8350->pmic.pdev[reg] = NULL;
1210 }
1211
1212 return ret;
1213}
1214EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1215
1216/**
1217 * wm8350_register_led - Register a WM8350 LED output
1218 *
1219 * @wm8350: The WM8350 device to configure.
1220 * @lednum: LED device index to create.
1221 * @dcdc: The DCDC to use for the LED.
1222 * @isink: The ISINK to use for the LED.
1223 * @pdata: Configuration for the LED.
1224 *
1225 * The WM8350 supports the use of an ISINK together with a DCDC to
1226 * provide a power-efficient LED driver. This function registers the
1227 * regulators and instantiates the platform device for a LED. The
1228 * operating modes for the LED regulators must be configured using
1229 * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1230 * wm8350_dcdc_set_slot() prior to calling this function.
1231 */
1232int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1233 struct wm8350_led_platform_data *pdata)
1234{
1235 struct wm8350_led *led;
1236 struct platform_device *pdev;
1237 int ret;
1238
1239 if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1240 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1241 return -ENODEV;
1242 }
1243
1244 led = &wm8350->pmic.led[lednum];
1245
1246 if (led->pdev) {
1247 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1248 return -EINVAL;
1249 }
1250
1251 pdev = platform_device_alloc("wm8350-led", lednum);
1252 if (pdev == NULL) {
1253 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1254 return -ENOMEM;
1255 }
1256
1257 led->isink_consumer.dev_name = dev_name(&pdev->dev);
1258 led->isink_consumer.supply = "led_isink";
1259 led->isink_init.num_consumer_supplies = 1;
1260 led->isink_init.consumer_supplies = &led->isink_consumer;
1261 led->isink_init.constraints.min_uA = 0;
1262 led->isink_init.constraints.max_uA = pdata->max_uA;
1263 led->isink_init.constraints.valid_ops_mask
1264 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1265 led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1266 ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1267 if (ret != 0) {
1268 platform_device_put(pdev);
1269 return ret;
1270 }
1271
1272 led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1273 led->dcdc_consumer.supply = "led_vcc";
1274 led->dcdc_init.num_consumer_supplies = 1;
1275 led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1276 led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1277 led->dcdc_init.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
1278 ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1279 if (ret != 0) {
1280 platform_device_put(pdev);
1281 return ret;
1282 }
1283
1284 switch (isink) {
1285 case WM8350_ISINK_A:
1286 wm8350->pmic.isink_A_dcdc = dcdc;
1287 break;
1288 case WM8350_ISINK_B:
1289 wm8350->pmic.isink_B_dcdc = dcdc;
1290 break;
1291 }
1292
1293 pdev->dev.platform_data = pdata;
1294 pdev->dev.parent = wm8350->dev;
1295 ret = platform_device_add(pdev);
1296 if (ret != 0) {
1297 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1298 lednum, ret);
1299 platform_device_put(pdev);
1300 return ret;
1301 }
1302
1303 led->pdev = pdev;
1304
1305 return 0;
1306}
1307EXPORT_SYMBOL_GPL(wm8350_register_led);
1308
1309static struct platform_driver wm8350_regulator_driver = {
1310 .probe = wm8350_regulator_probe,
1311 .remove = wm8350_regulator_remove,
1312 .driver = {
1313 .name = "wm8350-regulator",
1314 },
1315};
1316
1317static int __init wm8350_regulator_init(void)
1318{
1319 return platform_driver_register(&wm8350_regulator_driver);
1320}
1321subsys_initcall(wm8350_regulator_init);
1322
1323static void __exit wm8350_regulator_exit(void)
1324{
1325 platform_driver_unregister(&wm8350_regulator_driver);
1326}
1327module_exit(wm8350_regulator_exit);
1328
1329/* Module information */
1330MODULE_AUTHOR("Liam Girdwood");
1331MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1332MODULE_LICENSE("GPL");
1333MODULE_ALIAS("platform:wm8350-regulator");
1/*
2 * wm8350.c -- Voltage and current regulation for the Wolfson WM8350 PMIC
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood
7 * linux@wolfsonmicro.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/mfd/wm8350/pmic.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/machine.h>
26
27/* Maximum value possible for VSEL */
28#define WM8350_DCDC_MAX_VSEL 0x66
29
30/* Microamps */
31static const int isink_cur[] = {
32 4,
33 5,
34 6,
35 7,
36 8,
37 10,
38 11,
39 14,
40 16,
41 19,
42 23,
43 27,
44 32,
45 39,
46 46,
47 54,
48 65,
49 77,
50 92,
51 109,
52 130,
53 154,
54 183,
55 218,
56 259,
57 308,
58 367,
59 436,
60 518,
61 616,
62 733,
63 872,
64 1037,
65 1233,
66 1466,
67 1744,
68 2073,
69 2466,
70 2933,
71 3487,
72 4147,
73 4932,
74 5865,
75 6975,
76 8294,
77 9864,
78 11730,
79 13949,
80 16589,
81 19728,
82 23460,
83 27899,
84 33178,
85 39455,
86 46920,
87 55798,
88 66355,
89 78910,
90 93840,
91 111596,
92 132710,
93 157820,
94 187681,
95 223191
96};
97
98static int get_isink_val(int min_uA, int max_uA, u16 *setting)
99{
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(isink_cur); i++) {
103 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
104 *setting = i;
105 return 0;
106 }
107 }
108 return -EINVAL;
109}
110
111static inline int wm8350_ldo_val_to_mvolts(unsigned int val)
112{
113 if (val < 16)
114 return (val * 50) + 900;
115 else
116 return ((val - 16) * 100) + 1800;
117
118}
119
120static inline unsigned int wm8350_ldo_mvolts_to_val(int mV)
121{
122 if (mV < 1800)
123 return (mV - 900) / 50;
124 else
125 return ((mV - 1800) / 100) + 16;
126}
127
128static inline int wm8350_dcdc_val_to_mvolts(unsigned int val)
129{
130 return (val * 25) + 850;
131}
132
133static inline unsigned int wm8350_dcdc_mvolts_to_val(int mV)
134{
135 return (mV - 850) / 25;
136}
137
138static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
139 int max_uA)
140{
141 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
142 int isink = rdev_get_id(rdev);
143 u16 val, setting;
144 int ret;
145
146 ret = get_isink_val(min_uA, max_uA, &setting);
147 if (ret != 0)
148 return ret;
149
150 switch (isink) {
151 case WM8350_ISINK_A:
152 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
153 ~WM8350_CS1_ISEL_MASK;
154 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
155 val | setting);
156 break;
157 case WM8350_ISINK_B:
158 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
159 ~WM8350_CS1_ISEL_MASK;
160 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
161 val | setting);
162 break;
163 default:
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static int wm8350_isink_get_current(struct regulator_dev *rdev)
171{
172 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
173 int isink = rdev_get_id(rdev);
174 u16 val;
175
176 switch (isink) {
177 case WM8350_ISINK_A:
178 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
179 WM8350_CS1_ISEL_MASK;
180 break;
181 case WM8350_ISINK_B:
182 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
183 WM8350_CS1_ISEL_MASK;
184 break;
185 default:
186 return 0;
187 }
188
189 return isink_cur[val];
190}
191
192/* turn on ISINK followed by DCDC */
193static int wm8350_isink_enable(struct regulator_dev *rdev)
194{
195 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
196 int isink = rdev_get_id(rdev);
197
198 switch (isink) {
199 case WM8350_ISINK_A:
200 switch (wm8350->pmic.isink_A_dcdc) {
201 case WM8350_DCDC_2:
202 case WM8350_DCDC_5:
203 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
204 WM8350_CS1_ENA);
205 wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
206 WM8350_CS1_DRIVE);
207 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
208 1 << (wm8350->pmic.isink_A_dcdc -
209 WM8350_DCDC_1));
210 break;
211 default:
212 return -EINVAL;
213 }
214 break;
215 case WM8350_ISINK_B:
216 switch (wm8350->pmic.isink_B_dcdc) {
217 case WM8350_DCDC_2:
218 case WM8350_DCDC_5:
219 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
220 WM8350_CS2_ENA);
221 wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
222 WM8350_CS2_DRIVE);
223 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
224 1 << (wm8350->pmic.isink_B_dcdc -
225 WM8350_DCDC_1));
226 break;
227 default:
228 return -EINVAL;
229 }
230 break;
231 default:
232 return -EINVAL;
233 }
234 return 0;
235}
236
237static int wm8350_isink_disable(struct regulator_dev *rdev)
238{
239 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
240 int isink = rdev_get_id(rdev);
241
242 switch (isink) {
243 case WM8350_ISINK_A:
244 switch (wm8350->pmic.isink_A_dcdc) {
245 case WM8350_DCDC_2:
246 case WM8350_DCDC_5:
247 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
248 1 << (wm8350->pmic.isink_A_dcdc -
249 WM8350_DCDC_1));
250 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
251 WM8350_CS1_ENA);
252 break;
253 default:
254 return -EINVAL;
255 }
256 break;
257 case WM8350_ISINK_B:
258 switch (wm8350->pmic.isink_B_dcdc) {
259 case WM8350_DCDC_2:
260 case WM8350_DCDC_5:
261 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
262 1 << (wm8350->pmic.isink_B_dcdc -
263 WM8350_DCDC_1));
264 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
265 WM8350_CS2_ENA);
266 break;
267 default:
268 return -EINVAL;
269 }
270 break;
271 default:
272 return -EINVAL;
273 }
274 return 0;
275}
276
277static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
278{
279 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
280 int isink = rdev_get_id(rdev);
281
282 switch (isink) {
283 case WM8350_ISINK_A:
284 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
285 0x8000;
286 case WM8350_ISINK_B:
287 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
288 0x8000;
289 }
290 return -EINVAL;
291}
292
293static int wm8350_isink_enable_time(struct regulator_dev *rdev)
294{
295 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
296 int isink = rdev_get_id(rdev);
297 int reg;
298
299 switch (isink) {
300 case WM8350_ISINK_A:
301 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
302 break;
303 case WM8350_ISINK_B:
304 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
305 break;
306 default:
307 return -EINVAL;
308 }
309
310 if (reg & WM8350_CS1_FLASH_MODE) {
311 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
312 case 0:
313 return 0;
314 case 1:
315 return 1950;
316 case 2:
317 return 3910;
318 case 3:
319 return 7800;
320 }
321 } else {
322 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
323 case 0:
324 return 0;
325 case 1:
326 return 250000;
327 case 2:
328 return 500000;
329 case 3:
330 return 1000000;
331 }
332 }
333
334 return -EINVAL;
335}
336
337
338int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
339 u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
340 u16 drive)
341{
342 switch (isink) {
343 case WM8350_ISINK_A:
344 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
345 (mode ? WM8350_CS1_FLASH_MODE : 0) |
346 (trigger ? WM8350_CS1_TRIGSRC : 0) |
347 duration | on_ramp | off_ramp | drive);
348 break;
349 case WM8350_ISINK_B:
350 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
351 (mode ? WM8350_CS2_FLASH_MODE : 0) |
352 (trigger ? WM8350_CS2_TRIGSRC : 0) |
353 duration | on_ramp | off_ramp | drive);
354 break;
355 default:
356 return -EINVAL;
357 }
358 return 0;
359}
360EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
361
362static int wm8350_dcdc_set_voltage(struct regulator_dev *rdev, int min_uV,
363 int max_uV, unsigned *selector)
364{
365 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
366 int volt_reg, dcdc = rdev_get_id(rdev), mV,
367 min_mV = min_uV / 1000, max_mV = max_uV / 1000;
368 u16 val;
369
370 if (min_mV < 850 || min_mV > 4025)
371 return -EINVAL;
372 if (max_mV < 850 || max_mV > 4025)
373 return -EINVAL;
374
375 /* step size is 25mV */
376 mV = (min_mV - 826) / 25;
377 if (wm8350_dcdc_val_to_mvolts(mV) > max_mV)
378 return -EINVAL;
379 BUG_ON(wm8350_dcdc_val_to_mvolts(mV) < min_mV);
380
381 switch (dcdc) {
382 case WM8350_DCDC_1:
383 volt_reg = WM8350_DCDC1_CONTROL;
384 break;
385 case WM8350_DCDC_3:
386 volt_reg = WM8350_DCDC3_CONTROL;
387 break;
388 case WM8350_DCDC_4:
389 volt_reg = WM8350_DCDC4_CONTROL;
390 break;
391 case WM8350_DCDC_6:
392 volt_reg = WM8350_DCDC6_CONTROL;
393 break;
394 case WM8350_DCDC_2:
395 case WM8350_DCDC_5:
396 default:
397 return -EINVAL;
398 }
399
400 *selector = mV;
401
402 /* all DCDCs have same mV bits */
403 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
404 wm8350_reg_write(wm8350, volt_reg, val | mV);
405 return 0;
406}
407
408static int wm8350_dcdc_get_voltage_sel(struct regulator_dev *rdev)
409{
410 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
411 int volt_reg, dcdc = rdev_get_id(rdev);
412
413 switch (dcdc) {
414 case WM8350_DCDC_1:
415 volt_reg = WM8350_DCDC1_CONTROL;
416 break;
417 case WM8350_DCDC_3:
418 volt_reg = WM8350_DCDC3_CONTROL;
419 break;
420 case WM8350_DCDC_4:
421 volt_reg = WM8350_DCDC4_CONTROL;
422 break;
423 case WM8350_DCDC_6:
424 volt_reg = WM8350_DCDC6_CONTROL;
425 break;
426 case WM8350_DCDC_2:
427 case WM8350_DCDC_5:
428 default:
429 return -EINVAL;
430 }
431
432 /* all DCDCs have same mV bits */
433 return wm8350_reg_read(wm8350, volt_reg) & WM8350_DC1_VSEL_MASK;
434}
435
436static int wm8350_dcdc_list_voltage(struct regulator_dev *rdev,
437 unsigned selector)
438{
439 if (selector > WM8350_DCDC_MAX_VSEL)
440 return -EINVAL;
441 return wm8350_dcdc_val_to_mvolts(selector) * 1000;
442}
443
444static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
445{
446 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
447 int volt_reg, mV = uV / 1000, dcdc = rdev_get_id(rdev);
448 u16 val;
449
450 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, mV);
451
452 if (mV && (mV < 850 || mV > 4025)) {
453 dev_err(wm8350->dev,
454 "DCDC%d suspend voltage %d mV out of range\n",
455 dcdc, mV);
456 return -EINVAL;
457 }
458 if (mV == 0)
459 mV = 850;
460
461 switch (dcdc) {
462 case WM8350_DCDC_1:
463 volt_reg = WM8350_DCDC1_LOW_POWER;
464 break;
465 case WM8350_DCDC_3:
466 volt_reg = WM8350_DCDC3_LOW_POWER;
467 break;
468 case WM8350_DCDC_4:
469 volt_reg = WM8350_DCDC4_LOW_POWER;
470 break;
471 case WM8350_DCDC_6:
472 volt_reg = WM8350_DCDC6_LOW_POWER;
473 break;
474 case WM8350_DCDC_2:
475 case WM8350_DCDC_5:
476 default:
477 return -EINVAL;
478 }
479
480 /* all DCDCs have same mV bits */
481 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
482 wm8350_reg_write(wm8350, volt_reg,
483 val | wm8350_dcdc_mvolts_to_val(mV));
484 return 0;
485}
486
487static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
488{
489 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
490 int dcdc = rdev_get_id(rdev);
491 u16 val;
492
493 switch (dcdc) {
494 case WM8350_DCDC_1:
495 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
496 & ~WM8350_DCDC_HIB_MODE_MASK;
497 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
498 val | wm8350->pmic.dcdc1_hib_mode);
499 break;
500 case WM8350_DCDC_3:
501 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
502 & ~WM8350_DCDC_HIB_MODE_MASK;
503 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
504 val | wm8350->pmic.dcdc3_hib_mode);
505 break;
506 case WM8350_DCDC_4:
507 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
508 & ~WM8350_DCDC_HIB_MODE_MASK;
509 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
510 val | wm8350->pmic.dcdc4_hib_mode);
511 break;
512 case WM8350_DCDC_6:
513 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
514 & ~WM8350_DCDC_HIB_MODE_MASK;
515 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
516 val | wm8350->pmic.dcdc6_hib_mode);
517 break;
518 case WM8350_DCDC_2:
519 case WM8350_DCDC_5:
520 default:
521 return -EINVAL;
522 }
523
524 return 0;
525}
526
527static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
528{
529 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
530 int dcdc = rdev_get_id(rdev);
531 u16 val;
532
533 switch (dcdc) {
534 case WM8350_DCDC_1:
535 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
536 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
537 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
538 val | WM8350_DCDC_HIB_MODE_DIS);
539 break;
540 case WM8350_DCDC_3:
541 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
542 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
543 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
544 val | WM8350_DCDC_HIB_MODE_DIS);
545 break;
546 case WM8350_DCDC_4:
547 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
548 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
549 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
550 val | WM8350_DCDC_HIB_MODE_DIS);
551 break;
552 case WM8350_DCDC_6:
553 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
554 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
555 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
556 val | WM8350_DCDC_HIB_MODE_DIS);
557 break;
558 case WM8350_DCDC_2:
559 case WM8350_DCDC_5:
560 default:
561 return -EINVAL;
562 }
563
564 return 0;
565}
566
567static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
568{
569 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
570 int dcdc = rdev_get_id(rdev);
571 u16 val;
572
573 switch (dcdc) {
574 case WM8350_DCDC_2:
575 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
576 & ~WM8350_DC2_HIB_MODE_MASK;
577 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
578 (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
579 break;
580 case WM8350_DCDC_5:
581 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
582 & ~WM8350_DC5_HIB_MODE_MASK;
583 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
584 (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
585 break;
586 default:
587 return -EINVAL;
588 }
589 return 0;
590}
591
592static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
593{
594 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
595 int dcdc = rdev_get_id(rdev);
596 u16 val;
597
598 switch (dcdc) {
599 case WM8350_DCDC_2:
600 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
601 & ~WM8350_DC2_HIB_MODE_MASK;
602 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
603 (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
604 break;
605 case WM8350_DCDC_5:
606 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
607 & ~WM8350_DC5_HIB_MODE_MASK;
608 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
609 (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
610 break;
611 default:
612 return -EINVAL;
613 }
614 return 0;
615}
616
617static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
618 unsigned int mode)
619{
620 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
621 int dcdc = rdev_get_id(rdev);
622 u16 *hib_mode;
623
624 switch (dcdc) {
625 case WM8350_DCDC_1:
626 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
627 break;
628 case WM8350_DCDC_3:
629 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
630 break;
631 case WM8350_DCDC_4:
632 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
633 break;
634 case WM8350_DCDC_6:
635 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
636 break;
637 case WM8350_DCDC_2:
638 case WM8350_DCDC_5:
639 default:
640 return -EINVAL;
641 }
642
643 switch (mode) {
644 case REGULATOR_MODE_NORMAL:
645 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
646 break;
647 case REGULATOR_MODE_IDLE:
648 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
649 break;
650 case REGULATOR_MODE_STANDBY:
651 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 return 0;
658}
659
660static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
661{
662 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
663 int volt_reg, mV = uV / 1000, ldo = rdev_get_id(rdev);
664 u16 val;
665
666 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, mV);
667
668 if (mV < 900 || mV > 3300) {
669 dev_err(wm8350->dev, "LDO%d voltage %d mV out of range\n",
670 ldo, mV);
671 return -EINVAL;
672 }
673
674 switch (ldo) {
675 case WM8350_LDO_1:
676 volt_reg = WM8350_LDO1_LOW_POWER;
677 break;
678 case WM8350_LDO_2:
679 volt_reg = WM8350_LDO2_LOW_POWER;
680 break;
681 case WM8350_LDO_3:
682 volt_reg = WM8350_LDO3_LOW_POWER;
683 break;
684 case WM8350_LDO_4:
685 volt_reg = WM8350_LDO4_LOW_POWER;
686 break;
687 default:
688 return -EINVAL;
689 }
690
691 /* all LDOs have same mV bits */
692 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
693 wm8350_reg_write(wm8350, volt_reg,
694 val | wm8350_ldo_mvolts_to_val(mV));
695 return 0;
696}
697
698static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
699{
700 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
701 int volt_reg, ldo = rdev_get_id(rdev);
702 u16 val;
703
704 switch (ldo) {
705 case WM8350_LDO_1:
706 volt_reg = WM8350_LDO1_LOW_POWER;
707 break;
708 case WM8350_LDO_2:
709 volt_reg = WM8350_LDO2_LOW_POWER;
710 break;
711 case WM8350_LDO_3:
712 volt_reg = WM8350_LDO3_LOW_POWER;
713 break;
714 case WM8350_LDO_4:
715 volt_reg = WM8350_LDO4_LOW_POWER;
716 break;
717 default:
718 return -EINVAL;
719 }
720
721 /* all LDOs have same mV bits */
722 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
723 wm8350_reg_write(wm8350, volt_reg, val);
724 return 0;
725}
726
727static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
728{
729 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
730 int volt_reg, ldo = rdev_get_id(rdev);
731 u16 val;
732
733 switch (ldo) {
734 case WM8350_LDO_1:
735 volt_reg = WM8350_LDO1_LOW_POWER;
736 break;
737 case WM8350_LDO_2:
738 volt_reg = WM8350_LDO2_LOW_POWER;
739 break;
740 case WM8350_LDO_3:
741 volt_reg = WM8350_LDO3_LOW_POWER;
742 break;
743 case WM8350_LDO_4:
744 volt_reg = WM8350_LDO4_LOW_POWER;
745 break;
746 default:
747 return -EINVAL;
748 }
749
750 /* all LDOs have same mV bits */
751 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
752 wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
753 return 0;
754}
755
756static int wm8350_ldo_set_voltage(struct regulator_dev *rdev, int min_uV,
757 int max_uV, unsigned *selector)
758{
759 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
760 int volt_reg, ldo = rdev_get_id(rdev), mV, min_mV = min_uV / 1000,
761 max_mV = max_uV / 1000;
762 u16 val;
763
764 if (min_mV < 900 || min_mV > 3300)
765 return -EINVAL;
766 if (max_mV < 900 || max_mV > 3300)
767 return -EINVAL;
768
769 if (min_mV < 1800) {
770 /* step size is 50mV < 1800mV */
771 mV = (min_mV - 851) / 50;
772 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
773 return -EINVAL;
774 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
775 } else {
776 /* step size is 100mV > 1800mV */
777 mV = ((min_mV - 1701) / 100) + 16;
778 if (wm8350_ldo_val_to_mvolts(mV) > max_mV)
779 return -EINVAL;
780 BUG_ON(wm8350_ldo_val_to_mvolts(mV) < min_mV);
781 }
782
783 switch (ldo) {
784 case WM8350_LDO_1:
785 volt_reg = WM8350_LDO1_CONTROL;
786 break;
787 case WM8350_LDO_2:
788 volt_reg = WM8350_LDO2_CONTROL;
789 break;
790 case WM8350_LDO_3:
791 volt_reg = WM8350_LDO3_CONTROL;
792 break;
793 case WM8350_LDO_4:
794 volt_reg = WM8350_LDO4_CONTROL;
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 *selector = mV;
801
802 /* all LDOs have same mV bits */
803 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
804 wm8350_reg_write(wm8350, volt_reg, val | mV);
805 return 0;
806}
807
808static int wm8350_ldo_get_voltage_sel(struct regulator_dev *rdev)
809{
810 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
811 int volt_reg, ldo = rdev_get_id(rdev);
812
813 switch (ldo) {
814 case WM8350_LDO_1:
815 volt_reg = WM8350_LDO1_CONTROL;
816 break;
817 case WM8350_LDO_2:
818 volt_reg = WM8350_LDO2_CONTROL;
819 break;
820 case WM8350_LDO_3:
821 volt_reg = WM8350_LDO3_CONTROL;
822 break;
823 case WM8350_LDO_4:
824 volt_reg = WM8350_LDO4_CONTROL;
825 break;
826 default:
827 return -EINVAL;
828 }
829
830 /* all LDOs have same mV bits */
831 return wm8350_reg_read(wm8350, volt_reg) & WM8350_LDO1_VSEL_MASK;
832}
833
834static int wm8350_ldo_list_voltage(struct regulator_dev *rdev,
835 unsigned selector)
836{
837 if (selector > WM8350_LDO1_VSEL_MASK)
838 return -EINVAL;
839 return wm8350_ldo_val_to_mvolts(selector) * 1000;
840}
841
842int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
843 u16 stop, u16 fault)
844{
845 int slot_reg;
846 u16 val;
847
848 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
849 __func__, dcdc, start, stop);
850
851 /* slot valid ? */
852 if (start > 15 || stop > 15)
853 return -EINVAL;
854
855 switch (dcdc) {
856 case WM8350_DCDC_1:
857 slot_reg = WM8350_DCDC1_TIMEOUTS;
858 break;
859 case WM8350_DCDC_2:
860 slot_reg = WM8350_DCDC2_TIMEOUTS;
861 break;
862 case WM8350_DCDC_3:
863 slot_reg = WM8350_DCDC3_TIMEOUTS;
864 break;
865 case WM8350_DCDC_4:
866 slot_reg = WM8350_DCDC4_TIMEOUTS;
867 break;
868 case WM8350_DCDC_5:
869 slot_reg = WM8350_DCDC5_TIMEOUTS;
870 break;
871 case WM8350_DCDC_6:
872 slot_reg = WM8350_DCDC6_TIMEOUTS;
873 break;
874 default:
875 return -EINVAL;
876 }
877
878 val = wm8350_reg_read(wm8350, slot_reg) &
879 ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
880 WM8350_DC1_ERRACT_MASK);
881 wm8350_reg_write(wm8350, slot_reg,
882 val | (start << WM8350_DC1_ENSLOT_SHIFT) |
883 (stop << WM8350_DC1_SDSLOT_SHIFT) |
884 (fault << WM8350_DC1_ERRACT_SHIFT));
885
886 return 0;
887}
888EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
889
890int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
891{
892 int slot_reg;
893 u16 val;
894
895 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
896 __func__, ldo, start, stop);
897
898 /* slot valid ? */
899 if (start > 15 || stop > 15)
900 return -EINVAL;
901
902 switch (ldo) {
903 case WM8350_LDO_1:
904 slot_reg = WM8350_LDO1_TIMEOUTS;
905 break;
906 case WM8350_LDO_2:
907 slot_reg = WM8350_LDO2_TIMEOUTS;
908 break;
909 case WM8350_LDO_3:
910 slot_reg = WM8350_LDO3_TIMEOUTS;
911 break;
912 case WM8350_LDO_4:
913 slot_reg = WM8350_LDO4_TIMEOUTS;
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
920 wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
921 return 0;
922}
923EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
924
925int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
926 u16 ilim, u16 ramp, u16 feedback)
927{
928 u16 val;
929
930 dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
931 mode ? "normal" : "boost", ilim ? "low" : "normal");
932
933 switch (dcdc) {
934 case WM8350_DCDC_2:
935 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
936 & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
937 WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
938 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
939 (mode << WM8350_DC2_MODE_SHIFT) |
940 (ilim << WM8350_DC2_ILIM_SHIFT) |
941 (ramp << WM8350_DC2_RMP_SHIFT) |
942 (feedback << WM8350_DC2_FBSRC_SHIFT));
943 break;
944 case WM8350_DCDC_5:
945 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
946 & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
947 WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
948 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
949 (mode << WM8350_DC5_MODE_SHIFT) |
950 (ilim << WM8350_DC5_ILIM_SHIFT) |
951 (ramp << WM8350_DC5_RMP_SHIFT) |
952 (feedback << WM8350_DC5_FBSRC_SHIFT));
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 return 0;
959}
960EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
961
962static int wm8350_dcdc_enable(struct regulator_dev *rdev)
963{
964 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
965 int dcdc = rdev_get_id(rdev);
966 u16 shift;
967
968 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
969 return -EINVAL;
970
971 shift = dcdc - WM8350_DCDC_1;
972 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
973 return 0;
974}
975
976static int wm8350_dcdc_disable(struct regulator_dev *rdev)
977{
978 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
979 int dcdc = rdev_get_id(rdev);
980 u16 shift;
981
982 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
983 return -EINVAL;
984
985 shift = dcdc - WM8350_DCDC_1;
986 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
987
988 return 0;
989}
990
991static int wm8350_ldo_enable(struct regulator_dev *rdev)
992{
993 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
994 int ldo = rdev_get_id(rdev);
995 u16 shift;
996
997 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
998 return -EINVAL;
999
1000 shift = (ldo - WM8350_LDO_1) + 8;
1001 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
1002 return 0;
1003}
1004
1005static int wm8350_ldo_disable(struct regulator_dev *rdev)
1006{
1007 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1008 int ldo = rdev_get_id(rdev);
1009 u16 shift;
1010
1011 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1012 return -EINVAL;
1013
1014 shift = (ldo - WM8350_LDO_1) + 8;
1015 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED, 1 << shift);
1016 return 0;
1017}
1018
1019static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
1020{
1021 int reg = 0, ret;
1022
1023 switch (dcdc) {
1024 case WM8350_DCDC_1:
1025 reg = WM8350_DCDC1_FORCE_PWM;
1026 break;
1027 case WM8350_DCDC_3:
1028 reg = WM8350_DCDC3_FORCE_PWM;
1029 break;
1030 case WM8350_DCDC_4:
1031 reg = WM8350_DCDC4_FORCE_PWM;
1032 break;
1033 case WM8350_DCDC_6:
1034 reg = WM8350_DCDC6_FORCE_PWM;
1035 break;
1036 default:
1037 return -EINVAL;
1038 }
1039
1040 if (enable)
1041 ret = wm8350_set_bits(wm8350, reg,
1042 WM8350_DCDC1_FORCE_PWM_ENA);
1043 else
1044 ret = wm8350_clear_bits(wm8350, reg,
1045 WM8350_DCDC1_FORCE_PWM_ENA);
1046 return ret;
1047}
1048
1049static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
1050{
1051 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1052 int dcdc = rdev_get_id(rdev);
1053 u16 val;
1054
1055 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1056 return -EINVAL;
1057
1058 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
1059 return -EINVAL;
1060
1061 val = 1 << (dcdc - WM8350_DCDC_1);
1062
1063 switch (mode) {
1064 case REGULATOR_MODE_FAST:
1065 /* force continuous mode */
1066 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1067 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1068 force_continuous_enable(wm8350, dcdc, 1);
1069 break;
1070 case REGULATOR_MODE_NORMAL:
1071 /* active / pulse skipping */
1072 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1073 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1074 force_continuous_enable(wm8350, dcdc, 0);
1075 break;
1076 case REGULATOR_MODE_IDLE:
1077 /* standby mode */
1078 force_continuous_enable(wm8350, dcdc, 0);
1079 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1080 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
1081 break;
1082 case REGULATOR_MODE_STANDBY:
1083 /* LDO mode */
1084 force_continuous_enable(wm8350, dcdc, 0);
1085 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
1086 break;
1087 }
1088
1089 return 0;
1090}
1091
1092static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
1093{
1094 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1095 int dcdc = rdev_get_id(rdev);
1096 u16 mask, sleep, active, force;
1097 int mode = REGULATOR_MODE_NORMAL;
1098 int reg;
1099
1100 switch (dcdc) {
1101 case WM8350_DCDC_1:
1102 reg = WM8350_DCDC1_FORCE_PWM;
1103 break;
1104 case WM8350_DCDC_3:
1105 reg = WM8350_DCDC3_FORCE_PWM;
1106 break;
1107 case WM8350_DCDC_4:
1108 reg = WM8350_DCDC4_FORCE_PWM;
1109 break;
1110 case WM8350_DCDC_6:
1111 reg = WM8350_DCDC6_FORCE_PWM;
1112 break;
1113 default:
1114 return -EINVAL;
1115 }
1116
1117 mask = 1 << (dcdc - WM8350_DCDC_1);
1118 active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
1119 force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
1120 sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
1121
1122 dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
1123 mask, active, sleep, force);
1124
1125 if (active && !sleep) {
1126 if (force)
1127 mode = REGULATOR_MODE_FAST;
1128 else
1129 mode = REGULATOR_MODE_NORMAL;
1130 } else if (!active && !sleep)
1131 mode = REGULATOR_MODE_IDLE;
1132 else if (sleep)
1133 mode = REGULATOR_MODE_STANDBY;
1134
1135 return mode;
1136}
1137
1138static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
1139{
1140 return REGULATOR_MODE_NORMAL;
1141}
1142
1143struct wm8350_dcdc_efficiency {
1144 int uA_load_min;
1145 int uA_load_max;
1146 unsigned int mode;
1147};
1148
1149static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
1150 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1151 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1152 {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1153 {-1, -1, REGULATOR_MODE_NORMAL},
1154};
1155
1156static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
1157 {0, 10000, REGULATOR_MODE_STANDBY}, /* 0 - 10mA - LDO */
1158 {10000, 100000, REGULATOR_MODE_IDLE}, /* 10mA - 100mA - Standby */
1159 {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
1160 {-1, -1, REGULATOR_MODE_NORMAL},
1161};
1162
1163static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
1164{
1165 int i = 0;
1166
1167 while (eff[i].uA_load_min != -1) {
1168 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
1169 return eff[i].mode;
1170 }
1171 return REGULATOR_MODE_NORMAL;
1172}
1173
1174/* Query the regulator for it's most efficient mode @ uV,uA
1175 * WM8350 regulator efficiency is pretty similar over
1176 * different input and output uV.
1177 */
1178static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
1179 int input_uV, int output_uV,
1180 int output_uA)
1181{
1182 int dcdc = rdev_get_id(rdev), mode;
1183
1184 switch (dcdc) {
1185 case WM8350_DCDC_1:
1186 case WM8350_DCDC_6:
1187 mode = get_mode(output_uA, dcdc1_6_efficiency);
1188 break;
1189 case WM8350_DCDC_3:
1190 case WM8350_DCDC_4:
1191 mode = get_mode(output_uA, dcdc3_4_efficiency);
1192 break;
1193 default:
1194 mode = REGULATOR_MODE_NORMAL;
1195 break;
1196 }
1197 return mode;
1198}
1199
1200static int wm8350_dcdc_is_enabled(struct regulator_dev *rdev)
1201{
1202 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1203 int dcdc = rdev_get_id(rdev), shift;
1204
1205 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
1206 return -EINVAL;
1207
1208 shift = dcdc - WM8350_DCDC_1;
1209 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1210 & (1 << shift);
1211}
1212
1213static int wm8350_ldo_is_enabled(struct regulator_dev *rdev)
1214{
1215 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1216 int ldo = rdev_get_id(rdev), shift;
1217
1218 if (ldo < WM8350_LDO_1 || ldo > WM8350_LDO_4)
1219 return -EINVAL;
1220
1221 shift = (ldo - WM8350_LDO_1) + 8;
1222 return wm8350_reg_read(wm8350, WM8350_DCDC_LDO_REQUESTED)
1223 & (1 << shift);
1224}
1225
1226static struct regulator_ops wm8350_dcdc_ops = {
1227 .set_voltage = wm8350_dcdc_set_voltage,
1228 .get_voltage_sel = wm8350_dcdc_get_voltage_sel,
1229 .list_voltage = wm8350_dcdc_list_voltage,
1230 .enable = wm8350_dcdc_enable,
1231 .disable = wm8350_dcdc_disable,
1232 .get_mode = wm8350_dcdc_get_mode,
1233 .set_mode = wm8350_dcdc_set_mode,
1234 .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
1235 .is_enabled = wm8350_dcdc_is_enabled,
1236 .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
1237 .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
1238 .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
1239 .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
1240};
1241
1242static struct regulator_ops wm8350_dcdc2_5_ops = {
1243 .enable = wm8350_dcdc_enable,
1244 .disable = wm8350_dcdc_disable,
1245 .is_enabled = wm8350_dcdc_is_enabled,
1246 .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
1247 .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
1248};
1249
1250static struct regulator_ops wm8350_ldo_ops = {
1251 .set_voltage = wm8350_ldo_set_voltage,
1252 .get_voltage_sel = wm8350_ldo_get_voltage_sel,
1253 .list_voltage = wm8350_ldo_list_voltage,
1254 .enable = wm8350_ldo_enable,
1255 .disable = wm8350_ldo_disable,
1256 .is_enabled = wm8350_ldo_is_enabled,
1257 .get_mode = wm8350_ldo_get_mode,
1258 .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1259 .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1260 .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1261};
1262
1263static struct regulator_ops wm8350_isink_ops = {
1264 .set_current_limit = wm8350_isink_set_current,
1265 .get_current_limit = wm8350_isink_get_current,
1266 .enable = wm8350_isink_enable,
1267 .disable = wm8350_isink_disable,
1268 .is_enabled = wm8350_isink_is_enabled,
1269 .enable_time = wm8350_isink_enable_time,
1270};
1271
1272static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1273 {
1274 .name = "DCDC1",
1275 .id = WM8350_DCDC_1,
1276 .ops = &wm8350_dcdc_ops,
1277 .irq = WM8350_IRQ_UV_DC1,
1278 .type = REGULATOR_VOLTAGE,
1279 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1280 .owner = THIS_MODULE,
1281 },
1282 {
1283 .name = "DCDC2",
1284 .id = WM8350_DCDC_2,
1285 .ops = &wm8350_dcdc2_5_ops,
1286 .irq = WM8350_IRQ_UV_DC2,
1287 .type = REGULATOR_VOLTAGE,
1288 .owner = THIS_MODULE,
1289 },
1290 {
1291 .name = "DCDC3",
1292 .id = WM8350_DCDC_3,
1293 .ops = &wm8350_dcdc_ops,
1294 .irq = WM8350_IRQ_UV_DC3,
1295 .type = REGULATOR_VOLTAGE,
1296 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1297 .owner = THIS_MODULE,
1298 },
1299 {
1300 .name = "DCDC4",
1301 .id = WM8350_DCDC_4,
1302 .ops = &wm8350_dcdc_ops,
1303 .irq = WM8350_IRQ_UV_DC4,
1304 .type = REGULATOR_VOLTAGE,
1305 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1306 .owner = THIS_MODULE,
1307 },
1308 {
1309 .name = "DCDC5",
1310 .id = WM8350_DCDC_5,
1311 .ops = &wm8350_dcdc2_5_ops,
1312 .irq = WM8350_IRQ_UV_DC5,
1313 .type = REGULATOR_VOLTAGE,
1314 .owner = THIS_MODULE,
1315 },
1316 {
1317 .name = "DCDC6",
1318 .id = WM8350_DCDC_6,
1319 .ops = &wm8350_dcdc_ops,
1320 .irq = WM8350_IRQ_UV_DC6,
1321 .type = REGULATOR_VOLTAGE,
1322 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1323 .owner = THIS_MODULE,
1324 },
1325 {
1326 .name = "LDO1",
1327 .id = WM8350_LDO_1,
1328 .ops = &wm8350_ldo_ops,
1329 .irq = WM8350_IRQ_UV_LDO1,
1330 .type = REGULATOR_VOLTAGE,
1331 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1332 .owner = THIS_MODULE,
1333 },
1334 {
1335 .name = "LDO2",
1336 .id = WM8350_LDO_2,
1337 .ops = &wm8350_ldo_ops,
1338 .irq = WM8350_IRQ_UV_LDO2,
1339 .type = REGULATOR_VOLTAGE,
1340 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1341 .owner = THIS_MODULE,
1342 },
1343 {
1344 .name = "LDO3",
1345 .id = WM8350_LDO_3,
1346 .ops = &wm8350_ldo_ops,
1347 .irq = WM8350_IRQ_UV_LDO3,
1348 .type = REGULATOR_VOLTAGE,
1349 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1350 .owner = THIS_MODULE,
1351 },
1352 {
1353 .name = "LDO4",
1354 .id = WM8350_LDO_4,
1355 .ops = &wm8350_ldo_ops,
1356 .irq = WM8350_IRQ_UV_LDO4,
1357 .type = REGULATOR_VOLTAGE,
1358 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1359 .owner = THIS_MODULE,
1360 },
1361 {
1362 .name = "ISINKA",
1363 .id = WM8350_ISINK_A,
1364 .ops = &wm8350_isink_ops,
1365 .irq = WM8350_IRQ_CS1,
1366 .type = REGULATOR_CURRENT,
1367 .owner = THIS_MODULE,
1368 },
1369 {
1370 .name = "ISINKB",
1371 .id = WM8350_ISINK_B,
1372 .ops = &wm8350_isink_ops,
1373 .irq = WM8350_IRQ_CS2,
1374 .type = REGULATOR_CURRENT,
1375 .owner = THIS_MODULE,
1376 },
1377};
1378
1379static irqreturn_t pmic_uv_handler(int irq, void *data)
1380{
1381 struct regulator_dev *rdev = (struct regulator_dev *)data;
1382 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1383
1384 mutex_lock(&rdev->mutex);
1385 if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1386 regulator_notifier_call_chain(rdev,
1387 REGULATOR_EVENT_REGULATION_OUT,
1388 wm8350);
1389 else
1390 regulator_notifier_call_chain(rdev,
1391 REGULATOR_EVENT_UNDER_VOLTAGE,
1392 wm8350);
1393 mutex_unlock(&rdev->mutex);
1394
1395 return IRQ_HANDLED;
1396}
1397
1398static int wm8350_regulator_probe(struct platform_device *pdev)
1399{
1400 struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1401 struct regulator_config config = { };
1402 struct regulator_dev *rdev;
1403 int ret;
1404 u16 val;
1405
1406 if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1407 return -ENODEV;
1408
1409 /* do any regulatior specific init */
1410 switch (pdev->id) {
1411 case WM8350_DCDC_1:
1412 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1413 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1414 break;
1415 case WM8350_DCDC_3:
1416 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1417 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1418 break;
1419 case WM8350_DCDC_4:
1420 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1421 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1422 break;
1423 case WM8350_DCDC_6:
1424 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1425 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1426 break;
1427 }
1428
1429 config.dev = &pdev->dev;
1430 config.init_data = pdev->dev.platform_data;
1431 config.driver_data = dev_get_drvdata(&pdev->dev);
1432
1433 /* register regulator */
1434 rdev = regulator_register(&wm8350_reg[pdev->id], &config);
1435 if (IS_ERR(rdev)) {
1436 dev_err(&pdev->dev, "failed to register %s\n",
1437 wm8350_reg[pdev->id].name);
1438 return PTR_ERR(rdev);
1439 }
1440
1441 /* register regulator IRQ */
1442 ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1443 pmic_uv_handler, 0, "UV", rdev);
1444 if (ret < 0) {
1445 regulator_unregister(rdev);
1446 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1447 wm8350_reg[pdev->id].name);
1448 return ret;
1449 }
1450
1451 return 0;
1452}
1453
1454static int wm8350_regulator_remove(struct platform_device *pdev)
1455{
1456 struct regulator_dev *rdev = platform_get_drvdata(pdev);
1457 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1458
1459 wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1460
1461 regulator_unregister(rdev);
1462
1463 return 0;
1464}
1465
1466int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1467 struct regulator_init_data *initdata)
1468{
1469 struct platform_device *pdev;
1470 int ret;
1471 if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1472 return -EINVAL;
1473
1474 if (wm8350->pmic.pdev[reg])
1475 return -EBUSY;
1476
1477 if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1478 reg > wm8350->pmic.max_dcdc)
1479 return -ENODEV;
1480 if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1481 reg > wm8350->pmic.max_isink)
1482 return -ENODEV;
1483
1484 pdev = platform_device_alloc("wm8350-regulator", reg);
1485 if (!pdev)
1486 return -ENOMEM;
1487
1488 wm8350->pmic.pdev[reg] = pdev;
1489
1490 initdata->driver_data = wm8350;
1491
1492 pdev->dev.platform_data = initdata;
1493 pdev->dev.parent = wm8350->dev;
1494 platform_set_drvdata(pdev, wm8350);
1495
1496 ret = platform_device_add(pdev);
1497
1498 if (ret != 0) {
1499 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1500 reg, ret);
1501 platform_device_put(pdev);
1502 wm8350->pmic.pdev[reg] = NULL;
1503 }
1504
1505 return ret;
1506}
1507EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1508
1509/**
1510 * wm8350_register_led - Register a WM8350 LED output
1511 *
1512 * @param wm8350 The WM8350 device to configure.
1513 * @param lednum LED device index to create.
1514 * @param dcdc The DCDC to use for the LED.
1515 * @param isink The ISINK to use for the LED.
1516 * @param pdata Configuration for the LED.
1517 *
1518 * The WM8350 supports the use of an ISINK together with a DCDC to
1519 * provide a power-efficient LED driver. This function registers the
1520 * regulators and instantiates the platform device for a LED. The
1521 * operating modes for the LED regulators must be configured using
1522 * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1523 * wm8350_dcdc_set_slot() prior to calling this function.
1524 */
1525int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1526 struct wm8350_led_platform_data *pdata)
1527{
1528 struct wm8350_led *led;
1529 struct platform_device *pdev;
1530 int ret;
1531
1532 if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1533 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1534 return -ENODEV;
1535 }
1536
1537 led = &wm8350->pmic.led[lednum];
1538
1539 if (led->pdev) {
1540 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1541 return -EINVAL;
1542 }
1543
1544 pdev = platform_device_alloc("wm8350-led", lednum);
1545 if (pdev == NULL) {
1546 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1547 return -ENOMEM;
1548 }
1549
1550 led->isink_consumer.dev_name = dev_name(&pdev->dev);
1551 led->isink_consumer.supply = "led_isink";
1552 led->isink_init.num_consumer_supplies = 1;
1553 led->isink_init.consumer_supplies = &led->isink_consumer;
1554 led->isink_init.constraints.min_uA = 0;
1555 led->isink_init.constraints.max_uA = pdata->max_uA;
1556 led->isink_init.constraints.valid_ops_mask
1557 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1558 led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1559 ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1560 if (ret != 0) {
1561 platform_device_put(pdev);
1562 return ret;
1563 }
1564
1565 led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1566 led->dcdc_consumer.supply = "led_vcc";
1567 led->dcdc_init.num_consumer_supplies = 1;
1568 led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1569 led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1570 led->dcdc_init.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
1571 ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1572 if (ret != 0) {
1573 platform_device_put(pdev);
1574 return ret;
1575 }
1576
1577 switch (isink) {
1578 case WM8350_ISINK_A:
1579 wm8350->pmic.isink_A_dcdc = dcdc;
1580 break;
1581 case WM8350_ISINK_B:
1582 wm8350->pmic.isink_B_dcdc = dcdc;
1583 break;
1584 }
1585
1586 pdev->dev.platform_data = pdata;
1587 pdev->dev.parent = wm8350->dev;
1588 ret = platform_device_add(pdev);
1589 if (ret != 0) {
1590 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1591 lednum, ret);
1592 platform_device_put(pdev);
1593 return ret;
1594 }
1595
1596 led->pdev = pdev;
1597
1598 return 0;
1599}
1600EXPORT_SYMBOL_GPL(wm8350_register_led);
1601
1602static struct platform_driver wm8350_regulator_driver = {
1603 .probe = wm8350_regulator_probe,
1604 .remove = wm8350_regulator_remove,
1605 .driver = {
1606 .name = "wm8350-regulator",
1607 },
1608};
1609
1610static int __init wm8350_regulator_init(void)
1611{
1612 return platform_driver_register(&wm8350_regulator_driver);
1613}
1614subsys_initcall(wm8350_regulator_init);
1615
1616static void __exit wm8350_regulator_exit(void)
1617{
1618 platform_driver_unregister(&wm8350_regulator_driver);
1619}
1620module_exit(wm8350_regulator_exit);
1621
1622/* Module information */
1623MODULE_AUTHOR("Liam Girdwood");
1624MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1625MODULE_LICENSE("GPL");
1626MODULE_ALIAS("platform:wm8350-regulator");