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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * rcar_du_kms.c -- R-Car Display Unit Mode Setting
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <drm/drm_atomic.h>
11#include <drm/drm_atomic_helper.h>
12#include <drm/drm_crtc.h>
13#include <drm/drm_device.h>
14#include <drm/drm_fb_cma_helper.h>
15#include <drm/drm_gem_cma_helper.h>
16#include <drm/drm_gem_framebuffer_helper.h>
17#include <drm/drm_probe_helper.h>
18#include <drm/drm_vblank.h>
19
20#include <linux/device.h>
21#include <linux/of_graph.h>
22#include <linux/of_platform.h>
23#include <linux/wait.h>
24
25#include "rcar_du_crtc.h"
26#include "rcar_du_drv.h"
27#include "rcar_du_encoder.h"
28#include "rcar_du_kms.h"
29#include "rcar_du_regs.h"
30#include "rcar_du_vsp.h"
31#include "rcar_du_writeback.h"
32
33/* -----------------------------------------------------------------------------
34 * Format helpers
35 */
36
37static const struct rcar_du_format_info rcar_du_format_infos[] = {
38 {
39 .fourcc = DRM_FORMAT_RGB565,
40 .v4l2 = V4L2_PIX_FMT_RGB565,
41 .bpp = 16,
42 .planes = 1,
43 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
44 .edf = PnDDCR4_EDF_NONE,
45 }, {
46 .fourcc = DRM_FORMAT_ARGB1555,
47 .v4l2 = V4L2_PIX_FMT_ARGB555,
48 .bpp = 16,
49 .planes = 1,
50 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
51 .edf = PnDDCR4_EDF_NONE,
52 }, {
53 .fourcc = DRM_FORMAT_XRGB1555,
54 .v4l2 = V4L2_PIX_FMT_XRGB555,
55 .bpp = 16,
56 .planes = 1,
57 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
58 .edf = PnDDCR4_EDF_NONE,
59 }, {
60 .fourcc = DRM_FORMAT_XRGB8888,
61 .v4l2 = V4L2_PIX_FMT_XBGR32,
62 .bpp = 32,
63 .planes = 1,
64 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
65 .edf = PnDDCR4_EDF_RGB888,
66 }, {
67 .fourcc = DRM_FORMAT_ARGB8888,
68 .v4l2 = V4L2_PIX_FMT_ABGR32,
69 .bpp = 32,
70 .planes = 1,
71 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
72 .edf = PnDDCR4_EDF_ARGB8888,
73 }, {
74 .fourcc = DRM_FORMAT_UYVY,
75 .v4l2 = V4L2_PIX_FMT_UYVY,
76 .bpp = 16,
77 .planes = 1,
78 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
79 .edf = PnDDCR4_EDF_NONE,
80 }, {
81 .fourcc = DRM_FORMAT_YUYV,
82 .v4l2 = V4L2_PIX_FMT_YUYV,
83 .bpp = 16,
84 .planes = 1,
85 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
86 .edf = PnDDCR4_EDF_NONE,
87 }, {
88 .fourcc = DRM_FORMAT_NV12,
89 .v4l2 = V4L2_PIX_FMT_NV12M,
90 .bpp = 12,
91 .planes = 2,
92 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
93 .edf = PnDDCR4_EDF_NONE,
94 }, {
95 .fourcc = DRM_FORMAT_NV21,
96 .v4l2 = V4L2_PIX_FMT_NV21M,
97 .bpp = 12,
98 .planes = 2,
99 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
100 .edf = PnDDCR4_EDF_NONE,
101 }, {
102 .fourcc = DRM_FORMAT_NV16,
103 .v4l2 = V4L2_PIX_FMT_NV16M,
104 .bpp = 16,
105 .planes = 2,
106 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
107 .edf = PnDDCR4_EDF_NONE,
108 },
109 /*
110 * The following formats are not supported on Gen2 and thus have no
111 * associated .pnmr or .edf settings.
112 */
113 {
114 .fourcc = DRM_FORMAT_RGB332,
115 .v4l2 = V4L2_PIX_FMT_RGB332,
116 .bpp = 8,
117 .planes = 1,
118 }, {
119 .fourcc = DRM_FORMAT_ARGB4444,
120 .v4l2 = V4L2_PIX_FMT_ARGB444,
121 .bpp = 16,
122 .planes = 1,
123 }, {
124 .fourcc = DRM_FORMAT_XRGB4444,
125 .v4l2 = V4L2_PIX_FMT_XRGB444,
126 .bpp = 16,
127 .planes = 1,
128 }, {
129 .fourcc = DRM_FORMAT_RGBA4444,
130 .v4l2 = V4L2_PIX_FMT_RGBA444,
131 .bpp = 16,
132 .planes = 1,
133 }, {
134 .fourcc = DRM_FORMAT_RGBX4444,
135 .v4l2 = V4L2_PIX_FMT_RGBX444,
136 .bpp = 16,
137 .planes = 1,
138 }, {
139 .fourcc = DRM_FORMAT_ABGR4444,
140 .v4l2 = V4L2_PIX_FMT_ABGR444,
141 .bpp = 16,
142 .planes = 1,
143 }, {
144 .fourcc = DRM_FORMAT_XBGR4444,
145 .v4l2 = V4L2_PIX_FMT_XBGR444,
146 .bpp = 16,
147 .planes = 1,
148 }, {
149 .fourcc = DRM_FORMAT_BGRA4444,
150 .v4l2 = V4L2_PIX_FMT_BGRA444,
151 .bpp = 16,
152 .planes = 1,
153 }, {
154 .fourcc = DRM_FORMAT_BGRX4444,
155 .v4l2 = V4L2_PIX_FMT_BGRX444,
156 .bpp = 16,
157 .planes = 1,
158 }, {
159 .fourcc = DRM_FORMAT_RGBA5551,
160 .v4l2 = V4L2_PIX_FMT_RGBA555,
161 .bpp = 16,
162 .planes = 1,
163 }, {
164 .fourcc = DRM_FORMAT_RGBX5551,
165 .v4l2 = V4L2_PIX_FMT_RGBX555,
166 .bpp = 16,
167 .planes = 1,
168 }, {
169 .fourcc = DRM_FORMAT_ABGR1555,
170 .v4l2 = V4L2_PIX_FMT_ABGR555,
171 .bpp = 16,
172 .planes = 1,
173 }, {
174 .fourcc = DRM_FORMAT_XBGR1555,
175 .v4l2 = V4L2_PIX_FMT_XBGR555,
176 .bpp = 16,
177 .planes = 1,
178 }, {
179 .fourcc = DRM_FORMAT_BGRA5551,
180 .v4l2 = V4L2_PIX_FMT_BGRA555,
181 .bpp = 16,
182 .planes = 1,
183 }, {
184 .fourcc = DRM_FORMAT_BGRX5551,
185 .v4l2 = V4L2_PIX_FMT_BGRX555,
186 .bpp = 16,
187 .planes = 1,
188 }, {
189 .fourcc = DRM_FORMAT_BGR888,
190 .v4l2 = V4L2_PIX_FMT_RGB24,
191 .bpp = 24,
192 .planes = 1,
193 }, {
194 .fourcc = DRM_FORMAT_RGB888,
195 .v4l2 = V4L2_PIX_FMT_BGR24,
196 .bpp = 24,
197 .planes = 1,
198 }, {
199 .fourcc = DRM_FORMAT_RGBA8888,
200 .v4l2 = V4L2_PIX_FMT_BGRA32,
201 .bpp = 32,
202 .planes = 1,
203 }, {
204 .fourcc = DRM_FORMAT_RGBX8888,
205 .v4l2 = V4L2_PIX_FMT_BGRX32,
206 .bpp = 32,
207 .planes = 1,
208 }, {
209 .fourcc = DRM_FORMAT_ABGR8888,
210 .v4l2 = V4L2_PIX_FMT_RGBA32,
211 .bpp = 32,
212 .planes = 1,
213 }, {
214 .fourcc = DRM_FORMAT_XBGR8888,
215 .v4l2 = V4L2_PIX_FMT_RGBX32,
216 .bpp = 32,
217 .planes = 1,
218 }, {
219 .fourcc = DRM_FORMAT_BGRA8888,
220 .v4l2 = V4L2_PIX_FMT_ARGB32,
221 .bpp = 32,
222 .planes = 1,
223 }, {
224 .fourcc = DRM_FORMAT_BGRX8888,
225 .v4l2 = V4L2_PIX_FMT_XRGB32,
226 .bpp = 32,
227 .planes = 1,
228 }, {
229 .fourcc = DRM_FORMAT_YVYU,
230 .v4l2 = V4L2_PIX_FMT_YVYU,
231 .bpp = 16,
232 .planes = 1,
233 }, {
234 .fourcc = DRM_FORMAT_NV61,
235 .v4l2 = V4L2_PIX_FMT_NV61M,
236 .bpp = 16,
237 .planes = 2,
238 }, {
239 .fourcc = DRM_FORMAT_YUV420,
240 .v4l2 = V4L2_PIX_FMT_YUV420M,
241 .bpp = 12,
242 .planes = 3,
243 }, {
244 .fourcc = DRM_FORMAT_YVU420,
245 .v4l2 = V4L2_PIX_FMT_YVU420M,
246 .bpp = 12,
247 .planes = 3,
248 }, {
249 .fourcc = DRM_FORMAT_YUV422,
250 .v4l2 = V4L2_PIX_FMT_YUV422M,
251 .bpp = 16,
252 .planes = 3,
253 }, {
254 .fourcc = DRM_FORMAT_YVU422,
255 .v4l2 = V4L2_PIX_FMT_YVU422M,
256 .bpp = 16,
257 .planes = 3,
258 }, {
259 .fourcc = DRM_FORMAT_YUV444,
260 .v4l2 = V4L2_PIX_FMT_YUV444M,
261 .bpp = 24,
262 .planes = 3,
263 }, {
264 .fourcc = DRM_FORMAT_YVU444,
265 .v4l2 = V4L2_PIX_FMT_YVU444M,
266 .bpp = 24,
267 .planes = 3,
268 },
269};
270
271const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
272{
273 unsigned int i;
274
275 for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
276 if (rcar_du_format_infos[i].fourcc == fourcc)
277 return &rcar_du_format_infos[i];
278 }
279
280 return NULL;
281}
282
283/* -----------------------------------------------------------------------------
284 * Frame buffer
285 */
286
287int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
288 struct drm_mode_create_dumb *args)
289{
290 struct rcar_du_device *rcdu = dev->dev_private;
291 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
292 unsigned int align;
293
294 /*
295 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
296 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
297 */
298 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
299 align = 128;
300 else
301 align = 16 * args->bpp / 8;
302
303 args->pitch = roundup(min_pitch, align);
304
305 return drm_gem_cma_dumb_create_internal(file, dev, args);
306}
307
308static struct drm_framebuffer *
309rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
310 const struct drm_mode_fb_cmd2 *mode_cmd)
311{
312 struct rcar_du_device *rcdu = dev->dev_private;
313 const struct rcar_du_format_info *format;
314 unsigned int max_pitch;
315 unsigned int align;
316 unsigned int i;
317
318 format = rcar_du_format_info(mode_cmd->pixel_format);
319 if (format == NULL) {
320 dev_dbg(dev->dev, "unsupported pixel format %08x\n",
321 mode_cmd->pixel_format);
322 return ERR_PTR(-EINVAL);
323 }
324
325 if (rcdu->info->gen < 3) {
326 /*
327 * On Gen2 the DU limits the pitch to 4095 pixels and requires
328 * buffers to be aligned to a 16 pixels boundary (or 128 bytes
329 * on some platforms).
330 */
331 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
332
333 max_pitch = 4095 * bpp;
334
335 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
336 align = 128;
337 else
338 align = 16 * bpp;
339 } else {
340 /*
341 * On Gen3 the memory interface is handled by the VSP that
342 * limits the pitch to 65535 bytes and has no alignment
343 * constraint.
344 */
345 max_pitch = 65535;
346 align = 1;
347 }
348
349 if (mode_cmd->pitches[0] & (align - 1) ||
350 mode_cmd->pitches[0] > max_pitch) {
351 dev_dbg(dev->dev, "invalid pitch value %u\n",
352 mode_cmd->pitches[0]);
353 return ERR_PTR(-EINVAL);
354 }
355
356 for (i = 1; i < format->planes; ++i) {
357 if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
358 dev_dbg(dev->dev,
359 "luma and chroma pitches do not match\n");
360 return ERR_PTR(-EINVAL);
361 }
362 }
363
364 return drm_gem_fb_create(dev, file_priv, mode_cmd);
365}
366
367/* -----------------------------------------------------------------------------
368 * Atomic Check and Update
369 */
370
371static int rcar_du_atomic_check(struct drm_device *dev,
372 struct drm_atomic_state *state)
373{
374 struct rcar_du_device *rcdu = dev->dev_private;
375 int ret;
376
377 ret = drm_atomic_helper_check(dev, state);
378 if (ret)
379 return ret;
380
381 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
382 return 0;
383
384 return rcar_du_atomic_check_planes(dev, state);
385}
386
387static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
388{
389 struct drm_device *dev = old_state->dev;
390 struct rcar_du_device *rcdu = dev->dev_private;
391 struct drm_crtc_state *crtc_state;
392 struct drm_crtc *crtc;
393 unsigned int i;
394
395 /*
396 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
397 * when starting the CRTCs.
398 */
399 rcdu->dpad1_source = -1;
400
401 for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
402 struct rcar_du_crtc_state *rcrtc_state =
403 to_rcar_crtc_state(crtc_state);
404 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
405
406 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
407 rcdu->dpad0_source = rcrtc->index;
408
409 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
410 rcdu->dpad1_source = rcrtc->index;
411 }
412
413 /* Apply the atomic update. */
414 drm_atomic_helper_commit_modeset_disables(dev, old_state);
415 drm_atomic_helper_commit_planes(dev, old_state,
416 DRM_PLANE_COMMIT_ACTIVE_ONLY);
417 drm_atomic_helper_commit_modeset_enables(dev, old_state);
418
419 drm_atomic_helper_commit_hw_done(old_state);
420 drm_atomic_helper_wait_for_flip_done(dev, old_state);
421
422 drm_atomic_helper_cleanup_planes(dev, old_state);
423}
424
425/* -----------------------------------------------------------------------------
426 * Initialization
427 */
428
429static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
430 .atomic_commit_tail = rcar_du_atomic_commit_tail,
431};
432
433static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
434 .fb_create = rcar_du_fb_create,
435 .atomic_check = rcar_du_atomic_check,
436 .atomic_commit = drm_atomic_helper_commit,
437};
438
439static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
440 enum rcar_du_output output,
441 struct of_endpoint *ep)
442{
443 struct device_node *entity;
444 int ret;
445
446 /* Locate the connected entity and initialize the encoder. */
447 entity = of_graph_get_remote_port_parent(ep->local_node);
448 if (!entity) {
449 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
450 ep->local_node);
451 return -ENODEV;
452 }
453
454 if (!of_device_is_available(entity)) {
455 dev_dbg(rcdu->dev,
456 "connected entity %pOF is disabled, skipping\n",
457 entity);
458 of_node_put(entity);
459 return -ENODEV;
460 }
461
462 ret = rcar_du_encoder_init(rcdu, output, entity);
463 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
464 dev_warn(rcdu->dev,
465 "failed to initialize encoder %pOF on output %u (%d), skipping\n",
466 entity, output, ret);
467
468 of_node_put(entity);
469
470 return ret;
471}
472
473static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
474{
475 struct device_node *np = rcdu->dev->of_node;
476 struct device_node *ep_node;
477 unsigned int num_encoders = 0;
478
479 /*
480 * Iterate over the endpoints and create one encoder for each output
481 * pipeline.
482 */
483 for_each_endpoint_of_node(np, ep_node) {
484 enum rcar_du_output output;
485 struct of_endpoint ep;
486 unsigned int i;
487 int ret;
488
489 ret = of_graph_parse_endpoint(ep_node, &ep);
490 if (ret < 0) {
491 of_node_put(ep_node);
492 return ret;
493 }
494
495 /* Find the output route corresponding to the port number. */
496 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
497 if (rcdu->info->routes[i].possible_crtcs &&
498 rcdu->info->routes[i].port == ep.port) {
499 output = i;
500 break;
501 }
502 }
503
504 if (i == RCAR_DU_OUTPUT_MAX) {
505 dev_warn(rcdu->dev,
506 "port %u references unexisting output, skipping\n",
507 ep.port);
508 continue;
509 }
510
511 /* Process the output pipeline. */
512 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
513 if (ret < 0) {
514 if (ret == -EPROBE_DEFER) {
515 of_node_put(ep_node);
516 return ret;
517 }
518
519 continue;
520 }
521
522 num_encoders++;
523 }
524
525 return num_encoders;
526}
527
528static int rcar_du_properties_init(struct rcar_du_device *rcdu)
529{
530 /*
531 * The color key is expressed as an RGB888 triplet stored in a 32-bit
532 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
533 * or enable source color keying (1).
534 */
535 rcdu->props.colorkey =
536 drm_property_create_range(rcdu->ddev, 0, "colorkey",
537 0, 0x01ffffff);
538 if (rcdu->props.colorkey == NULL)
539 return -ENOMEM;
540
541 return 0;
542}
543
544static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
545{
546 const struct device_node *np = rcdu->dev->of_node;
547 const char *vsps_prop_name = "renesas,vsps";
548 struct of_phandle_args args;
549 struct {
550 struct device_node *np;
551 unsigned int crtcs_mask;
552 } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
553 unsigned int vsps_count = 0;
554 unsigned int cells;
555 unsigned int i;
556 int ret;
557
558 /*
559 * First parse the DT vsps property to populate the list of VSPs. Each
560 * entry contains a pointer to the VSP DT node and a bitmask of the
561 * connected DU CRTCs.
562 */
563 ret = of_property_count_u32_elems(np, vsps_prop_name);
564 if (ret < 0) {
565 /* Backward compatibility with old DTBs. */
566 vsps_prop_name = "vsps";
567 ret = of_property_count_u32_elems(np, vsps_prop_name);
568 }
569 cells = ret / rcdu->num_crtcs - 1;
570 if (cells > 1)
571 return -EINVAL;
572
573 for (i = 0; i < rcdu->num_crtcs; ++i) {
574 unsigned int j;
575
576 ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
577 cells, i, &args);
578 if (ret < 0)
579 goto error;
580
581 /*
582 * Add the VSP to the list or update the corresponding existing
583 * entry if the VSP has already been added.
584 */
585 for (j = 0; j < vsps_count; ++j) {
586 if (vsps[j].np == args.np)
587 break;
588 }
589
590 if (j < vsps_count)
591 of_node_put(args.np);
592 else
593 vsps[vsps_count++].np = args.np;
594
595 vsps[j].crtcs_mask |= BIT(i);
596
597 /*
598 * Store the VSP pointer and pipe index in the CRTC. If the
599 * second cell of the 'renesas,vsps' specifier isn't present,
600 * default to 0 to remain compatible with older DT bindings.
601 */
602 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
603 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
604 }
605
606 /*
607 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
608 * computed previously.
609 */
610 for (i = 0; i < vsps_count; ++i) {
611 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
612
613 vsp->index = i;
614 vsp->dev = rcdu;
615
616 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
617 if (ret < 0)
618 goto error;
619 }
620
621 return 0;
622
623error:
624 for (i = 0; i < ARRAY_SIZE(vsps); ++i)
625 of_node_put(vsps[i].np);
626
627 return ret;
628}
629
630static int rcar_du_cmm_init(struct rcar_du_device *rcdu)
631{
632 const struct device_node *np = rcdu->dev->of_node;
633 unsigned int i;
634 int cells;
635
636 cells = of_property_count_u32_elems(np, "renesas,cmms");
637 if (cells == -EINVAL)
638 return 0;
639
640 if (cells > rcdu->num_crtcs) {
641 dev_err(rcdu->dev,
642 "Invalid number of entries in 'renesas,cmms'\n");
643 return -EINVAL;
644 }
645
646 for (i = 0; i < cells; ++i) {
647 struct platform_device *pdev;
648 struct device_link *link;
649 struct device_node *cmm;
650 int ret;
651
652 cmm = of_parse_phandle(np, "renesas,cmms", i);
653 if (IS_ERR(cmm)) {
654 dev_err(rcdu->dev,
655 "Failed to parse 'renesas,cmms' property\n");
656 return PTR_ERR(cmm);
657 }
658
659 if (!of_device_is_available(cmm)) {
660 /* It's fine to have a phandle to a non-enabled CMM. */
661 of_node_put(cmm);
662 continue;
663 }
664
665 pdev = of_find_device_by_node(cmm);
666 if (IS_ERR(pdev)) {
667 dev_err(rcdu->dev, "No device found for CMM%u\n", i);
668 of_node_put(cmm);
669 return PTR_ERR(pdev);
670 }
671
672 of_node_put(cmm);
673
674 /*
675 * -ENODEV is used to report that the CMM config option is
676 * disabled: return 0 and let the DU continue probing.
677 */
678 ret = rcar_cmm_init(pdev);
679 if (ret)
680 return ret == -ENODEV ? 0 : ret;
681
682 /*
683 * Enforce suspend/resume ordering by making the CMM a provider
684 * of the DU: CMM is suspended after and resumed before the DU.
685 */
686 link = device_link_add(rcdu->dev, &pdev->dev, DL_FLAG_STATELESS);
687 if (!link) {
688 dev_err(rcdu->dev,
689 "Failed to create device link to CMM%u\n", i);
690 return -EINVAL;
691 }
692
693 rcdu->cmms[i] = pdev;
694 }
695
696 return 0;
697}
698
699int rcar_du_modeset_init(struct rcar_du_device *rcdu)
700{
701 static const unsigned int mmio_offsets[] = {
702 DU0_REG_OFFSET, DU2_REG_OFFSET
703 };
704
705 struct drm_device *dev = rcdu->ddev;
706 struct drm_encoder *encoder;
707 unsigned int dpad0_sources;
708 unsigned int num_encoders;
709 unsigned int num_groups;
710 unsigned int swindex;
711 unsigned int hwindex;
712 unsigned int i;
713 int ret;
714
715 ret = drmm_mode_config_init(dev);
716 if (ret)
717 return ret;
718
719 dev->mode_config.min_width = 0;
720 dev->mode_config.min_height = 0;
721 dev->mode_config.normalize_zpos = true;
722 dev->mode_config.funcs = &rcar_du_mode_config_funcs;
723 dev->mode_config.helper_private = &rcar_du_mode_config_helper;
724
725 if (rcdu->info->gen < 3) {
726 dev->mode_config.max_width = 4095;
727 dev->mode_config.max_height = 2047;
728 } else {
729 /*
730 * The Gen3 DU uses the VSP1 for memory access, and is limited
731 * to frame sizes of 8190x8190.
732 */
733 dev->mode_config.max_width = 8190;
734 dev->mode_config.max_height = 8190;
735 }
736
737 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
738
739 ret = rcar_du_properties_init(rcdu);
740 if (ret < 0)
741 return ret;
742
743 /*
744 * Initialize vertical blanking interrupts handling. Start with vblank
745 * disabled for all CRTCs.
746 */
747 ret = drm_vblank_init(dev, rcdu->num_crtcs);
748 if (ret < 0)
749 return ret;
750
751 /* Initialize the groups. */
752 num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
753
754 for (i = 0; i < num_groups; ++i) {
755 struct rcar_du_group *rgrp = &rcdu->groups[i];
756
757 mutex_init(&rgrp->lock);
758
759 rgrp->dev = rcdu;
760 rgrp->mmio_offset = mmio_offsets[i];
761 rgrp->index = i;
762 /* Extract the channel mask for this group only. */
763 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
764 & GENMASK(1, 0);
765 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
766
767 /*
768 * If we have more than one CRTCs in this group pre-associate
769 * the low-order planes with CRTC 0 and the high-order planes
770 * with CRTC 1 to minimize flicker occurring when the
771 * association is changed.
772 */
773 rgrp->dptsr_planes = rgrp->num_crtcs > 1
774 ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
775 : 0;
776
777 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
778 ret = rcar_du_planes_init(rgrp);
779 if (ret < 0)
780 return ret;
781 }
782 }
783
784 /* Initialize the compositors. */
785 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
786 ret = rcar_du_vsps_init(rcdu);
787 if (ret < 0)
788 return ret;
789 }
790
791 /* Initialize the Color Management Modules. */
792 ret = rcar_du_cmm_init(rcdu);
793 if (ret)
794 return ret;
795
796 /* Create the CRTCs. */
797 for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
798 struct rcar_du_group *rgrp;
799
800 /* Skip unpopulated DU channels. */
801 if (!(rcdu->info->channels_mask & BIT(hwindex)))
802 continue;
803
804 rgrp = &rcdu->groups[hwindex / 2];
805
806 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
807 if (ret < 0)
808 return ret;
809 }
810
811 /* Initialize the encoders. */
812 ret = rcar_du_encoders_init(rcdu);
813 if (ret < 0)
814 return ret;
815
816 if (ret == 0) {
817 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
818 return -EINVAL;
819 }
820
821 num_encoders = ret;
822
823 /*
824 * Set the possible CRTCs and possible clones. There's always at least
825 * one way for all encoders to clone each other, set all bits in the
826 * possible clones field.
827 */
828 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
829 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
830 const struct rcar_du_output_routing *route =
831 &rcdu->info->routes[renc->output];
832
833 encoder->possible_crtcs = route->possible_crtcs;
834 encoder->possible_clones = (1 << num_encoders) - 1;
835 }
836
837 /* Create the writeback connectors. */
838 if (rcdu->info->gen >= 3) {
839 for (i = 0; i < rcdu->num_crtcs; ++i) {
840 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
841
842 ret = rcar_du_writeback_init(rcdu, rcrtc);
843 if (ret < 0)
844 return ret;
845 }
846 }
847
848 /*
849 * Initialize the default DPAD0 source to the index of the first DU
850 * channel that can be connected to DPAD0. The exact value doesn't
851 * matter as it should be overwritten by mode setting for the RGB
852 * output, but it is nonetheless required to ensure a valid initial
853 * hardware configuration on Gen3 where DU0 can't always be connected to
854 * DPAD0.
855 */
856 dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
857 rcdu->dpad0_source = ffs(dpad0_sources) - 1;
858
859 drm_mode_config_reset(dev);
860
861 drm_kms_helper_poll_init(dev);
862
863 return 0;
864}