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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) STMicroelectronics SA 2017
5 *
6 * Modified by Philippe Cornu <philippe.cornu@st.com>
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
9 */
10
11#include <linux/clk.h>
12#include <linux/component.h>
13#include <linux/debugfs.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <video/mipi_display.h>
21
22#include <drm/bridge/dw_mipi_dsi.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_bridge.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_mipi_dsi.h>
27#include <drm/drm_modes.h>
28#include <drm/drm_of.h>
29#include <drm/drm_print.h>
30
31#define HWVER_131 0x31333100 /* IP version 1.31 */
32
33#define DSI_VERSION 0x00
34#define VERSION GENMASK(31, 8)
35
36#define DSI_PWR_UP 0x04
37#define RESET 0
38#define POWERUP BIT(0)
39
40#define DSI_CLKMGR_CFG 0x08
41#define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
42#define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
43
44#define DSI_DPI_VCID 0x0c
45#define DPI_VCID(vcid) ((vcid) & 0x3)
46
47#define DSI_DPI_COLOR_CODING 0x10
48#define LOOSELY18_EN BIT(8)
49#define DPI_COLOR_CODING_16BIT_1 0x0
50#define DPI_COLOR_CODING_16BIT_2 0x1
51#define DPI_COLOR_CODING_16BIT_3 0x2
52#define DPI_COLOR_CODING_18BIT_1 0x3
53#define DPI_COLOR_CODING_18BIT_2 0x4
54#define DPI_COLOR_CODING_24BIT 0x5
55
56#define DSI_DPI_CFG_POL 0x14
57#define COLORM_ACTIVE_LOW BIT(4)
58#define SHUTD_ACTIVE_LOW BIT(3)
59#define HSYNC_ACTIVE_LOW BIT(2)
60#define VSYNC_ACTIVE_LOW BIT(1)
61#define DATAEN_ACTIVE_LOW BIT(0)
62
63#define DSI_DPI_LP_CMD_TIM 0x18
64#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
65#define INVACT_LPCMD_TIME(p) ((p) & 0xff)
66
67#define DSI_DBI_VCID 0x1c
68#define DSI_DBI_CFG 0x20
69#define DSI_DBI_PARTITIONING_EN 0x24
70#define DSI_DBI_CMDSIZE 0x28
71
72#define DSI_PCKHDL_CFG 0x2c
73#define CRC_RX_EN BIT(4)
74#define ECC_RX_EN BIT(3)
75#define BTA_EN BIT(2)
76#define EOTP_RX_EN BIT(1)
77#define EOTP_TX_EN BIT(0)
78
79#define DSI_GEN_VCID 0x30
80
81#define DSI_MODE_CFG 0x34
82#define ENABLE_VIDEO_MODE 0
83#define ENABLE_CMD_MODE BIT(0)
84
85#define DSI_VID_MODE_CFG 0x38
86#define ENABLE_LOW_POWER (0x3f << 8)
87#define ENABLE_LOW_POWER_MASK (0x3f << 8)
88#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
89#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
90#define VID_MODE_TYPE_BURST 0x2
91#define VID_MODE_TYPE_MASK 0x3
92#define VID_MODE_VPG_ENABLE BIT(16)
93#define VID_MODE_VPG_HORIZONTAL BIT(24)
94
95#define DSI_VID_PKT_SIZE 0x3c
96#define VID_PKT_SIZE(p) ((p) & 0x3fff)
97
98#define DSI_VID_NUM_CHUNKS 0x40
99#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
100
101#define DSI_VID_NULL_SIZE 0x44
102#define VID_NULL_SIZE(b) ((b) & 0x1fff)
103
104#define DSI_VID_HSA_TIME 0x48
105#define DSI_VID_HBP_TIME 0x4c
106#define DSI_VID_HLINE_TIME 0x50
107#define DSI_VID_VSA_LINES 0x54
108#define DSI_VID_VBP_LINES 0x58
109#define DSI_VID_VFP_LINES 0x5c
110#define DSI_VID_VACTIVE_LINES 0x60
111#define DSI_EDPI_CMD_SIZE 0x64
112
113#define DSI_CMD_MODE_CFG 0x68
114#define MAX_RD_PKT_SIZE_LP BIT(24)
115#define DCS_LW_TX_LP BIT(19)
116#define DCS_SR_0P_TX_LP BIT(18)
117#define DCS_SW_1P_TX_LP BIT(17)
118#define DCS_SW_0P_TX_LP BIT(16)
119#define GEN_LW_TX_LP BIT(14)
120#define GEN_SR_2P_TX_LP BIT(13)
121#define GEN_SR_1P_TX_LP BIT(12)
122#define GEN_SR_0P_TX_LP BIT(11)
123#define GEN_SW_2P_TX_LP BIT(10)
124#define GEN_SW_1P_TX_LP BIT(9)
125#define GEN_SW_0P_TX_LP BIT(8)
126#define ACK_RQST_EN BIT(1)
127#define TEAR_FX_EN BIT(0)
128
129#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
130 DCS_LW_TX_LP | \
131 DCS_SR_0P_TX_LP | \
132 DCS_SW_1P_TX_LP | \
133 DCS_SW_0P_TX_LP | \
134 GEN_LW_TX_LP | \
135 GEN_SR_2P_TX_LP | \
136 GEN_SR_1P_TX_LP | \
137 GEN_SR_0P_TX_LP | \
138 GEN_SW_2P_TX_LP | \
139 GEN_SW_1P_TX_LP | \
140 GEN_SW_0P_TX_LP)
141
142#define DSI_GEN_HDR 0x6c
143#define DSI_GEN_PLD_DATA 0x70
144
145#define DSI_CMD_PKT_STATUS 0x74
146#define GEN_RD_CMD_BUSY BIT(6)
147#define GEN_PLD_R_FULL BIT(5)
148#define GEN_PLD_R_EMPTY BIT(4)
149#define GEN_PLD_W_FULL BIT(3)
150#define GEN_PLD_W_EMPTY BIT(2)
151#define GEN_CMD_FULL BIT(1)
152#define GEN_CMD_EMPTY BIT(0)
153
154#define DSI_TO_CNT_CFG 0x78
155#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
156#define LPRX_TO_CNT(p) ((p) & 0xffff)
157
158#define DSI_HS_RD_TO_CNT 0x7c
159#define DSI_LP_RD_TO_CNT 0x80
160#define DSI_HS_WR_TO_CNT 0x84
161#define DSI_LP_WR_TO_CNT 0x88
162#define DSI_BTA_TO_CNT 0x8c
163
164#define DSI_LPCLK_CTRL 0x94
165#define AUTO_CLKLANE_CTRL BIT(1)
166#define PHY_TXREQUESTCLKHS BIT(0)
167
168#define DSI_PHY_TMR_LPCLK_CFG 0x98
169#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
170#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
171
172#define DSI_PHY_TMR_CFG 0x9c
173#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
174#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
175#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
176#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
177#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
178
179#define DSI_PHY_RSTZ 0xa0
180#define PHY_DISFORCEPLL 0
181#define PHY_ENFORCEPLL BIT(3)
182#define PHY_DISABLECLK 0
183#define PHY_ENABLECLK BIT(2)
184#define PHY_RSTZ 0
185#define PHY_UNRSTZ BIT(1)
186#define PHY_SHUTDOWNZ 0
187#define PHY_UNSHUTDOWNZ BIT(0)
188
189#define DSI_PHY_IF_CFG 0xa4
190#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
191#define N_LANES(n) (((n) - 1) & 0x3)
192
193#define DSI_PHY_ULPS_CTRL 0xa8
194#define DSI_PHY_TX_TRIGGERS 0xac
195
196#define DSI_PHY_STATUS 0xb0
197#define PHY_STOP_STATE_CLK_LANE BIT(2)
198#define PHY_LOCK BIT(0)
199
200#define DSI_PHY_TST_CTRL0 0xb4
201#define PHY_TESTCLK BIT(1)
202#define PHY_UNTESTCLK 0
203#define PHY_TESTCLR BIT(0)
204#define PHY_UNTESTCLR 0
205
206#define DSI_PHY_TST_CTRL1 0xb8
207#define PHY_TESTEN BIT(16)
208#define PHY_UNTESTEN 0
209#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
210#define PHY_TESTDIN(n) ((n) & 0xff)
211
212#define DSI_INT_ST0 0xbc
213#define DSI_INT_ST1 0xc0
214#define DSI_INT_MSK0 0xc4
215#define DSI_INT_MSK1 0xc8
216
217#define DSI_PHY_TMR_RD_CFG 0xf4
218#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
219
220#define PHY_STATUS_TIMEOUT_US 10000
221#define CMD_PKT_STATUS_TIMEOUT_US 20000
222
223struct dw_mipi_dsi {
224 struct drm_bridge bridge;
225 struct mipi_dsi_host dsi_host;
226 struct drm_bridge *panel_bridge;
227 struct device *dev;
228 void __iomem *base;
229
230 struct clk *pclk;
231
232 unsigned int lane_mbps; /* per lane */
233 u32 channel;
234 u32 lanes;
235 u32 format;
236 unsigned long mode_flags;
237
238#ifdef CONFIG_DEBUG_FS
239 struct dentry *debugfs;
240
241 bool vpg;
242 bool vpg_horizontal;
243#endif /* CONFIG_DEBUG_FS */
244
245 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
246 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
247
248 const struct dw_mipi_dsi_plat_data *plat_data;
249};
250
251/*
252 * Check if either a link to a master or slave is present
253 */
254static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
255{
256 return dsi->slave || dsi->master;
257}
258
259/*
260 * The controller should generate 2 frames before
261 * preparing the peripheral.
262 */
263static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
264{
265 int refresh, two_frames;
266
267 refresh = drm_mode_vrefresh(mode);
268 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
269 msleep(two_frames);
270}
271
272static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
273{
274 return container_of(host, struct dw_mipi_dsi, dsi_host);
275}
276
277static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
278{
279 return container_of(bridge, struct dw_mipi_dsi, bridge);
280}
281
282static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
283{
284 writel(val, dsi->base + reg);
285}
286
287static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
288{
289 return readl(dsi->base + reg);
290}
291
292static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
293 struct mipi_dsi_device *device)
294{
295 struct dw_mipi_dsi *dsi = host_to_dsi(host);
296 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
297 struct drm_bridge *bridge;
298 struct drm_panel *panel;
299 int ret;
300
301 if (device->lanes > dsi->plat_data->max_data_lanes) {
302 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
303 device->lanes);
304 return -EINVAL;
305 }
306
307 dsi->lanes = device->lanes;
308 dsi->channel = device->channel;
309 dsi->format = device->format;
310 dsi->mode_flags = device->mode_flags;
311
312 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
313 &panel, &bridge);
314 if (ret)
315 return ret;
316
317 if (panel) {
318 bridge = drm_panel_bridge_add_typed(panel,
319 DRM_MODE_CONNECTOR_DSI);
320 if (IS_ERR(bridge))
321 return PTR_ERR(bridge);
322 }
323
324 dsi->panel_bridge = bridge;
325
326 drm_bridge_add(&dsi->bridge);
327
328 if (pdata->host_ops && pdata->host_ops->attach) {
329 ret = pdata->host_ops->attach(pdata->priv_data, device);
330 if (ret < 0)
331 return ret;
332 }
333
334 return 0;
335}
336
337static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
338 struct mipi_dsi_device *device)
339{
340 struct dw_mipi_dsi *dsi = host_to_dsi(host);
341 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
342 int ret;
343
344 if (pdata->host_ops && pdata->host_ops->detach) {
345 ret = pdata->host_ops->detach(pdata->priv_data, device);
346 if (ret < 0)
347 return ret;
348 }
349
350 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
351
352 drm_bridge_remove(&dsi->bridge);
353
354 return 0;
355}
356
357static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
358 const struct mipi_dsi_msg *msg)
359{
360 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
361 u32 val = 0;
362
363 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
364 val |= ACK_RQST_EN;
365 if (lpm)
366 val |= CMD_MODE_ALL_LP;
367
368 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
369 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
370}
371
372static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
373{
374 int ret;
375 u32 val, mask;
376
377 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
378 val, !(val & GEN_CMD_FULL), 1000,
379 CMD_PKT_STATUS_TIMEOUT_US);
380 if (ret) {
381 dev_err(dsi->dev, "failed to get available command FIFO\n");
382 return ret;
383 }
384
385 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
386
387 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
388 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
389 val, (val & mask) == mask,
390 1000, CMD_PKT_STATUS_TIMEOUT_US);
391 if (ret) {
392 dev_err(dsi->dev, "failed to write command FIFO\n");
393 return ret;
394 }
395
396 return 0;
397}
398
399static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
400 const struct mipi_dsi_packet *packet)
401{
402 const u8 *tx_buf = packet->payload;
403 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
404 __le32 word;
405 u32 val;
406
407 while (len) {
408 if (len < pld_data_bytes) {
409 word = 0;
410 memcpy(&word, tx_buf, len);
411 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
412 len = 0;
413 } else {
414 memcpy(&word, tx_buf, pld_data_bytes);
415 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
416 tx_buf += pld_data_bytes;
417 len -= pld_data_bytes;
418 }
419
420 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
421 val, !(val & GEN_PLD_W_FULL), 1000,
422 CMD_PKT_STATUS_TIMEOUT_US);
423 if (ret) {
424 dev_err(dsi->dev,
425 "failed to get available write payload FIFO\n");
426 return ret;
427 }
428 }
429
430 word = 0;
431 memcpy(&word, packet->header, sizeof(packet->header));
432 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
433}
434
435static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
436 const struct mipi_dsi_msg *msg)
437{
438 int i, j, ret, len = msg->rx_len;
439 u8 *buf = msg->rx_buf;
440 u32 val;
441
442 /* Wait end of the read operation */
443 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
444 val, !(val & GEN_RD_CMD_BUSY),
445 1000, CMD_PKT_STATUS_TIMEOUT_US);
446 if (ret) {
447 dev_err(dsi->dev, "Timeout during read operation\n");
448 return ret;
449 }
450
451 for (i = 0; i < len; i += 4) {
452 /* Read fifo must not be empty before all bytes are read */
453 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
454 val, !(val & GEN_PLD_R_EMPTY),
455 1000, CMD_PKT_STATUS_TIMEOUT_US);
456 if (ret) {
457 dev_err(dsi->dev, "Read payload FIFO is empty\n");
458 return ret;
459 }
460
461 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
462 for (j = 0; j < 4 && j + i < len; j++)
463 buf[i + j] = val >> (8 * j);
464 }
465
466 return ret;
467}
468
469static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
470 const struct mipi_dsi_msg *msg)
471{
472 struct dw_mipi_dsi *dsi = host_to_dsi(host);
473 struct mipi_dsi_packet packet;
474 int ret, nb_bytes;
475
476 ret = mipi_dsi_create_packet(&packet, msg);
477 if (ret) {
478 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
479 return ret;
480 }
481
482 dw_mipi_message_config(dsi, msg);
483 if (dsi->slave)
484 dw_mipi_message_config(dsi->slave, msg);
485
486 ret = dw_mipi_dsi_write(dsi, &packet);
487 if (ret)
488 return ret;
489 if (dsi->slave) {
490 ret = dw_mipi_dsi_write(dsi->slave, &packet);
491 if (ret)
492 return ret;
493 }
494
495 if (msg->rx_buf && msg->rx_len) {
496 ret = dw_mipi_dsi_read(dsi, msg);
497 if (ret)
498 return ret;
499 nb_bytes = msg->rx_len;
500 } else {
501 nb_bytes = packet.size;
502 }
503
504 return nb_bytes;
505}
506
507static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
508 .attach = dw_mipi_dsi_host_attach,
509 .detach = dw_mipi_dsi_host_detach,
510 .transfer = dw_mipi_dsi_host_transfer,
511};
512
513static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
514{
515 u32 val;
516
517 /*
518 * TODO dw drv improvements
519 * enabling low power is panel-dependent, we should use the
520 * panel configuration here...
521 */
522 val = ENABLE_LOW_POWER;
523
524 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
525 val |= VID_MODE_TYPE_BURST;
526 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
527 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
528 else
529 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
530
531#ifdef CONFIG_DEBUG_FS
532 if (dsi->vpg) {
533 val |= VID_MODE_VPG_ENABLE;
534 val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
535 }
536#endif /* CONFIG_DEBUG_FS */
537
538 dsi_write(dsi, DSI_VID_MODE_CFG, val);
539}
540
541static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
542 unsigned long mode_flags)
543{
544 dsi_write(dsi, DSI_PWR_UP, RESET);
545
546 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
547 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
548 dw_mipi_dsi_video_mode_config(dsi);
549 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
550 } else {
551 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
552 }
553
554 dsi_write(dsi, DSI_PWR_UP, POWERUP);
555}
556
557static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
558{
559 dsi_write(dsi, DSI_PWR_UP, RESET);
560 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
561}
562
563static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
564{
565 /*
566 * The maximum permitted escape clock is 20MHz and it is derived from
567 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
568 *
569 * (lane_mbps >> 3) / esc_clk_division < 20
570 * which is:
571 * (lane_mbps >> 3) / 20 > esc_clk_division
572 */
573 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
574
575 dsi_write(dsi, DSI_PWR_UP, RESET);
576
577 /*
578 * TODO dw drv improvements
579 * timeout clock division should be computed with the
580 * high speed transmission counter timeout and byte lane...
581 */
582 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
583 TX_ESC_CLK_DIVISION(esc_clk_division));
584}
585
586static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
587 const struct drm_display_mode *mode)
588{
589 u32 val = 0, color = 0;
590
591 switch (dsi->format) {
592 case MIPI_DSI_FMT_RGB888:
593 color = DPI_COLOR_CODING_24BIT;
594 break;
595 case MIPI_DSI_FMT_RGB666:
596 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
597 break;
598 case MIPI_DSI_FMT_RGB666_PACKED:
599 color = DPI_COLOR_CODING_18BIT_1;
600 break;
601 case MIPI_DSI_FMT_RGB565:
602 color = DPI_COLOR_CODING_16BIT_1;
603 break;
604 }
605
606 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
607 val |= VSYNC_ACTIVE_LOW;
608 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
609 val |= HSYNC_ACTIVE_LOW;
610
611 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
612 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
613 dsi_write(dsi, DSI_DPI_CFG_POL, val);
614 /*
615 * TODO dw drv improvements
616 * largest packet sizes during hfp or during vsa/vpb/vfp
617 * should be computed according to byte lane, lane number and only
618 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
619 */
620 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
621 | INVACT_LPCMD_TIME(4));
622}
623
624static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
625{
626 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
627}
628
629static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
630 const struct drm_display_mode *mode)
631{
632 /*
633 * TODO dw drv improvements
634 * only burst mode is supported here. For non-burst video modes,
635 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
636 * DSI_VNPCR.NPSIZE... especially because this driver supports
637 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
638 */
639
640 dsi_write(dsi, DSI_VID_PKT_SIZE,
641 dw_mipi_is_dual_mode(dsi) ?
642 VID_PKT_SIZE(mode->hdisplay / 2) :
643 VID_PKT_SIZE(mode->hdisplay));
644}
645
646static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
647{
648 /*
649 * TODO dw drv improvements
650 * compute high speed transmission counter timeout according
651 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
652 */
653 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
654 /*
655 * TODO dw drv improvements
656 * the Bus-Turn-Around Timeout Counter should be computed
657 * according to byte lane...
658 */
659 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
660 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
661}
662
663/* Get lane byte clock cycles. */
664static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
665 const struct drm_display_mode *mode,
666 u32 hcomponent)
667{
668 u32 frac, lbcc;
669
670 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
671
672 frac = lbcc % mode->clock;
673 lbcc = lbcc / mode->clock;
674 if (frac)
675 lbcc++;
676
677 return lbcc;
678}
679
680static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
681 const struct drm_display_mode *mode)
682{
683 u32 htotal, hsa, hbp, lbcc;
684
685 htotal = mode->htotal;
686 hsa = mode->hsync_end - mode->hsync_start;
687 hbp = mode->htotal - mode->hsync_end;
688
689 /*
690 * TODO dw drv improvements
691 * computations below may be improved...
692 */
693 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
694 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
695
696 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
697 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
698
699 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
700 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
701}
702
703static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
704 const struct drm_display_mode *mode)
705{
706 u32 vactive, vsa, vfp, vbp;
707
708 vactive = mode->vdisplay;
709 vsa = mode->vsync_end - mode->vsync_start;
710 vfp = mode->vsync_start - mode->vdisplay;
711 vbp = mode->vtotal - mode->vsync_end;
712
713 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
714 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
715 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
716 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
717}
718
719static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
720{
721 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
722 struct dw_mipi_dsi_dphy_timing timing;
723 u32 hw_version;
724 int ret;
725
726 ret = phy_ops->get_timing(dsi->plat_data->priv_data,
727 dsi->lane_mbps, &timing);
728 if (ret)
729 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
730
731 /*
732 * TODO dw drv improvements
733 * data & clock lane timers should be computed according to panel
734 * blankings and to the automatic clock lane control mode...
735 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
736 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
737 */
738
739 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
740
741 if (hw_version >= HWVER_131) {
742 dsi_write(dsi, DSI_PHY_TMR_CFG,
743 PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
744 PHY_LP2HS_TIME_V131(timing.data_lp2hs));
745 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
746 } else {
747 dsi_write(dsi, DSI_PHY_TMR_CFG,
748 PHY_HS2LP_TIME(timing.data_hs2lp) |
749 PHY_LP2HS_TIME(timing.data_lp2hs) |
750 MAX_RD_TIME(10000));
751 }
752
753 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
754 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
755 PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
756}
757
758static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
759{
760 /*
761 * TODO dw drv improvements
762 * stop wait time should be the maximum between host dsi
763 * and panel stop wait times
764 */
765 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
766 N_LANES(dsi->lanes));
767}
768
769static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
770{
771 /* Clear PHY state */
772 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
773 | PHY_RSTZ | PHY_SHUTDOWNZ);
774 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
775 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
776 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
777}
778
779static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
780{
781 u32 val;
782 int ret;
783
784 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
785 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
786
787 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
788 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
789 if (ret)
790 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
791
792 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
793 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
794 PHY_STATUS_TIMEOUT_US);
795 if (ret)
796 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
797}
798
799static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
800{
801 dsi_read(dsi, DSI_INT_ST0);
802 dsi_read(dsi, DSI_INT_ST1);
803 dsi_write(dsi, DSI_INT_MSK0, 0);
804 dsi_write(dsi, DSI_INT_MSK1, 0);
805}
806
807static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
808{
809 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
810 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
811
812 /*
813 * Switch to command mode before panel-bridge post_disable &
814 * panel unprepare.
815 * Note: panel-bridge disable & panel disable has been called
816 * before by the drm framework.
817 */
818 dw_mipi_dsi_set_mode(dsi, 0);
819
820 /*
821 * TODO Only way found to call panel-bridge post_disable &
822 * panel unprepare before the dsi "final" disable...
823 * This needs to be fixed in the drm_bridge framework and the API
824 * needs to be updated to manage our own call chains...
825 */
826 if (dsi->panel_bridge->funcs->post_disable)
827 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
828
829 if (phy_ops->power_off)
830 phy_ops->power_off(dsi->plat_data->priv_data);
831
832 if (dsi->slave) {
833 dw_mipi_dsi_disable(dsi->slave);
834 clk_disable_unprepare(dsi->slave->pclk);
835 pm_runtime_put(dsi->slave->dev);
836 }
837 dw_mipi_dsi_disable(dsi);
838
839 clk_disable_unprepare(dsi->pclk);
840 pm_runtime_put(dsi->dev);
841}
842
843static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
844{
845 /* this instance is the slave, so add the master's lanes */
846 if (dsi->master)
847 return dsi->master->lanes + dsi->lanes;
848
849 /* this instance is the master, so add the slave's lanes */
850 if (dsi->slave)
851 return dsi->lanes + dsi->slave->lanes;
852
853 /* single-dsi, so no other instance to consider */
854 return dsi->lanes;
855}
856
857static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
858 const struct drm_display_mode *adjusted_mode)
859{
860 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
861 void *priv_data = dsi->plat_data->priv_data;
862 int ret;
863 u32 lanes = dw_mipi_dsi_get_lanes(dsi);
864
865 clk_prepare_enable(dsi->pclk);
866
867 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
868 lanes, dsi->format, &dsi->lane_mbps);
869 if (ret)
870 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
871
872 pm_runtime_get_sync(dsi->dev);
873 dw_mipi_dsi_init(dsi);
874 dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
875 dw_mipi_dsi_packet_handler_config(dsi);
876 dw_mipi_dsi_video_mode_config(dsi);
877 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
878 dw_mipi_dsi_command_mode_config(dsi);
879 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
880 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
881
882 dw_mipi_dsi_dphy_init(dsi);
883 dw_mipi_dsi_dphy_timing_config(dsi);
884 dw_mipi_dsi_dphy_interface_config(dsi);
885
886 dw_mipi_dsi_clear_err(dsi);
887
888 ret = phy_ops->init(priv_data);
889 if (ret)
890 DRM_DEBUG_DRIVER("Phy init() failed\n");
891
892 dw_mipi_dsi_dphy_enable(dsi);
893
894 dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
895
896 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
897 dw_mipi_dsi_set_mode(dsi, 0);
898
899 if (phy_ops->power_on)
900 phy_ops->power_on(dsi->plat_data->priv_data);
901}
902
903static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
904 const struct drm_display_mode *mode,
905 const struct drm_display_mode *adjusted_mode)
906{
907 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
908
909 dw_mipi_dsi_mode_set(dsi, adjusted_mode);
910 if (dsi->slave)
911 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode);
912}
913
914static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
915{
916 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
917
918 /* Switch to video mode for panel-bridge enable & panel enable */
919 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
920 if (dsi->slave)
921 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
922}
923
924static enum drm_mode_status
925dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
926 const struct drm_display_info *info,
927 const struct drm_display_mode *mode)
928{
929 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
930 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
931 enum drm_mode_status mode_status = MODE_OK;
932
933 if (pdata->mode_valid)
934 mode_status = pdata->mode_valid(pdata->priv_data, mode);
935
936 return mode_status;
937}
938
939static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge,
940 enum drm_bridge_attach_flags flags)
941{
942 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
943
944 if (!bridge->encoder) {
945 DRM_ERROR("Parent encoder object not found\n");
946 return -ENODEV;
947 }
948
949 /* Set the encoder type as caller does not know it */
950 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
951
952 /* Attach the panel-bridge to the dsi bridge */
953 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
954 flags);
955}
956
957static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
958 .mode_set = dw_mipi_dsi_bridge_mode_set,
959 .enable = dw_mipi_dsi_bridge_enable,
960 .post_disable = dw_mipi_dsi_bridge_post_disable,
961 .mode_valid = dw_mipi_dsi_bridge_mode_valid,
962 .attach = dw_mipi_dsi_bridge_attach,
963};
964
965#ifdef CONFIG_DEBUG_FS
966
967static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
968{
969 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
970 if (IS_ERR(dsi->debugfs)) {
971 dev_err(dsi->dev, "failed to create debugfs root\n");
972 return;
973 }
974
975 debugfs_create_bool("vpg", 0660, dsi->debugfs, &dsi->vpg);
976 debugfs_create_bool("vpg_horizontal", 0660, dsi->debugfs,
977 &dsi->vpg_horizontal);
978}
979
980static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
981{
982 debugfs_remove_recursive(dsi->debugfs);
983}
984
985#else
986
987static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
988static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
989
990#endif /* CONFIG_DEBUG_FS */
991
992static struct dw_mipi_dsi *
993__dw_mipi_dsi_probe(struct platform_device *pdev,
994 const struct dw_mipi_dsi_plat_data *plat_data)
995{
996 struct device *dev = &pdev->dev;
997 struct reset_control *apb_rst;
998 struct dw_mipi_dsi *dsi;
999 int ret;
1000
1001 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1002 if (!dsi)
1003 return ERR_PTR(-ENOMEM);
1004
1005 dsi->dev = dev;
1006 dsi->plat_data = plat_data;
1007
1008 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
1009 !plat_data->phy_ops->get_timing) {
1010 DRM_ERROR("Phy not properly configured\n");
1011 return ERR_PTR(-ENODEV);
1012 }
1013
1014 if (!plat_data->base) {
1015 dsi->base = devm_platform_ioremap_resource(pdev, 0);
1016 if (IS_ERR(dsi->base))
1017 return ERR_PTR(-ENODEV);
1018
1019 } else {
1020 dsi->base = plat_data->base;
1021 }
1022
1023 dsi->pclk = devm_clk_get(dev, "pclk");
1024 if (IS_ERR(dsi->pclk)) {
1025 ret = PTR_ERR(dsi->pclk);
1026 dev_err(dev, "Unable to get pclk: %d\n", ret);
1027 return ERR_PTR(ret);
1028 }
1029
1030 /*
1031 * Note that the reset was not defined in the initial device tree, so
1032 * we have to be prepared for it not being found.
1033 */
1034 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
1035 if (IS_ERR(apb_rst)) {
1036 ret = PTR_ERR(apb_rst);
1037
1038 if (ret != -EPROBE_DEFER)
1039 dev_err(dev, "Unable to get reset control: %d\n", ret);
1040
1041 return ERR_PTR(ret);
1042 }
1043
1044 if (apb_rst) {
1045 ret = clk_prepare_enable(dsi->pclk);
1046 if (ret) {
1047 dev_err(dev, "%s: Failed to enable pclk\n", __func__);
1048 return ERR_PTR(ret);
1049 }
1050
1051 reset_control_assert(apb_rst);
1052 usleep_range(10, 20);
1053 reset_control_deassert(apb_rst);
1054
1055 clk_disable_unprepare(dsi->pclk);
1056 }
1057
1058 dw_mipi_dsi_debugfs_init(dsi);
1059 pm_runtime_enable(dev);
1060
1061 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1062 dsi->dsi_host.dev = dev;
1063 ret = mipi_dsi_host_register(&dsi->dsi_host);
1064 if (ret) {
1065 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
1066 dw_mipi_dsi_debugfs_remove(dsi);
1067 return ERR_PTR(ret);
1068 }
1069
1070 dsi->bridge.driver_private = dsi;
1071 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
1072#ifdef CONFIG_OF
1073 dsi->bridge.of_node = pdev->dev.of_node;
1074#endif
1075
1076 return dsi;
1077}
1078
1079static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1080{
1081 mipi_dsi_host_unregister(&dsi->dsi_host);
1082
1083 pm_runtime_disable(dsi->dev);
1084 dw_mipi_dsi_debugfs_remove(dsi);
1085}
1086
1087void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1088{
1089 /* introduce controllers to each other */
1090 dsi->slave = slave;
1091 dsi->slave->master = dsi;
1092
1093 /* migrate settings for already attached displays */
1094 dsi->slave->lanes = dsi->lanes;
1095 dsi->slave->channel = dsi->channel;
1096 dsi->slave->format = dsi->format;
1097 dsi->slave->mode_flags = dsi->mode_flags;
1098}
1099EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
1100
1101/*
1102 * Probe/remove API, used from platforms based on the DRM bridge API.
1103 */
1104struct dw_mipi_dsi *
1105dw_mipi_dsi_probe(struct platform_device *pdev,
1106 const struct dw_mipi_dsi_plat_data *plat_data)
1107{
1108 return __dw_mipi_dsi_probe(pdev, plat_data);
1109}
1110EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
1111
1112void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1113{
1114 __dw_mipi_dsi_remove(dsi);
1115}
1116EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
1117
1118/*
1119 * Bind/unbind API, used from platforms based on the component framework.
1120 */
1121int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1122{
1123 int ret;
1124
1125 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1126 if (ret) {
1127 DRM_ERROR("Failed to initialize bridge with drm\n");
1128 return ret;
1129 }
1130
1131 return ret;
1132}
1133EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
1134
1135void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1136{
1137}
1138EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1139
1140MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1141MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1142MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
1143MODULE_LICENSE("GPL");
1144MODULE_ALIAS("platform:dw-mipi-dsi");