1/*
  2 * Copyright 2008 Advanced Micro Devices, Inc.
  3 * Copyright 2008 Red Hat Inc.
  4 * Copyright 2009 Jerome Glisse.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 22 * OTHER DEALINGS IN THE SOFTWARE.
 23 *
 24 * Authors: Dave Airlie
 25 *          Alex Deucher
 26 *          Jerome Glisse
 27 */
 28
 29/**
 30 * DOC: Interrupt Handling
 31 *
 32 * Interrupts generated within GPU hardware raise interrupt requests that are
 33 * passed to amdgpu IRQ handler which is responsible for detecting source and
 34 * type of the interrupt and dispatching matching handlers. If handling an
 35 * interrupt requires calling kernel functions that may sleep processing is
 36 * dispatched to work handlers.
 37 *
 38 * If MSI functionality is not disabled by module parameter then MSI
 39 * support will be enabled.
 40 *
 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
 42 * support is used (with mapping between virtual and hardware IRQs).
 43 */
 44
 45#include <linux/irq.h>
 46#include <linux/pci.h>
 47
 48#include <drm/drm_crtc_helper.h>
 49#include <drm/drm_irq.h>
 50#include <drm/drm_vblank.h>
 51#include <drm/amdgpu_drm.h>
 52#include "amdgpu.h"
 53#include "amdgpu_ih.h"
 54#include "atom.h"
 55#include "amdgpu_connectors.h"
 56#include "amdgpu_trace.h"
 57#include "amdgpu_amdkfd.h"
 58#include "amdgpu_ras.h"
 59
 60#include <linux/pm_runtime.h>
 61
 62#ifdef CONFIG_DRM_AMD_DC
 63#include "amdgpu_dm_irq.h"
 64#endif
 65
 66#define AMDGPU_WAIT_IDLE_TIMEOUT 200
 67
 68/**
 69 * amdgpu_hotplug_work_func - work handler for display hotplug event
 70 *
 71 * @work: work struct pointer
 72 *
 73 * This is the hotplug event work handler (all ASICs).
 74 * The work gets scheduled from the IRQ handler if there
 75 * was a hotplug interrupt.  It walks through the connector table
 76 * and calls hotplug handler for each connector. After this, it sends
 77 * a DRM hotplug event to alert userspace.
 78 *
 79 * This design approach is required in order to defer hotplug event handling
 80 * from the IRQ handler to a work handler because hotplug handler has to use
 81 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
 82 * sleep).
 83 */
 84static void amdgpu_hotplug_work_func(struct work_struct *work)
 85{
 86	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
 87						  hotplug_work);
 88	struct drm_device *dev = adev->ddev;
 89	struct drm_mode_config *mode_config = &dev->mode_config;
 90	struct drm_connector *connector;
 91	struct drm_connector_list_iter iter;
 92
 93	mutex_lock(&mode_config->mutex);
 94	drm_connector_list_iter_begin(dev, &iter);
 95	drm_for_each_connector_iter(connector, &iter)
 96		amdgpu_connector_hotplug(connector);
 97	drm_connector_list_iter_end(&iter);
 98	mutex_unlock(&mode_config->mutex);
 99	/* Just fire off a uevent and let userspace tell us what to do */
100	drm_helper_hpd_irq_event(dev);
101}
102
103/**
104 * amdgpu_irq_disable_all - disable *all* interrupts
105 *
106 * @adev: amdgpu device pointer
107 *
108 * Disable all types of interrupts from all sources.
109 */
110void amdgpu_irq_disable_all(struct amdgpu_device *adev)
111{
112	unsigned long irqflags;
113	unsigned i, j, k;
114	int r;
115
116	spin_lock_irqsave(&adev->irq.lock, irqflags);
117	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
118		if (!adev->irq.client[i].sources)
119			continue;
120
121		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
122			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
123
124			if (!src || !src->funcs->set || !src->num_types)
125				continue;
126
127			for (k = 0; k < src->num_types; ++k) {
128				atomic_set(&src->enabled_types[k], 0);
129				r = src->funcs->set(adev, src, k,
130						    AMDGPU_IRQ_STATE_DISABLE);
131				if (r)
132					DRM_ERROR("error disabling interrupt (%d)\n",
133						  r);
134			}
135		}
136	}
137	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
138}
139
140/**
141 * amdgpu_irq_handler - IRQ handler
142 *
143 * @irq: IRQ number (unused)
144 * @arg: pointer to DRM device
145 *
146 * IRQ handler for amdgpu driver (all ASICs).
147 *
148 * Returns:
149 * result of handling the IRQ, as defined by &irqreturn_t
150 */
151irqreturn_t amdgpu_irq_handler(int irq, void *arg)
152{
153	struct drm_device *dev = (struct drm_device *) arg;
154	struct amdgpu_device *adev = dev->dev_private;
155	irqreturn_t ret;
156
157	ret = amdgpu_ih_process(adev, &adev->irq.ih);
158	if (ret == IRQ_HANDLED)
159		pm_runtime_mark_last_busy(dev->dev);
160
161	/* For the hardware that cannot enable bif ring for both ras_controller_irq
162         * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
163	 * register to check whether the interrupt is triggered or not, and properly
164	 * ack the interrupt if it is there
165	 */
166	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
167		if (adev->nbio.funcs &&
168		    adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
169			adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
170
171		if (adev->nbio.funcs &&
172		    adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
173			adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
174	}
175
176	return ret;
177}
178
179/**
180 * amdgpu_irq_handle_ih1 - kick of processing for IH1
181 *
182 * @work: work structure in struct amdgpu_irq
183 *
184 * Kick of processing IH ring 1.
185 */
186static void amdgpu_irq_handle_ih1(struct work_struct *work)
187{
188	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
189						  irq.ih1_work);
190
191	amdgpu_ih_process(adev, &adev->irq.ih1);
192}
193
194/**
195 * amdgpu_irq_handle_ih2 - kick of processing for IH2
196 *
197 * @work: work structure in struct amdgpu_irq
198 *
199 * Kick of processing IH ring 2.
200 */
201static void amdgpu_irq_handle_ih2(struct work_struct *work)
202{
203	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
204						  irq.ih2_work);
205
206	amdgpu_ih_process(adev, &adev->irq.ih2);
207}
208
209/**
210 * amdgpu_msi_ok - check whether MSI functionality is enabled
211 *
212 * @adev: amdgpu device pointer (unused)
213 *
214 * Checks whether MSI functionality has been disabled via module parameter
215 * (all ASICs).
216 *
217 * Returns:
218 * *true* if MSIs are allowed to be enabled or *false* otherwise
219 */
220static bool amdgpu_msi_ok(struct amdgpu_device *adev)
221{
222	if (amdgpu_msi == 1)
223		return true;
224	else if (amdgpu_msi == 0)
225		return false;
226
227	return true;
228}
229
230/**
231 * amdgpu_irq_init - initialize interrupt handling
232 *
233 * @adev: amdgpu device pointer
234 *
235 * Sets up work functions for hotplug and reset interrupts, enables MSI
236 * functionality, initializes vblank, hotplug and reset interrupt handling.
237 *
238 * Returns:
239 * 0 on success or error code on failure
240 */
241int amdgpu_irq_init(struct amdgpu_device *adev)
242{
243	int r = 0;
244
245	spin_lock_init(&adev->irq.lock);
246
247	/* Enable MSI if not disabled by module parameter */
248	adev->irq.msi_enabled = false;
249
250	if (amdgpu_msi_ok(adev)) {
251		int nvec = pci_msix_vec_count(adev->pdev);
252		unsigned int flags;
253
254		if (nvec <= 0) {
255			flags = PCI_IRQ_MSI;
256		} else {
257			flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
258		}
259		/* we only need one vector */
260		nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
261		if (nvec > 0) {
262			adev->irq.msi_enabled = true;
263			dev_dbg(adev->dev, "using MSI/MSI-X.\n");
264		}
265	}
266
267	if (!amdgpu_device_has_dc_support(adev)) {
268		if (!adev->enable_virtual_display)
269			/* Disable vblank IRQs aggressively for power-saving */
270			/* XXX: can this be enabled for DC? */
271			adev->ddev->vblank_disable_immediate = true;
272
273		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
274		if (r)
275			return r;
276
277		/* Pre-DCE11 */
278		INIT_WORK(&adev->hotplug_work,
279				amdgpu_hotplug_work_func);
280	}
281
282	INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
283	INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
284
285	adev->irq.installed = true;
286	/* Use vector 0 for MSI-X */
287	r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
288	if (r) {
289		adev->irq.installed = false;
290		if (!amdgpu_device_has_dc_support(adev))
291			flush_work(&adev->hotplug_work);
292		return r;
293	}
294	adev->ddev->max_vblank_count = 0x00ffffff;
295
296	DRM_DEBUG("amdgpu: irq initialized.\n");
297	return 0;
298}
299
300/**
301 * amdgpu_irq_fini - shut down interrupt handling
302 *
303 * @adev: amdgpu device pointer
304 *
305 * Tears down work functions for hotplug and reset interrupts, disables MSI
306 * functionality, shuts down vblank, hotplug and reset interrupt handling,
307 * turns off interrupts from all sources (all ASICs).
308 */
309void amdgpu_irq_fini(struct amdgpu_device *adev)
310{
311	unsigned i, j;
312
313	if (adev->irq.installed) {
314		drm_irq_uninstall(adev->ddev);
315		adev->irq.installed = false;
316		if (adev->irq.msi_enabled)
317			pci_free_irq_vectors(adev->pdev);
318		if (!amdgpu_device_has_dc_support(adev))
319			flush_work(&adev->hotplug_work);
320	}
321
322	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
323		if (!adev->irq.client[i].sources)
324			continue;
325
326		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
327			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
328
329			if (!src)
330				continue;
331
332			kfree(src->enabled_types);
333			src->enabled_types = NULL;
334			if (src->data) {
335				kfree(src->data);
336				kfree(src);
337				adev->irq.client[i].sources[j] = NULL;
338			}
339		}
340		kfree(adev->irq.client[i].sources);
341		adev->irq.client[i].sources = NULL;
342	}
343}
344
345/**
346 * amdgpu_irq_add_id - register IRQ source
347 *
348 * @adev: amdgpu device pointer
349 * @client_id: client id
350 * @src_id: source id
351 * @source: IRQ source pointer
352 *
353 * Registers IRQ source on a client.
354 *
355 * Returns:
356 * 0 on success or error code otherwise
357 */
358int amdgpu_irq_add_id(struct amdgpu_device *adev,
359		      unsigned client_id, unsigned src_id,
360		      struct amdgpu_irq_src *source)
361{
362	if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
363		return -EINVAL;
364
365	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
366		return -EINVAL;
367
368	if (!source->funcs)
369		return -EINVAL;
370
371	if (!adev->irq.client[client_id].sources) {
372		adev->irq.client[client_id].sources =
373			kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
374				sizeof(struct amdgpu_irq_src *),
375				GFP_KERNEL);
376		if (!adev->irq.client[client_id].sources)
377			return -ENOMEM;
378	}
379
380	if (adev->irq.client[client_id].sources[src_id] != NULL)
381		return -EINVAL;
382
383	if (source->num_types && !source->enabled_types) {
384		atomic_t *types;
385
386		types = kcalloc(source->num_types, sizeof(atomic_t),
387				GFP_KERNEL);
388		if (!types)
389			return -ENOMEM;
390
391		source->enabled_types = types;
392	}
393
394	adev->irq.client[client_id].sources[src_id] = source;
395	return 0;
396}
397
398/**
399 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
400 *
401 * @adev: amdgpu device pointer
402 * @ih: interrupt ring instance
403 *
404 * Dispatches IRQ to IP blocks.
405 */
406void amdgpu_irq_dispatch(struct amdgpu_device *adev,
407			 struct amdgpu_ih_ring *ih)
408{
409	u32 ring_index = ih->rptr >> 2;
410	struct amdgpu_iv_entry entry;
411	unsigned client_id, src_id;
412	struct amdgpu_irq_src *src;
413	bool handled = false;
414	int r;
415
416	entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
417	amdgpu_ih_decode_iv(adev, &entry);
418
419	trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
420
421	client_id = entry.client_id;
422	src_id = entry.src_id;
423
424	if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
425		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
426
427	} else	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
428		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
429
430	} else if (adev->irq.virq[src_id]) {
431		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
432
433	} else if (!adev->irq.client[client_id].sources) {
434		DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
435			  client_id, src_id);
436
437	} else if ((src = adev->irq.client[client_id].sources[src_id])) {
438		r = src->funcs->process(adev, src, &entry);
439		if (r < 0)
440			DRM_ERROR("error processing interrupt (%d)\n", r);
441		else if (r)
442			handled = true;
443
444	} else {
445		DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
446	}
447
448	/* Send it to amdkfd as well if it isn't already handled */
449	if (!handled)
450		amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
451}
452
453/**
454 * amdgpu_irq_update - update hardware interrupt state
455 *
456 * @adev: amdgpu device pointer
457 * @src: interrupt source pointer
458 * @type: type of interrupt
459 *
460 * Updates interrupt state for the specific source (all ASICs).
461 */
462int amdgpu_irq_update(struct amdgpu_device *adev,
463			     struct amdgpu_irq_src *src, unsigned type)
464{
465	unsigned long irqflags;
466	enum amdgpu_interrupt_state state;
467	int r;
468
469	spin_lock_irqsave(&adev->irq.lock, irqflags);
470
471	/* We need to determine after taking the lock, otherwise
472	   we might disable just enabled interrupts again */
473	if (amdgpu_irq_enabled(adev, src, type))
474		state = AMDGPU_IRQ_STATE_ENABLE;
475	else
476		state = AMDGPU_IRQ_STATE_DISABLE;
477
478	r = src->funcs->set(adev, src, type, state);
479	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
480	return r;
481}
482
483/**
484 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
485 *
486 * @adev: amdgpu device pointer
487 *
488 * Updates state of all types of interrupts on all sources on resume after
489 * reset.
490 */
491void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
492{
493	int i, j, k;
494
495	for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
496		if (!adev->irq.client[i].sources)
497			continue;
498
499		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
500			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
501
502			if (!src)
503				continue;
504			for (k = 0; k < src->num_types; k++)
505				amdgpu_irq_update(adev, src, k);
506		}
507	}
508}
509
510/**
511 * amdgpu_irq_get - enable interrupt
512 *
513 * @adev: amdgpu device pointer
514 * @src: interrupt source pointer
515 * @type: type of interrupt
516 *
517 * Enables specified type of interrupt on the specified source (all ASICs).
518 *
519 * Returns:
520 * 0 on success or error code otherwise
521 */
522int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
523		   unsigned type)
524{
525	if (!adev->ddev->irq_enabled)
526		return -ENOENT;
527
528	if (type >= src->num_types)
529		return -EINVAL;
530
531	if (!src->enabled_types || !src->funcs->set)
532		return -EINVAL;
533
534	if (atomic_inc_return(&src->enabled_types[type]) == 1)
535		return amdgpu_irq_update(adev, src, type);
536
537	return 0;
538}
539
540/**
541 * amdgpu_irq_put - disable interrupt
542 *
543 * @adev: amdgpu device pointer
544 * @src: interrupt source pointer
545 * @type: type of interrupt
546 *
547 * Enables specified type of interrupt on the specified source (all ASICs).
548 *
549 * Returns:
550 * 0 on success or error code otherwise
551 */
552int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
553		   unsigned type)
554{
555	if (!adev->ddev->irq_enabled)
556		return -ENOENT;
557
558	if (type >= src->num_types)
559		return -EINVAL;
560
561	if (!src->enabled_types || !src->funcs->set)
562		return -EINVAL;
563
564	if (atomic_dec_and_test(&src->enabled_types[type]))
565		return amdgpu_irq_update(adev, src, type);
566
567	return 0;
568}
569
570/**
571 * amdgpu_irq_enabled - check whether interrupt is enabled or not
572 *
573 * @adev: amdgpu device pointer
574 * @src: interrupt source pointer
575 * @type: type of interrupt
576 *
577 * Checks whether the given type of interrupt is enabled on the given source.
578 *
579 * Returns:
580 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
581 * invalid parameters
582 */
583bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
584			unsigned type)
585{
586	if (!adev->ddev->irq_enabled)
587		return false;
588
589	if (type >= src->num_types)
590		return false;
591
592	if (!src->enabled_types || !src->funcs->set)
593		return false;
594
595	return !!atomic_read(&src->enabled_types[type]);
596}
597
598/* XXX: Generic IRQ handling */
599static void amdgpu_irq_mask(struct irq_data *irqd)
600{
601	/* XXX */
602}
603
604static void amdgpu_irq_unmask(struct irq_data *irqd)
605{
606	/* XXX */
607}
608
609/* amdgpu hardware interrupt chip descriptor */
610static struct irq_chip amdgpu_irq_chip = {
611	.name = "amdgpu-ih",
612	.irq_mask = amdgpu_irq_mask,
613	.irq_unmask = amdgpu_irq_unmask,
614};
615
616/**
617 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
618 *
619 * @d: amdgpu IRQ domain pointer (unused)
620 * @irq: virtual IRQ number
621 * @hwirq: hardware irq number
622 *
623 * Current implementation assigns simple interrupt handler to the given virtual
624 * IRQ.
625 *
626 * Returns:
627 * 0 on success or error code otherwise
628 */
629static int amdgpu_irqdomain_map(struct irq_domain *d,
630				unsigned int irq, irq_hw_number_t hwirq)
631{
632	if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
633		return -EPERM;
634
635	irq_set_chip_and_handler(irq,
636				 &amdgpu_irq_chip, handle_simple_irq);
637	return 0;
638}
639
640/* Implementation of methods for amdgpu IRQ domain */
641static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
642	.map = amdgpu_irqdomain_map,
643};
644
645/**
646 * amdgpu_irq_add_domain - create a linear IRQ domain
647 *
648 * @adev: amdgpu device pointer
649 *
650 * Creates an IRQ domain for GPU interrupt sources
651 * that may be driven by another driver (e.g., ACP).
652 *
653 * Returns:
654 * 0 on success or error code otherwise
655 */
656int amdgpu_irq_add_domain(struct amdgpu_device *adev)
657{
658	adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
659						 &amdgpu_hw_irqdomain_ops, adev);
660	if (!adev->irq.domain) {
661		DRM_ERROR("GPU irq add domain failed\n");
662		return -ENODEV;
663	}
664
665	return 0;
666}
667
668/**
669 * amdgpu_irq_remove_domain - remove the IRQ domain
670 *
671 * @adev: amdgpu device pointer
672 *
673 * Removes the IRQ domain for GPU interrupt sources
674 * that may be driven by another driver (e.g., ACP).
675 */
676void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
677{
678	if (adev->irq.domain) {
679		irq_domain_remove(adev->irq.domain);
680		adev->irq.domain = NULL;
681	}
682}
683
684/**
685 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
686 *
687 * @adev: amdgpu device pointer
688 * @src_id: IH source id
689 *
690 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
691 * Use this for components that generate a GPU interrupt, but are driven
692 * by a different driver (e.g., ACP).
693 *
694 * Returns:
695 * Linux IRQ
696 */
697unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
698{
699	adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
700
701	return adev->irq.virq[src_id];
702}