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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52
53#include <drm/ttm/ttm_bo_api.h>
54#include <drm/ttm/ttm_bo_driver.h>
55#include <drm/ttm/ttm_placement.h>
56#include <drm/ttm/ttm_module.h>
57#include <drm/ttm/ttm_execbuf_util.h>
58
59#include <drm/amdgpu_drm.h>
60#include <drm/drm_gem.h>
61#include <drm/drm_ioctl.h>
62#include <drm/gpu_scheduler.h>
63
64#include <kgd_kfd_interface.h>
65#include "dm_pp_interface.h"
66#include "kgd_pp_interface.h"
67
68#include "amd_shared.h"
69#include "amdgpu_mode.h"
70#include "amdgpu_ih.h"
71#include "amdgpu_irq.h"
72#include "amdgpu_ucode.h"
73#include "amdgpu_ttm.h"
74#include "amdgpu_psp.h"
75#include "amdgpu_gds.h"
76#include "amdgpu_sync.h"
77#include "amdgpu_ring.h"
78#include "amdgpu_vm.h"
79#include "amdgpu_dpm.h"
80#include "amdgpu_acp.h"
81#include "amdgpu_uvd.h"
82#include "amdgpu_vce.h"
83#include "amdgpu_vcn.h"
84#include "amdgpu_jpeg.h"
85#include "amdgpu_mn.h"
86#include "amdgpu_gmc.h"
87#include "amdgpu_gfx.h"
88#include "amdgpu_sdma.h"
89#include "amdgpu_nbio.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_gart.h"
94#include "amdgpu_debugfs.h"
95#include "amdgpu_job.h"
96#include "amdgpu_bo_list.h"
97#include "amdgpu_gem.h"
98#include "amdgpu_doorbell.h"
99#include "amdgpu_amdkfd.h"
100#include "amdgpu_smu.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_df.h"
106
107#define MAX_GPU_INSTANCE 16
108
109struct amdgpu_gpu_instance
110{
111 struct amdgpu_device *adev;
112 int mgpu_fan_enabled;
113};
114
115struct amdgpu_mgpu_info
116{
117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
118 struct mutex mutex;
119 uint32_t num_gpu;
120 uint32_t num_dgpu;
121 uint32_t num_apu;
122};
123
124#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
125
126/*
127 * Modules parameters.
128 */
129extern int amdgpu_modeset;
130extern int amdgpu_vram_limit;
131extern int amdgpu_vis_vram_limit;
132extern int amdgpu_gart_size;
133extern int amdgpu_gtt_size;
134extern int amdgpu_moverate;
135extern int amdgpu_benchmarking;
136extern int amdgpu_testing;
137extern int amdgpu_audio;
138extern int amdgpu_disp_priority;
139extern int amdgpu_hw_i2c;
140extern int amdgpu_pcie_gen2;
141extern int amdgpu_msi;
142extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
143extern int amdgpu_dpm;
144extern int amdgpu_fw_load_type;
145extern int amdgpu_aspm;
146extern int amdgpu_runtime_pm;
147extern uint amdgpu_ip_block_mask;
148extern int amdgpu_bapm;
149extern int amdgpu_deep_color;
150extern int amdgpu_vm_size;
151extern int amdgpu_vm_block_size;
152extern int amdgpu_vm_fragment_size;
153extern int amdgpu_vm_fault_stop;
154extern int amdgpu_vm_debug;
155extern int amdgpu_vm_update_mode;
156extern int amdgpu_exp_hw_support;
157extern int amdgpu_dc;
158extern int amdgpu_sched_jobs;
159extern int amdgpu_sched_hw_submission;
160extern uint amdgpu_pcie_gen_cap;
161extern uint amdgpu_pcie_lane_cap;
162extern uint amdgpu_cg_mask;
163extern uint amdgpu_pg_mask;
164extern uint amdgpu_sdma_phase_quantum;
165extern char *amdgpu_disable_cu;
166extern char *amdgpu_virtual_display;
167extern uint amdgpu_pp_feature_mask;
168extern uint amdgpu_force_long_training;
169extern int amdgpu_job_hang_limit;
170extern int amdgpu_lbpw;
171extern int amdgpu_compute_multipipe;
172extern int amdgpu_gpu_recovery;
173extern int amdgpu_emu_mode;
174extern uint amdgpu_smu_memory_pool_size;
175extern uint amdgpu_dc_feature_mask;
176extern uint amdgpu_dc_debug_mask;
177extern uint amdgpu_dm_abm_level;
178extern struct amdgpu_mgpu_info mgpu_info;
179extern int amdgpu_ras_enable;
180extern uint amdgpu_ras_mask;
181extern int amdgpu_async_gfx_ring;
182extern int amdgpu_mcbp;
183extern int amdgpu_discovery;
184extern int amdgpu_mes;
185extern int amdgpu_noretry;
186extern int amdgpu_force_asic_type;
187#ifdef CONFIG_HSA_AMD
188extern int sched_policy;
189extern bool debug_evictions;
190#else
191static const int sched_policy = KFD_SCHED_POLICY_HWS;
192static const bool debug_evictions; /* = false */
193#endif
194
195extern int amdgpu_tmz;
196extern int amdgpu_reset_method;
197
198#ifdef CONFIG_DRM_AMDGPU_SI
199extern int amdgpu_si_support;
200#endif
201#ifdef CONFIG_DRM_AMDGPU_CIK
202extern int amdgpu_cik_support;
203#endif
204
205#define AMDGPU_VM_MAX_NUM_CTX 4096
206#define AMDGPU_SG_THRESHOLD (256*1024*1024)
207#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
208#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
209#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
210#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
211#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
212#define AMDGPUFB_CONN_LIMIT 4
213#define AMDGPU_BIOS_NUM_SCRATCH 16
214
215/* hard reset data */
216#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
217
218/* reset flags */
219#define AMDGPU_RESET_GFX (1 << 0)
220#define AMDGPU_RESET_COMPUTE (1 << 1)
221#define AMDGPU_RESET_DMA (1 << 2)
222#define AMDGPU_RESET_CP (1 << 3)
223#define AMDGPU_RESET_GRBM (1 << 4)
224#define AMDGPU_RESET_DMA1 (1 << 5)
225#define AMDGPU_RESET_RLC (1 << 6)
226#define AMDGPU_RESET_SEM (1 << 7)
227#define AMDGPU_RESET_IH (1 << 8)
228#define AMDGPU_RESET_VMC (1 << 9)
229#define AMDGPU_RESET_MC (1 << 10)
230#define AMDGPU_RESET_DISPLAY (1 << 11)
231#define AMDGPU_RESET_UVD (1 << 12)
232#define AMDGPU_RESET_VCE (1 << 13)
233#define AMDGPU_RESET_VCE1 (1 << 14)
234
235/* max cursor sizes (in pixels) */
236#define CIK_CURSOR_WIDTH 128
237#define CIK_CURSOR_HEIGHT 128
238
239struct amdgpu_device;
240struct amdgpu_ib;
241struct amdgpu_cs_parser;
242struct amdgpu_job;
243struct amdgpu_irq_src;
244struct amdgpu_fpriv;
245struct amdgpu_bo_va_mapping;
246struct amdgpu_atif;
247struct kfd_vm_fault_info;
248
249enum amdgpu_cp_irq {
250 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
251 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
252 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
253 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
254 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
255 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
256 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
257 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
258 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
259 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
260
261 AMDGPU_CP_IRQ_LAST
262};
263
264enum amdgpu_thermal_irq {
265 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
266 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
267
268 AMDGPU_THERMAL_IRQ_LAST
269};
270
271enum amdgpu_kiq_irq {
272 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
273 AMDGPU_CP_KIQ_IRQ_LAST
274};
275
276#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
277#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
278#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
279
280int amdgpu_device_ip_set_clockgating_state(void *dev,
281 enum amd_ip_block_type block_type,
282 enum amd_clockgating_state state);
283int amdgpu_device_ip_set_powergating_state(void *dev,
284 enum amd_ip_block_type block_type,
285 enum amd_powergating_state state);
286void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
287 u32 *flags);
288int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
289 enum amd_ip_block_type block_type);
290bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
291 enum amd_ip_block_type block_type);
292
293#define AMDGPU_MAX_IP_NUM 16
294
295struct amdgpu_ip_block_status {
296 bool valid;
297 bool sw;
298 bool hw;
299 bool late_initialized;
300 bool hang;
301};
302
303struct amdgpu_ip_block_version {
304 const enum amd_ip_block_type type;
305 const u32 major;
306 const u32 minor;
307 const u32 rev;
308 const struct amd_ip_funcs *funcs;
309};
310
311#define HW_REV(_Major, _Minor, _Rev) \
312 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
313
314struct amdgpu_ip_block {
315 struct amdgpu_ip_block_status status;
316 const struct amdgpu_ip_block_version *version;
317};
318
319int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
320 enum amd_ip_block_type type,
321 u32 major, u32 minor);
322
323struct amdgpu_ip_block *
324amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
325 enum amd_ip_block_type type);
326
327int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
328 const struct amdgpu_ip_block_version *ip_block_version);
329
330/*
331 * BIOS.
332 */
333bool amdgpu_get_bios(struct amdgpu_device *adev);
334bool amdgpu_read_bios(struct amdgpu_device *adev);
335
336/*
337 * Clocks
338 */
339
340#define AMDGPU_MAX_PPLL 3
341
342struct amdgpu_clock {
343 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
344 struct amdgpu_pll spll;
345 struct amdgpu_pll mpll;
346 /* 10 Khz units */
347 uint32_t default_mclk;
348 uint32_t default_sclk;
349 uint32_t default_dispclk;
350 uint32_t current_dispclk;
351 uint32_t dp_extclk;
352 uint32_t max_pixel_clock;
353};
354
355/* sub-allocation manager, it has to be protected by another lock.
356 * By conception this is an helper for other part of the driver
357 * like the indirect buffer or semaphore, which both have their
358 * locking.
359 *
360 * Principe is simple, we keep a list of sub allocation in offset
361 * order (first entry has offset == 0, last entry has the highest
362 * offset).
363 *
364 * When allocating new object we first check if there is room at
365 * the end total_size - (last_object_offset + last_object_size) >=
366 * alloc_size. If so we allocate new object there.
367 *
368 * When there is not enough room at the end, we start waiting for
369 * each sub object until we reach object_offset+object_size >=
370 * alloc_size, this object then become the sub object we return.
371 *
372 * Alignment can't be bigger than page size.
373 *
374 * Hole are not considered for allocation to keep things simple.
375 * Assumption is that there won't be hole (all object on same
376 * alignment).
377 */
378
379#define AMDGPU_SA_NUM_FENCE_LISTS 32
380
381struct amdgpu_sa_manager {
382 wait_queue_head_t wq;
383 struct amdgpu_bo *bo;
384 struct list_head *hole;
385 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
386 struct list_head olist;
387 unsigned size;
388 uint64_t gpu_addr;
389 void *cpu_ptr;
390 uint32_t domain;
391 uint32_t align;
392};
393
394/* sub-allocation buffer */
395struct amdgpu_sa_bo {
396 struct list_head olist;
397 struct list_head flist;
398 struct amdgpu_sa_manager *manager;
399 unsigned soffset;
400 unsigned eoffset;
401 struct dma_fence *fence;
402};
403
404int amdgpu_fence_slab_init(void);
405void amdgpu_fence_slab_fini(void);
406
407/*
408 * IRQS.
409 */
410
411struct amdgpu_flip_work {
412 struct delayed_work flip_work;
413 struct work_struct unpin_work;
414 struct amdgpu_device *adev;
415 int crtc_id;
416 u32 target_vblank;
417 uint64_t base;
418 struct drm_pending_vblank_event *event;
419 struct amdgpu_bo *old_abo;
420 struct dma_fence *excl;
421 unsigned shared_count;
422 struct dma_fence **shared;
423 struct dma_fence_cb cb;
424 bool async;
425};
426
427
428/*
429 * CP & rings.
430 */
431
432struct amdgpu_ib {
433 struct amdgpu_sa_bo *sa_bo;
434 uint32_t length_dw;
435 uint64_t gpu_addr;
436 uint32_t *ptr;
437 uint32_t flags;
438};
439
440extern const struct drm_sched_backend_ops amdgpu_sched_ops;
441
442/*
443 * file private structure
444 */
445
446struct amdgpu_fpriv {
447 struct amdgpu_vm vm;
448 struct amdgpu_bo_va *prt_va;
449 struct amdgpu_bo_va *csa_va;
450 struct mutex bo_list_lock;
451 struct idr bo_list_handles;
452 struct amdgpu_ctx_mgr ctx_mgr;
453};
454
455int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
456
457int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
458 unsigned size,
459 enum amdgpu_ib_pool_type pool,
460 struct amdgpu_ib *ib);
461void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
462 struct dma_fence *f);
463int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
464 struct amdgpu_ib *ibs, struct amdgpu_job *job,
465 struct dma_fence **f);
466int amdgpu_ib_pool_init(struct amdgpu_device *adev);
467void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
468int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
469
470/*
471 * CS.
472 */
473struct amdgpu_cs_chunk {
474 uint32_t chunk_id;
475 uint32_t length_dw;
476 void *kdata;
477};
478
479struct amdgpu_cs_post_dep {
480 struct drm_syncobj *syncobj;
481 struct dma_fence_chain *chain;
482 u64 point;
483};
484
485struct amdgpu_cs_parser {
486 struct amdgpu_device *adev;
487 struct drm_file *filp;
488 struct amdgpu_ctx *ctx;
489
490 /* chunks */
491 unsigned nchunks;
492 struct amdgpu_cs_chunk *chunks;
493
494 /* scheduler job object */
495 struct amdgpu_job *job;
496 struct drm_sched_entity *entity;
497
498 /* buffer objects */
499 struct ww_acquire_ctx ticket;
500 struct amdgpu_bo_list *bo_list;
501 struct amdgpu_mn *mn;
502 struct amdgpu_bo_list_entry vm_pd;
503 struct list_head validated;
504 struct dma_fence *fence;
505 uint64_t bytes_moved_threshold;
506 uint64_t bytes_moved_vis_threshold;
507 uint64_t bytes_moved;
508 uint64_t bytes_moved_vis;
509
510 /* user fence */
511 struct amdgpu_bo_list_entry uf_entry;
512
513 unsigned num_post_deps;
514 struct amdgpu_cs_post_dep *post_deps;
515};
516
517static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
518 uint32_t ib_idx, int idx)
519{
520 return p->job->ibs[ib_idx].ptr[idx];
521}
522
523static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
524 uint32_t ib_idx, int idx,
525 uint32_t value)
526{
527 p->job->ibs[ib_idx].ptr[idx] = value;
528}
529
530/*
531 * Writeback
532 */
533#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
534
535struct amdgpu_wb {
536 struct amdgpu_bo *wb_obj;
537 volatile uint32_t *wb;
538 uint64_t gpu_addr;
539 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
540 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
541};
542
543int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
544void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
545
546/*
547 * Benchmarking
548 */
549void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
550
551
552/*
553 * Testing
554 */
555void amdgpu_test_moves(struct amdgpu_device *adev);
556
557/*
558 * ASIC specific register table accessible by UMD
559 */
560struct amdgpu_allowed_register_entry {
561 uint32_t reg_offset;
562 bool grbm_indexed;
563};
564
565enum amd_reset_method {
566 AMD_RESET_METHOD_LEGACY = 0,
567 AMD_RESET_METHOD_MODE0,
568 AMD_RESET_METHOD_MODE1,
569 AMD_RESET_METHOD_MODE2,
570 AMD_RESET_METHOD_BACO
571};
572
573/*
574 * ASIC specific functions.
575 */
576struct amdgpu_asic_funcs {
577 bool (*read_disabled_bios)(struct amdgpu_device *adev);
578 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
579 u8 *bios, u32 length_bytes);
580 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
581 u32 sh_num, u32 reg_offset, u32 *value);
582 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
583 int (*reset)(struct amdgpu_device *adev);
584 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
585 /* get the reference clock */
586 u32 (*get_xclk)(struct amdgpu_device *adev);
587 /* MM block clocks */
588 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
589 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
590 /* static power management */
591 int (*get_pcie_lanes)(struct amdgpu_device *adev);
592 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
593 /* get config memsize register */
594 u32 (*get_config_memsize)(struct amdgpu_device *adev);
595 /* flush hdp write queue */
596 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
597 /* invalidate hdp read cache */
598 void (*invalidate_hdp)(struct amdgpu_device *adev,
599 struct amdgpu_ring *ring);
600 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
601 /* check if the asic needs a full reset of if soft reset will work */
602 bool (*need_full_reset)(struct amdgpu_device *adev);
603 /* initialize doorbell layout for specific asic*/
604 void (*init_doorbell_index)(struct amdgpu_device *adev);
605 /* PCIe bandwidth usage */
606 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
607 uint64_t *count1);
608 /* do we need to reset the asic at init time (e.g., kexec) */
609 bool (*need_reset_on_init)(struct amdgpu_device *adev);
610 /* PCIe replay counter */
611 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
612 /* device supports BACO */
613 bool (*supports_baco)(struct amdgpu_device *adev);
614};
615
616/*
617 * IOCTL.
618 */
619int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
620 struct drm_file *filp);
621
622int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
623int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
624 struct drm_file *filp);
625int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
626int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
627 struct drm_file *filp);
628
629/* VRAM scratch page for HDP bug, default vram page */
630struct amdgpu_vram_scratch {
631 struct amdgpu_bo *robj;
632 volatile uint32_t *ptr;
633 u64 gpu_addr;
634};
635
636/*
637 * ACPI
638 */
639struct amdgpu_atcs_functions {
640 bool get_ext_state;
641 bool pcie_perf_req;
642 bool pcie_dev_rdy;
643 bool pcie_bus_width;
644};
645
646struct amdgpu_atcs {
647 struct amdgpu_atcs_functions functions;
648};
649
650/*
651 * Firmware VRAM reservation
652 */
653struct amdgpu_fw_vram_usage {
654 u64 start_offset;
655 u64 size;
656 struct amdgpu_bo *reserved_bo;
657 void *va;
658};
659
660/*
661 * CGS
662 */
663struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
664void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
665
666/*
667 * Core structure, functions and helpers.
668 */
669typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
670typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
671
672typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
673typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
674
675typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
676typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
677
678struct amdgpu_mmio_remap {
679 u32 reg_offset;
680 resource_size_t bus_addr;
681};
682
683/* Define the HW IP blocks will be used in driver , add more if necessary */
684enum amd_hw_ip_block_type {
685 GC_HWIP = 1,
686 HDP_HWIP,
687 SDMA0_HWIP,
688 SDMA1_HWIP,
689 SDMA2_HWIP,
690 SDMA3_HWIP,
691 SDMA4_HWIP,
692 SDMA5_HWIP,
693 SDMA6_HWIP,
694 SDMA7_HWIP,
695 MMHUB_HWIP,
696 ATHUB_HWIP,
697 NBIO_HWIP,
698 MP0_HWIP,
699 MP1_HWIP,
700 UVD_HWIP,
701 VCN_HWIP = UVD_HWIP,
702 JPEG_HWIP = VCN_HWIP,
703 VCE_HWIP,
704 DF_HWIP,
705 DCE_HWIP,
706 OSSSYS_HWIP,
707 SMUIO_HWIP,
708 PWR_HWIP,
709 NBIF_HWIP,
710 THM_HWIP,
711 CLK_HWIP,
712 UMC_HWIP,
713 RSMU_HWIP,
714 MAX_HWIP
715};
716
717#define HWIP_MAX_INSTANCE 8
718
719struct amd_powerplay {
720 void *pp_handle;
721 const struct amd_pm_funcs *pp_funcs;
722};
723
724#define AMDGPU_RESET_MAGIC_NUM 64
725#define AMDGPU_MAX_DF_PERFMONS 4
726struct amdgpu_device {
727 struct device *dev;
728 struct drm_device *ddev;
729 struct pci_dev *pdev;
730
731#ifdef CONFIG_DRM_AMD_ACP
732 struct amdgpu_acp acp;
733#endif
734
735 /* ASIC */
736 enum amd_asic_type asic_type;
737 uint32_t family;
738 uint32_t rev_id;
739 uint32_t external_rev_id;
740 unsigned long flags;
741 unsigned long apu_flags;
742 int usec_timeout;
743 const struct amdgpu_asic_funcs *asic_funcs;
744 bool shutdown;
745 bool need_swiotlb;
746 bool accel_working;
747 struct notifier_block acpi_nb;
748 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
749 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
750 unsigned debugfs_count;
751#if defined(CONFIG_DEBUG_FS)
752 struct dentry *debugfs_preempt;
753 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
754#endif
755 struct amdgpu_atif *atif;
756 struct amdgpu_atcs atcs;
757 struct mutex srbm_mutex;
758 /* GRBM index mutex. Protects concurrent access to GRBM index */
759 struct mutex grbm_idx_mutex;
760 struct dev_pm_domain vga_pm_domain;
761 bool have_disp_power_ref;
762 bool have_atomics_support;
763
764 /* BIOS */
765 bool is_atom_fw;
766 uint8_t *bios;
767 uint32_t bios_size;
768 struct amdgpu_bo *stolen_vga_memory;
769 uint32_t bios_scratch_reg_offset;
770 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
771
772 /* Register/doorbell mmio */
773 resource_size_t rmmio_base;
774 resource_size_t rmmio_size;
775 void __iomem *rmmio;
776 /* protects concurrent MM_INDEX/DATA based register access */
777 spinlock_t mmio_idx_lock;
778 struct amdgpu_mmio_remap rmmio_remap;
779 /* protects concurrent SMC based register access */
780 spinlock_t smc_idx_lock;
781 amdgpu_rreg_t smc_rreg;
782 amdgpu_wreg_t smc_wreg;
783 /* protects concurrent PCIE register access */
784 spinlock_t pcie_idx_lock;
785 amdgpu_rreg_t pcie_rreg;
786 amdgpu_wreg_t pcie_wreg;
787 amdgpu_rreg_t pciep_rreg;
788 amdgpu_wreg_t pciep_wreg;
789 amdgpu_rreg64_t pcie_rreg64;
790 amdgpu_wreg64_t pcie_wreg64;
791 /* protects concurrent UVD register access */
792 spinlock_t uvd_ctx_idx_lock;
793 amdgpu_rreg_t uvd_ctx_rreg;
794 amdgpu_wreg_t uvd_ctx_wreg;
795 /* protects concurrent DIDT register access */
796 spinlock_t didt_idx_lock;
797 amdgpu_rreg_t didt_rreg;
798 amdgpu_wreg_t didt_wreg;
799 /* protects concurrent gc_cac register access */
800 spinlock_t gc_cac_idx_lock;
801 amdgpu_rreg_t gc_cac_rreg;
802 amdgpu_wreg_t gc_cac_wreg;
803 /* protects concurrent se_cac register access */
804 spinlock_t se_cac_idx_lock;
805 amdgpu_rreg_t se_cac_rreg;
806 amdgpu_wreg_t se_cac_wreg;
807 /* protects concurrent ENDPOINT (audio) register access */
808 spinlock_t audio_endpt_idx_lock;
809 amdgpu_block_rreg_t audio_endpt_rreg;
810 amdgpu_block_wreg_t audio_endpt_wreg;
811 void __iomem *rio_mem;
812 resource_size_t rio_mem_size;
813 struct amdgpu_doorbell doorbell;
814
815 /* clock/pll info */
816 struct amdgpu_clock clock;
817
818 /* MC */
819 struct amdgpu_gmc gmc;
820 struct amdgpu_gart gart;
821 dma_addr_t dummy_page_addr;
822 struct amdgpu_vm_manager vm_manager;
823 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
824 unsigned num_vmhubs;
825
826 /* memory management */
827 struct amdgpu_mman mman;
828 struct amdgpu_vram_scratch vram_scratch;
829 struct amdgpu_wb wb;
830 atomic64_t num_bytes_moved;
831 atomic64_t num_evictions;
832 atomic64_t num_vram_cpu_page_faults;
833 atomic_t gpu_reset_counter;
834 atomic_t vram_lost_counter;
835
836 /* data for buffer migration throttling */
837 struct {
838 spinlock_t lock;
839 s64 last_update_us;
840 s64 accum_us; /* accumulated microseconds */
841 s64 accum_us_vis; /* for visible VRAM */
842 u32 log2_max_MBps;
843 } mm_stats;
844
845 /* display */
846 bool enable_virtual_display;
847 struct amdgpu_mode_info mode_info;
848 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
849 struct work_struct hotplug_work;
850 struct amdgpu_irq_src crtc_irq;
851 struct amdgpu_irq_src vupdate_irq;
852 struct amdgpu_irq_src pageflip_irq;
853 struct amdgpu_irq_src hpd_irq;
854
855 /* rings */
856 u64 fence_context;
857 unsigned num_rings;
858 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
859 bool ib_pool_ready;
860 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
861 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
862
863 /* interrupts */
864 struct amdgpu_irq irq;
865
866 /* powerplay */
867 struct amd_powerplay powerplay;
868 bool pp_force_state_enabled;
869
870 /* smu */
871 struct smu_context smu;
872
873 /* dpm */
874 struct amdgpu_pm pm;
875 u32 cg_flags;
876 u32 pg_flags;
877
878 /* nbio */
879 struct amdgpu_nbio nbio;
880
881 /* mmhub */
882 struct amdgpu_mmhub mmhub;
883
884 /* gfx */
885 struct amdgpu_gfx gfx;
886
887 /* sdma */
888 struct amdgpu_sdma sdma;
889
890 /* uvd */
891 struct amdgpu_uvd uvd;
892
893 /* vce */
894 struct amdgpu_vce vce;
895
896 /* vcn */
897 struct amdgpu_vcn vcn;
898
899 /* jpeg */
900 struct amdgpu_jpeg jpeg;
901
902 /* firmwares */
903 struct amdgpu_firmware firmware;
904
905 /* PSP */
906 struct psp_context psp;
907
908 /* GDS */
909 struct amdgpu_gds gds;
910
911 /* KFD */
912 struct amdgpu_kfd_dev kfd;
913
914 /* UMC */
915 struct amdgpu_umc umc;
916
917 /* display related functionality */
918 struct amdgpu_display_manager dm;
919
920 /* discovery */
921 uint8_t *discovery_bin;
922 uint32_t discovery_tmr_size;
923 struct amdgpu_bo *discovery_memory;
924
925 /* mes */
926 bool enable_mes;
927 struct amdgpu_mes mes;
928
929 /* df */
930 struct amdgpu_df df;
931
932 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
933 int num_ip_blocks;
934 struct mutex mn_lock;
935 DECLARE_HASHTABLE(mn_hash, 7);
936
937 /* tracking pinned memory */
938 atomic64_t vram_pin_size;
939 atomic64_t visible_pin_size;
940 atomic64_t gart_pin_size;
941
942 /* soc15 register offset based on ip, instance and segment */
943 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
944
945 /* delayed work_func for deferring clockgating during resume */
946 struct delayed_work delayed_init_work;
947
948 struct amdgpu_virt virt;
949 /* firmware VRAM reservation */
950 struct amdgpu_fw_vram_usage fw_vram_usage;
951
952 /* link all shadow bo */
953 struct list_head shadow_list;
954 struct mutex shadow_list_lock;
955
956 /* record hw reset is performed */
957 bool has_hw_reset;
958 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
959
960 /* s3/s4 mask */
961 bool in_suspend;
962 bool in_hibernate;
963
964 bool in_gpu_reset;
965 enum pp_mp1_state mp1_state;
966 struct mutex lock_reset;
967 struct amdgpu_doorbell_index doorbell_index;
968
969 struct mutex notifier_lock;
970
971 int asic_reset_res;
972 struct work_struct xgmi_reset_work;
973
974 long gfx_timeout;
975 long sdma_timeout;
976 long video_timeout;
977 long compute_timeout;
978
979 uint64_t unique_id;
980 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
981
982 /* enable runtime pm on the device */
983 bool runpm;
984 bool in_runpm;
985
986 bool pm_sysfs_en;
987 bool ucode_sysfs_en;
988
989 /* Chip product information */
990 char product_number[16];
991 char product_name[32];
992 char serial[20];
993
994 struct amdgpu_autodump autodump;
995
996 atomic_t throttling_logging_enabled;
997 struct ratelimit_state throttling_logging_rs;
998};
999
1000static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1001{
1002 return container_of(bdev, struct amdgpu_device, mman.bdev);
1003}
1004
1005int amdgpu_device_init(struct amdgpu_device *adev,
1006 struct drm_device *ddev,
1007 struct pci_dev *pdev,
1008 uint32_t flags);
1009void amdgpu_device_fini(struct amdgpu_device *adev);
1010int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1011
1012void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1013 uint32_t *buf, size_t size, bool write);
1014uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1015 uint32_t acc_flags);
1016void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1017 uint32_t acc_flags);
1018void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1019 uint32_t acc_flags);
1020void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1021uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1022
1023u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1024void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1025
1026bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1027bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1028
1029int emu_soc_asic_init(struct amdgpu_device *adev);
1030
1031/*
1032 * Registers read & write functions.
1033 */
1034#define AMDGPU_REGS_NO_KIQ (1<<1)
1035
1036#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1037#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1038
1039#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1040#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1041
1042#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1043#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1044
1045#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1046#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1047#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1048#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1049#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1050#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1051#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1052#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1053#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1054#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1055#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1056#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1057#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1058#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1059#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1060#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1061#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1062#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1063#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1064#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1065#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1066#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1067#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1068#define WREG32_P(reg, val, mask) \
1069 do { \
1070 uint32_t tmp_ = RREG32(reg); \
1071 tmp_ &= (mask); \
1072 tmp_ |= ((val) & ~(mask)); \
1073 WREG32(reg, tmp_); \
1074 } while (0)
1075#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1076#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1077#define WREG32_PLL_P(reg, val, mask) \
1078 do { \
1079 uint32_t tmp_ = RREG32_PLL(reg); \
1080 tmp_ &= (mask); \
1081 tmp_ |= ((val) & ~(mask)); \
1082 WREG32_PLL(reg, tmp_); \
1083 } while (0)
1084
1085#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1086 do { \
1087 u32 tmp = RREG32_SMC(_Reg); \
1088 tmp &= (_Mask); \
1089 tmp |= ((_Val) & ~(_Mask)); \
1090 WREG32_SMC(_Reg, tmp); \
1091 } while (0)
1092
1093#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1094#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1095#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1096
1097#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1098#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1099
1100#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1101 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1102 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1103
1104#define REG_GET_FIELD(value, reg, field) \
1105 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1106
1107#define WREG32_FIELD(reg, field, val) \
1108 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1109
1110#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1111 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1112
1113/*
1114 * BIOS helpers.
1115 */
1116#define RBIOS8(i) (adev->bios[i])
1117#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1118#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1119
1120/*
1121 * ASICs macro.
1122 */
1123#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1124#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1125#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1126#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1127#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1128#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1129#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1130#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1131#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1132#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1133#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1134#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1135#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1136#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1137#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1138#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1139#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1140#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1141#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1142#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1143#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1144
1145#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1146
1147/* Common functions */
1148bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1149int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1150 struct amdgpu_job* job);
1151void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1152bool amdgpu_device_need_post(struct amdgpu_device *adev);
1153
1154void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1155 u64 num_vis_bytes);
1156int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1157void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1158 const u32 *registers,
1159 const u32 array_size);
1160
1161bool amdgpu_device_supports_boco(struct drm_device *dev);
1162bool amdgpu_device_supports_baco(struct drm_device *dev);
1163bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1164 struct amdgpu_device *peer_adev);
1165int amdgpu_device_baco_enter(struct drm_device *dev);
1166int amdgpu_device_baco_exit(struct drm_device *dev);
1167
1168/* atpx handler */
1169#if defined(CONFIG_VGA_SWITCHEROO)
1170void amdgpu_register_atpx_handler(void);
1171void amdgpu_unregister_atpx_handler(void);
1172bool amdgpu_has_atpx_dgpu_power_cntl(void);
1173bool amdgpu_is_atpx_hybrid(void);
1174bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1175bool amdgpu_has_atpx(void);
1176#else
1177static inline void amdgpu_register_atpx_handler(void) {}
1178static inline void amdgpu_unregister_atpx_handler(void) {}
1179static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1180static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1181static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1182static inline bool amdgpu_has_atpx(void) { return false; }
1183#endif
1184
1185#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1186void *amdgpu_atpx_get_dhandle(void);
1187#else
1188static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1189#endif
1190
1191/*
1192 * KMS
1193 */
1194extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1195extern const int amdgpu_max_kms_ioctl;
1196
1197int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1198void amdgpu_driver_unload_kms(struct drm_device *dev);
1199void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1200int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1201void amdgpu_driver_postclose_kms(struct drm_device *dev,
1202 struct drm_file *file_priv);
1203int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1204int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1205int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1206u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1207int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1208void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1209long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1210 unsigned long arg);
1211
1212/*
1213 * functions used by amdgpu_encoder.c
1214 */
1215struct amdgpu_afmt_acr {
1216 u32 clock;
1217
1218 int n_32khz;
1219 int cts_32khz;
1220
1221 int n_44_1khz;
1222 int cts_44_1khz;
1223
1224 int n_48khz;
1225 int cts_48khz;
1226
1227};
1228
1229struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1230
1231/* amdgpu_acpi.c */
1232#if defined(CONFIG_ACPI)
1233int amdgpu_acpi_init(struct amdgpu_device *adev);
1234void amdgpu_acpi_fini(struct amdgpu_device *adev);
1235bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1236int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1237 u8 perf_req, bool advertise);
1238int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1239
1240void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1241 struct amdgpu_dm_backlight_caps *caps);
1242#else
1243static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1244static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1245#endif
1246
1247int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1248 uint64_t addr, struct amdgpu_bo **bo,
1249 struct amdgpu_bo_va_mapping **mapping);
1250
1251#if defined(CONFIG_DRM_AMD_DC)
1252int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1253#else
1254static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1255#endif
1256
1257
1258void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1259void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1260
1261#include "amdgpu_object.h"
1262
1263/* used by df_v3_6.c and amdgpu_pmu.c */
1264#define AMDGPU_PMU_ATTR(_name, _object) \
1265static ssize_t \
1266_name##_show(struct device *dev, \
1267 struct device_attribute *attr, \
1268 char *page) \
1269{ \
1270 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1271 return sprintf(page, _object "\n"); \
1272} \
1273 \
1274static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1275
1276static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1277{
1278 return adev->gmc.tmz_enabled;
1279}
1280
1281#endif