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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains miscellaneous low-level functions.
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras.
8 *
9 */
10
11#include <linux/sys.h>
12#include <asm/unistd.h>
13#include <asm/errno.h>
14#include <asm/reg.h>
15#include <asm/page.h>
16#include <asm/cache.h>
17#include <asm/cputable.h>
18#include <asm/mmu.h>
19#include <asm/ppc_asm.h>
20#include <asm/thread_info.h>
21#include <asm/asm-offsets.h>
22#include <asm/processor.h>
23#include <asm/bug.h>
24#include <asm/ptrace.h>
25#include <asm/export.h>
26#include <asm/feature-fixups.h>
27
28 .text
29
30/*
31 * We store the saved ksp_limit in the unused part
32 * of the STACK_FRAME_OVERHEAD
33 */
34_GLOBAL(call_do_softirq)
35 mflr r0
36 stw r0,4(r1)
37 lwz r10,THREAD+KSP_LIMIT(r2)
38 stw r3, THREAD+KSP_LIMIT(r2)
39 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
40 mr r1,r3
41 stw r10,8(r1)
42 bl __do_softirq
43 lwz r10,8(r1)
44 lwz r1,0(r1)
45 lwz r0,4(r1)
46 stw r10,THREAD+KSP_LIMIT(r2)
47 mtlr r0
48 blr
49
50/*
51 * void call_do_irq(struct pt_regs *regs, void *sp);
52 */
53_GLOBAL(call_do_irq)
54 mflr r0
55 stw r0,4(r1)
56 lwz r10,THREAD+KSP_LIMIT(r2)
57 stw r4, THREAD+KSP_LIMIT(r2)
58 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
59 mr r1,r4
60 stw r10,8(r1)
61 bl __do_irq
62 lwz r10,8(r1)
63 lwz r1,0(r1)
64 lwz r0,4(r1)
65 stw r10,THREAD+KSP_LIMIT(r2)
66 mtlr r0
67 blr
68
69/*
70 * This returns the high 64 bits of the product of two 64-bit numbers.
71 */
72_GLOBAL(mulhdu)
73 cmpwi r6,0
74 cmpwi cr1,r3,0
75 mr r10,r4
76 mulhwu r4,r4,r5
77 beq 1f
78 mulhwu r0,r10,r6
79 mullw r7,r10,r5
80 addc r7,r0,r7
81 addze r4,r4
821: beqlr cr1 /* all done if high part of A is 0 */
83 mullw r9,r3,r5
84 mulhwu r10,r3,r5
85 beq 2f
86 mullw r0,r3,r6
87 mulhwu r8,r3,r6
88 addc r7,r0,r7
89 adde r4,r4,r8
90 addze r10,r10
912: addc r4,r4,r9
92 addze r3,r10
93 blr
94
95/*
96 * reloc_got2 runs through the .got2 section adding an offset
97 * to each entry.
98 */
99_GLOBAL(reloc_got2)
100 mflr r11
101 lis r7,__got2_start@ha
102 addi r7,r7,__got2_start@l
103 lis r8,__got2_end@ha
104 addi r8,r8,__got2_end@l
105 subf r8,r7,r8
106 srwi. r8,r8,2
107 beqlr
108 mtctr r8
109 bl 1f
1101: mflr r0
111 lis r4,1b@ha
112 addi r4,r4,1b@l
113 subf r0,r4,r0
114 add r7,r0,r7
1152: lwz r0,0(r7)
116 add r0,r0,r3
117 stw r0,0(r7)
118 addi r7,r7,4
119 bdnz 2b
120 mtlr r11
121 blr
122
123/*
124 * call_setup_cpu - call the setup_cpu function for this cpu
125 * r3 = data offset, r24 = cpu number
126 *
127 * Setup function is called with:
128 * r3 = data offset
129 * r4 = ptr to CPU spec (relocated)
130 */
131_GLOBAL(call_setup_cpu)
132 addis r4,r3,cur_cpu_spec@ha
133 addi r4,r4,cur_cpu_spec@l
134 lwz r4,0(r4)
135 add r4,r4,r3
136 lwz r5,CPU_SPEC_SETUP(r4)
137 cmpwi 0,r5,0
138 add r5,r5,r3
139 beqlr
140 mtctr r5
141 bctr
142
143#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32)
144
145/* This gets called by via-pmu.c to switch the PLL selection
146 * on 750fx CPU. This function should really be moved to some
147 * other place (as most of the cpufreq code in via-pmu
148 */
149_GLOBAL(low_choose_750fx_pll)
150 /* Clear MSR:EE */
151 mfmsr r7
152 rlwinm r0,r7,0,17,15
153 mtmsr r0
154
155 /* If switching to PLL1, disable HID0:BTIC */
156 cmplwi cr0,r3,0
157 beq 1f
158 mfspr r5,SPRN_HID0
159 rlwinm r5,r5,0,27,25
160 sync
161 mtspr SPRN_HID0,r5
162 isync
163 sync
164
1651:
166 /* Calc new HID1 value */
167 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
168 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
169 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
170 or r4,r4,r5
171 mtspr SPRN_HID1,r4
172
173#ifdef CONFIG_SMP
174 /* Store new HID1 image */
175 lwz r6,TASK_CPU(r2)
176 slwi r6,r6,2
177#else
178 li r6, 0
179#endif
180 addis r6,r6,nap_save_hid1@ha
181 stw r4,nap_save_hid1@l(r6)
182
183 /* If switching to PLL0, enable HID0:BTIC */
184 cmplwi cr0,r3,0
185 bne 1f
186 mfspr r5,SPRN_HID0
187 ori r5,r5,HID0_BTIC
188 sync
189 mtspr SPRN_HID0,r5
190 isync
191 sync
192
1931:
194 /* Return */
195 mtmsr r7
196 blr
197
198_GLOBAL(low_choose_7447a_dfs)
199 /* Clear MSR:EE */
200 mfmsr r7
201 rlwinm r0,r7,0,17,15
202 mtmsr r0
203
204 /* Calc new HID1 value */
205 mfspr r4,SPRN_HID1
206 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
207 sync
208 mtspr SPRN_HID1,r4
209 sync
210 isync
211
212 /* Return */
213 mtmsr r7
214 blr
215
216#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
217
218/*
219 * complement mask on the msr then "or" some values on.
220 * _nmask_and_or_msr(nmask, value_to_or)
221 */
222_GLOBAL(_nmask_and_or_msr)
223 mfmsr r0 /* Get current msr */
224 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
225 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
226 SYNC /* Some chip revs have problems here... */
227 mtmsr r0 /* Update machine state */
228 isync
229 blr /* Done */
230
231#ifdef CONFIG_40x
232
233/*
234 * Do an IO access in real mode
235 */
236_GLOBAL(real_readb)
237 mfmsr r7
238 rlwinm r0,r7,0,~MSR_DR
239 sync
240 mtmsr r0
241 sync
242 isync
243 lbz r3,0(r3)
244 sync
245 mtmsr r7
246 sync
247 isync
248 blr
249_ASM_NOKPROBE_SYMBOL(real_readb)
250
251 /*
252 * Do an IO access in real mode
253 */
254_GLOBAL(real_writeb)
255 mfmsr r7
256 rlwinm r0,r7,0,~MSR_DR
257 sync
258 mtmsr r0
259 sync
260 isync
261 stb r3,0(r4)
262 sync
263 mtmsr r7
264 sync
265 isync
266 blr
267_ASM_NOKPROBE_SYMBOL(real_writeb)
268
269#endif /* CONFIG_40x */
270
271
272/*
273 * Flush instruction cache.
274 * This is a no-op on the 601.
275 */
276#ifndef CONFIG_PPC_8xx
277_GLOBAL(flush_instruction_cache)
278#if defined(CONFIG_4xx)
279 lis r3, KERNELBASE@h
280 iccci 0,r3
281#elif defined(CONFIG_FSL_BOOKE)
282#ifdef CONFIG_E200
283 mfspr r3,SPRN_L1CSR0
284 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
285 /* msync; isync recommended here */
286 mtspr SPRN_L1CSR0,r3
287 isync
288 blr
289#endif
290 mfspr r3,SPRN_L1CSR1
291 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
292 mtspr SPRN_L1CSR1,r3
293#elif defined(CONFIG_PPC_BOOK3S_601)
294 blr /* for 601, do nothing */
295#else
296 /* 603/604 processor - use invalidate-all bit in HID0 */
297 mfspr r3,SPRN_HID0
298 ori r3,r3,HID0_ICFI
299 mtspr SPRN_HID0,r3
300#endif /* CONFIG_4xx */
301 isync
302 blr
303EXPORT_SYMBOL(flush_instruction_cache)
304#endif /* CONFIG_PPC_8xx */
305
306/*
307 * Copy a whole page. We use the dcbz instruction on the destination
308 * to reduce memory traffic (it eliminates the unnecessary reads of
309 * the destination into cache). This requires that the destination
310 * is cacheable.
311 */
312#define COPY_16_BYTES \
313 lwz r6,4(r4); \
314 lwz r7,8(r4); \
315 lwz r8,12(r4); \
316 lwzu r9,16(r4); \
317 stw r6,4(r3); \
318 stw r7,8(r3); \
319 stw r8,12(r3); \
320 stwu r9,16(r3)
321
322_GLOBAL(copy_page)
323 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
324 addi r3,r3,-4
325
3260: twnei r5, 0 /* WARN if r3 is not cache aligned */
327 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
328
329 addi r4,r4,-4
330
331 li r5,4
332
333#if MAX_COPY_PREFETCH > 1
334 li r0,MAX_COPY_PREFETCH
335 li r11,4
336 mtctr r0
33711: dcbt r11,r4
338 addi r11,r11,L1_CACHE_BYTES
339 bdnz 11b
340#else /* MAX_COPY_PREFETCH == 1 */
341 dcbt r5,r4
342 li r11,L1_CACHE_BYTES+4
343#endif /* MAX_COPY_PREFETCH */
344 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
345 crclr 4*cr0+eq
3462:
347 mtctr r0
3481:
349 dcbt r11,r4
350 dcbz r5,r3
351 COPY_16_BYTES
352#if L1_CACHE_BYTES >= 32
353 COPY_16_BYTES
354#if L1_CACHE_BYTES >= 64
355 COPY_16_BYTES
356 COPY_16_BYTES
357#if L1_CACHE_BYTES >= 128
358 COPY_16_BYTES
359 COPY_16_BYTES
360 COPY_16_BYTES
361 COPY_16_BYTES
362#endif
363#endif
364#endif
365 bdnz 1b
366 beqlr
367 crnot 4*cr0+eq,4*cr0+eq
368 li r0,MAX_COPY_PREFETCH
369 li r11,4
370 b 2b
371EXPORT_SYMBOL(copy_page)
372
373/*
374 * Extended precision shifts.
375 *
376 * Updated to be valid for shift counts from 0 to 63 inclusive.
377 * -- Gabriel
378 *
379 * R3/R4 has 64 bit value
380 * R5 has shift count
381 * result in R3/R4
382 *
383 * ashrdi3: arithmetic right shift (sign propagation)
384 * lshrdi3: logical right shift
385 * ashldi3: left shift
386 */
387_GLOBAL(__ashrdi3)
388 subfic r6,r5,32
389 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
390 addi r7,r5,32 # could be xori, or addi with -32
391 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
392 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
393 sraw r7,r3,r7 # t2 = MSW >> (count-32)
394 or r4,r4,r6 # LSW |= t1
395 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
396 sraw r3,r3,r5 # MSW = MSW >> count
397 or r4,r4,r7 # LSW |= t2
398 blr
399EXPORT_SYMBOL(__ashrdi3)
400
401_GLOBAL(__ashldi3)
402 subfic r6,r5,32
403 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
404 addi r7,r5,32 # could be xori, or addi with -32
405 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
406 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
407 or r3,r3,r6 # MSW |= t1
408 slw r4,r4,r5 # LSW = LSW << count
409 or r3,r3,r7 # MSW |= t2
410 blr
411EXPORT_SYMBOL(__ashldi3)
412
413_GLOBAL(__lshrdi3)
414 subfic r6,r5,32
415 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
416 addi r7,r5,32 # could be xori, or addi with -32
417 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
418 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
419 or r4,r4,r6 # LSW |= t1
420 srw r3,r3,r5 # MSW = MSW >> count
421 or r4,r4,r7 # LSW |= t2
422 blr
423EXPORT_SYMBOL(__lshrdi3)
424
425/*
426 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
427 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
428 */
429_GLOBAL(__cmpdi2)
430 cmpw r3,r5
431 li r3,1
432 bne 1f
433 cmplw r4,r6
434 beqlr
4351: li r3,0
436 bltlr
437 li r3,2
438 blr
439EXPORT_SYMBOL(__cmpdi2)
440/*
441 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
442 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
443 */
444_GLOBAL(__ucmpdi2)
445 cmplw r3,r5
446 li r3,1
447 bne 1f
448 cmplw r4,r6
449 beqlr
4501: li r3,0
451 bltlr
452 li r3,2
453 blr
454EXPORT_SYMBOL(__ucmpdi2)
455
456_GLOBAL(__bswapdi2)
457 rotlwi r9,r4,8
458 rotlwi r10,r3,8
459 rlwimi r9,r4,24,0,7
460 rlwimi r10,r3,24,0,7
461 rlwimi r9,r4,24,16,23
462 rlwimi r10,r3,24,16,23
463 mr r3,r9
464 mr r4,r10
465 blr
466EXPORT_SYMBOL(__bswapdi2)
467
468#ifdef CONFIG_SMP
469_GLOBAL(start_secondary_resume)
470 /* Reset stack */
471 rlwinm r1, r1, 0, 0, 31 - THREAD_SHIFT
472 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
473 li r3,0
474 stw r3,0(r1) /* Zero the stack frame pointer */
475 bl start_secondary
476 b .
477#endif /* CONFIG_SMP */
478
479/*
480 * This routine is just here to keep GCC happy - sigh...
481 */
482_GLOBAL(__main)
483 blr
1/*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * kexec bits:
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 */
20
21#include <linux/sys.h>
22#include <asm/unistd.h>
23#include <asm/errno.h>
24#include <asm/reg.h>
25#include <asm/page.h>
26#include <asm/cache.h>
27#include <asm/cputable.h>
28#include <asm/mmu.h>
29#include <asm/ppc_asm.h>
30#include <asm/thread_info.h>
31#include <asm/asm-offsets.h>
32#include <asm/processor.h>
33#include <asm/kexec.h>
34#include <asm/bug.h>
35#include <asm/ptrace.h>
36
37 .text
38
39_GLOBAL(call_do_softirq)
40 mflr r0
41 stw r0,4(r1)
42 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
43 mr r1,r3
44 bl __do_softirq
45 lwz r1,0(r1)
46 lwz r0,4(r1)
47 mtlr r0
48 blr
49
50_GLOBAL(call_handle_irq)
51 mflr r0
52 stw r0,4(r1)
53 mtctr r6
54 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
55 mr r1,r5
56 bctrl
57 lwz r1,0(r1)
58 lwz r0,4(r1)
59 mtlr r0
60 blr
61
62/*
63 * This returns the high 64 bits of the product of two 64-bit numbers.
64 */
65_GLOBAL(mulhdu)
66 cmpwi r6,0
67 cmpwi cr1,r3,0
68 mr r10,r4
69 mulhwu r4,r4,r5
70 beq 1f
71 mulhwu r0,r10,r6
72 mullw r7,r10,r5
73 addc r7,r0,r7
74 addze r4,r4
751: beqlr cr1 /* all done if high part of A is 0 */
76 mr r10,r3
77 mullw r9,r3,r5
78 mulhwu r3,r3,r5
79 beq 2f
80 mullw r0,r10,r6
81 mulhwu r8,r10,r6
82 addc r7,r0,r7
83 adde r4,r4,r8
84 addze r3,r3
852: addc r4,r4,r9
86 addze r3,r3
87 blr
88
89/*
90 * sub_reloc_offset(x) returns x - reloc_offset().
91 */
92_GLOBAL(sub_reloc_offset)
93 mflr r0
94 bl 1f
951: mflr r5
96 lis r4,1b@ha
97 addi r4,r4,1b@l
98 subf r5,r4,r5
99 subf r3,r5,r3
100 mtlr r0
101 blr
102
103/*
104 * reloc_got2 runs through the .got2 section adding an offset
105 * to each entry.
106 */
107_GLOBAL(reloc_got2)
108 mflr r11
109 lis r7,__got2_start@ha
110 addi r7,r7,__got2_start@l
111 lis r8,__got2_end@ha
112 addi r8,r8,__got2_end@l
113 subf r8,r7,r8
114 srwi. r8,r8,2
115 beqlr
116 mtctr r8
117 bl 1f
1181: mflr r0
119 lis r4,1b@ha
120 addi r4,r4,1b@l
121 subf r0,r4,r0
122 add r7,r0,r7
1232: lwz r0,0(r7)
124 add r0,r0,r3
125 stw r0,0(r7)
126 addi r7,r7,4
127 bdnz 2b
128 mtlr r11
129 blr
130
131/*
132 * call_setup_cpu - call the setup_cpu function for this cpu
133 * r3 = data offset, r24 = cpu number
134 *
135 * Setup function is called with:
136 * r3 = data offset
137 * r4 = ptr to CPU spec (relocated)
138 */
139_GLOBAL(call_setup_cpu)
140 addis r4,r3,cur_cpu_spec@ha
141 addi r4,r4,cur_cpu_spec@l
142 lwz r4,0(r4)
143 add r4,r4,r3
144 lwz r5,CPU_SPEC_SETUP(r4)
145 cmpwi 0,r5,0
146 add r5,r5,r3
147 beqlr
148 mtctr r5
149 bctr
150
151#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
152
153/* This gets called by via-pmu.c to switch the PLL selection
154 * on 750fx CPU. This function should really be moved to some
155 * other place (as most of the cpufreq code in via-pmu
156 */
157_GLOBAL(low_choose_750fx_pll)
158 /* Clear MSR:EE */
159 mfmsr r7
160 rlwinm r0,r7,0,17,15
161 mtmsr r0
162
163 /* If switching to PLL1, disable HID0:BTIC */
164 cmplwi cr0,r3,0
165 beq 1f
166 mfspr r5,SPRN_HID0
167 rlwinm r5,r5,0,27,25
168 sync
169 mtspr SPRN_HID0,r5
170 isync
171 sync
172
1731:
174 /* Calc new HID1 value */
175 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
176 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
177 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
178 or r4,r4,r5
179 mtspr SPRN_HID1,r4
180
181 /* Store new HID1 image */
182 rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
183 lwz r6,TI_CPU(r6)
184 slwi r6,r6,2
185 addis r6,r6,nap_save_hid1@ha
186 stw r4,nap_save_hid1@l(r6)
187
188 /* If switching to PLL0, enable HID0:BTIC */
189 cmplwi cr0,r3,0
190 bne 1f
191 mfspr r5,SPRN_HID0
192 ori r5,r5,HID0_BTIC
193 sync
194 mtspr SPRN_HID0,r5
195 isync
196 sync
197
1981:
199 /* Return */
200 mtmsr r7
201 blr
202
203_GLOBAL(low_choose_7447a_dfs)
204 /* Clear MSR:EE */
205 mfmsr r7
206 rlwinm r0,r7,0,17,15
207 mtmsr r0
208
209 /* Calc new HID1 value */
210 mfspr r4,SPRN_HID1
211 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
212 sync
213 mtspr SPRN_HID1,r4
214 sync
215 isync
216
217 /* Return */
218 mtmsr r7
219 blr
220
221#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
222
223/*
224 * complement mask on the msr then "or" some values on.
225 * _nmask_and_or_msr(nmask, value_to_or)
226 */
227_GLOBAL(_nmask_and_or_msr)
228 mfmsr r0 /* Get current msr */
229 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
230 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
231 SYNC /* Some chip revs have problems here... */
232 mtmsr r0 /* Update machine state */
233 isync
234 blr /* Done */
235
236#ifdef CONFIG_40x
237
238/*
239 * Do an IO access in real mode
240 */
241_GLOBAL(real_readb)
242 mfmsr r7
243 ori r0,r7,MSR_DR
244 xori r0,r0,MSR_DR
245 sync
246 mtmsr r0
247 sync
248 isync
249 lbz r3,0(r3)
250 sync
251 mtmsr r7
252 sync
253 isync
254 blr
255
256 /*
257 * Do an IO access in real mode
258 */
259_GLOBAL(real_writeb)
260 mfmsr r7
261 ori r0,r7,MSR_DR
262 xori r0,r0,MSR_DR
263 sync
264 mtmsr r0
265 sync
266 isync
267 stb r3,0(r4)
268 sync
269 mtmsr r7
270 sync
271 isync
272 blr
273
274#endif /* CONFIG_40x */
275
276
277/*
278 * Flush instruction cache.
279 * This is a no-op on the 601.
280 */
281_GLOBAL(flush_instruction_cache)
282#if defined(CONFIG_8xx)
283 isync
284 lis r5, IDC_INVALL@h
285 mtspr SPRN_IC_CST, r5
286#elif defined(CONFIG_4xx)
287#ifdef CONFIG_403GCX
288 li r3, 512
289 mtctr r3
290 lis r4, KERNELBASE@h
2911: iccci 0, r4
292 addi r4, r4, 16
293 bdnz 1b
294#else
295 lis r3, KERNELBASE@h
296 iccci 0,r3
297#endif
298#elif CONFIG_FSL_BOOKE
299BEGIN_FTR_SECTION
300 mfspr r3,SPRN_L1CSR0
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
302 /* msync; isync recommended here */
303 mtspr SPRN_L1CSR0,r3
304 isync
305 blr
306END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
307 mfspr r3,SPRN_L1CSR1
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
309 mtspr SPRN_L1CSR1,r3
310#else
311 mfspr r3,SPRN_PVR
312 rlwinm r3,r3,16,16,31
313 cmpwi 0,r3,1
314 beqlr /* for 601, do nothing */
315 /* 603/604 processor - use invalidate-all bit in HID0 */
316 mfspr r3,SPRN_HID0
317 ori r3,r3,HID0_ICFI
318 mtspr SPRN_HID0,r3
319#endif /* CONFIG_8xx/4xx */
320 isync
321 blr
322
323/*
324 * Write any modified data cache blocks out to memory
325 * and invalidate the corresponding instruction cache blocks.
326 * This is a no-op on the 601.
327 *
328 * flush_icache_range(unsigned long start, unsigned long stop)
329 */
330_KPROBE(__flush_icache_range)
331BEGIN_FTR_SECTION
332 blr /* for 601, do nothing */
333END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
334 li r5,L1_CACHE_BYTES-1
335 andc r3,r3,r5
336 subf r4,r3,r4
337 add r4,r4,r5
338 srwi. r4,r4,L1_CACHE_SHIFT
339 beqlr
340 mtctr r4
341 mr r6,r3
3421: dcbst 0,r3
343 addi r3,r3,L1_CACHE_BYTES
344 bdnz 1b
345 sync /* wait for dcbst's to get to ram */
346#ifndef CONFIG_44x
347 mtctr r4
3482: icbi 0,r6
349 addi r6,r6,L1_CACHE_BYTES
350 bdnz 2b
351#else
352 /* Flash invalidate on 44x because we are passed kmapped addresses and
353 this doesn't work for userspace pages due to the virtually tagged
354 icache. Sigh. */
355 iccci 0, r0
356#endif
357 sync /* additional sync needed on g4 */
358 isync
359 blr
360/*
361 * Write any modified data cache blocks out to memory.
362 * Does not invalidate the corresponding cache lines (especially for
363 * any corresponding instruction cache).
364 *
365 * clean_dcache_range(unsigned long start, unsigned long stop)
366 */
367_GLOBAL(clean_dcache_range)
368 li r5,L1_CACHE_BYTES-1
369 andc r3,r3,r5
370 subf r4,r3,r4
371 add r4,r4,r5
372 srwi. r4,r4,L1_CACHE_SHIFT
373 beqlr
374 mtctr r4
375
3761: dcbst 0,r3
377 addi r3,r3,L1_CACHE_BYTES
378 bdnz 1b
379 sync /* wait for dcbst's to get to ram */
380 blr
381
382/*
383 * Write any modified data cache blocks out to memory and invalidate them.
384 * Does not invalidate the corresponding instruction cache blocks.
385 *
386 * flush_dcache_range(unsigned long start, unsigned long stop)
387 */
388_GLOBAL(flush_dcache_range)
389 li r5,L1_CACHE_BYTES-1
390 andc r3,r3,r5
391 subf r4,r3,r4
392 add r4,r4,r5
393 srwi. r4,r4,L1_CACHE_SHIFT
394 beqlr
395 mtctr r4
396
3971: dcbf 0,r3
398 addi r3,r3,L1_CACHE_BYTES
399 bdnz 1b
400 sync /* wait for dcbst's to get to ram */
401 blr
402
403/*
404 * Like above, but invalidate the D-cache. This is used by the 8xx
405 * to invalidate the cache so the PPC core doesn't get stale data
406 * from the CPM (no cache snooping here :-).
407 *
408 * invalidate_dcache_range(unsigned long start, unsigned long stop)
409 */
410_GLOBAL(invalidate_dcache_range)
411 li r5,L1_CACHE_BYTES-1
412 andc r3,r3,r5
413 subf r4,r3,r4
414 add r4,r4,r5
415 srwi. r4,r4,L1_CACHE_SHIFT
416 beqlr
417 mtctr r4
418
4191: dcbi 0,r3
420 addi r3,r3,L1_CACHE_BYTES
421 bdnz 1b
422 sync /* wait for dcbi's to get to ram */
423 blr
424
425/*
426 * Flush a particular page from the data cache to RAM.
427 * Note: this is necessary because the instruction cache does *not*
428 * snoop from the data cache.
429 * This is a no-op on the 601 which has a unified cache.
430 *
431 * void __flush_dcache_icache(void *page)
432 */
433_GLOBAL(__flush_dcache_icache)
434BEGIN_FTR_SECTION
435 blr
436END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
437 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
438 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
439 mtctr r4
440 mr r6,r3
4410: dcbst 0,r3 /* Write line to ram */
442 addi r3,r3,L1_CACHE_BYTES
443 bdnz 0b
444 sync
445#ifdef CONFIG_44x
446 /* We don't flush the icache on 44x. Those have a virtual icache
447 * and we don't have access to the virtual address here (it's
448 * not the page vaddr but where it's mapped in user space). The
449 * flushing of the icache on these is handled elsewhere, when
450 * a change in the address space occurs, before returning to
451 * user space
452 */
453BEGIN_MMU_FTR_SECTION
454 blr
455END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
456#endif /* CONFIG_44x */
457 mtctr r4
4581: icbi 0,r6
459 addi r6,r6,L1_CACHE_BYTES
460 bdnz 1b
461 sync
462 isync
463 blr
464
465#ifndef CONFIG_BOOKE
466/*
467 * Flush a particular page from the data cache to RAM, identified
468 * by its physical address. We turn off the MMU so we can just use
469 * the physical address (this may be a highmem page without a kernel
470 * mapping).
471 *
472 * void __flush_dcache_icache_phys(unsigned long physaddr)
473 */
474_GLOBAL(__flush_dcache_icache_phys)
475BEGIN_FTR_SECTION
476 blr /* for 601, do nothing */
477END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
478 mfmsr r10
479 rlwinm r0,r10,0,28,26 /* clear DR */
480 mtmsr r0
481 isync
482 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
483 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
484 mtctr r4
485 mr r6,r3
4860: dcbst 0,r3 /* Write line to ram */
487 addi r3,r3,L1_CACHE_BYTES
488 bdnz 0b
489 sync
490 mtctr r4
4911: icbi 0,r6
492 addi r6,r6,L1_CACHE_BYTES
493 bdnz 1b
494 sync
495 mtmsr r10 /* restore DR */
496 isync
497 blr
498#endif /* CONFIG_BOOKE */
499
500/*
501 * Clear pages using the dcbz instruction, which doesn't cause any
502 * memory traffic (except to write out any cache lines which get
503 * displaced). This only works on cacheable memory.
504 *
505 * void clear_pages(void *page, int order) ;
506 */
507_GLOBAL(clear_pages)
508 li r0,PAGE_SIZE/L1_CACHE_BYTES
509 slw r0,r0,r4
510 mtctr r0
5111: dcbz 0,r3
512 addi r3,r3,L1_CACHE_BYTES
513 bdnz 1b
514 blr
515
516/*
517 * Copy a whole page. We use the dcbz instruction on the destination
518 * to reduce memory traffic (it eliminates the unnecessary reads of
519 * the destination into cache). This requires that the destination
520 * is cacheable.
521 */
522#define COPY_16_BYTES \
523 lwz r6,4(r4); \
524 lwz r7,8(r4); \
525 lwz r8,12(r4); \
526 lwzu r9,16(r4); \
527 stw r6,4(r3); \
528 stw r7,8(r3); \
529 stw r8,12(r3); \
530 stwu r9,16(r3)
531
532_GLOBAL(copy_page)
533 addi r3,r3,-4
534 addi r4,r4,-4
535
536 li r5,4
537
538#if MAX_COPY_PREFETCH > 1
539 li r0,MAX_COPY_PREFETCH
540 li r11,4
541 mtctr r0
54211: dcbt r11,r4
543 addi r11,r11,L1_CACHE_BYTES
544 bdnz 11b
545#else /* MAX_COPY_PREFETCH == 1 */
546 dcbt r5,r4
547 li r11,L1_CACHE_BYTES+4
548#endif /* MAX_COPY_PREFETCH */
549 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
550 crclr 4*cr0+eq
5512:
552 mtctr r0
5531:
554 dcbt r11,r4
555 dcbz r5,r3
556 COPY_16_BYTES
557#if L1_CACHE_BYTES >= 32
558 COPY_16_BYTES
559#if L1_CACHE_BYTES >= 64
560 COPY_16_BYTES
561 COPY_16_BYTES
562#if L1_CACHE_BYTES >= 128
563 COPY_16_BYTES
564 COPY_16_BYTES
565 COPY_16_BYTES
566 COPY_16_BYTES
567#endif
568#endif
569#endif
570 bdnz 1b
571 beqlr
572 crnot 4*cr0+eq,4*cr0+eq
573 li r0,MAX_COPY_PREFETCH
574 li r11,4
575 b 2b
576
577/*
578 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
579 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
580 */
581_GLOBAL(atomic_clear_mask)
58210: lwarx r5,0,r4
583 andc r5,r5,r3
584 PPC405_ERR77(0,r4)
585 stwcx. r5,0,r4
586 bne- 10b
587 blr
588_GLOBAL(atomic_set_mask)
58910: lwarx r5,0,r4
590 or r5,r5,r3
591 PPC405_ERR77(0,r4)
592 stwcx. r5,0,r4
593 bne- 10b
594 blr
595
596/*
597 * Extended precision shifts.
598 *
599 * Updated to be valid for shift counts from 0 to 63 inclusive.
600 * -- Gabriel
601 *
602 * R3/R4 has 64 bit value
603 * R5 has shift count
604 * result in R3/R4
605 *
606 * ashrdi3: arithmetic right shift (sign propagation)
607 * lshrdi3: logical right shift
608 * ashldi3: left shift
609 */
610_GLOBAL(__ashrdi3)
611 subfic r6,r5,32
612 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
613 addi r7,r5,32 # could be xori, or addi with -32
614 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
615 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
616 sraw r7,r3,r7 # t2 = MSW >> (count-32)
617 or r4,r4,r6 # LSW |= t1
618 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
619 sraw r3,r3,r5 # MSW = MSW >> count
620 or r4,r4,r7 # LSW |= t2
621 blr
622
623_GLOBAL(__ashldi3)
624 subfic r6,r5,32
625 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
626 addi r7,r5,32 # could be xori, or addi with -32
627 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
628 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
629 or r3,r3,r6 # MSW |= t1
630 slw r4,r4,r5 # LSW = LSW << count
631 or r3,r3,r7 # MSW |= t2
632 blr
633
634_GLOBAL(__lshrdi3)
635 subfic r6,r5,32
636 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
637 addi r7,r5,32 # could be xori, or addi with -32
638 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
639 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
640 or r4,r4,r6 # LSW |= t1
641 srw r3,r3,r5 # MSW = MSW >> count
642 or r4,r4,r7 # LSW |= t2
643 blr
644
645/*
646 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
647 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
648 */
649_GLOBAL(__ucmpdi2)
650 cmplw r3,r5
651 li r3,1
652 bne 1f
653 cmplw r4,r6
654 beqlr
6551: li r3,0
656 bltlr
657 li r3,2
658 blr
659
660_GLOBAL(abs)
661 srawi r4,r3,31
662 xor r3,r3,r4
663 sub r3,r3,r4
664 blr
665
666/*
667 * Create a kernel thread
668 * kernel_thread(fn, arg, flags)
669 */
670_GLOBAL(kernel_thread)
671 stwu r1,-16(r1)
672 stw r30,8(r1)
673 stw r31,12(r1)
674 mr r30,r3 /* function */
675 mr r31,r4 /* argument */
676 ori r3,r5,CLONE_VM /* flags */
677 oris r3,r3,CLONE_UNTRACED>>16
678 li r4,0 /* new sp (unused) */
679 li r0,__NR_clone
680 sc
681 bns+ 1f /* did system call indicate error? */
682 neg r3,r3 /* if so, make return code negative */
6831: cmpwi 0,r3,0 /* parent or child? */
684 bne 2f /* return if parent */
685 li r0,0 /* make top-level stack frame */
686 stwu r0,-16(r1)
687 mtlr r30 /* fn addr in lr */
688 mr r3,r31 /* load arg and call fn */
689 PPC440EP_ERR42
690 blrl
691 li r0,__NR_exit /* exit if function returns */
692 li r3,0
693 sc
6942: lwz r30,8(r1)
695 lwz r31,12(r1)
696 addi r1,r1,16
697 blr
698
699#ifdef CONFIG_SMP
700_GLOBAL(start_secondary_resume)
701 /* Reset stack */
702 rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
703 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
704 li r3,0
705 stw r3,0(r1) /* Zero the stack frame pointer */
706 bl start_secondary
707 b .
708#endif /* CONFIG_SMP */
709
710/*
711 * This routine is just here to keep GCC happy - sigh...
712 */
713_GLOBAL(__main)
714 blr
715
716#ifdef CONFIG_KEXEC
717 /*
718 * Must be relocatable PIC code callable as a C function.
719 */
720 .globl relocate_new_kernel
721relocate_new_kernel:
722 /* r3 = page_list */
723 /* r4 = reboot_code_buffer */
724 /* r5 = start_address */
725
726#ifdef CONFIG_FSL_BOOKE
727
728 mr r29, r3
729 mr r30, r4
730 mr r31, r5
731
732#define ENTRY_MAPPING_KEXEC_SETUP
733#include "fsl_booke_entry_mapping.S"
734#undef ENTRY_MAPPING_KEXEC_SETUP
735
736 mr r3, r29
737 mr r4, r30
738 mr r5, r31
739
740 li r0, 0
741#elif defined(CONFIG_44x)
742
743 /* Save our parameters */
744 mr r29, r3
745 mr r30, r4
746 mr r31, r5
747
748#ifdef CONFIG_PPC_47x
749 /* Check for 47x cores */
750 mfspr r3,SPRN_PVR
751 srwi r3,r3,16
752 cmplwi cr0,r3,PVR_476@h
753 beq setup_map_47x
754 cmplwi cr0,r3,PVR_476_ISS@h
755 beq setup_map_47x
756#endif /* CONFIG_PPC_47x */
757
758/*
759 * Code for setting up 1:1 mapping for PPC440x for KEXEC
760 *
761 * We cannot switch off the MMU on PPC44x.
762 * So we:
763 * 1) Invalidate all the mappings except the one we are running from.
764 * 2) Create a tmp mapping for our code in the other address space(TS) and
765 * jump to it. Invalidate the entry we started in.
766 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
767 * 4) Jump to the 1:1 mapping in original TS.
768 * 5) Invalidate the tmp mapping.
769 *
770 * - Based on the kexec support code for FSL BookE
771 *
772 */
773
774 /*
775 * Load the PID with kernel PID (0).
776 * Also load our MSR_IS and TID to MMUCR for TLB search.
777 */
778 li r3, 0
779 mtspr SPRN_PID, r3
780 mfmsr r4
781 andi. r4,r4,MSR_IS@l
782 beq wmmucr
783 oris r3,r3,PPC44x_MMUCR_STS@h
784wmmucr:
785 mtspr SPRN_MMUCR,r3
786 sync
787
788 /*
789 * Invalidate all the TLB entries except the current entry
790 * where we are running from
791 */
792 bl 0f /* Find our address */
7930: mflr r5 /* Make it accessible */
794 tlbsx r23,0,r5 /* Find entry we are in */
795 li r4,0 /* Start at TLB entry 0 */
796 li r3,0 /* Set PAGEID inval value */
7971: cmpw r23,r4 /* Is this our entry? */
798 beq skip /* If so, skip the inval */
799 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
800skip:
801 addi r4,r4,1 /* Increment */
802 cmpwi r4,64 /* Are we done? */
803 bne 1b /* If not, repeat */
804 isync
805
806 /* Create a temp mapping and jump to it */
807 andi. r6, r23, 1 /* Find the index to use */
808 addi r24, r6, 1 /* r24 will contain 1 or 2 */
809
810 mfmsr r9 /* get the MSR */
811 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
812 xori r7, r5, 1 /* Use the other address space */
813
814 /* Read the current mapping entries */
815 tlbre r3, r23, PPC44x_TLB_PAGEID
816 tlbre r4, r23, PPC44x_TLB_XLAT
817 tlbre r5, r23, PPC44x_TLB_ATTRIB
818
819 /* Save our current XLAT entry */
820 mr r25, r4
821
822 /* Extract the TLB PageSize */
823 li r10, 1 /* r10 will hold PageSize */
824 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
825
826 /* XXX: As of now we use 256M, 4K pages */
827 cmpwi r11, PPC44x_TLB_256M
828 bne tlb_4k
829 rotlwi r10, r10, 28 /* r10 = 256M */
830 b write_out
831tlb_4k:
832 cmpwi r11, PPC44x_TLB_4K
833 bne default
834 rotlwi r10, r10, 12 /* r10 = 4K */
835 b write_out
836default:
837 rotlwi r10, r10, 10 /* r10 = 1K */
838
839write_out:
840 /*
841 * Write out the tmp 1:1 mapping for this code in other address space
842 * Fixup EPN = RPN , TS=other address space
843 */
844 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
845
846 /* Write out the tmp mapping entries */
847 tlbwe r3, r24, PPC44x_TLB_PAGEID
848 tlbwe r4, r24, PPC44x_TLB_XLAT
849 tlbwe r5, r24, PPC44x_TLB_ATTRIB
850
851 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
852 not r10, r11 /* Mask for PageNum */
853
854 /* Switch to other address space in MSR */
855 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
856
857 bl 1f
8581: mflr r8
859 addi r8, r8, (2f-1b) /* Find the target offset */
860
861 /* Jump to the tmp mapping */
862 mtspr SPRN_SRR0, r8
863 mtspr SPRN_SRR1, r9
864 rfi
865
8662:
867 /* Invalidate the entry we were executing from */
868 li r3, 0
869 tlbwe r3, r23, PPC44x_TLB_PAGEID
870
871 /* attribute fields. rwx for SUPERVISOR mode */
872 li r5, 0
873 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
874
875 /* Create 1:1 mapping in 256M pages */
876 xori r7, r7, 1 /* Revert back to Original TS */
877
878 li r8, 0 /* PageNumber */
879 li r6, 3 /* TLB Index, start at 3 */
880
881next_tlb:
882 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
883 mr r4, r3 /* RPN = EPN */
884 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
885 insrwi r3, r7, 1, 23 /* Set TS from r7 */
886
887 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
888 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
889 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
890
891 addi r8, r8, 1 /* Increment PN */
892 addi r6, r6, 1 /* Increment TLB Index */
893 cmpwi r8, 8 /* Are we done ? */
894 bne next_tlb
895 isync
896
897 /* Jump to the new mapping 1:1 */
898 li r9,0
899 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
900
901 bl 1f
9021: mflr r8
903 and r8, r8, r11 /* Get our offset within page */
904 addi r8, r8, (2f-1b)
905
906 and r5, r25, r10 /* Get our target PageNum */
907 or r8, r8, r5 /* Target jump address */
908
909 mtspr SPRN_SRR0, r8
910 mtspr SPRN_SRR1, r9
911 rfi
9122:
913 /* Invalidate the tmp entry we used */
914 li r3, 0
915 tlbwe r3, r24, PPC44x_TLB_PAGEID
916 sync
917 b ppc44x_map_done
918
919#ifdef CONFIG_PPC_47x
920
921 /* 1:1 mapping for 47x */
922
923setup_map_47x:
924
925 /*
926 * Load the kernel pid (0) to PID and also to MMUCR[TID].
927 * Also set the MSR IS->MMUCR STS
928 */
929 li r3, 0
930 mtspr SPRN_PID, r3 /* Set PID */
931 mfmsr r4 /* Get MSR */
932 andi. r4, r4, MSR_IS@l /* TS=1? */
933 beq 1f /* If not, leave STS=0 */
934 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
9351: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
936 sync
937
938 /* Find the entry we are running from */
939 bl 2f
9402: mflr r23
941 tlbsx r23, 0, r23
942 tlbre r24, r23, 0 /* TLB Word 0 */
943 tlbre r25, r23, 1 /* TLB Word 1 */
944 tlbre r26, r23, 2 /* TLB Word 2 */
945
946
947 /*
948 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
949 * of 4k page size in all 4 ways (0-3 in r3).
950 * This would invalidate the entire UTLB including the one we are
951 * running from. However the shadow TLB entries would help us
952 * to continue the execution, until we flush them (rfi/isync).
953 */
954 addis r3, 0, 0x8000 /* specify the way */
955 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
956 addi r5, 0, 0
957 b clear_utlb_entry
958
959 /* Align the loop to speed things up. from head_44x.S */
960 .align 6
961
962clear_utlb_entry:
963
964 tlbwe r4, r3, 0
965 tlbwe r5, r3, 1
966 tlbwe r5, r3, 2
967 addis r3, r3, 0x2000 /* Increment the way */
968 cmpwi r3, 0
969 bne clear_utlb_entry
970 addis r3, 0, 0x8000
971 addis r4, r4, 0x100 /* Increment the EPN */
972 cmpwi r4, 0
973 bne clear_utlb_entry
974
975 /* Create the entries in the other address space */
976 mfmsr r5
977 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
978 xori r7, r7, 1 /* r7 = !TS */
979
980 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
981
982 /*
983 * write out the TLB entries for the tmp mapping
984 * Use way '0' so that we could easily invalidate it later.
985 */
986 lis r3, 0x8000 /* Way '0' */
987
988 tlbwe r24, r3, 0
989 tlbwe r25, r3, 1
990 tlbwe r26, r3, 2
991
992 /* Update the msr to the new TS */
993 insrwi r5, r7, 1, 26
994
995 bl 1f
9961: mflr r6
997 addi r6, r6, (2f-1b)
998
999 mtspr SPRN_SRR0, r6
1000 mtspr SPRN_SRR1, r5
1001 rfi
1002
1003 /*
1004 * Now we are in the tmp address space.
1005 * Create a 1:1 mapping for 0-2GiB in the original TS.
1006 */
10072:
1008 li r3, 0
1009 li r4, 0 /* TLB Word 0 */
1010 li r5, 0 /* TLB Word 1 */
1011 li r6, 0
1012 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
1013
1014 li r8, 0 /* PageIndex */
1015
1016 xori r7, r7, 1 /* revert back to original TS */
1017
1018write_utlb:
1019 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
1020 /* ERPN = 0 as we don't use memory above 2G */
1021
1022 mr r4, r5 /* EPN = RPN */
1023 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1024 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1025
1026 tlbwe r4, r3, 0 /* Write out the entries */
1027 tlbwe r5, r3, 1
1028 tlbwe r6, r3, 2
1029 addi r8, r8, 1
1030 cmpwi r8, 8 /* Have we completed ? */
1031 bne write_utlb
1032
1033 /* make sure we complete the TLB write up */
1034 isync
1035
1036 /*
1037 * Prepare to jump to the 1:1 mapping.
1038 * 1) Extract page size of the tmp mapping
1039 * DSIZ = TLB_Word0[22:27]
1040 * 2) Calculate the physical address of the address
1041 * to jump to.
1042 */
1043 rlwinm r10, r24, 0, 22, 27
1044
1045 cmpwi r10, PPC47x_TLB0_4K
1046 bne 0f
1047 li r10, 0x1000 /* r10 = 4k */
1048 bl 1f
1049
10500:
1051 /* Defaults to 256M */
1052 lis r10, 0x1000
1053
1054 bl 1f
10551: mflr r4
1056 addi r4, r4, (2f-1b) /* virtual address of 2f */
1057
1058 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
1059 not r10, r11 /* Pagemask = ~(offsetmask) */
1060
1061 and r5, r25, r10 /* Physical page */
1062 and r6, r4, r11 /* offset within the current page */
1063
1064 or r5, r5, r6 /* Physical address for 2f */
1065
1066 /* Switch the TS in MSR to the original one */
1067 mfmsr r8
1068 insrwi r8, r7, 1, 26
1069
1070 mtspr SPRN_SRR1, r8
1071 mtspr SPRN_SRR0, r5
1072 rfi
1073
10742:
1075 /* Invalidate the tmp mapping */
1076 lis r3, 0x8000 /* Way '0' */
1077
1078 clrrwi r24, r24, 12 /* Clear the valid bit */
1079 tlbwe r24, r3, 0
1080 tlbwe r25, r3, 1
1081 tlbwe r26, r3, 2
1082
1083 /* Make sure we complete the TLB write and flush the shadow TLB */
1084 isync
1085
1086#endif
1087
1088ppc44x_map_done:
1089
1090
1091 /* Restore the parameters */
1092 mr r3, r29
1093 mr r4, r30
1094 mr r5, r31
1095
1096 li r0, 0
1097#else
1098 li r0, 0
1099
1100 /*
1101 * Set Machine Status Register to a known status,
1102 * switch the MMU off and jump to 1: in a single step.
1103 */
1104
1105 mr r8, r0
1106 ori r8, r8, MSR_RI|MSR_ME
1107 mtspr SPRN_SRR1, r8
1108 addi r8, r4, 1f - relocate_new_kernel
1109 mtspr SPRN_SRR0, r8
1110 sync
1111 rfi
1112
11131:
1114#endif
1115 /* from this point address translation is turned off */
1116 /* and interrupts are disabled */
1117
1118 /* set a new stack at the bottom of our page... */
1119 /* (not really needed now) */
1120 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1121 stw r0, 0(r1)
1122
1123 /* Do the copies */
1124 li r6, 0 /* checksum */
1125 mr r0, r3
1126 b 1f
1127
11280: /* top, read another word for the indirection page */
1129 lwzu r0, 4(r3)
1130
11311:
1132 /* is it a destination page? (r8) */
1133 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1134 beq 2f
1135
1136 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1137 b 0b
1138
11392: /* is it an indirection page? (r3) */
1140 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1141 beq 2f
1142
1143 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1144 subi r3, r3, 4
1145 b 0b
1146
11472: /* are we done? */
1148 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1149 beq 2f
1150 b 3f
1151
11522: /* is it a source page? (r9) */
1153 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1154 beq 0b
1155
1156 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1157
1158 li r7, PAGE_SIZE / 4
1159 mtctr r7
1160 subi r9, r9, 4
1161 subi r8, r8, 4
11629:
1163 lwzu r0, 4(r9) /* do the copy */
1164 xor r6, r6, r0
1165 stwu r0, 4(r8)
1166 dcbst 0, r8
1167 sync
1168 icbi 0, r8
1169 bdnz 9b
1170
1171 addi r9, r9, 4
1172 addi r8, r8, 4
1173 b 0b
1174
11753:
1176
1177 /* To be certain of avoiding problems with self-modifying code
1178 * execute a serializing instruction here.
1179 */
1180 isync
1181 sync
1182
1183 mfspr r3, SPRN_PIR /* current core we are running on */
1184 mr r4, r5 /* load physical address of chunk called */
1185
1186 /* jump to the entry point, usually the setup routine */
1187 mtlr r5
1188 blrl
1189
11901: b 1b
1191
1192relocate_new_kernel_end:
1193
1194 .globl relocate_new_kernel_size
1195relocate_new_kernel_size:
1196 .long relocate_new_kernel_end - relocate_new_kernel
1197#endif