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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SMP boot-related support
4 *
5 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 2001, 2004-2005 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Ashok Raj <ashok.raj@intel.com>
12 *
13 * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
14 * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
15 * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
16 * smp_boot_cpus()/smp_commence() is replaced by
17 * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
18 * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
19 * 04/12/26 Jin Gordon <gordon.jin@intel.com>
20 * 04/12/26 Rohit Seth <rohit.seth@intel.com>
21 * Add multi-threading and multi-core detection
22 * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
23 * Setup cpu_sibling_map and cpu_core_map
24 */
25
26#include <linux/module.h>
27#include <linux/acpi.h>
28#include <linux/memblock.h>
29#include <linux/cpu.h>
30#include <linux/delay.h>
31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/irq.h>
34#include <linux/kernel.h>
35#include <linux/kernel_stat.h>
36#include <linux/mm.h>
37#include <linux/notifier.h>
38#include <linux/smp.h>
39#include <linux/spinlock.h>
40#include <linux/efi.h>
41#include <linux/percpu.h>
42#include <linux/bitops.h>
43
44#include <linux/atomic.h>
45#include <asm/cache.h>
46#include <asm/current.h>
47#include <asm/delay.h>
48#include <asm/io.h>
49#include <asm/irq.h>
50#include <asm/mca.h>
51#include <asm/page.h>
52#include <asm/processor.h>
53#include <asm/ptrace.h>
54#include <asm/sal.h>
55#include <asm/tlbflush.h>
56#include <asm/unistd.h>
57
58#define SMP_DEBUG 0
59
60#if SMP_DEBUG
61#define Dprintk(x...) printk(x)
62#else
63#define Dprintk(x...)
64#endif
65
66#ifdef CONFIG_HOTPLUG_CPU
67#ifdef CONFIG_PERMIT_BSP_REMOVE
68#define bsp_remove_ok 1
69#else
70#define bsp_remove_ok 0
71#endif
72
73/*
74 * Global array allocated for NR_CPUS at boot time
75 */
76struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
77
78/*
79 * start_ap in head.S uses this to store current booting cpu
80 * info.
81 */
82struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
83
84#define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
85
86#else
87#define set_brendez_area(x)
88#endif
89
90
91/*
92 * ITC synchronization related stuff:
93 */
94#define MASTER (0)
95#define SLAVE (SMP_CACHE_BYTES/8)
96
97#define NUM_ROUNDS 64 /* magic value */
98#define NUM_ITERS 5 /* likewise */
99
100static DEFINE_SPINLOCK(itc_sync_lock);
101static volatile unsigned long go[SLAVE + 1];
102
103#define DEBUG_ITC_SYNC 0
104
105extern void start_ap (void);
106extern unsigned long ia64_iobase;
107
108struct task_struct *task_for_booting_cpu;
109
110/*
111 * State for each CPU
112 */
113DEFINE_PER_CPU(int, cpu_state);
114
115cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
116EXPORT_SYMBOL(cpu_core_map);
117DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
118EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
119
120int smp_num_siblings = 1;
121
122/* which logical CPU number maps to which CPU (physical APIC ID) */
123volatile int ia64_cpu_to_sapicid[NR_CPUS];
124EXPORT_SYMBOL(ia64_cpu_to_sapicid);
125
126static cpumask_t cpu_callin_map;
127
128struct smp_boot_data smp_boot_data __initdata;
129
130unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
131
132char __initdata no_int_routing;
133
134unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
135
136#ifdef CONFIG_FORCE_CPEI_RETARGET
137#define CPEI_OVERRIDE_DEFAULT (1)
138#else
139#define CPEI_OVERRIDE_DEFAULT (0)
140#endif
141
142unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
143
144static int __init
145cmdl_force_cpei(char *str)
146{
147 int value=0;
148
149 get_option (&str, &value);
150 force_cpei_retarget = value;
151
152 return 1;
153}
154
155__setup("force_cpei=", cmdl_force_cpei);
156
157static int __init
158nointroute (char *str)
159{
160 no_int_routing = 1;
161 printk ("no_int_routing on\n");
162 return 1;
163}
164
165__setup("nointroute", nointroute);
166
167static void fix_b0_for_bsp(void)
168{
169#ifdef CONFIG_HOTPLUG_CPU
170 int cpuid;
171 static int fix_bsp_b0 = 1;
172
173 cpuid = smp_processor_id();
174
175 /*
176 * Cache the b0 value on the first AP that comes up
177 */
178 if (!(fix_bsp_b0 && cpuid))
179 return;
180
181 sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
182 printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
183
184 fix_bsp_b0 = 0;
185#endif
186}
187
188void
189sync_master (void *arg)
190{
191 unsigned long flags, i;
192
193 go[MASTER] = 0;
194
195 local_irq_save(flags);
196 {
197 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
198 while (!go[MASTER])
199 cpu_relax();
200 go[MASTER] = 0;
201 go[SLAVE] = ia64_get_itc();
202 }
203 }
204 local_irq_restore(flags);
205}
206
207/*
208 * Return the number of cycles by which our itc differs from the itc on the master
209 * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
210 * negative that it is behind.
211 */
212static inline long
213get_delta (long *rt, long *master)
214{
215 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
216 unsigned long tcenter, t0, t1, tm;
217 long i;
218
219 for (i = 0; i < NUM_ITERS; ++i) {
220 t0 = ia64_get_itc();
221 go[MASTER] = 1;
222 while (!(tm = go[SLAVE]))
223 cpu_relax();
224 go[SLAVE] = 0;
225 t1 = ia64_get_itc();
226
227 if (t1 - t0 < best_t1 - best_t0)
228 best_t0 = t0, best_t1 = t1, best_tm = tm;
229 }
230
231 *rt = best_t1 - best_t0;
232 *master = best_tm - best_t0;
233
234 /* average best_t0 and best_t1 without overflow: */
235 tcenter = (best_t0/2 + best_t1/2);
236 if (best_t0 % 2 + best_t1 % 2 == 2)
237 ++tcenter;
238 return tcenter - best_tm;
239}
240
241/*
242 * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
243 * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
244 * unaccounted-for errors (such as getting a machine check in the middle of a calibration
245 * step). The basic idea is for the slave to ask the master what itc value it has and to
246 * read its own itc before and after the master responds. Each iteration gives us three
247 * timestamps:
248 *
249 * slave master
250 *
251 * t0 ---\
252 * ---\
253 * --->
254 * tm
255 * /---
256 * /---
257 * t1 <---
258 *
259 *
260 * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
261 * and t1. If we achieve this, the clocks are synchronized provided the interconnect
262 * between the slave and the master is symmetric. Even if the interconnect were
263 * asymmetric, we would still know that the synchronization error is smaller than the
264 * roundtrip latency (t0 - t1).
265 *
266 * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
267 * within one or two cycles. However, we can only *guarantee* that the synchronization is
268 * accurate to within a round-trip time, which is typically in the range of several
269 * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
270 * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
271 * than half a micro second or so.
272 */
273void
274ia64_sync_itc (unsigned int master)
275{
276 long i, delta, adj, adjust_latency = 0, done = 0;
277 unsigned long flags, rt, master_time_stamp, bound;
278#if DEBUG_ITC_SYNC
279 struct {
280 long rt; /* roundtrip time */
281 long master; /* master's timestamp */
282 long diff; /* difference between midpoint and master's timestamp */
283 long lat; /* estimate of itc adjustment latency */
284 } t[NUM_ROUNDS];
285#endif
286
287 /*
288 * Make sure local timer ticks are disabled while we sync. If
289 * they were enabled, we'd have to worry about nasty issues
290 * like setting the ITC ahead of (or a long time before) the
291 * next scheduled tick.
292 */
293 BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
294
295 go[MASTER] = 1;
296
297 if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
298 printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
299 return;
300 }
301
302 while (go[MASTER])
303 cpu_relax(); /* wait for master to be ready */
304
305 spin_lock_irqsave(&itc_sync_lock, flags);
306 {
307 for (i = 0; i < NUM_ROUNDS; ++i) {
308 delta = get_delta(&rt, &master_time_stamp);
309 if (delta == 0) {
310 done = 1; /* let's lock on to this... */
311 bound = rt;
312 }
313
314 if (!done) {
315 if (i > 0) {
316 adjust_latency += -delta;
317 adj = -delta + adjust_latency/4;
318 } else
319 adj = -delta;
320
321 ia64_set_itc(ia64_get_itc() + adj);
322 }
323#if DEBUG_ITC_SYNC
324 t[i].rt = rt;
325 t[i].master = master_time_stamp;
326 t[i].diff = delta;
327 t[i].lat = adjust_latency/4;
328#endif
329 }
330 }
331 spin_unlock_irqrestore(&itc_sync_lock, flags);
332
333#if DEBUG_ITC_SYNC
334 for (i = 0; i < NUM_ROUNDS; ++i)
335 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
336 t[i].rt, t[i].master, t[i].diff, t[i].lat);
337#endif
338
339 printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
340 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
341}
342
343/*
344 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
345 */
346static inline void smp_setup_percpu_timer(void)
347{
348}
349
350static void
351smp_callin (void)
352{
353 int cpuid, phys_id, itc_master;
354 struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
355 extern void ia64_init_itm(void);
356 extern volatile int time_keeper_id;
357
358#ifdef CONFIG_PERFMON
359 extern void pfm_init_percpu(void);
360#endif
361
362 cpuid = smp_processor_id();
363 phys_id = hard_smp_processor_id();
364 itc_master = time_keeper_id;
365
366 if (cpu_online(cpuid)) {
367 printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
368 phys_id, cpuid);
369 BUG();
370 }
371
372 fix_b0_for_bsp();
373
374 /*
375 * numa_node_id() works after this.
376 */
377 set_numa_node(cpu_to_node_map[cpuid]);
378 set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
379
380 spin_lock(&vector_lock);
381 /* Setup the per cpu irq handling data structures */
382 __setup_vector_irq(cpuid);
383 notify_cpu_starting(cpuid);
384 set_cpu_online(cpuid, true);
385 per_cpu(cpu_state, cpuid) = CPU_ONLINE;
386 spin_unlock(&vector_lock);
387
388 smp_setup_percpu_timer();
389
390 ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
391
392#ifdef CONFIG_PERFMON
393 pfm_init_percpu();
394#endif
395
396 local_irq_enable();
397
398 if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
399 /*
400 * Synchronize the ITC with the BP. Need to do this after irqs are
401 * enabled because ia64_sync_itc() calls smp_call_function_single(), which
402 * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
403 * local_bh_enable(), which bugs out if irqs are not enabled...
404 */
405 Dprintk("Going to syncup ITC with ITC Master.\n");
406 ia64_sync_itc(itc_master);
407 }
408
409 /*
410 * Get our bogomips.
411 */
412 ia64_init_itm();
413
414 /*
415 * Delay calibration can be skipped if new processor is identical to the
416 * previous processor.
417 */
418 last_cpuinfo = cpu_data(cpuid - 1);
419 this_cpuinfo = local_cpu_data;
420 if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
421 last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
422 last_cpuinfo->features != this_cpuinfo->features ||
423 last_cpuinfo->revision != this_cpuinfo->revision ||
424 last_cpuinfo->family != this_cpuinfo->family ||
425 last_cpuinfo->archrev != this_cpuinfo->archrev ||
426 last_cpuinfo->model != this_cpuinfo->model)
427 calibrate_delay();
428 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
429
430 /*
431 * Allow the master to continue.
432 */
433 cpumask_set_cpu(cpuid, &cpu_callin_map);
434 Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
435}
436
437
438/*
439 * Activate a secondary processor. head.S calls this.
440 */
441int
442start_secondary (void *unused)
443{
444 /* Early console may use I/O ports */
445 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
446#ifndef CONFIG_PRINTK_TIME
447 Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
448#endif
449 efi_map_pal_code();
450 cpu_init();
451 preempt_disable();
452 smp_callin();
453
454 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
455 return 0;
456}
457
458static int
459do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
460{
461 int timeout;
462
463 task_for_booting_cpu = idle;
464 Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
465
466 set_brendez_area(cpu);
467 ia64_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
468
469 /*
470 * Wait 10s total for the AP to start
471 */
472 Dprintk("Waiting on callin_map ...");
473 for (timeout = 0; timeout < 100000; timeout++) {
474 if (cpumask_test_cpu(cpu, &cpu_callin_map))
475 break; /* It has booted */
476 barrier(); /* Make sure we re-read cpu_callin_map */
477 udelay(100);
478 }
479 Dprintk("\n");
480
481 if (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
482 printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
483 ia64_cpu_to_sapicid[cpu] = -1;
484 set_cpu_online(cpu, false); /* was set in smp_callin() */
485 return -EINVAL;
486 }
487 return 0;
488}
489
490static int __init
491decay (char *str)
492{
493 int ticks;
494 get_option (&str, &ticks);
495 return 1;
496}
497
498__setup("decay=", decay);
499
500/*
501 * Initialize the logical CPU number to SAPICID mapping
502 */
503void __init
504smp_build_cpu_map (void)
505{
506 int sapicid, cpu, i;
507 int boot_cpu_id = hard_smp_processor_id();
508
509 for (cpu = 0; cpu < NR_CPUS; cpu++) {
510 ia64_cpu_to_sapicid[cpu] = -1;
511 }
512
513 ia64_cpu_to_sapicid[0] = boot_cpu_id;
514 init_cpu_present(cpumask_of(0));
515 set_cpu_possible(0, true);
516 for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
517 sapicid = smp_boot_data.cpu_phys_id[i];
518 if (sapicid == boot_cpu_id)
519 continue;
520 set_cpu_present(cpu, true);
521 set_cpu_possible(cpu, true);
522 ia64_cpu_to_sapicid[cpu] = sapicid;
523 cpu++;
524 }
525}
526
527/*
528 * Cycle through the APs sending Wakeup IPIs to boot each.
529 */
530void __init
531smp_prepare_cpus (unsigned int max_cpus)
532{
533 int boot_cpu_id = hard_smp_processor_id();
534
535 /*
536 * Initialize the per-CPU profiling counter/multiplier
537 */
538
539 smp_setup_percpu_timer();
540
541 cpumask_set_cpu(0, &cpu_callin_map);
542
543 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
544 ia64_cpu_to_sapicid[0] = boot_cpu_id;
545
546 printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
547
548 current_thread_info()->cpu = 0;
549
550 /*
551 * If SMP should be disabled, then really disable it!
552 */
553 if (!max_cpus) {
554 printk(KERN_INFO "SMP mode deactivated.\n");
555 init_cpu_online(cpumask_of(0));
556 init_cpu_present(cpumask_of(0));
557 init_cpu_possible(cpumask_of(0));
558 return;
559 }
560}
561
562void smp_prepare_boot_cpu(void)
563{
564 set_cpu_online(smp_processor_id(), true);
565 cpumask_set_cpu(smp_processor_id(), &cpu_callin_map);
566 set_numa_node(cpu_to_node_map[smp_processor_id()]);
567 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
568}
569
570#ifdef CONFIG_HOTPLUG_CPU
571static inline void
572clear_cpu_sibling_map(int cpu)
573{
574 int i;
575
576 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
577 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
578 for_each_cpu(i, &cpu_core_map[cpu])
579 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
580
581 per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
582}
583
584static void
585remove_siblinginfo(int cpu)
586{
587 int last = 0;
588
589 if (cpu_data(cpu)->threads_per_core == 1 &&
590 cpu_data(cpu)->cores_per_socket == 1) {
591 cpumask_clear_cpu(cpu, &cpu_core_map[cpu]);
592 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
593 return;
594 }
595
596 last = (cpumask_weight(&cpu_core_map[cpu]) == 1 ? 1 : 0);
597
598 /* remove it from all sibling map's */
599 clear_cpu_sibling_map(cpu);
600}
601
602extern void fixup_irqs(void);
603
604int migrate_platform_irqs(unsigned int cpu)
605{
606 int new_cpei_cpu;
607 struct irq_data *data = NULL;
608 const struct cpumask *mask;
609 int retval = 0;
610
611 /*
612 * dont permit CPEI target to removed.
613 */
614 if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
615 printk ("CPU (%d) is CPEI Target\n", cpu);
616 if (can_cpei_retarget()) {
617 /*
618 * Now re-target the CPEI to a different processor
619 */
620 new_cpei_cpu = cpumask_any(cpu_online_mask);
621 mask = cpumask_of(new_cpei_cpu);
622 set_cpei_target_cpu(new_cpei_cpu);
623 data = irq_get_irq_data(ia64_cpe_irq);
624 /*
625 * Switch for now, immediately, we need to do fake intr
626 * as other interrupts, but need to study CPEI behaviour with
627 * polling before making changes.
628 */
629 if (data && data->chip) {
630 data->chip->irq_disable(data);
631 data->chip->irq_set_affinity(data, mask, false);
632 data->chip->irq_enable(data);
633 printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
634 }
635 }
636 if (!data) {
637 printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
638 retval = -EBUSY;
639 }
640 }
641 return retval;
642}
643
644/* must be called with cpucontrol mutex held */
645int __cpu_disable(void)
646{
647 int cpu = smp_processor_id();
648
649 /*
650 * dont permit boot processor for now
651 */
652 if (cpu == 0 && !bsp_remove_ok) {
653 printk ("Your platform does not support removal of BSP\n");
654 return (-EBUSY);
655 }
656
657 set_cpu_online(cpu, false);
658
659 if (migrate_platform_irqs(cpu)) {
660 set_cpu_online(cpu, true);
661 return -EBUSY;
662 }
663
664 remove_siblinginfo(cpu);
665 fixup_irqs();
666 local_flush_tlb_all();
667 cpumask_clear_cpu(cpu, &cpu_callin_map);
668 return 0;
669}
670
671void __cpu_die(unsigned int cpu)
672{
673 unsigned int i;
674
675 for (i = 0; i < 100; i++) {
676 /* They ack this in play_dead by setting CPU_DEAD */
677 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
678 {
679 printk ("CPU %d is now offline\n", cpu);
680 return;
681 }
682 msleep(100);
683 }
684 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
685}
686#endif /* CONFIG_HOTPLUG_CPU */
687
688void
689smp_cpus_done (unsigned int dummy)
690{
691 int cpu;
692 unsigned long bogosum = 0;
693
694 /*
695 * Allow the user to impress friends.
696 */
697
698 for_each_online_cpu(cpu) {
699 bogosum += cpu_data(cpu)->loops_per_jiffy;
700 }
701
702 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
703 (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
704}
705
706static inline void set_cpu_sibling_map(int cpu)
707{
708 int i;
709
710 for_each_online_cpu(i) {
711 if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
712 cpumask_set_cpu(i, &cpu_core_map[cpu]);
713 cpumask_set_cpu(cpu, &cpu_core_map[i]);
714 if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
715 cpumask_set_cpu(i,
716 &per_cpu(cpu_sibling_map, cpu));
717 cpumask_set_cpu(cpu,
718 &per_cpu(cpu_sibling_map, i));
719 }
720 }
721 }
722}
723
724int
725__cpu_up(unsigned int cpu, struct task_struct *tidle)
726{
727 int ret;
728 int sapicid;
729
730 sapicid = ia64_cpu_to_sapicid[cpu];
731 if (sapicid == -1)
732 return -EINVAL;
733
734 /*
735 * Already booted cpu? not valid anymore since we dont
736 * do idle loop tightspin anymore.
737 */
738 if (cpumask_test_cpu(cpu, &cpu_callin_map))
739 return -EINVAL;
740
741 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
742 /* Processor goes to start_secondary(), sets online flag */
743 ret = do_boot_cpu(sapicid, cpu, tidle);
744 if (ret < 0)
745 return ret;
746
747 if (cpu_data(cpu)->threads_per_core == 1 &&
748 cpu_data(cpu)->cores_per_socket == 1) {
749 cpumask_set_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
750 cpumask_set_cpu(cpu, &cpu_core_map[cpu]);
751 return 0;
752 }
753
754 set_cpu_sibling_map(cpu);
755
756 return 0;
757}
758
759/*
760 * Assume that CPUs have been discovered by some platform-dependent interface. For
761 * SoftSDV/Lion, that would be ACPI.
762 *
763 * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
764 */
765void __init
766init_smp_config(void)
767{
768 struct fptr {
769 unsigned long fp;
770 unsigned long gp;
771 } *ap_startup;
772 long sal_ret;
773
774 /* Tell SAL where to drop the APs. */
775 ap_startup = (struct fptr *) start_ap;
776 sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
777 ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
778 if (sal_ret < 0)
779 printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
780 ia64_sal_strerror(sal_ret));
781}
782
783/*
784 * identify_siblings(cpu) gets called from identify_cpu. This populates the
785 * information related to logical execution units in per_cpu_data structure.
786 */
787void identify_siblings(struct cpuinfo_ia64 *c)
788{
789 long status;
790 u16 pltid;
791 pal_logical_to_physical_t info;
792
793 status = ia64_pal_logical_to_phys(-1, &info);
794 if (status != PAL_STATUS_SUCCESS) {
795 if (status != PAL_STATUS_UNIMPLEMENTED) {
796 printk(KERN_ERR
797 "ia64_pal_logical_to_phys failed with %ld\n",
798 status);
799 return;
800 }
801
802 info.overview_ppid = 0;
803 info.overview_cpp = 1;
804 info.overview_tpc = 1;
805 }
806
807 status = ia64_sal_physical_id_info(&pltid);
808 if (status != PAL_STATUS_SUCCESS) {
809 if (status != PAL_STATUS_UNIMPLEMENTED)
810 printk(KERN_ERR
811 "ia64_sal_pltid failed with %ld\n",
812 status);
813 return;
814 }
815
816 c->socket_id = (pltid << 8) | info.overview_ppid;
817
818 if (info.overview_cpp == 1 && info.overview_tpc == 1)
819 return;
820
821 c->cores_per_socket = info.overview_cpp;
822 c->threads_per_core = info.overview_tpc;
823 c->num_log = info.overview_num_log;
824
825 c->core_id = info.log1_cid;
826 c->thread_id = info.log1_tid;
827}
828
829/*
830 * returns non zero, if multi-threading is enabled
831 * on at least one physical package. Due to hotplug cpu
832 * and (maxcpus=), all threads may not necessarily be enabled
833 * even though the processor supports multi-threading.
834 */
835int is_multithreading_enabled(void)
836{
837 int i, j;
838
839 for_each_present_cpu(i) {
840 for_each_present_cpu(j) {
841 if (j == i)
842 continue;
843 if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
844 if (cpu_data(j)->core_id == cpu_data(i)->core_id)
845 return 1;
846 }
847 }
848 }
849 return 0;
850}
851EXPORT_SYMBOL_GPL(is_multithreading_enabled);
1/*
2 * SMP boot-related support
3 *
4 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Copyright (C) 2001, 2004-2005 Intel Corp
7 * Rohit Seth <rohit.seth@intel.com>
8 * Suresh Siddha <suresh.b.siddha@intel.com>
9 * Gordon Jin <gordon.jin@intel.com>
10 * Ashok Raj <ashok.raj@intel.com>
11 *
12 * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
13 * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
14 * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
15 * smp_boot_cpus()/smp_commence() is replaced by
16 * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
17 * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
18 * 04/12/26 Jin Gordon <gordon.jin@intel.com>
19 * 04/12/26 Rohit Seth <rohit.seth@intel.com>
20 * Add multi-threading and multi-core detection
21 * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
22 * Setup cpu_sibling_map and cpu_core_map
23 */
24
25#include <linux/module.h>
26#include <linux/acpi.h>
27#include <linux/bootmem.h>
28#include <linux/cpu.h>
29#include <linux/delay.h>
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/kernel.h>
34#include <linux/kernel_stat.h>
35#include <linux/mm.h>
36#include <linux/notifier.h>
37#include <linux/smp.h>
38#include <linux/spinlock.h>
39#include <linux/efi.h>
40#include <linux/percpu.h>
41#include <linux/bitops.h>
42
43#include <linux/atomic.h>
44#include <asm/cache.h>
45#include <asm/current.h>
46#include <asm/delay.h>
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/machvec.h>
50#include <asm/mca.h>
51#include <asm/page.h>
52#include <asm/paravirt.h>
53#include <asm/pgalloc.h>
54#include <asm/pgtable.h>
55#include <asm/processor.h>
56#include <asm/ptrace.h>
57#include <asm/sal.h>
58#include <asm/tlbflush.h>
59#include <asm/unistd.h>
60#include <asm/sn/arch.h>
61
62#define SMP_DEBUG 0
63
64#if SMP_DEBUG
65#define Dprintk(x...) printk(x)
66#else
67#define Dprintk(x...)
68#endif
69
70#ifdef CONFIG_HOTPLUG_CPU
71#ifdef CONFIG_PERMIT_BSP_REMOVE
72#define bsp_remove_ok 1
73#else
74#define bsp_remove_ok 0
75#endif
76
77/*
78 * Global array allocated for NR_CPUS at boot time
79 */
80struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
81
82/*
83 * start_ap in head.S uses this to store current booting cpu
84 * info.
85 */
86struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
87
88#define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
89
90#else
91#define set_brendez_area(x)
92#endif
93
94
95/*
96 * ITC synchronization related stuff:
97 */
98#define MASTER (0)
99#define SLAVE (SMP_CACHE_BYTES/8)
100
101#define NUM_ROUNDS 64 /* magic value */
102#define NUM_ITERS 5 /* likewise */
103
104static DEFINE_SPINLOCK(itc_sync_lock);
105static volatile unsigned long go[SLAVE + 1];
106
107#define DEBUG_ITC_SYNC 0
108
109extern void start_ap (void);
110extern unsigned long ia64_iobase;
111
112struct task_struct *task_for_booting_cpu;
113
114/*
115 * State for each CPU
116 */
117DEFINE_PER_CPU(int, cpu_state);
118
119cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
120EXPORT_SYMBOL(cpu_core_map);
121DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
122EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
123
124int smp_num_siblings = 1;
125
126/* which logical CPU number maps to which CPU (physical APIC ID) */
127volatile int ia64_cpu_to_sapicid[NR_CPUS];
128EXPORT_SYMBOL(ia64_cpu_to_sapicid);
129
130static volatile cpumask_t cpu_callin_map;
131
132struct smp_boot_data smp_boot_data __initdata;
133
134unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
135
136char __initdata no_int_routing;
137
138unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
139
140#ifdef CONFIG_FORCE_CPEI_RETARGET
141#define CPEI_OVERRIDE_DEFAULT (1)
142#else
143#define CPEI_OVERRIDE_DEFAULT (0)
144#endif
145
146unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
147
148static int __init
149cmdl_force_cpei(char *str)
150{
151 int value=0;
152
153 get_option (&str, &value);
154 force_cpei_retarget = value;
155
156 return 1;
157}
158
159__setup("force_cpei=", cmdl_force_cpei);
160
161static int __init
162nointroute (char *str)
163{
164 no_int_routing = 1;
165 printk ("no_int_routing on\n");
166 return 1;
167}
168
169__setup("nointroute", nointroute);
170
171static void fix_b0_for_bsp(void)
172{
173#ifdef CONFIG_HOTPLUG_CPU
174 int cpuid;
175 static int fix_bsp_b0 = 1;
176
177 cpuid = smp_processor_id();
178
179 /*
180 * Cache the b0 value on the first AP that comes up
181 */
182 if (!(fix_bsp_b0 && cpuid))
183 return;
184
185 sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
186 printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
187
188 fix_bsp_b0 = 0;
189#endif
190}
191
192void
193sync_master (void *arg)
194{
195 unsigned long flags, i;
196
197 go[MASTER] = 0;
198
199 local_irq_save(flags);
200 {
201 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
202 while (!go[MASTER])
203 cpu_relax();
204 go[MASTER] = 0;
205 go[SLAVE] = ia64_get_itc();
206 }
207 }
208 local_irq_restore(flags);
209}
210
211/*
212 * Return the number of cycles by which our itc differs from the itc on the master
213 * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
214 * negative that it is behind.
215 */
216static inline long
217get_delta (long *rt, long *master)
218{
219 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
220 unsigned long tcenter, t0, t1, tm;
221 long i;
222
223 for (i = 0; i < NUM_ITERS; ++i) {
224 t0 = ia64_get_itc();
225 go[MASTER] = 1;
226 while (!(tm = go[SLAVE]))
227 cpu_relax();
228 go[SLAVE] = 0;
229 t1 = ia64_get_itc();
230
231 if (t1 - t0 < best_t1 - best_t0)
232 best_t0 = t0, best_t1 = t1, best_tm = tm;
233 }
234
235 *rt = best_t1 - best_t0;
236 *master = best_tm - best_t0;
237
238 /* average best_t0 and best_t1 without overflow: */
239 tcenter = (best_t0/2 + best_t1/2);
240 if (best_t0 % 2 + best_t1 % 2 == 2)
241 ++tcenter;
242 return tcenter - best_tm;
243}
244
245/*
246 * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
247 * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
248 * unaccounted-for errors (such as getting a machine check in the middle of a calibration
249 * step). The basic idea is for the slave to ask the master what itc value it has and to
250 * read its own itc before and after the master responds. Each iteration gives us three
251 * timestamps:
252 *
253 * slave master
254 *
255 * t0 ---\
256 * ---\
257 * --->
258 * tm
259 * /---
260 * /---
261 * t1 <---
262 *
263 *
264 * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
265 * and t1. If we achieve this, the clocks are synchronized provided the interconnect
266 * between the slave and the master is symmetric. Even if the interconnect were
267 * asymmetric, we would still know that the synchronization error is smaller than the
268 * roundtrip latency (t0 - t1).
269 *
270 * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
271 * within one or two cycles. However, we can only *guarantee* that the synchronization is
272 * accurate to within a round-trip time, which is typically in the range of several
273 * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
274 * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
275 * than half a micro second or so.
276 */
277void
278ia64_sync_itc (unsigned int master)
279{
280 long i, delta, adj, adjust_latency = 0, done = 0;
281 unsigned long flags, rt, master_time_stamp, bound;
282#if DEBUG_ITC_SYNC
283 struct {
284 long rt; /* roundtrip time */
285 long master; /* master's timestamp */
286 long diff; /* difference between midpoint and master's timestamp */
287 long lat; /* estimate of itc adjustment latency */
288 } t[NUM_ROUNDS];
289#endif
290
291 /*
292 * Make sure local timer ticks are disabled while we sync. If
293 * they were enabled, we'd have to worry about nasty issues
294 * like setting the ITC ahead of (or a long time before) the
295 * next scheduled tick.
296 */
297 BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
298
299 go[MASTER] = 1;
300
301 if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
302 printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
303 return;
304 }
305
306 while (go[MASTER])
307 cpu_relax(); /* wait for master to be ready */
308
309 spin_lock_irqsave(&itc_sync_lock, flags);
310 {
311 for (i = 0; i < NUM_ROUNDS; ++i) {
312 delta = get_delta(&rt, &master_time_stamp);
313 if (delta == 0) {
314 done = 1; /* let's lock on to this... */
315 bound = rt;
316 }
317
318 if (!done) {
319 if (i > 0) {
320 adjust_latency += -delta;
321 adj = -delta + adjust_latency/4;
322 } else
323 adj = -delta;
324
325 ia64_set_itc(ia64_get_itc() + adj);
326 }
327#if DEBUG_ITC_SYNC
328 t[i].rt = rt;
329 t[i].master = master_time_stamp;
330 t[i].diff = delta;
331 t[i].lat = adjust_latency/4;
332#endif
333 }
334 }
335 spin_unlock_irqrestore(&itc_sync_lock, flags);
336
337#if DEBUG_ITC_SYNC
338 for (i = 0; i < NUM_ROUNDS; ++i)
339 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
340 t[i].rt, t[i].master, t[i].diff, t[i].lat);
341#endif
342
343 printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
344 "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
345}
346
347/*
348 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
349 */
350static inline void __devinit
351smp_setup_percpu_timer (void)
352{
353}
354
355static void __cpuinit
356smp_callin (void)
357{
358 int cpuid, phys_id, itc_master;
359 struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
360 extern void ia64_init_itm(void);
361 extern volatile int time_keeper_id;
362
363#ifdef CONFIG_PERFMON
364 extern void pfm_init_percpu(void);
365#endif
366
367 cpuid = smp_processor_id();
368 phys_id = hard_smp_processor_id();
369 itc_master = time_keeper_id;
370
371 if (cpu_online(cpuid)) {
372 printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
373 phys_id, cpuid);
374 BUG();
375 }
376
377 fix_b0_for_bsp();
378
379 /*
380 * numa_node_id() works after this.
381 */
382 set_numa_node(cpu_to_node_map[cpuid]);
383 set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
384
385 ipi_call_lock_irq();
386 spin_lock(&vector_lock);
387 /* Setup the per cpu irq handling data structures */
388 __setup_vector_irq(cpuid);
389 notify_cpu_starting(cpuid);
390 set_cpu_online(cpuid, true);
391 per_cpu(cpu_state, cpuid) = CPU_ONLINE;
392 spin_unlock(&vector_lock);
393 ipi_call_unlock_irq();
394
395 smp_setup_percpu_timer();
396
397 ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
398
399#ifdef CONFIG_PERFMON
400 pfm_init_percpu();
401#endif
402
403 local_irq_enable();
404
405 if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
406 /*
407 * Synchronize the ITC with the BP. Need to do this after irqs are
408 * enabled because ia64_sync_itc() calls smp_call_function_single(), which
409 * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
410 * local_bh_enable(), which bugs out if irqs are not enabled...
411 */
412 Dprintk("Going to syncup ITC with ITC Master.\n");
413 ia64_sync_itc(itc_master);
414 }
415
416 /*
417 * Get our bogomips.
418 */
419 ia64_init_itm();
420
421 /*
422 * Delay calibration can be skipped if new processor is identical to the
423 * previous processor.
424 */
425 last_cpuinfo = cpu_data(cpuid - 1);
426 this_cpuinfo = local_cpu_data;
427 if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
428 last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
429 last_cpuinfo->features != this_cpuinfo->features ||
430 last_cpuinfo->revision != this_cpuinfo->revision ||
431 last_cpuinfo->family != this_cpuinfo->family ||
432 last_cpuinfo->archrev != this_cpuinfo->archrev ||
433 last_cpuinfo->model != this_cpuinfo->model)
434 calibrate_delay();
435 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
436
437 /*
438 * Allow the master to continue.
439 */
440 cpu_set(cpuid, cpu_callin_map);
441 Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
442}
443
444
445/*
446 * Activate a secondary processor. head.S calls this.
447 */
448int __cpuinit
449start_secondary (void *unused)
450{
451 /* Early console may use I/O ports */
452 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
453#ifndef CONFIG_PRINTK_TIME
454 Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
455#endif
456 efi_map_pal_code();
457 cpu_init();
458 preempt_disable();
459 smp_callin();
460
461 cpu_idle();
462 return 0;
463}
464
465struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
466{
467 return NULL;
468}
469
470static int __cpuinit
471do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
472{
473 int timeout;
474
475 task_for_booting_cpu = idle;
476 Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
477
478 set_brendez_area(cpu);
479 platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
480
481 /*
482 * Wait 10s total for the AP to start
483 */
484 Dprintk("Waiting on callin_map ...");
485 for (timeout = 0; timeout < 100000; timeout++) {
486 if (cpu_isset(cpu, cpu_callin_map))
487 break; /* It has booted */
488 udelay(100);
489 }
490 Dprintk("\n");
491
492 if (!cpu_isset(cpu, cpu_callin_map)) {
493 printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
494 ia64_cpu_to_sapicid[cpu] = -1;
495 set_cpu_online(cpu, false); /* was set in smp_callin() */
496 return -EINVAL;
497 }
498 return 0;
499}
500
501static int __init
502decay (char *str)
503{
504 int ticks;
505 get_option (&str, &ticks);
506 return 1;
507}
508
509__setup("decay=", decay);
510
511/*
512 * Initialize the logical CPU number to SAPICID mapping
513 */
514void __init
515smp_build_cpu_map (void)
516{
517 int sapicid, cpu, i;
518 int boot_cpu_id = hard_smp_processor_id();
519
520 for (cpu = 0; cpu < NR_CPUS; cpu++) {
521 ia64_cpu_to_sapicid[cpu] = -1;
522 }
523
524 ia64_cpu_to_sapicid[0] = boot_cpu_id;
525 init_cpu_present(cpumask_of(0));
526 set_cpu_possible(0, true);
527 for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
528 sapicid = smp_boot_data.cpu_phys_id[i];
529 if (sapicid == boot_cpu_id)
530 continue;
531 set_cpu_present(cpu, true);
532 set_cpu_possible(cpu, true);
533 ia64_cpu_to_sapicid[cpu] = sapicid;
534 cpu++;
535 }
536}
537
538/*
539 * Cycle through the APs sending Wakeup IPIs to boot each.
540 */
541void __init
542smp_prepare_cpus (unsigned int max_cpus)
543{
544 int boot_cpu_id = hard_smp_processor_id();
545
546 /*
547 * Initialize the per-CPU profiling counter/multiplier
548 */
549
550 smp_setup_percpu_timer();
551
552 cpu_set(0, cpu_callin_map);
553
554 local_cpu_data->loops_per_jiffy = loops_per_jiffy;
555 ia64_cpu_to_sapicid[0] = boot_cpu_id;
556
557 printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
558
559 current_thread_info()->cpu = 0;
560
561 /*
562 * If SMP should be disabled, then really disable it!
563 */
564 if (!max_cpus) {
565 printk(KERN_INFO "SMP mode deactivated.\n");
566 init_cpu_online(cpumask_of(0));
567 init_cpu_present(cpumask_of(0));
568 init_cpu_possible(cpumask_of(0));
569 return;
570 }
571}
572
573void __devinit smp_prepare_boot_cpu(void)
574{
575 set_cpu_online(smp_processor_id(), true);
576 cpu_set(smp_processor_id(), cpu_callin_map);
577 set_numa_node(cpu_to_node_map[smp_processor_id()]);
578 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
579 paravirt_post_smp_prepare_boot_cpu();
580}
581
582#ifdef CONFIG_HOTPLUG_CPU
583static inline void
584clear_cpu_sibling_map(int cpu)
585{
586 int i;
587
588 for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
589 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
590 for_each_cpu_mask(i, cpu_core_map[cpu])
591 cpu_clear(cpu, cpu_core_map[i]);
592
593 per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
594}
595
596static void
597remove_siblinginfo(int cpu)
598{
599 int last = 0;
600
601 if (cpu_data(cpu)->threads_per_core == 1 &&
602 cpu_data(cpu)->cores_per_socket == 1) {
603 cpu_clear(cpu, cpu_core_map[cpu]);
604 cpu_clear(cpu, per_cpu(cpu_sibling_map, cpu));
605 return;
606 }
607
608 last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
609
610 /* remove it from all sibling map's */
611 clear_cpu_sibling_map(cpu);
612}
613
614extern void fixup_irqs(void);
615
616int migrate_platform_irqs(unsigned int cpu)
617{
618 int new_cpei_cpu;
619 struct irq_data *data = NULL;
620 const struct cpumask *mask;
621 int retval = 0;
622
623 /*
624 * dont permit CPEI target to removed.
625 */
626 if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
627 printk ("CPU (%d) is CPEI Target\n", cpu);
628 if (can_cpei_retarget()) {
629 /*
630 * Now re-target the CPEI to a different processor
631 */
632 new_cpei_cpu = cpumask_any(cpu_online_mask);
633 mask = cpumask_of(new_cpei_cpu);
634 set_cpei_target_cpu(new_cpei_cpu);
635 data = irq_get_irq_data(ia64_cpe_irq);
636 /*
637 * Switch for now, immediately, we need to do fake intr
638 * as other interrupts, but need to study CPEI behaviour with
639 * polling before making changes.
640 */
641 if (data && data->chip) {
642 data->chip->irq_disable(data);
643 data->chip->irq_set_affinity(data, mask, false);
644 data->chip->irq_enable(data);
645 printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
646 }
647 }
648 if (!data) {
649 printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
650 retval = -EBUSY;
651 }
652 }
653 return retval;
654}
655
656/* must be called with cpucontrol mutex held */
657int __cpu_disable(void)
658{
659 int cpu = smp_processor_id();
660
661 /*
662 * dont permit boot processor for now
663 */
664 if (cpu == 0 && !bsp_remove_ok) {
665 printk ("Your platform does not support removal of BSP\n");
666 return (-EBUSY);
667 }
668
669 if (ia64_platform_is("sn2")) {
670 if (!sn_cpu_disable_allowed(cpu))
671 return -EBUSY;
672 }
673
674 set_cpu_online(cpu, false);
675
676 if (migrate_platform_irqs(cpu)) {
677 set_cpu_online(cpu, true);
678 return -EBUSY;
679 }
680
681 remove_siblinginfo(cpu);
682 fixup_irqs();
683 local_flush_tlb_all();
684 cpu_clear(cpu, cpu_callin_map);
685 return 0;
686}
687
688void __cpu_die(unsigned int cpu)
689{
690 unsigned int i;
691
692 for (i = 0; i < 100; i++) {
693 /* They ack this in play_dead by setting CPU_DEAD */
694 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
695 {
696 printk ("CPU %d is now offline\n", cpu);
697 return;
698 }
699 msleep(100);
700 }
701 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
702}
703#endif /* CONFIG_HOTPLUG_CPU */
704
705void
706smp_cpus_done (unsigned int dummy)
707{
708 int cpu;
709 unsigned long bogosum = 0;
710
711 /*
712 * Allow the user to impress friends.
713 */
714
715 for_each_online_cpu(cpu) {
716 bogosum += cpu_data(cpu)->loops_per_jiffy;
717 }
718
719 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
720 (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
721}
722
723static inline void __devinit
724set_cpu_sibling_map(int cpu)
725{
726 int i;
727
728 for_each_online_cpu(i) {
729 if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
730 cpu_set(i, cpu_core_map[cpu]);
731 cpu_set(cpu, cpu_core_map[i]);
732 if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
733 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
734 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
735 }
736 }
737 }
738}
739
740int __cpuinit
741__cpu_up(unsigned int cpu, struct task_struct *tidle)
742{
743 int ret;
744 int sapicid;
745
746 sapicid = ia64_cpu_to_sapicid[cpu];
747 if (sapicid == -1)
748 return -EINVAL;
749
750 /*
751 * Already booted cpu? not valid anymore since we dont
752 * do idle loop tightspin anymore.
753 */
754 if (cpu_isset(cpu, cpu_callin_map))
755 return -EINVAL;
756
757 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
758 /* Processor goes to start_secondary(), sets online flag */
759 ret = do_boot_cpu(sapicid, cpu, tidle);
760 if (ret < 0)
761 return ret;
762
763 if (cpu_data(cpu)->threads_per_core == 1 &&
764 cpu_data(cpu)->cores_per_socket == 1) {
765 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
766 cpu_set(cpu, cpu_core_map[cpu]);
767 return 0;
768 }
769
770 set_cpu_sibling_map(cpu);
771
772 return 0;
773}
774
775/*
776 * Assume that CPUs have been discovered by some platform-dependent interface. For
777 * SoftSDV/Lion, that would be ACPI.
778 *
779 * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
780 */
781void __init
782init_smp_config(void)
783{
784 struct fptr {
785 unsigned long fp;
786 unsigned long gp;
787 } *ap_startup;
788 long sal_ret;
789
790 /* Tell SAL where to drop the APs. */
791 ap_startup = (struct fptr *) start_ap;
792 sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
793 ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
794 if (sal_ret < 0)
795 printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
796 ia64_sal_strerror(sal_ret));
797}
798
799/*
800 * identify_siblings(cpu) gets called from identify_cpu. This populates the
801 * information related to logical execution units in per_cpu_data structure.
802 */
803void __devinit
804identify_siblings(struct cpuinfo_ia64 *c)
805{
806 long status;
807 u16 pltid;
808 pal_logical_to_physical_t info;
809
810 status = ia64_pal_logical_to_phys(-1, &info);
811 if (status != PAL_STATUS_SUCCESS) {
812 if (status != PAL_STATUS_UNIMPLEMENTED) {
813 printk(KERN_ERR
814 "ia64_pal_logical_to_phys failed with %ld\n",
815 status);
816 return;
817 }
818
819 info.overview_ppid = 0;
820 info.overview_cpp = 1;
821 info.overview_tpc = 1;
822 }
823
824 status = ia64_sal_physical_id_info(&pltid);
825 if (status != PAL_STATUS_SUCCESS) {
826 if (status != PAL_STATUS_UNIMPLEMENTED)
827 printk(KERN_ERR
828 "ia64_sal_pltid failed with %ld\n",
829 status);
830 return;
831 }
832
833 c->socket_id = (pltid << 8) | info.overview_ppid;
834
835 if (info.overview_cpp == 1 && info.overview_tpc == 1)
836 return;
837
838 c->cores_per_socket = info.overview_cpp;
839 c->threads_per_core = info.overview_tpc;
840 c->num_log = info.overview_num_log;
841
842 c->core_id = info.log1_cid;
843 c->thread_id = info.log1_tid;
844}
845
846/*
847 * returns non zero, if multi-threading is enabled
848 * on at least one physical package. Due to hotplug cpu
849 * and (maxcpus=), all threads may not necessarily be enabled
850 * even though the processor supports multi-threading.
851 */
852int is_multithreading_enabled(void)
853{
854 int i, j;
855
856 for_each_present_cpu(i) {
857 for_each_present_cpu(j) {
858 if (j == i)
859 continue;
860 if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
861 if (cpu_data(j)->core_id == cpu_data(i)->core_id)
862 return 1;
863 }
864 }
865 }
866 return 0;
867}
868EXPORT_SYMBOL_GPL(is_multithreading_enabled);