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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * C-Media CMI8788 driver - main driver module
4 *
5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6 */
7
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/mutex.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <sound/ac97_codec.h>
15#include <sound/asoundef.h>
16#include <sound/core.h>
17#include <sound/info.h>
18#include <sound/mpu401.h>
19#include <sound/pcm.h>
20#include "oxygen.h"
21#include "cm9780.h"
22
23MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
24MODULE_DESCRIPTION("C-Media CMI8788 helper library");
25MODULE_LICENSE("GPL v2");
26
27#define DRIVER "oxygen"
28
29static inline int oxygen_uart_input_ready(struct oxygen *chip)
30{
31 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
32}
33
34static void oxygen_read_uart(struct oxygen *chip)
35{
36 if (unlikely(!oxygen_uart_input_ready(chip))) {
37 /* no data, but read it anyway to clear the interrupt */
38 oxygen_read8(chip, OXYGEN_MPU401);
39 return;
40 }
41 do {
42 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
43 if (data == MPU401_ACK)
44 continue;
45 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
46 chip->uart_input_count = 0;
47 chip->uart_input[chip->uart_input_count++] = data;
48 } while (oxygen_uart_input_ready(chip));
49 if (chip->model.uart_input)
50 chip->model.uart_input(chip);
51}
52
53static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
54{
55 struct oxygen *chip = dev_id;
56 unsigned int status, clear, elapsed_streams, i;
57
58 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
59 if (!status)
60 return IRQ_NONE;
61
62 spin_lock(&chip->reg_lock);
63
64 clear = status & (OXYGEN_CHANNEL_A |
65 OXYGEN_CHANNEL_B |
66 OXYGEN_CHANNEL_C |
67 OXYGEN_CHANNEL_SPDIF |
68 OXYGEN_CHANNEL_MULTICH |
69 OXYGEN_CHANNEL_AC97 |
70 OXYGEN_INT_SPDIF_IN_DETECT |
71 OXYGEN_INT_GPIO |
72 OXYGEN_INT_AC97);
73 if (clear) {
74 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
75 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
76 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
77 chip->interrupt_mask & ~clear);
78 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
79 chip->interrupt_mask);
80 }
81
82 elapsed_streams = status & chip->pcm_running;
83
84 spin_unlock(&chip->reg_lock);
85
86 for (i = 0; i < PCM_COUNT; ++i)
87 if ((elapsed_streams & (1 << i)) && chip->streams[i])
88 snd_pcm_period_elapsed(chip->streams[i]);
89
90 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
91 spin_lock(&chip->reg_lock);
92 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
93 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
94 OXYGEN_SPDIF_RATE_INT)) {
95 /* write the interrupt bit(s) to clear */
96 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
97 schedule_work(&chip->spdif_input_bits_work);
98 }
99 spin_unlock(&chip->reg_lock);
100 }
101
102 if (status & OXYGEN_INT_GPIO)
103 schedule_work(&chip->gpio_work);
104
105 if (status & OXYGEN_INT_MIDI) {
106 if (chip->midi)
107 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
108 else
109 oxygen_read_uart(chip);
110 }
111
112 if (status & OXYGEN_INT_AC97)
113 wake_up(&chip->ac97_waitqueue);
114
115 return IRQ_HANDLED;
116}
117
118static void oxygen_spdif_input_bits_changed(struct work_struct *work)
119{
120 struct oxygen *chip = container_of(work, struct oxygen,
121 spdif_input_bits_work);
122 u32 reg;
123
124 /*
125 * This function gets called when there is new activity on the SPDIF
126 * input, or when we lose lock on the input signal, or when the rate
127 * changes.
128 */
129 msleep(1);
130 spin_lock_irq(&chip->reg_lock);
131 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
132 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
133 OXYGEN_SPDIF_LOCK_STATUS))
134 == OXYGEN_SPDIF_SENSE_STATUS) {
135 /*
136 * If we detect activity on the SPDIF input but cannot lock to
137 * a signal, the clock bit is likely to be wrong.
138 */
139 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
140 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
141 spin_unlock_irq(&chip->reg_lock);
142 msleep(1);
143 spin_lock_irq(&chip->reg_lock);
144 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
145 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
146 OXYGEN_SPDIF_LOCK_STATUS))
147 == OXYGEN_SPDIF_SENSE_STATUS) {
148 /* nothing detected with either clock; give up */
149 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
150 == OXYGEN_SPDIF_IN_CLOCK_192) {
151 /*
152 * Reset clock to <= 96 kHz because this is
153 * more likely to be received next time.
154 */
155 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
156 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
157 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
158 }
159 }
160 }
161 spin_unlock_irq(&chip->reg_lock);
162
163 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
164 spin_lock_irq(&chip->reg_lock);
165 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
166 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
167 chip->interrupt_mask);
168 spin_unlock_irq(&chip->reg_lock);
169
170 /*
171 * We don't actually know that any channel status bits have
172 * changed, but let's send a notification just to be sure.
173 */
174 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
175 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
176 }
177}
178
179static void oxygen_gpio_changed(struct work_struct *work)
180{
181 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
182
183 if (chip->model.gpio_changed)
184 chip->model.gpio_changed(chip);
185}
186
187static void oxygen_proc_read(struct snd_info_entry *entry,
188 struct snd_info_buffer *buffer)
189{
190 struct oxygen *chip = entry->private_data;
191 int i, j;
192
193 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
194 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
195 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
196 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
197 default: i = '?'; break;
198 }
199 snd_iprintf(buffer, "CMI878%c:\n", i);
200 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
201 snd_iprintf(buffer, "%02x:", i);
202 for (j = 0; j < 0x10; ++j)
203 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
204 snd_iprintf(buffer, "\n");
205 }
206 if (mutex_lock_interruptible(&chip->mutex) < 0)
207 return;
208 if (chip->has_ac97_0) {
209 snd_iprintf(buffer, "\nAC97:\n");
210 for (i = 0; i < 0x80; i += 0x10) {
211 snd_iprintf(buffer, "%02x:", i);
212 for (j = 0; j < 0x10; j += 2)
213 snd_iprintf(buffer, " %04x",
214 oxygen_read_ac97(chip, 0, i + j));
215 snd_iprintf(buffer, "\n");
216 }
217 }
218 if (chip->has_ac97_1) {
219 snd_iprintf(buffer, "\nAC97 2:\n");
220 for (i = 0; i < 0x80; i += 0x10) {
221 snd_iprintf(buffer, "%02x:", i);
222 for (j = 0; j < 0x10; j += 2)
223 snd_iprintf(buffer, " %04x",
224 oxygen_read_ac97(chip, 1, i + j));
225 snd_iprintf(buffer, "\n");
226 }
227 }
228 mutex_unlock(&chip->mutex);
229 if (chip->model.dump_registers)
230 chip->model.dump_registers(chip, buffer);
231}
232
233static void oxygen_proc_init(struct oxygen *chip)
234{
235 snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
236}
237
238static const struct pci_device_id *
239oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
240{
241 u16 subdevice;
242
243 /*
244 * Make sure the EEPROM pins are available, i.e., not used for SPI.
245 * (This function is called before we initialize or use SPI.)
246 */
247 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
248 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
249 /*
250 * Read the subsystem device ID directly from the EEPROM, because the
251 * chip didn't if the first EEPROM word was overwritten.
252 */
253 subdevice = oxygen_read_eeprom(chip, 2);
254 /* use default ID if EEPROM is missing */
255 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
256 subdevice = 0x8788;
257 /*
258 * We use only the subsystem device ID for searching because it is
259 * unique even without the subsystem vendor ID, which may have been
260 * overwritten in the EEPROM.
261 */
262 for (; ids->vendor; ++ids)
263 if (ids->subdevice == subdevice &&
264 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
265 return ids;
266 return NULL;
267}
268
269static void oxygen_restore_eeprom(struct oxygen *chip,
270 const struct pci_device_id *id)
271{
272 u16 eeprom_id;
273
274 eeprom_id = oxygen_read_eeprom(chip, 0);
275 if (eeprom_id != OXYGEN_EEPROM_ID &&
276 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
277 /*
278 * This function gets called only when a known card model has
279 * been detected, i.e., we know there is a valid subsystem
280 * product ID at index 2 in the EEPROM. Therefore, we have
281 * been able to deduce the correct subsystem vendor ID, and
282 * this is enough information to restore the original EEPROM
283 * contents.
284 */
285 oxygen_write_eeprom(chip, 1, id->subvendor);
286 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
287
288 oxygen_set_bits8(chip, OXYGEN_MISC,
289 OXYGEN_MISC_WRITE_PCI_SUBID);
290 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
291 id->subvendor);
292 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
293 id->subdevice);
294 oxygen_clear_bits8(chip, OXYGEN_MISC,
295 OXYGEN_MISC_WRITE_PCI_SUBID);
296
297 dev_info(chip->card->dev, "EEPROM ID restored\n");
298 }
299}
300
301static void configure_pcie_bridge(struct pci_dev *pci)
302{
303 enum { PEX811X, PI7C9X110, XIO2001 };
304 static const struct pci_device_id bridge_ids[] = {
305 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
306 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
307 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
308 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
309 { }
310 };
311 struct pci_dev *bridge;
312 const struct pci_device_id *id;
313 u32 tmp;
314
315 if (!pci->bus || !pci->bus->self)
316 return;
317 bridge = pci->bus->self;
318
319 id = pci_match_id(bridge_ids, bridge);
320 if (!id)
321 return;
322
323 switch (id->driver_data) {
324 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
325 pci_read_config_dword(bridge, 0x48, &tmp);
326 tmp |= 1; /* enable blind prefetching */
327 tmp |= 1 << 11; /* enable beacon generation */
328 pci_write_config_dword(bridge, 0x48, tmp);
329
330 pci_write_config_dword(bridge, 0x84, 0x0c);
331 pci_read_config_dword(bridge, 0x88, &tmp);
332 tmp &= ~(7 << 27);
333 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
334 pci_write_config_dword(bridge, 0x88, tmp);
335 break;
336
337 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
338 pci_read_config_dword(bridge, 0x40, &tmp);
339 tmp |= 1; /* park the PCI arbiter to the sound chip */
340 pci_write_config_dword(bridge, 0x40, tmp);
341 break;
342
343 case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
344 pci_read_config_dword(bridge, 0xe8, &tmp);
345 tmp &= ~0xf; /* request length limit: 64 bytes */
346 tmp &= ~(0xf << 8);
347 tmp |= 1 << 8; /* request count limit: one buffer */
348 pci_write_config_dword(bridge, 0xe8, tmp);
349 break;
350 }
351}
352
353static void oxygen_init(struct oxygen *chip)
354{
355 unsigned int i;
356
357 chip->dac_routing = 1;
358 for (i = 0; i < 8; ++i)
359 chip->dac_volume[i] = chip->model.dac_volume_min;
360 chip->dac_mute = 1;
361 chip->spdif_playback_enable = 0;
362 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
363 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
364 chip->spdif_pcm_bits = chip->spdif_bits;
365
366 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
367 oxygen_set_bits8(chip, OXYGEN_MISC,
368 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
369
370 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
371 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
372 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
373
374 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
375 OXYGEN_FUNCTION_RESET_CODEC |
376 chip->model.function_flags,
377 OXYGEN_FUNCTION_RESET_CODEC |
378 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
379 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
380 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
381 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
382 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
383 OXYGEN_PLAY_CHANNELS_2 |
384 OXYGEN_DMA_A_BURST_8 |
385 OXYGEN_DMA_MULTICH_BURST_8);
386 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
387 oxygen_write8_masked(chip, OXYGEN_MISC,
388 chip->model.misc_flags,
389 OXYGEN_MISC_WRITE_PCI_SUBID |
390 OXYGEN_MISC_REC_C_FROM_SPDIF |
391 OXYGEN_MISC_REC_B_FROM_AC97 |
392 OXYGEN_MISC_REC_A_FROM_MULTICH |
393 OXYGEN_MISC_MIDI);
394 oxygen_write8(chip, OXYGEN_REC_FORMAT,
395 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
396 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
397 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
398 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
399 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
400 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
401 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
402 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
403 OXYGEN_RATE_48000 |
404 chip->model.dac_i2s_format |
405 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
406 OXYGEN_I2S_BITS_16 |
407 OXYGEN_I2S_MASTER |
408 OXYGEN_I2S_BCLK_64);
409 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
410 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
411 OXYGEN_RATE_48000 |
412 chip->model.adc_i2s_format |
413 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
414 OXYGEN_I2S_BITS_16 |
415 OXYGEN_I2S_MASTER |
416 OXYGEN_I2S_BCLK_64);
417 else
418 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
419 OXYGEN_I2S_MASTER |
420 OXYGEN_I2S_MUTE_MCLK);
421 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
422 CAPTURE_2_FROM_I2S_2))
423 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
424 OXYGEN_RATE_48000 |
425 chip->model.adc_i2s_format |
426 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
427 OXYGEN_I2S_BITS_16 |
428 OXYGEN_I2S_MASTER |
429 OXYGEN_I2S_BCLK_64);
430 else
431 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
432 OXYGEN_I2S_MASTER |
433 OXYGEN_I2S_MUTE_MCLK);
434 if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
435 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
436 OXYGEN_RATE_48000 |
437 chip->model.adc_i2s_format |
438 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
439 OXYGEN_I2S_BITS_16 |
440 OXYGEN_I2S_MASTER |
441 OXYGEN_I2S_BCLK_64);
442 else
443 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
444 OXYGEN_I2S_MASTER |
445 OXYGEN_I2S_MUTE_MCLK);
446 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
447 OXYGEN_SPDIF_OUT_ENABLE |
448 OXYGEN_SPDIF_LOOPBACK);
449 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
450 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
451 OXYGEN_SPDIF_SENSE_MASK |
452 OXYGEN_SPDIF_LOCK_MASK |
453 OXYGEN_SPDIF_RATE_MASK |
454 OXYGEN_SPDIF_LOCK_PAR |
455 OXYGEN_SPDIF_IN_CLOCK_96,
456 OXYGEN_SPDIF_SENSE_MASK |
457 OXYGEN_SPDIF_LOCK_MASK |
458 OXYGEN_SPDIF_RATE_MASK |
459 OXYGEN_SPDIF_SENSE_PAR |
460 OXYGEN_SPDIF_LOCK_PAR |
461 OXYGEN_SPDIF_IN_CLOCK_MASK);
462 else
463 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
464 OXYGEN_SPDIF_SENSE_MASK |
465 OXYGEN_SPDIF_LOCK_MASK |
466 OXYGEN_SPDIF_RATE_MASK);
467 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
468 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
469 OXYGEN_2WIRE_LENGTH_8 |
470 OXYGEN_2WIRE_INTERRUPT_MASK |
471 OXYGEN_2WIRE_SPEED_STANDARD);
472 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
473 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
474 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
475 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
476 OXYGEN_PLAY_MULTICH_I2S_DAC |
477 OXYGEN_PLAY_SPDIF_SPDIF |
478 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
479 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
480 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
481 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
482 oxygen_write8(chip, OXYGEN_REC_ROUTING,
483 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
484 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
485 OXYGEN_REC_C_ROUTE_SPDIF);
486 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
487 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
488 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
489 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
490 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
491 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
492
493 if (chip->has_ac97_0 | chip->has_ac97_1)
494 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
495 OXYGEN_AC97_INT_READ_DONE |
496 OXYGEN_AC97_INT_WRITE_DONE);
497 else
498 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
499 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
500 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
501 if (!(chip->has_ac97_0 | chip->has_ac97_1))
502 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
503 OXYGEN_AC97_CLOCK_DISABLE);
504 if (!chip->has_ac97_0) {
505 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
506 OXYGEN_AC97_NO_CODEC_0);
507 } else {
508 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
509 msleep(1);
510 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
511 CM9780_GPIO0IO | CM9780_GPIO1IO);
512 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
513 CM9780_BSTSEL | CM9780_STRO_MIC |
514 CM9780_MIX2FR | CM9780_PCBSW);
515 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
516 CM9780_RSOE | CM9780_CBOE |
517 CM9780_SSOE | CM9780_FROE |
518 CM9780_MIC2MIC | CM9780_LI2LI);
519 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
520 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
521 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
522 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
523 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
524 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
525 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
526 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
527 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
528 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
529 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
530 CM9780_GPO0);
531 /* power down unused ADCs and DACs */
532 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
533 AC97_PD_PR0 | AC97_PD_PR1);
534 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
535 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
536 }
537 if (chip->has_ac97_1) {
538 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
539 OXYGEN_AC97_CODEC1_SLOT3 |
540 OXYGEN_AC97_CODEC1_SLOT4);
541 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
542 msleep(1);
543 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
544 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
545 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
546 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
547 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
548 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
549 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
550 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
551 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
552 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
553 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
554 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
555 }
556}
557
558static void oxygen_shutdown(struct oxygen *chip)
559{
560 spin_lock_irq(&chip->reg_lock);
561 chip->interrupt_mask = 0;
562 chip->pcm_running = 0;
563 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
564 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
565 spin_unlock_irq(&chip->reg_lock);
566}
567
568static void oxygen_card_free(struct snd_card *card)
569{
570 struct oxygen *chip = card->private_data;
571
572 oxygen_shutdown(chip);
573 if (chip->irq >= 0)
574 free_irq(chip->irq, chip);
575 flush_work(&chip->spdif_input_bits_work);
576 flush_work(&chip->gpio_work);
577 chip->model.cleanup(chip);
578 kfree(chip->model_data);
579 mutex_destroy(&chip->mutex);
580 pci_release_regions(chip->pci);
581 pci_disable_device(chip->pci);
582}
583
584int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
585 struct module *owner,
586 const struct pci_device_id *ids,
587 int (*get_model)(struct oxygen *chip,
588 const struct pci_device_id *id
589 )
590 )
591{
592 struct snd_card *card;
593 struct oxygen *chip;
594 const struct pci_device_id *pci_id;
595 int err;
596
597 err = snd_card_new(&pci->dev, index, id, owner,
598 sizeof(*chip), &card);
599 if (err < 0)
600 return err;
601
602 chip = card->private_data;
603 chip->card = card;
604 chip->pci = pci;
605 chip->irq = -1;
606 spin_lock_init(&chip->reg_lock);
607 mutex_init(&chip->mutex);
608 INIT_WORK(&chip->spdif_input_bits_work,
609 oxygen_spdif_input_bits_changed);
610 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
611 init_waitqueue_head(&chip->ac97_waitqueue);
612
613 err = pci_enable_device(pci);
614 if (err < 0)
615 goto err_card;
616
617 err = pci_request_regions(pci, DRIVER);
618 if (err < 0) {
619 dev_err(card->dev, "cannot reserve PCI resources\n");
620 goto err_pci_enable;
621 }
622
623 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
624 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
625 dev_err(card->dev, "invalid PCI I/O range\n");
626 err = -ENXIO;
627 goto err_pci_regions;
628 }
629 chip->addr = pci_resource_start(pci, 0);
630
631 pci_id = oxygen_search_pci_id(chip, ids);
632 if (!pci_id) {
633 err = -ENODEV;
634 goto err_pci_regions;
635 }
636 oxygen_restore_eeprom(chip, pci_id);
637 err = get_model(chip, pci_id);
638 if (err < 0)
639 goto err_pci_regions;
640
641 if (chip->model.model_data_size) {
642 chip->model_data = kzalloc(chip->model.model_data_size,
643 GFP_KERNEL);
644 if (!chip->model_data) {
645 err = -ENOMEM;
646 goto err_pci_regions;
647 }
648 }
649
650 pci_set_master(pci);
651 card->private_free = oxygen_card_free;
652
653 configure_pcie_bridge(pci);
654 oxygen_init(chip);
655 chip->model.init(chip);
656
657 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
658 KBUILD_MODNAME, chip);
659 if (err < 0) {
660 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
661 goto err_card;
662 }
663 chip->irq = pci->irq;
664 card->sync_irq = chip->irq;
665
666 strcpy(card->driver, chip->model.chip);
667 strcpy(card->shortname, chip->model.shortname);
668 sprintf(card->longname, "%s at %#lx, irq %i",
669 chip->model.longname, chip->addr, chip->irq);
670 strcpy(card->mixername, chip->model.chip);
671 snd_component_add(card, chip->model.chip);
672
673 err = oxygen_pcm_init(chip);
674 if (err < 0)
675 goto err_card;
676
677 err = oxygen_mixer_init(chip);
678 if (err < 0)
679 goto err_card;
680
681 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
682 unsigned int info_flags =
683 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
684 if (chip->model.device_config & MIDI_OUTPUT)
685 info_flags |= MPU401_INFO_OUTPUT;
686 if (chip->model.device_config & MIDI_INPUT)
687 info_flags |= MPU401_INFO_INPUT;
688 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
689 chip->addr + OXYGEN_MPU401,
690 info_flags, -1, &chip->midi);
691 if (err < 0)
692 goto err_card;
693 }
694
695 oxygen_proc_init(chip);
696
697 spin_lock_irq(&chip->reg_lock);
698 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
699 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
700 if (chip->has_ac97_0 | chip->has_ac97_1)
701 chip->interrupt_mask |= OXYGEN_INT_AC97;
702 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
703 spin_unlock_irq(&chip->reg_lock);
704
705 err = snd_card_register(card);
706 if (err < 0)
707 goto err_card;
708
709 pci_set_drvdata(pci, card);
710 return 0;
711
712err_pci_regions:
713 pci_release_regions(pci);
714err_pci_enable:
715 pci_disable_device(pci);
716err_card:
717 snd_card_free(card);
718 return err;
719}
720EXPORT_SYMBOL(oxygen_pci_probe);
721
722void oxygen_pci_remove(struct pci_dev *pci)
723{
724 snd_card_free(pci_get_drvdata(pci));
725}
726EXPORT_SYMBOL(oxygen_pci_remove);
727
728#ifdef CONFIG_PM_SLEEP
729static int oxygen_pci_suspend(struct device *dev)
730{
731 struct snd_card *card = dev_get_drvdata(dev);
732 struct oxygen *chip = card->private_data;
733 unsigned int saved_interrupt_mask;
734
735 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
736
737 if (chip->model.suspend)
738 chip->model.suspend(chip);
739
740 spin_lock_irq(&chip->reg_lock);
741 saved_interrupt_mask = chip->interrupt_mask;
742 chip->interrupt_mask = 0;
743 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
744 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
745 spin_unlock_irq(&chip->reg_lock);
746
747 flush_work(&chip->spdif_input_bits_work);
748 flush_work(&chip->gpio_work);
749 chip->interrupt_mask = saved_interrupt_mask;
750 return 0;
751}
752
753static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
754 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
755 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
756};
757static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
758 { 0x18284fa2, 0x03060000 },
759 { 0x00007fa6, 0x00200000 }
760};
761
762static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
763{
764 return bitmap[bit / 32] & (1 << (bit & 31));
765}
766
767static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
768{
769 unsigned int i;
770
771 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
772 msleep(1);
773 for (i = 1; i < 0x40; ++i)
774 if (is_bit_set(ac97_registers_to_restore[codec], i))
775 oxygen_write_ac97(chip, codec, i * 2,
776 chip->saved_ac97_registers[codec][i]);
777}
778
779static int oxygen_pci_resume(struct device *dev)
780{
781 struct snd_card *card = dev_get_drvdata(dev);
782 struct oxygen *chip = card->private_data;
783 unsigned int i;
784
785 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
786 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
787 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
788 if (is_bit_set(registers_to_restore, i))
789 oxygen_write8(chip, i, chip->saved_registers._8[i]);
790 if (chip->has_ac97_0)
791 oxygen_restore_ac97(chip, 0);
792 if (chip->has_ac97_1)
793 oxygen_restore_ac97(chip, 1);
794
795 if (chip->model.resume)
796 chip->model.resume(chip);
797
798 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
799
800 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
801 return 0;
802}
803
804SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
805EXPORT_SYMBOL(oxygen_pci_pm);
806#endif /* CONFIG_PM_SLEEP */
807
808void oxygen_pci_shutdown(struct pci_dev *pci)
809{
810 struct snd_card *card = pci_get_drvdata(pci);
811 struct oxygen *chip = card->private_data;
812
813 oxygen_shutdown(chip);
814 chip->model.cleanup(chip);
815}
816EXPORT_SYMBOL(oxygen_pci_shutdown);
1/*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/mutex.h>
23#include <linux/pci.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <sound/ac97_codec.h>
27#include <sound/asoundef.h>
28#include <sound/core.h>
29#include <sound/info.h>
30#include <sound/mpu401.h>
31#include <sound/pcm.h>
32#include "oxygen.h"
33#include "cm9780.h"
34
35MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
36MODULE_DESCRIPTION("C-Media CMI8788 helper library");
37MODULE_LICENSE("GPL v2");
38
39#define DRIVER "oxygen"
40
41static inline int oxygen_uart_input_ready(struct oxygen *chip)
42{
43 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
44}
45
46static void oxygen_read_uart(struct oxygen *chip)
47{
48 if (unlikely(!oxygen_uart_input_ready(chip))) {
49 /* no data, but read it anyway to clear the interrupt */
50 oxygen_read8(chip, OXYGEN_MPU401);
51 return;
52 }
53 do {
54 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
55 if (data == MPU401_ACK)
56 continue;
57 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
58 chip->uart_input_count = 0;
59 chip->uart_input[chip->uart_input_count++] = data;
60 } while (oxygen_uart_input_ready(chip));
61 if (chip->model.uart_input)
62 chip->model.uart_input(chip);
63}
64
65static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
66{
67 struct oxygen *chip = dev_id;
68 unsigned int status, clear, elapsed_streams, i;
69
70 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
71 if (!status)
72 return IRQ_NONE;
73
74 spin_lock(&chip->reg_lock);
75
76 clear = status & (OXYGEN_CHANNEL_A |
77 OXYGEN_CHANNEL_B |
78 OXYGEN_CHANNEL_C |
79 OXYGEN_CHANNEL_SPDIF |
80 OXYGEN_CHANNEL_MULTICH |
81 OXYGEN_CHANNEL_AC97 |
82 OXYGEN_INT_SPDIF_IN_DETECT |
83 OXYGEN_INT_GPIO |
84 OXYGEN_INT_AC97);
85 if (clear) {
86 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
87 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89 chip->interrupt_mask & ~clear);
90 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
91 chip->interrupt_mask);
92 }
93
94 elapsed_streams = status & chip->pcm_running;
95
96 spin_unlock(&chip->reg_lock);
97
98 for (i = 0; i < PCM_COUNT; ++i)
99 if ((elapsed_streams & (1 << i)) && chip->streams[i])
100 snd_pcm_period_elapsed(chip->streams[i]);
101
102 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
103 spin_lock(&chip->reg_lock);
104 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
105 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
106 OXYGEN_SPDIF_RATE_INT)) {
107 /* write the interrupt bit(s) to clear */
108 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
109 schedule_work(&chip->spdif_input_bits_work);
110 }
111 spin_unlock(&chip->reg_lock);
112 }
113
114 if (status & OXYGEN_INT_GPIO)
115 schedule_work(&chip->gpio_work);
116
117 if (status & OXYGEN_INT_MIDI) {
118 if (chip->midi)
119 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
120 else
121 oxygen_read_uart(chip);
122 }
123
124 if (status & OXYGEN_INT_AC97)
125 wake_up(&chip->ac97_waitqueue);
126
127 return IRQ_HANDLED;
128}
129
130static void oxygen_spdif_input_bits_changed(struct work_struct *work)
131{
132 struct oxygen *chip = container_of(work, struct oxygen,
133 spdif_input_bits_work);
134 u32 reg;
135
136 /*
137 * This function gets called when there is new activity on the SPDIF
138 * input, or when we lose lock on the input signal, or when the rate
139 * changes.
140 */
141 msleep(1);
142 spin_lock_irq(&chip->reg_lock);
143 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
144 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
145 OXYGEN_SPDIF_LOCK_STATUS))
146 == OXYGEN_SPDIF_SENSE_STATUS) {
147 /*
148 * If we detect activity on the SPDIF input but cannot lock to
149 * a signal, the clock bit is likely to be wrong.
150 */
151 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
152 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
153 spin_unlock_irq(&chip->reg_lock);
154 msleep(1);
155 spin_lock_irq(&chip->reg_lock);
156 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
157 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
158 OXYGEN_SPDIF_LOCK_STATUS))
159 == OXYGEN_SPDIF_SENSE_STATUS) {
160 /* nothing detected with either clock; give up */
161 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
162 == OXYGEN_SPDIF_IN_CLOCK_192) {
163 /*
164 * Reset clock to <= 96 kHz because this is
165 * more likely to be received next time.
166 */
167 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
168 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
169 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
170 }
171 }
172 }
173 spin_unlock_irq(&chip->reg_lock);
174
175 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
176 spin_lock_irq(&chip->reg_lock);
177 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
178 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
179 chip->interrupt_mask);
180 spin_unlock_irq(&chip->reg_lock);
181
182 /*
183 * We don't actually know that any channel status bits have
184 * changed, but let's send a notification just to be sure.
185 */
186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
187 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
188 }
189}
190
191static void oxygen_gpio_changed(struct work_struct *work)
192{
193 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
194
195 if (chip->model.gpio_changed)
196 chip->model.gpio_changed(chip);
197}
198
199#ifdef CONFIG_PROC_FS
200static void oxygen_proc_read(struct snd_info_entry *entry,
201 struct snd_info_buffer *buffer)
202{
203 struct oxygen *chip = entry->private_data;
204 int i, j;
205
206 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
207 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
208 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
209 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
210 default: i = '?'; break;
211 }
212 snd_iprintf(buffer, "CMI878%c:\n", i);
213 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
214 snd_iprintf(buffer, "%02x:", i);
215 for (j = 0; j < 0x10; ++j)
216 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
217 snd_iprintf(buffer, "\n");
218 }
219 if (mutex_lock_interruptible(&chip->mutex) < 0)
220 return;
221 if (chip->has_ac97_0) {
222 snd_iprintf(buffer, "\nAC97:\n");
223 for (i = 0; i < 0x80; i += 0x10) {
224 snd_iprintf(buffer, "%02x:", i);
225 for (j = 0; j < 0x10; j += 2)
226 snd_iprintf(buffer, " %04x",
227 oxygen_read_ac97(chip, 0, i + j));
228 snd_iprintf(buffer, "\n");
229 }
230 }
231 if (chip->has_ac97_1) {
232 snd_iprintf(buffer, "\nAC97 2:\n");
233 for (i = 0; i < 0x80; i += 0x10) {
234 snd_iprintf(buffer, "%02x:", i);
235 for (j = 0; j < 0x10; j += 2)
236 snd_iprintf(buffer, " %04x",
237 oxygen_read_ac97(chip, 1, i + j));
238 snd_iprintf(buffer, "\n");
239 }
240 }
241 mutex_unlock(&chip->mutex);
242 if (chip->model.dump_registers)
243 chip->model.dump_registers(chip, buffer);
244}
245
246static void oxygen_proc_init(struct oxygen *chip)
247{
248 struct snd_info_entry *entry;
249
250 if (!snd_card_proc_new(chip->card, "oxygen", &entry))
251 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
252}
253#else
254#define oxygen_proc_init(chip)
255#endif
256
257static const struct pci_device_id *
258oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
259{
260 u16 subdevice;
261
262 /*
263 * Make sure the EEPROM pins are available, i.e., not used for SPI.
264 * (This function is called before we initialize or use SPI.)
265 */
266 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
267 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
268 /*
269 * Read the subsystem device ID directly from the EEPROM, because the
270 * chip didn't if the first EEPROM word was overwritten.
271 */
272 subdevice = oxygen_read_eeprom(chip, 2);
273 /* use default ID if EEPROM is missing */
274 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
275 subdevice = 0x8788;
276 /*
277 * We use only the subsystem device ID for searching because it is
278 * unique even without the subsystem vendor ID, which may have been
279 * overwritten in the EEPROM.
280 */
281 for (; ids->vendor; ++ids)
282 if (ids->subdevice == subdevice &&
283 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
284 return ids;
285 return NULL;
286}
287
288static void oxygen_restore_eeprom(struct oxygen *chip,
289 const struct pci_device_id *id)
290{
291 u16 eeprom_id;
292
293 eeprom_id = oxygen_read_eeprom(chip, 0);
294 if (eeprom_id != OXYGEN_EEPROM_ID &&
295 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
296 /*
297 * This function gets called only when a known card model has
298 * been detected, i.e., we know there is a valid subsystem
299 * product ID at index 2 in the EEPROM. Therefore, we have
300 * been able to deduce the correct subsystem vendor ID, and
301 * this is enough information to restore the original EEPROM
302 * contents.
303 */
304 oxygen_write_eeprom(chip, 1, id->subvendor);
305 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
306
307 oxygen_set_bits8(chip, OXYGEN_MISC,
308 OXYGEN_MISC_WRITE_PCI_SUBID);
309 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
310 id->subvendor);
311 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
312 id->subdevice);
313 oxygen_clear_bits8(chip, OXYGEN_MISC,
314 OXYGEN_MISC_WRITE_PCI_SUBID);
315
316 snd_printk(KERN_INFO "EEPROM ID restored\n");
317 }
318}
319
320static void configure_pcie_bridge(struct pci_dev *pci)
321{
322 enum { PEX811X, PI7C9X110 };
323 static const struct pci_device_id bridge_ids[] = {
324 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
325 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
326 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
327 { }
328 };
329 struct pci_dev *bridge;
330 const struct pci_device_id *id;
331 u32 tmp;
332
333 if (!pci->bus || !pci->bus->self)
334 return;
335 bridge = pci->bus->self;
336
337 id = pci_match_id(bridge_ids, bridge);
338 if (!id)
339 return;
340
341 switch (id->driver_data) {
342 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
343 pci_read_config_dword(bridge, 0x48, &tmp);
344 tmp |= 1; /* enable blind prefetching */
345 tmp |= 1 << 11; /* enable beacon generation */
346 pci_write_config_dword(bridge, 0x48, tmp);
347
348 pci_write_config_dword(bridge, 0x84, 0x0c);
349 pci_read_config_dword(bridge, 0x88, &tmp);
350 tmp &= ~(7 << 27);
351 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
352 pci_write_config_dword(bridge, 0x88, tmp);
353 break;
354
355 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
356 pci_read_config_dword(bridge, 0x40, &tmp);
357 tmp |= 1; /* park the PCI arbiter to the sound chip */
358 pci_write_config_dword(bridge, 0x40, tmp);
359 break;
360 }
361}
362
363static void oxygen_init(struct oxygen *chip)
364{
365 unsigned int i;
366
367 chip->dac_routing = 1;
368 for (i = 0; i < 8; ++i)
369 chip->dac_volume[i] = chip->model.dac_volume_min;
370 chip->dac_mute = 1;
371 chip->spdif_playback_enable = 1;
372 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
373 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
374 chip->spdif_pcm_bits = chip->spdif_bits;
375
376 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
377 oxygen_set_bits8(chip, OXYGEN_MISC,
378 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
379
380 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
381 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
382 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
383
384 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
385 OXYGEN_FUNCTION_RESET_CODEC |
386 chip->model.function_flags,
387 OXYGEN_FUNCTION_RESET_CODEC |
388 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
389 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
390 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
391 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
392 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
393 OXYGEN_PLAY_CHANNELS_2 |
394 OXYGEN_DMA_A_BURST_8 |
395 OXYGEN_DMA_MULTICH_BURST_8);
396 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
397 oxygen_write8_masked(chip, OXYGEN_MISC,
398 chip->model.misc_flags,
399 OXYGEN_MISC_WRITE_PCI_SUBID |
400 OXYGEN_MISC_REC_C_FROM_SPDIF |
401 OXYGEN_MISC_REC_B_FROM_AC97 |
402 OXYGEN_MISC_REC_A_FROM_MULTICH |
403 OXYGEN_MISC_MIDI);
404 oxygen_write8(chip, OXYGEN_REC_FORMAT,
405 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
406 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
407 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
408 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
409 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
410 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
411 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
412 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
413 OXYGEN_RATE_48000 |
414 chip->model.dac_i2s_format |
415 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
416 OXYGEN_I2S_BITS_16 |
417 OXYGEN_I2S_MASTER |
418 OXYGEN_I2S_BCLK_64);
419 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
420 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
421 OXYGEN_RATE_48000 |
422 chip->model.adc_i2s_format |
423 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
424 OXYGEN_I2S_BITS_16 |
425 OXYGEN_I2S_MASTER |
426 OXYGEN_I2S_BCLK_64);
427 else
428 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
429 OXYGEN_I2S_MASTER |
430 OXYGEN_I2S_MUTE_MCLK);
431 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
432 CAPTURE_2_FROM_I2S_2))
433 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
434 OXYGEN_RATE_48000 |
435 chip->model.adc_i2s_format |
436 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
437 OXYGEN_I2S_BITS_16 |
438 OXYGEN_I2S_MASTER |
439 OXYGEN_I2S_BCLK_64);
440 else
441 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
442 OXYGEN_I2S_MASTER |
443 OXYGEN_I2S_MUTE_MCLK);
444 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
445 OXYGEN_I2S_MASTER |
446 OXYGEN_I2S_MUTE_MCLK);
447 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
448 OXYGEN_SPDIF_OUT_ENABLE |
449 OXYGEN_SPDIF_LOOPBACK);
450 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
451 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
452 OXYGEN_SPDIF_SENSE_MASK |
453 OXYGEN_SPDIF_LOCK_MASK |
454 OXYGEN_SPDIF_RATE_MASK |
455 OXYGEN_SPDIF_LOCK_PAR |
456 OXYGEN_SPDIF_IN_CLOCK_96,
457 OXYGEN_SPDIF_SENSE_MASK |
458 OXYGEN_SPDIF_LOCK_MASK |
459 OXYGEN_SPDIF_RATE_MASK |
460 OXYGEN_SPDIF_SENSE_PAR |
461 OXYGEN_SPDIF_LOCK_PAR |
462 OXYGEN_SPDIF_IN_CLOCK_MASK);
463 else
464 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
465 OXYGEN_SPDIF_SENSE_MASK |
466 OXYGEN_SPDIF_LOCK_MASK |
467 OXYGEN_SPDIF_RATE_MASK);
468 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
469 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
470 OXYGEN_2WIRE_LENGTH_8 |
471 OXYGEN_2WIRE_INTERRUPT_MASK |
472 OXYGEN_2WIRE_SPEED_STANDARD);
473 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
474 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
475 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
476 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
477 OXYGEN_PLAY_MULTICH_I2S_DAC |
478 OXYGEN_PLAY_SPDIF_SPDIF |
479 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
480 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
481 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
482 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
483 oxygen_write8(chip, OXYGEN_REC_ROUTING,
484 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
485 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
486 OXYGEN_REC_C_ROUTE_SPDIF);
487 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
488 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
489 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
490 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
491 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
492 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
493
494 if (chip->has_ac97_0 | chip->has_ac97_1)
495 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
496 OXYGEN_AC97_INT_READ_DONE |
497 OXYGEN_AC97_INT_WRITE_DONE);
498 else
499 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
500 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
501 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
502 if (!(chip->has_ac97_0 | chip->has_ac97_1))
503 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
504 OXYGEN_AC97_CLOCK_DISABLE);
505 if (!chip->has_ac97_0) {
506 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
507 OXYGEN_AC97_NO_CODEC_0);
508 } else {
509 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
510 msleep(1);
511 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
512 CM9780_GPIO0IO | CM9780_GPIO1IO);
513 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
514 CM9780_BSTSEL | CM9780_STRO_MIC |
515 CM9780_MIX2FR | CM9780_PCBSW);
516 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
517 CM9780_RSOE | CM9780_CBOE |
518 CM9780_SSOE | CM9780_FROE |
519 CM9780_MIC2MIC | CM9780_LI2LI);
520 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
521 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
522 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
523 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
524 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
525 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
526 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
527 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
528 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
529 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
530 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
531 CM9780_GPO0);
532 /* power down unused ADCs and DACs */
533 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
534 AC97_PD_PR0 | AC97_PD_PR1);
535 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
536 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
537 }
538 if (chip->has_ac97_1) {
539 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
540 OXYGEN_AC97_CODEC1_SLOT3 |
541 OXYGEN_AC97_CODEC1_SLOT4);
542 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
543 msleep(1);
544 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
545 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
546 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
547 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
548 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
549 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
550 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
551 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
552 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
553 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
554 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
555 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
556 }
557}
558
559static void oxygen_shutdown(struct oxygen *chip)
560{
561 spin_lock_irq(&chip->reg_lock);
562 chip->interrupt_mask = 0;
563 chip->pcm_running = 0;
564 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
565 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
566 spin_unlock_irq(&chip->reg_lock);
567}
568
569static void oxygen_card_free(struct snd_card *card)
570{
571 struct oxygen *chip = card->private_data;
572
573 oxygen_shutdown(chip);
574 if (chip->irq >= 0)
575 free_irq(chip->irq, chip);
576 flush_work_sync(&chip->spdif_input_bits_work);
577 flush_work_sync(&chip->gpio_work);
578 chip->model.cleanup(chip);
579 kfree(chip->model_data);
580 mutex_destroy(&chip->mutex);
581 pci_release_regions(chip->pci);
582 pci_disable_device(chip->pci);
583}
584
585int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
586 struct module *owner,
587 const struct pci_device_id *ids,
588 int (*get_model)(struct oxygen *chip,
589 const struct pci_device_id *id
590 )
591 )
592{
593 struct snd_card *card;
594 struct oxygen *chip;
595 const struct pci_device_id *pci_id;
596 int err;
597
598 err = snd_card_create(index, id, owner, sizeof(*chip), &card);
599 if (err < 0)
600 return err;
601
602 chip = card->private_data;
603 chip->card = card;
604 chip->pci = pci;
605 chip->irq = -1;
606 spin_lock_init(&chip->reg_lock);
607 mutex_init(&chip->mutex);
608 INIT_WORK(&chip->spdif_input_bits_work,
609 oxygen_spdif_input_bits_changed);
610 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
611 init_waitqueue_head(&chip->ac97_waitqueue);
612
613 err = pci_enable_device(pci);
614 if (err < 0)
615 goto err_card;
616
617 err = pci_request_regions(pci, DRIVER);
618 if (err < 0) {
619 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
620 goto err_pci_enable;
621 }
622
623 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
624 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
625 snd_printk(KERN_ERR "invalid PCI I/O range\n");
626 err = -ENXIO;
627 goto err_pci_regions;
628 }
629 chip->addr = pci_resource_start(pci, 0);
630
631 pci_id = oxygen_search_pci_id(chip, ids);
632 if (!pci_id) {
633 err = -ENODEV;
634 goto err_pci_regions;
635 }
636 oxygen_restore_eeprom(chip, pci_id);
637 err = get_model(chip, pci_id);
638 if (err < 0)
639 goto err_pci_regions;
640
641 if (chip->model.model_data_size) {
642 chip->model_data = kzalloc(chip->model.model_data_size,
643 GFP_KERNEL);
644 if (!chip->model_data) {
645 err = -ENOMEM;
646 goto err_pci_regions;
647 }
648 }
649
650 pci_set_master(pci);
651 snd_card_set_dev(card, &pci->dev);
652 card->private_free = oxygen_card_free;
653
654 configure_pcie_bridge(pci);
655 oxygen_init(chip);
656 chip->model.init(chip);
657
658 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
659 KBUILD_MODNAME, chip);
660 if (err < 0) {
661 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
662 goto err_card;
663 }
664 chip->irq = pci->irq;
665
666 strcpy(card->driver, chip->model.chip);
667 strcpy(card->shortname, chip->model.shortname);
668 sprintf(card->longname, "%s at %#lx, irq %i",
669 chip->model.longname, chip->addr, chip->irq);
670 strcpy(card->mixername, chip->model.chip);
671 snd_component_add(card, chip->model.chip);
672
673 err = oxygen_pcm_init(chip);
674 if (err < 0)
675 goto err_card;
676
677 err = oxygen_mixer_init(chip);
678 if (err < 0)
679 goto err_card;
680
681 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
682 unsigned int info_flags =
683 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
684 if (chip->model.device_config & MIDI_OUTPUT)
685 info_flags |= MPU401_INFO_OUTPUT;
686 if (chip->model.device_config & MIDI_INPUT)
687 info_flags |= MPU401_INFO_INPUT;
688 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
689 chip->addr + OXYGEN_MPU401,
690 info_flags, -1, &chip->midi);
691 if (err < 0)
692 goto err_card;
693 }
694
695 oxygen_proc_init(chip);
696
697 spin_lock_irq(&chip->reg_lock);
698 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
699 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
700 if (chip->has_ac97_0 | chip->has_ac97_1)
701 chip->interrupt_mask |= OXYGEN_INT_AC97;
702 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
703 spin_unlock_irq(&chip->reg_lock);
704
705 err = snd_card_register(card);
706 if (err < 0)
707 goto err_card;
708
709 pci_set_drvdata(pci, card);
710 return 0;
711
712err_pci_regions:
713 pci_release_regions(pci);
714err_pci_enable:
715 pci_disable_device(pci);
716err_card:
717 snd_card_free(card);
718 return err;
719}
720EXPORT_SYMBOL(oxygen_pci_probe);
721
722void oxygen_pci_remove(struct pci_dev *pci)
723{
724 snd_card_free(pci_get_drvdata(pci));
725 pci_set_drvdata(pci, NULL);
726}
727EXPORT_SYMBOL(oxygen_pci_remove);
728
729#ifdef CONFIG_PM
730int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
731{
732 struct snd_card *card = pci_get_drvdata(pci);
733 struct oxygen *chip = card->private_data;
734 unsigned int i, saved_interrupt_mask;
735
736 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
737
738 for (i = 0; i < PCM_COUNT; ++i)
739 if (chip->streams[i])
740 snd_pcm_suspend(chip->streams[i]);
741
742 if (chip->model.suspend)
743 chip->model.suspend(chip);
744
745 spin_lock_irq(&chip->reg_lock);
746 saved_interrupt_mask = chip->interrupt_mask;
747 chip->interrupt_mask = 0;
748 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
749 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
750 spin_unlock_irq(&chip->reg_lock);
751
752 synchronize_irq(chip->irq);
753 flush_work_sync(&chip->spdif_input_bits_work);
754 flush_work_sync(&chip->gpio_work);
755 chip->interrupt_mask = saved_interrupt_mask;
756
757 pci_disable_device(pci);
758 pci_save_state(pci);
759 pci_set_power_state(pci, pci_choose_state(pci, state));
760 return 0;
761}
762EXPORT_SYMBOL(oxygen_pci_suspend);
763
764static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
765 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
766 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
767};
768static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
769 { 0x18284fa2, 0x03060000 },
770 { 0x00007fa6, 0x00200000 }
771};
772
773static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
774{
775 return bitmap[bit / 32] & (1 << (bit & 31));
776}
777
778static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
779{
780 unsigned int i;
781
782 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
783 msleep(1);
784 for (i = 1; i < 0x40; ++i)
785 if (is_bit_set(ac97_registers_to_restore[codec], i))
786 oxygen_write_ac97(chip, codec, i * 2,
787 chip->saved_ac97_registers[codec][i]);
788}
789
790int oxygen_pci_resume(struct pci_dev *pci)
791{
792 struct snd_card *card = pci_get_drvdata(pci);
793 struct oxygen *chip = card->private_data;
794 unsigned int i;
795
796 pci_set_power_state(pci, PCI_D0);
797 pci_restore_state(pci);
798 if (pci_enable_device(pci) < 0) {
799 snd_printk(KERN_ERR "cannot reenable device");
800 snd_card_disconnect(card);
801 return -EIO;
802 }
803 pci_set_master(pci);
804
805 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
806 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
807 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
808 if (is_bit_set(registers_to_restore, i))
809 oxygen_write8(chip, i, chip->saved_registers._8[i]);
810 if (chip->has_ac97_0)
811 oxygen_restore_ac97(chip, 0);
812 if (chip->has_ac97_1)
813 oxygen_restore_ac97(chip, 1);
814
815 if (chip->model.resume)
816 chip->model.resume(chip);
817
818 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
819
820 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
821 return 0;
822}
823EXPORT_SYMBOL(oxygen_pci_resume);
824#endif /* CONFIG_PM */
825
826void oxygen_pci_shutdown(struct pci_dev *pci)
827{
828 struct snd_card *card = pci_get_drvdata(pci);
829 struct oxygen *chip = card->private_data;
830
831 oxygen_shutdown(chip);
832 chip->model.cleanup(chip);
833}
834EXPORT_SYMBOL(oxygen_pci_shutdown);