1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * core.c - ChipIdea USB IP core family device controller
   4 *
   5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   6 * Copyright (C) 2020 NXP
   7 *
   8 * Author: David Lopo
   9 *	   Peter Chen <peter.chen@nxp.com>
  10 *
  11 * Main Features:
  12 * - Four transfers are supported, usbtest is passed
  13 * - USB Certification for gadget: CH9 and Mass Storage are passed
  14 * - Low power mode
  15 * - USB wakeup
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  16 */
  17#include <linux/delay.h>
  18#include <linux/device.h>
 
  19#include <linux/dma-mapping.h>
  20#include <linux/extcon.h>
  21#include <linux/phy/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/module.h>
  24#include <linux/idr.h>
  25#include <linux/interrupt.h>
  26#include <linux/io.h>
 
  27#include <linux/kernel.h>
  28#include <linux/slab.h>
  29#include <linux/pm_runtime.h>
  30#include <linux/pinctrl/consumer.h>
  31#include <linux/usb/ch9.h>
  32#include <linux/usb/gadget.h>
  33#include <linux/usb/otg.h>
  34#include <linux/usb/chipidea.h>
  35#include <linux/usb/of.h>
  36#include <linux/of.h>
  37#include <linux/regulator/consumer.h>
  38#include <linux/usb/ehci_def.h>
  39
  40#include "ci.h"
  41#include "udc.h"
  42#include "bits.h"
  43#include "host.h"
  44#include "otg.h"
  45#include "otg_fsm.h"
  46
  47/* Controller register map */
  48static const u8 ci_regs_nolpm[] = {
  49	[CAP_CAPLENGTH]		= 0x00U,
  50	[CAP_HCCPARAMS]		= 0x08U,
  51	[CAP_DCCPARAMS]		= 0x24U,
  52	[CAP_TESTMODE]		= 0x38U,
  53	[OP_USBCMD]		= 0x00U,
  54	[OP_USBSTS]		= 0x04U,
  55	[OP_USBINTR]		= 0x08U,
  56	[OP_DEVICEADDR]		= 0x14U,
  57	[OP_ENDPTLISTADDR]	= 0x18U,
  58	[OP_TTCTRL]		= 0x1CU,
  59	[OP_BURSTSIZE]		= 0x20U,
  60	[OP_ULPI_VIEWPORT]	= 0x30U,
  61	[OP_PORTSC]		= 0x44U,
  62	[OP_DEVLC]		= 0x84U,
  63	[OP_OTGSC]		= 0x64U,
  64	[OP_USBMODE]		= 0x68U,
  65	[OP_ENDPTSETUPSTAT]	= 0x6CU,
  66	[OP_ENDPTPRIME]		= 0x70U,
  67	[OP_ENDPTFLUSH]		= 0x74U,
  68	[OP_ENDPTSTAT]		= 0x78U,
  69	[OP_ENDPTCOMPLETE]	= 0x7CU,
  70	[OP_ENDPTCTRL]		= 0x80U,
  71};
  72
  73static const u8 ci_regs_lpm[] = {
  74	[CAP_CAPLENGTH]		= 0x00U,
  75	[CAP_HCCPARAMS]		= 0x08U,
  76	[CAP_DCCPARAMS]		= 0x24U,
  77	[CAP_TESTMODE]		= 0xFCU,
  78	[OP_USBCMD]		= 0x00U,
  79	[OP_USBSTS]		= 0x04U,
  80	[OP_USBINTR]		= 0x08U,
  81	[OP_DEVICEADDR]		= 0x14U,
  82	[OP_ENDPTLISTADDR]	= 0x18U,
  83	[OP_TTCTRL]		= 0x1CU,
  84	[OP_BURSTSIZE]		= 0x20U,
  85	[OP_ULPI_VIEWPORT]	= 0x30U,
  86	[OP_PORTSC]		= 0x44U,
  87	[OP_DEVLC]		= 0x84U,
  88	[OP_OTGSC]		= 0xC4U,
  89	[OP_USBMODE]		= 0xC8U,
  90	[OP_ENDPTSETUPSTAT]	= 0xD8U,
  91	[OP_ENDPTPRIME]		= 0xDCU,
  92	[OP_ENDPTFLUSH]		= 0xE0U,
  93	[OP_ENDPTSTAT]		= 0xE4U,
  94	[OP_ENDPTCOMPLETE]	= 0xE8U,
  95	[OP_ENDPTCTRL]		= 0xECU,
  96};
  97
  98static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
  99{
 100	int i;
 101
 
 
 
 
 
 
 
 102	for (i = 0; i < OP_ENDPTCTRL; i++)
 103		ci->hw_bank.regmap[i] =
 104			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
 105			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
 106
 107	for (; i <= OP_LAST; i++)
 108		ci->hw_bank.regmap[i] = ci->hw_bank.op +
 109			4 * (i - OP_ENDPTCTRL) +
 110			(is_lpm
 111			 ? ci_regs_lpm[OP_ENDPTCTRL]
 112			 : ci_regs_nolpm[OP_ENDPTCTRL]);
 113
 114}
 115
 116static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
 117{
 118	int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
 119	enum ci_revision rev = CI_REVISION_UNKNOWN;
 120
 121	if (ver == 0x2) {
 122		rev = hw_read_id_reg(ci, ID_ID, REVISION)
 123			>> __ffs(REVISION);
 124		rev += CI_REVISION_20;
 125	} else if (ver == 0x0) {
 126		rev = CI_REVISION_1X;
 127	}
 128
 129	return rev;
 130}
 131
 132/**
 133 * hw_read_intr_enable: returns interrupt enable register
 134 *
 135 * @ci: the controller
 136 *
 137 * This function returns register data
 138 */
 139u32 hw_read_intr_enable(struct ci_hdrc *ci)
 140{
 141	return hw_read(ci, OP_USBINTR, ~0);
 142}
 143
 144/**
 145 * hw_read_intr_status: returns interrupt status register
 146 *
 147 * @ci: the controller
 148 *
 149 * This function returns register data
 150 */
 151u32 hw_read_intr_status(struct ci_hdrc *ci)
 152{
 153	return hw_read(ci, OP_USBSTS, ~0);
 154}
 155
 156/**
 157 * hw_port_test_set: writes port test mode (execute without interruption)
 158 * @ci: the controller
 159 * @mode: new value
 160 *
 161 * This function returns an error code
 162 */
 163int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
 164{
 165	const u8 TEST_MODE_MAX = 7;
 166
 167	if (mode > TEST_MODE_MAX)
 168		return -EINVAL;
 169
 170	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
 171	return 0;
 172}
 173
 174/**
 175 * hw_port_test_get: reads port test mode value
 176 *
 177 * @ci: the controller
 178 *
 179 * This function returns port test mode value
 180 */
 181u8 hw_port_test_get(struct ci_hdrc *ci)
 182{
 183	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
 184}
 185
 186static void hw_wait_phy_stable(void)
 187{
 188	/*
 189	 * The phy needs some delay to output the stable status from low
 190	 * power mode. And for OTGSC, the status inputs are debounced
 191	 * using a 1 ms time constant, so, delay 2ms for controller to get
 192	 * the stable status, like vbus and id when the phy leaves low power.
 193	 */
 194	usleep_range(2000, 2500);
 195}
 196
 197/* The PHY enters/leaves low power mode */
 198static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
 199{
 200	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
 201	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
 202
 203	if (enable && !lpm)
 204		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 205				PORTSC_PHCD(ci->hw_bank.lpm));
 206	else if (!enable && lpm)
 207		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
 208				0);
 209}
 210
 211static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
 212{
 213	u32 reg;
 214
 215	/* bank is a module variable */
 216	ci->hw_bank.abs = base;
 217
 218	ci->hw_bank.cap = ci->hw_bank.abs;
 219	ci->hw_bank.cap += ci->platdata->capoffset;
 220	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
 221
 222	hw_alloc_regmap(ci, false);
 223	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
 224		__ffs(HCCPARAMS_LEN);
 225	ci->hw_bank.lpm  = reg;
 226	if (reg)
 227		hw_alloc_regmap(ci, !!reg);
 228	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
 229	ci->hw_bank.size += OP_LAST;
 230	ci->hw_bank.size /= sizeof(u32);
 231
 232	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
 233		__ffs(DCCPARAMS_DEN);
 234	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */
 235
 236	if (ci->hw_ep_max > ENDPT_MAX)
 237		return -ENODEV;
 238
 239	ci_hdrc_enter_lpm(ci, false);
 240
 241	/* Disable all interrupts bits */
 242	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
 243
 244	/* Clear all interrupts status bits*/
 245	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
 246
 247	ci->rev = ci_get_revision(ci);
 248
 249	dev_dbg(ci->dev,
 250		"revision: %d, lpm: %d; cap: %px op: %px\n",
 251		ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
 252
 253	/* setup lock mode ? */
 254
 255	/* ENDPTSETUPSTAT is '0' by default */
 256
 257	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
 258
 259	return 0;
 260}
 261
 262void hw_phymode_configure(struct ci_hdrc *ci)
 263{
 264	u32 portsc, lpm, sts = 0;
 265
 266	switch (ci->platdata->phy_mode) {
 267	case USBPHY_INTERFACE_MODE_UTMI:
 268		portsc = PORTSC_PTS(PTS_UTMI);
 269		lpm = DEVLC_PTS(PTS_UTMI);
 270		break;
 271	case USBPHY_INTERFACE_MODE_UTMIW:
 272		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
 273		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
 274		break;
 275	case USBPHY_INTERFACE_MODE_ULPI:
 276		portsc = PORTSC_PTS(PTS_ULPI);
 277		lpm = DEVLC_PTS(PTS_ULPI);
 278		break;
 279	case USBPHY_INTERFACE_MODE_SERIAL:
 280		portsc = PORTSC_PTS(PTS_SERIAL);
 281		lpm = DEVLC_PTS(PTS_SERIAL);
 282		sts = 1;
 283		break;
 284	case USBPHY_INTERFACE_MODE_HSIC:
 285		portsc = PORTSC_PTS(PTS_HSIC);
 286		lpm = DEVLC_PTS(PTS_HSIC);
 287		break;
 288	default:
 289		return;
 290	}
 291
 292	if (ci->hw_bank.lpm) {
 293		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
 294		if (sts)
 295			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
 296	} else {
 297		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
 298		if (sts)
 299			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
 300	}
 301}
 302EXPORT_SYMBOL_GPL(hw_phymode_configure);
 303
 304/**
 305 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
 306 * interfaces
 307 * @ci: the controller
 308 *
 309 * This function returns an error code if the phy failed to init
 310 */
 311static int _ci_usb_phy_init(struct ci_hdrc *ci)
 312{
 313	int ret;
 314
 315	if (ci->phy) {
 316		ret = phy_init(ci->phy);
 317		if (ret)
 318			return ret;
 319
 320		ret = phy_power_on(ci->phy);
 321		if (ret) {
 322			phy_exit(ci->phy);
 323			return ret;
 324		}
 325	} else {
 326		ret = usb_phy_init(ci->usb_phy);
 327	}
 328
 329	return ret;
 330}
 331
 332/**
 333 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
 334 * interfaces
 335 * @ci: the controller
 336 */
 337static void ci_usb_phy_exit(struct ci_hdrc *ci)
 338{
 339	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
 340		return;
 341
 342	if (ci->phy) {
 343		phy_power_off(ci->phy);
 344		phy_exit(ci->phy);
 345	} else {
 346		usb_phy_shutdown(ci->usb_phy);
 347	}
 348}
 349
 350/**
 351 * ci_usb_phy_init: initialize phy according to different phy type
 352 * @ci: the controller
 353 *
 354 * This function returns an error code if usb_phy_init has failed
 355 */
 356static int ci_usb_phy_init(struct ci_hdrc *ci)
 357{
 358	int ret;
 359
 360	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
 361		return 0;
 362
 363	switch (ci->platdata->phy_mode) {
 364	case USBPHY_INTERFACE_MODE_UTMI:
 365	case USBPHY_INTERFACE_MODE_UTMIW:
 366	case USBPHY_INTERFACE_MODE_HSIC:
 367		ret = _ci_usb_phy_init(ci);
 368		if (!ret)
 369			hw_wait_phy_stable();
 370		else
 371			return ret;
 372		hw_phymode_configure(ci);
 373		break;
 374	case USBPHY_INTERFACE_MODE_ULPI:
 375	case USBPHY_INTERFACE_MODE_SERIAL:
 376		hw_phymode_configure(ci);
 377		ret = _ci_usb_phy_init(ci);
 378		if (ret)
 379			return ret;
 380		break;
 381	default:
 382		ret = _ci_usb_phy_init(ci);
 383		if (!ret)
 384			hw_wait_phy_stable();
 385	}
 386
 387	return ret;
 388}
 389
 390
 391/**
 392 * ci_platform_configure: do controller configure
 393 * @ci: the controller
 394 *
 395 */
 396void ci_platform_configure(struct ci_hdrc *ci)
 397{
 398	bool is_device_mode, is_host_mode;
 399
 400	is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
 401	is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
 402
 403	if (is_device_mode) {
 404		phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
 405
 406		if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
 407			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
 408				 USBMODE_CI_SDIS);
 409	}
 410
 411	if (is_host_mode) {
 412		phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
 413
 414		if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
 415			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
 416				 USBMODE_CI_SDIS);
 417	}
 418
 419	if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
 420		if (ci->hw_bank.lpm)
 421			hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
 422		else
 423			hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
 424	}
 425
 426	if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
 427		hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
 428
 429	hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
 430
 431	if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
 432		hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
 433			ci->platdata->ahb_burst_config);
 434
 435	/* override burst size, take effect only when ahb_burst_config is 0 */
 436	if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
 437		if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
 438			hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
 439			ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
 440
 441		if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
 442			hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
 443				ci->platdata->rx_burst_size);
 444	}
 445}
 446
 447/**
 448 * hw_controller_reset: do controller reset
 449 * @ci: the controller
 450  *
 451 * This function returns an error code
 452 */
 453static int hw_controller_reset(struct ci_hdrc *ci)
 454{
 455	int count = 0;
 456
 457	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
 458	while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
 459		udelay(10);
 460		if (count++ > 1000)
 461			return -ETIMEDOUT;
 462	}
 463
 464	return 0;
 465}
 466
 467/**
 468 * hw_device_reset: resets chip (execute without interruption)
 469 * @ci: the controller
 470 *
 471 * This function returns an error code
 472 */
 473int hw_device_reset(struct ci_hdrc *ci)
 474{
 475	int ret;
 476
 477	/* should flush & stop before reset */
 478	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
 479	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
 480
 481	ret = hw_controller_reset(ci);
 482	if (ret) {
 483		dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
 484		return ret;
 485	}
 486
 487	if (ci->platdata->notify_event) {
 488		ret = ci->platdata->notify_event(ci,
 489			CI_HDRC_CONTROLLER_RESET_EVENT);
 490		if (ret)
 491			return ret;
 492	}
 
 493
 494	/* USBMODE should be configured step by step */
 495	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
 496	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
 497	/* HW >= 2.3 */
 498	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
 499
 500	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
 501		dev_err(ci->dev, "cannot enter in %s device mode\n",
 502			ci_role(ci)->name);
 503		dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
 504		return -ENODEV;
 505	}
 506
 507	ci_platform_configure(ci);
 508
 509	return 0;
 510}
 511
 512static irqreturn_t ci_irq(int irq, void *data)
 513{
 514	struct ci_hdrc *ci = data;
 515	irqreturn_t ret = IRQ_NONE;
 516	u32 otgsc = 0;
 517
 518	if (ci->in_lpm) {
 519		disable_irq_nosync(irq);
 520		ci->wakeup_int = true;
 521		pm_runtime_get(ci->dev);
 522		return IRQ_HANDLED;
 523	}
 524
 525	if (ci->is_otg) {
 526		otgsc = hw_read_otgsc(ci, ~0);
 527		if (ci_otg_is_fsm_mode(ci)) {
 528			ret = ci_otg_fsm_irq(ci);
 529			if (ret == IRQ_HANDLED)
 530				return ret;
 531		}
 532	}
 533
 534	/*
 535	 * Handle id change interrupt, it indicates device/host function
 536	 * switch.
 537	 */
 538	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
 539		ci->id_event = true;
 540		/* Clear ID change irq status */
 541		hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
 542		ci_otg_queue_work(ci);
 543		return IRQ_HANDLED;
 544	}
 545
 546	/*
 547	 * Handle vbus change interrupt, it indicates device connection
 548	 * and disconnection events.
 549	 */
 550	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
 551		ci->b_sess_valid_event = true;
 552		/* Clear BSV irq */
 553		hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
 554		ci_otg_queue_work(ci);
 555		return IRQ_HANDLED;
 556	}
 557
 558	/* Handle device/host interrupt */
 559	if (ci->role != CI_ROLE_END)
 560		ret = ci_role(ci)->irq(ci);
 561
 562	return ret;
 563}
 564
 565static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
 566			     void *ptr)
 567{
 568	struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
 569	struct ci_hdrc *ci = cbl->ci;
 570
 571	cbl->connected = event;
 572	cbl->changed = true;
 573
 574	ci_irq(ci->irq, ci);
 575	return NOTIFY_DONE;
 576}
 577
 578static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
 579{
 580	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
 581	enum usb_role role;
 582	unsigned long flags;
 583
 584	spin_lock_irqsave(&ci->lock, flags);
 585	role = ci_role_to_usb_role(ci);
 586	spin_unlock_irqrestore(&ci->lock, flags);
 587
 588	return role;
 589}
 590
 591static int ci_usb_role_switch_set(struct usb_role_switch *sw,
 592				  enum usb_role role)
 593{
 594	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
 595	struct ci_hdrc_cable *cable = NULL;
 596	enum usb_role current_role = ci_role_to_usb_role(ci);
 597	enum ci_role ci_role = usb_role_to_ci_role(role);
 598	unsigned long flags;
 599
 600	if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
 601	    (current_role == role))
 602		return 0;
 603
 604	pm_runtime_get_sync(ci->dev);
 605	/* Stop current role */
 606	spin_lock_irqsave(&ci->lock, flags);
 607	if (current_role == USB_ROLE_DEVICE)
 608		cable = &ci->platdata->vbus_extcon;
 609	else if (current_role == USB_ROLE_HOST)
 610		cable = &ci->platdata->id_extcon;
 611
 612	if (cable) {
 613		cable->changed = true;
 614		cable->connected = false;
 615		ci_irq(ci->irq, ci);
 616		spin_unlock_irqrestore(&ci->lock, flags);
 617		if (ci->wq && role != USB_ROLE_NONE)
 618			flush_workqueue(ci->wq);
 619		spin_lock_irqsave(&ci->lock, flags);
 620	}
 621
 622	cable = NULL;
 623
 624	/* Start target role */
 625	if (role == USB_ROLE_DEVICE)
 626		cable = &ci->platdata->vbus_extcon;
 627	else if (role == USB_ROLE_HOST)
 628		cable = &ci->platdata->id_extcon;
 629
 630	if (cable) {
 631		cable->changed = true;
 632		cable->connected = true;
 633		ci_irq(ci->irq, ci);
 634	}
 635	spin_unlock_irqrestore(&ci->lock, flags);
 636	pm_runtime_put_sync(ci->dev);
 637
 638	return 0;
 639}
 640
 641static struct usb_role_switch_desc ci_role_switch = {
 642	.set = ci_usb_role_switch_set,
 643	.get = ci_usb_role_switch_get,
 644	.allow_userspace_control = true,
 645};
 646
 647static int ci_get_platdata(struct device *dev,
 648		struct ci_hdrc_platform_data *platdata)
 649{
 650	struct extcon_dev *ext_vbus, *ext_id;
 651	struct ci_hdrc_cable *cable;
 652	int ret;
 653
 654	if (!platdata->phy_mode)
 655		platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
 656
 657	if (!platdata->dr_mode)
 658		platdata->dr_mode = usb_get_dr_mode(dev);
 659
 660	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
 661		platdata->dr_mode = USB_DR_MODE_OTG;
 662
 663	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
 664		/* Get the vbus regulator */
 665		platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
 666		if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
 667			return -EPROBE_DEFER;
 668		} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
 669			/* no vbus regulator is needed */
 670			platdata->reg_vbus = NULL;
 671		} else if (IS_ERR(platdata->reg_vbus)) {
 672			dev_err(dev, "Getting regulator error: %ld\n",
 673				PTR_ERR(platdata->reg_vbus));
 674			return PTR_ERR(platdata->reg_vbus);
 675		}
 676		/* Get TPL support */
 677		if (!platdata->tpl_support)
 678			platdata->tpl_support =
 679				of_usb_host_tpl_support(dev->of_node);
 680	}
 681
 682	if (platdata->dr_mode == USB_DR_MODE_OTG) {
 683		/* We can support HNP and SRP of OTG 2.0 */
 684		platdata->ci_otg_caps.otg_rev = 0x0200;
 685		platdata->ci_otg_caps.hnp_support = true;
 686		platdata->ci_otg_caps.srp_support = true;
 687
 688		/* Update otg capabilities by DT properties */
 689		ret = of_usb_update_otg_caps(dev->of_node,
 690					&platdata->ci_otg_caps);
 691		if (ret)
 692			return ret;
 693	}
 694
 695	if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
 696		platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
 697
 698	of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
 699				     &platdata->phy_clkgate_delay_us);
 700
 701	platdata->itc_setting = 1;
 702
 703	of_property_read_u32(dev->of_node, "itc-setting",
 704					&platdata->itc_setting);
 705
 706	ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
 707				&platdata->ahb_burst_config);
 708	if (!ret) {
 709		platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
 710	} else if (ret != -EINVAL) {
 711		dev_err(dev, "failed to get ahb-burst-config\n");
 712		return ret;
 713	}
 714
 715	ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
 716				&platdata->tx_burst_size);
 717	if (!ret) {
 718		platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
 719	} else if (ret != -EINVAL) {
 720		dev_err(dev, "failed to get tx-burst-size-dword\n");
 721		return ret;
 722	}
 723
 724	ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
 725				&platdata->rx_burst_size);
 726	if (!ret) {
 727		platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
 728	} else if (ret != -EINVAL) {
 729		dev_err(dev, "failed to get rx-burst-size-dword\n");
 730		return ret;
 731	}
 732
 733	if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
 734		platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
 735
 736	ext_id = ERR_PTR(-ENODEV);
 737	ext_vbus = ERR_PTR(-ENODEV);
 738	if (of_property_read_bool(dev->of_node, "extcon")) {
 739		/* Each one of them is not mandatory */
 740		ext_vbus = extcon_get_edev_by_phandle(dev, 0);
 741		if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
 742			return PTR_ERR(ext_vbus);
 743
 744		ext_id = extcon_get_edev_by_phandle(dev, 1);
 745		if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
 746			return PTR_ERR(ext_id);
 747	}
 748
 749	cable = &platdata->vbus_extcon;
 750	cable->nb.notifier_call = ci_cable_notifier;
 751	cable->edev = ext_vbus;
 752
 753	if (!IS_ERR(ext_vbus)) {
 754		ret = extcon_get_state(cable->edev, EXTCON_USB);
 755		if (ret)
 756			cable->connected = true;
 757		else
 758			cable->connected = false;
 759	}
 760
 761	cable = &platdata->id_extcon;
 762	cable->nb.notifier_call = ci_cable_notifier;
 763	cable->edev = ext_id;
 764
 765	if (!IS_ERR(ext_id)) {
 766		ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
 767		if (ret)
 768			cable->connected = true;
 769		else
 770			cable->connected = false;
 771	}
 772
 773	if (device_property_read_bool(dev, "usb-role-switch"))
 774		ci_role_switch.fwnode = dev->fwnode;
 775
 776	platdata->pctl = devm_pinctrl_get(dev);
 777	if (!IS_ERR(platdata->pctl)) {
 778		struct pinctrl_state *p;
 779
 780		p = pinctrl_lookup_state(platdata->pctl, "default");
 781		if (!IS_ERR(p))
 782			platdata->pins_default = p;
 783
 784		p = pinctrl_lookup_state(platdata->pctl, "host");
 785		if (!IS_ERR(p))
 786			platdata->pins_host = p;
 787
 788		p = pinctrl_lookup_state(platdata->pctl, "device");
 789		if (!IS_ERR(p))
 790			platdata->pins_device = p;
 791	}
 792
 793	return 0;
 794}
 795
 796static int ci_extcon_register(struct ci_hdrc *ci)
 797{
 798	struct ci_hdrc_cable *id, *vbus;
 799	int ret;
 800
 801	id = &ci->platdata->id_extcon;
 802	id->ci = ci;
 803	if (!IS_ERR_OR_NULL(id->edev)) {
 804		ret = devm_extcon_register_notifier(ci->dev, id->edev,
 805						EXTCON_USB_HOST, &id->nb);
 806		if (ret < 0) {
 807			dev_err(ci->dev, "register ID failed\n");
 808			return ret;
 809		}
 810	}
 811
 812	vbus = &ci->platdata->vbus_extcon;
 813	vbus->ci = ci;
 814	if (!IS_ERR_OR_NULL(vbus->edev)) {
 815		ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
 816						EXTCON_USB, &vbus->nb);
 817		if (ret < 0) {
 818			dev_err(ci->dev, "register VBUS failed\n");
 819			return ret;
 820		}
 821	}
 822
 823	return 0;
 824}
 825
 826static DEFINE_IDA(ci_ida);
 827
 828struct platform_device *ci_hdrc_add_device(struct device *dev,
 829			struct resource *res, int nres,
 830			struct ci_hdrc_platform_data *platdata)
 831{
 832	struct platform_device *pdev;
 833	int id, ret;
 834
 835	ret = ci_get_platdata(dev, platdata);
 836	if (ret)
 837		return ERR_PTR(ret);
 838
 839	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
 840	if (id < 0)
 841		return ERR_PTR(id);
 842
 843	pdev = platform_device_alloc("ci_hdrc", id);
 844	if (!pdev) {
 845		ret = -ENOMEM;
 846		goto put_id;
 847	}
 848
 849	pdev->dev.parent = dev;
 850
 851	ret = platform_device_add_resources(pdev, res, nres);
 852	if (ret)
 853		goto err;
 854
 855	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
 856	if (ret)
 857		goto err;
 858
 859	ret = platform_device_add(pdev);
 860	if (ret)
 861		goto err;
 862
 863	return pdev;
 864
 865err:
 866	platform_device_put(pdev);
 867put_id:
 868	ida_simple_remove(&ci_ida, id);
 869	return ERR_PTR(ret);
 870}
 871EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
 872
 873void ci_hdrc_remove_device(struct platform_device *pdev)
 874{
 875	int id = pdev->id;
 876	platform_device_unregister(pdev);
 877	ida_simple_remove(&ci_ida, id);
 878}
 879EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
 880
 881/**
 882 * ci_hdrc_query_available_role: get runtime available operation mode
 883 *
 884 * The glue layer can get current operation mode (host/peripheral/otg)
 885 * This function should be called after ci core device has created.
 886 *
 887 * @pdev: the platform device of ci core.
 888 *
 889 * Return runtime usb_dr_mode.
 890 */
 891enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
 892{
 893	struct ci_hdrc *ci = platform_get_drvdata(pdev);
 
 894
 895	if (!ci)
 896		return USB_DR_MODE_UNKNOWN;
 897	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
 898		return USB_DR_MODE_OTG;
 899	else if (ci->roles[CI_ROLE_HOST])
 900		return USB_DR_MODE_HOST;
 901	else if (ci->roles[CI_ROLE_GADGET])
 902		return USB_DR_MODE_PERIPHERAL;
 903	else
 904		return USB_DR_MODE_UNKNOWN;
 905}
 906EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
 907
 908static inline void ci_role_destroy(struct ci_hdrc *ci)
 909{
 910	ci_hdrc_gadget_destroy(ci);
 911	ci_hdrc_host_destroy(ci);
 912	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
 913		ci_hdrc_otg_destroy(ci);
 914}
 915
 916static void ci_get_otg_capable(struct ci_hdrc *ci)
 917{
 918	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
 919		ci->is_otg = false;
 920	else
 921		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
 922				DCCPARAMS_DC | DCCPARAMS_HC)
 923					== (DCCPARAMS_DC | DCCPARAMS_HC));
 924	if (ci->is_otg) {
 925		dev_dbg(ci->dev, "It is OTG capable controller\n");
 926		/* Disable and clear all OTG irq */
 927		hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
 928							OTGSC_INT_STATUS_BITS);
 929	}
 930}
 931
 932static ssize_t role_show(struct device *dev, struct device_attribute *attr,
 933			  char *buf)
 934{
 935	struct ci_hdrc *ci = dev_get_drvdata(dev);
 936
 937	if (ci->role != CI_ROLE_END)
 938		return sprintf(buf, "%s\n", ci_role(ci)->name);
 939
 940	return 0;
 941}
 942
 943static ssize_t role_store(struct device *dev,
 944		struct device_attribute *attr, const char *buf, size_t n)
 945{
 946	struct ci_hdrc *ci = dev_get_drvdata(dev);
 947	enum ci_role role;
 948	int ret;
 949
 950	if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
 951		dev_warn(dev, "Current configuration is not dual-role, quit\n");
 952		return -EPERM;
 953	}
 954
 955	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
 956		if (!strncmp(buf, ci->roles[role]->name,
 957			     strlen(ci->roles[role]->name)))
 958			break;
 959
 960	if (role == CI_ROLE_END || role == ci->role)
 961		return -EINVAL;
 962
 963	pm_runtime_get_sync(dev);
 964	disable_irq(ci->irq);
 965	ci_role_stop(ci);
 966	ret = ci_role_start(ci, role);
 967	if (!ret && ci->role == CI_ROLE_GADGET)
 968		ci_handle_vbus_change(ci);
 969	enable_irq(ci->irq);
 970	pm_runtime_put_sync(dev);
 971
 972	return (ret == 0) ? n : ret;
 973}
 974static DEVICE_ATTR_RW(role);
 975
 976static struct attribute *ci_attrs[] = {
 977	&dev_attr_role.attr,
 978	NULL,
 979};
 980ATTRIBUTE_GROUPS(ci);
 
 
 
 
 
 
 
 
 
 
 
 
 
 981
 982static int ci_hdrc_probe(struct platform_device *pdev)
 983{
 984	struct device	*dev = &pdev->dev;
 985	struct ci_hdrc	*ci;
 986	struct resource	*res;
 987	void __iomem	*base;
 988	int		ret;
 989	enum usb_dr_mode dr_mode;
 990
 991	if (!dev_get_platdata(dev)) {
 992		dev_err(dev, "platform data missing\n");
 993		return -ENODEV;
 994	}
 995
 996	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 997	base = devm_ioremap_resource(dev, res);
 998	if (IS_ERR(base))
 999		return PTR_ERR(base);
 
 
 
 
 
 
 
1000
1001	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1002	if (!ci)
 
1003		return -ENOMEM;
 
1004
1005	spin_lock_init(&ci->lock);
1006	ci->dev = dev;
1007	ci->platdata = dev_get_platdata(dev);
1008	ci->imx28_write_fix = !!(ci->platdata->flags &
1009		CI_HDRC_IMX28_WRITE_FIX);
1010	ci->supports_runtime_pm = !!(ci->platdata->flags &
1011		CI_HDRC_SUPPORTS_RUNTIME_PM);
1012	platform_set_drvdata(pdev, ci);
1013
1014	ret = hw_device_init(ci, base);
1015	if (ret < 0) {
1016		dev_err(dev, "can't initialize hardware\n");
1017		return -ENODEV;
1018	}
1019
1020	ret = ci_ulpi_init(ci);
1021	if (ret)
1022		return ret;
1023
1024	if (ci->platdata->phy) {
1025		ci->phy = ci->platdata->phy;
1026	} else if (ci->platdata->usb_phy) {
1027		ci->usb_phy = ci->platdata->usb_phy;
1028	} else {
1029		/* Look for a generic PHY first */
1030		ci->phy = devm_phy_get(dev->parent, "usb-phy");
1031
1032		if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1033			ret = -EPROBE_DEFER;
1034			goto ulpi_exit;
1035		} else if (IS_ERR(ci->phy)) {
1036			ci->phy = NULL;
1037		}
1038
1039		/* Look for a legacy USB PHY from device-tree next */
1040		if (!ci->phy) {
1041			ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1042								  "phys", 0);
1043
1044			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1045				ret = -EPROBE_DEFER;
1046				goto ulpi_exit;
1047			} else if (IS_ERR(ci->usb_phy)) {
1048				ci->usb_phy = NULL;
1049			}
1050		}
1051
1052		/* Look for any registered legacy USB PHY as last resort */
1053		if (!ci->phy && !ci->usb_phy) {
1054			ci->usb_phy = devm_usb_get_phy(dev->parent,
1055						       USB_PHY_TYPE_USB2);
1056
1057			if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1058				ret = -EPROBE_DEFER;
1059				goto ulpi_exit;
1060			} else if (IS_ERR(ci->usb_phy)) {
1061				ci->usb_phy = NULL;
1062			}
1063		}
1064
1065		/* No USB PHY was found in the end */
1066		if (!ci->phy && !ci->usb_phy) {
1067			ret = -ENXIO;
1068			goto ulpi_exit;
1069		}
1070	}
1071
1072	ret = ci_usb_phy_init(ci);
1073	if (ret) {
1074		dev_err(dev, "unable to init phy: %d\n", ret);
1075		return ret;
1076	}
1077
1078	ci->hw_bank.phys = res->start;
1079
1080	ci->irq = platform_get_irq(pdev, 0);
1081	if (ci->irq < 0) {
1082		ret = ci->irq;
1083		goto deinit_phy;
1084	}
1085
1086	ci_get_otg_capable(ci);
 
 
 
 
 
1087
1088	dr_mode = ci->platdata->dr_mode;
1089	/* initialize role(s) before the interrupt is requested */
1090	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1091		ret = ci_hdrc_host_init(ci);
1092		if (ret) {
1093			if (ret == -ENXIO)
1094				dev_info(dev, "doesn't support host\n");
1095			else
1096				goto deinit_phy;
1097		}
1098	}
1099
1100	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1101		ret = ci_hdrc_gadget_init(ci);
1102		if (ret) {
1103			if (ret == -ENXIO)
1104				dev_info(dev, "doesn't support gadget\n");
1105			else
1106				goto deinit_host;
1107		}
1108	}
1109
1110	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1111		dev_err(dev, "no supported roles\n");
1112		ret = -ENODEV;
1113		goto deinit_gadget;
1114	}
1115
1116	if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1117		ret = ci_hdrc_otg_init(ci);
1118		if (ret) {
1119			dev_err(dev, "init otg fails, ret = %d\n", ret);
1120			goto deinit_gadget;
1121		}
1122	}
1123
1124	if (ci_role_switch.fwnode) {
1125		ci_role_switch.driver_data = ci;
1126		ci->role_switch = usb_role_switch_register(dev,
1127					&ci_role_switch);
1128		if (IS_ERR(ci->role_switch)) {
1129			ret = PTR_ERR(ci->role_switch);
1130			goto deinit_otg;
1131		}
1132	}
1133
1134	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1135		if (ci->is_otg) {
1136			ci->role = ci_otg_role(ci);
1137			/* Enable ID change irq */
1138			hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1139		} else {
1140			/*
1141			 * If the controller is not OTG capable, but support
1142			 * role switch, the defalt role is gadget, and the
1143			 * user can switch it through debugfs.
1144			 */
1145			ci->role = CI_ROLE_GADGET;
1146		}
1147	} else {
1148		ci->role = ci->roles[CI_ROLE_HOST]
1149			? CI_ROLE_HOST
1150			: CI_ROLE_GADGET;
1151	}
1152
1153	if (!ci_otg_is_fsm_mode(ci)) {
1154		/* only update vbus status for peripheral */
1155		if (ci->role == CI_ROLE_GADGET) {
1156			/* Pull down DP for possible charger detection */
1157			hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1158			ci_handle_vbus_change(ci);
1159		}
1160
1161		ret = ci_role_start(ci, ci->role);
1162		if (ret) {
1163			dev_err(dev, "can't start %s role\n",
1164						ci_role(ci)->name);
1165			goto stop;
1166		}
1167	}
1168
1169	ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1170			ci->platdata->name, ci);
 
1171	if (ret)
1172		goto stop;
1173
1174	ret = ci_extcon_register(ci);
1175	if (ret)
1176		goto stop;
1177
1178	if (ci->supports_runtime_pm) {
1179		pm_runtime_set_active(&pdev->dev);
1180		pm_runtime_enable(&pdev->dev);
1181		pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1182		pm_runtime_mark_last_busy(ci->dev);
1183		pm_runtime_use_autosuspend(&pdev->dev);
1184	}
1185
1186	if (ci_otg_is_fsm_mode(ci))
1187		ci_hdrc_otg_fsm_start(ci);
1188
1189	device_set_wakeup_capable(&pdev->dev, true);
1190	dbg_create_files(ci);
1191
1192	return 0;
1193
1194stop:
1195	if (ci->role_switch)
1196		usb_role_switch_unregister(ci->role_switch);
1197deinit_otg:
1198	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1199		ci_hdrc_otg_destroy(ci);
1200deinit_gadget:
1201	ci_hdrc_gadget_destroy(ci);
1202deinit_host:
1203	ci_hdrc_host_destroy(ci);
1204deinit_phy:
1205	ci_usb_phy_exit(ci);
1206ulpi_exit:
1207	ci_ulpi_exit(ci);
1208
1209	return ret;
1210}
1211
1212static int ci_hdrc_remove(struct platform_device *pdev)
1213{
1214	struct ci_hdrc *ci = platform_get_drvdata(pdev);
1215
1216	if (ci->role_switch)
1217		usb_role_switch_unregister(ci->role_switch);
1218
1219	if (ci->supports_runtime_pm) {
1220		pm_runtime_get_sync(&pdev->dev);
1221		pm_runtime_disable(&pdev->dev);
1222		pm_runtime_put_noidle(&pdev->dev);
1223	}
1224
1225	dbg_remove_files(ci);
1226	ci_role_destroy(ci);
1227	ci_hdrc_enter_lpm(ci, true);
1228	ci_usb_phy_exit(ci);
1229	ci_ulpi_exit(ci);
1230
1231	return 0;
1232}
1233
1234#ifdef CONFIG_PM
1235/* Prepare wakeup by SRP before suspend */
1236static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1237{
1238	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1239				!hw_read_otgsc(ci, OTGSC_ID)) {
1240		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1241								PORTSC_PP);
1242		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1243								PORTSC_WKCN);
1244	}
1245}
1246
1247/* Handle SRP when wakeup by data pulse */
1248static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1249{
1250	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1251		(ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1252		if (!hw_read_otgsc(ci, OTGSC_ID)) {
1253			ci->fsm.a_srp_det = 1;
1254			ci->fsm.a_bus_drop = 0;
1255		} else {
1256			ci->fsm.id = 1;
1257		}
1258		ci_otg_queue_work(ci);
1259	}
1260}
1261
1262static void ci_controller_suspend(struct ci_hdrc *ci)
1263{
1264	disable_irq(ci->irq);
1265	ci_hdrc_enter_lpm(ci, true);
1266	if (ci->platdata->phy_clkgate_delay_us)
1267		usleep_range(ci->platdata->phy_clkgate_delay_us,
1268			     ci->platdata->phy_clkgate_delay_us + 50);
1269	usb_phy_set_suspend(ci->usb_phy, 1);
1270	ci->in_lpm = true;
1271	enable_irq(ci->irq);
1272}
1273
1274/*
1275 * Handle the wakeup interrupt triggered by extcon connector
1276 * We need to call ci_irq again for extcon since the first
1277 * interrupt (wakeup int) only let the controller be out of
1278 * low power mode, but not handle any interrupts.
1279 */
1280static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1281{
1282	struct ci_hdrc_cable *cable_id, *cable_vbus;
1283	u32 otgsc = hw_read_otgsc(ci, ~0);
1284
1285	cable_id = &ci->platdata->id_extcon;
1286	cable_vbus = &ci->platdata->vbus_extcon;
1287
1288	if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1289		(otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1290		ci_irq(ci->irq, ci);
1291
1292	if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1293		(otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1294		ci_irq(ci->irq, ci);
1295}
1296
1297static int ci_controller_resume(struct device *dev)
1298{
1299	struct ci_hdrc *ci = dev_get_drvdata(dev);
1300	int ret;
1301
1302	dev_dbg(dev, "at %s\n", __func__);
1303
1304	if (!ci->in_lpm) {
1305		WARN_ON(1);
1306		return 0;
1307	}
1308
1309	ci_hdrc_enter_lpm(ci, false);
1310
1311	ret = ci_ulpi_resume(ci);
1312	if (ret)
1313		return ret;
1314
1315	if (ci->usb_phy) {
1316		usb_phy_set_suspend(ci->usb_phy, 0);
1317		usb_phy_set_wakeup(ci->usb_phy, false);
1318		hw_wait_phy_stable();
1319	}
1320
1321	ci->in_lpm = false;
1322	if (ci->wakeup_int) {
1323		ci->wakeup_int = false;
1324		pm_runtime_mark_last_busy(ci->dev);
1325		pm_runtime_put_autosuspend(ci->dev);
1326		enable_irq(ci->irq);
1327		if (ci_otg_is_fsm_mode(ci))
1328			ci_otg_fsm_wakeup_by_srp(ci);
1329		ci_extcon_wakeup_int(ci);
1330	}
1331
1332	return 0;
1333}
1334
1335#ifdef CONFIG_PM_SLEEP
1336static int ci_suspend(struct device *dev)
1337{
1338	struct ci_hdrc *ci = dev_get_drvdata(dev);
1339
1340	if (ci->wq)
1341		flush_workqueue(ci->wq);
1342	/*
1343	 * Controller needs to be active during suspend, otherwise the core
1344	 * may run resume when the parent is at suspend if other driver's
1345	 * suspend fails, it occurs before parent's suspend has not started,
1346	 * but the core suspend has finished.
1347	 */
1348	if (ci->in_lpm)
1349		pm_runtime_resume(dev);
1350
1351	if (ci->in_lpm) {
1352		WARN_ON(1);
1353		return 0;
1354	}
1355
1356	if (device_may_wakeup(dev)) {
1357		if (ci_otg_is_fsm_mode(ci))
1358			ci_otg_fsm_suspend_for_srp(ci);
1359
1360		usb_phy_set_wakeup(ci->usb_phy, true);
1361		enable_irq_wake(ci->irq);
1362	}
1363
1364	ci_controller_suspend(ci);
1365
1366	return 0;
1367}
1368
1369static int ci_resume(struct device *dev)
1370{
1371	struct ci_hdrc *ci = dev_get_drvdata(dev);
1372	int ret;
1373
1374	if (device_may_wakeup(dev))
1375		disable_irq_wake(ci->irq);
1376
1377	ret = ci_controller_resume(dev);
1378	if (ret)
1379		return ret;
1380
1381	if (ci->supports_runtime_pm) {
1382		pm_runtime_disable(dev);
1383		pm_runtime_set_active(dev);
1384		pm_runtime_enable(dev);
1385	}
1386
1387	return ret;
1388}
1389#endif /* CONFIG_PM_SLEEP */
1390
1391static int ci_runtime_suspend(struct device *dev)
1392{
1393	struct ci_hdrc *ci = dev_get_drvdata(dev);
1394
1395	dev_dbg(dev, "at %s\n", __func__);
1396
1397	if (ci->in_lpm) {
1398		WARN_ON(1);
1399		return 0;
1400	}
1401
1402	if (ci_otg_is_fsm_mode(ci))
1403		ci_otg_fsm_suspend_for_srp(ci);
1404
1405	usb_phy_set_wakeup(ci->usb_phy, true);
1406	ci_controller_suspend(ci);
1407
1408	return 0;
1409}
1410
1411static int ci_runtime_resume(struct device *dev)
1412{
1413	return ci_controller_resume(dev);
1414}
1415
1416#endif /* CONFIG_PM */
1417static const struct dev_pm_ops ci_pm_ops = {
1418	SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1419	SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1420};
1421
1422static struct platform_driver ci_hdrc_driver = {
1423	.probe	= ci_hdrc_probe,
1424	.remove	= ci_hdrc_remove,
1425	.driver	= {
1426		.name	= "ci_hdrc",
1427		.pm	= &ci_pm_ops,
1428		.dev_groups = ci_groups,
1429	},
1430};
1431
1432static int __init ci_hdrc_platform_register(void)
1433{
1434	ci_hdrc_host_driver_init();
1435	return platform_driver_register(&ci_hdrc_driver);
1436}
1437module_init(ci_hdrc_platform_register);
1438
1439static void __exit ci_hdrc_platform_unregister(void)
1440{
1441	platform_driver_unregister(&ci_hdrc_driver);
1442}
1443module_exit(ci_hdrc_platform_unregister);
1444
1445MODULE_ALIAS("platform:ci_hdrc");
 
1446MODULE_LICENSE("GPL v2");
1447MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1448MODULE_DESCRIPTION("ChipIdea HDRC Driver");