1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2015 Intel Corporation. All rights reserved.
  4 *
  5 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  6 */
  7
  8#include <linux/platform_device.h>
  9#include <linux/regmap.h>
 10#include <linux/mfd/intel_soc_pmic.h>
 11#include <linux/pwm.h>
 12
 13#define PWM0_CLK_DIV		0x4B
 14#define  PWM_OUTPUT_ENABLE	BIT(7)
 15#define  PWM_DIV_CLK_0		0x00 /* DIVIDECLK = BASECLK */
 16#define  PWM_DIV_CLK_100	0x63 /* DIVIDECLK = BASECLK/100 */
 17#define  PWM_DIV_CLK_128	0x7F /* DIVIDECLK = BASECLK/128 */
 18
 19#define PWM0_DUTY_CYCLE		0x4E
 20#define BACKLIGHT_EN		0x51
 21
 22#define PWM_MAX_LEVEL		0xFF
 23
 24#define PWM_BASE_CLK		6000000  /* 6 MHz */
 25#define PWM_MAX_PERIOD_NS	21333    /* 46.875KHz */
 26
 27/**
 28 * struct crystalcove_pwm - Crystal Cove PWM controller
 29 * @chip: the abstract pwm_chip structure.
 30 * @regmap: the regmap from the parent device.
 31 */
 32struct crystalcove_pwm {
 33	struct pwm_chip chip;
 34	struct regmap *regmap;
 35};
 36
 37static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
 38{
 39	return container_of(pc, struct crystalcove_pwm, chip);
 40}
 41
 42static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
 43{
 44	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
 45
 46	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
 47
 48	return 0;
 49}
 50
 51static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
 52{
 53	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
 54
 55	regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
 56}
 57
 58static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
 59			  int duty_ns, int period_ns)
 60{
 61	struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
 62	struct device *dev = crc_pwm->chip.dev;
 63	int level;
 64
 65	if (period_ns > PWM_MAX_PERIOD_NS) {
 66		dev_err(dev, "un-supported period_ns\n");
 67		return -EINVAL;
 68	}
 69
 70	if (pwm_get_period(pwm) != period_ns) {
 71		int clk_div;
 72
 73		/* changing the clk divisor, need to disable fisrt */
 74		crc_pwm_disable(c, pwm);
 75		clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC;
 76
 77		regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
 78					clk_div | PWM_OUTPUT_ENABLE);
 79
 80		/* enable back */
 81		crc_pwm_enable(c, pwm);
 82	}
 83
 84	/* change the pwm duty cycle */
 85	level = duty_ns * PWM_MAX_LEVEL / period_ns;
 86	regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
 87
 88	return 0;
 89}
 90
 91static const struct pwm_ops crc_pwm_ops = {
 92	.config = crc_pwm_config,
 93	.enable = crc_pwm_enable,
 94	.disable = crc_pwm_disable,
 95};
 96
 97static int crystalcove_pwm_probe(struct platform_device *pdev)
 98{
 99	struct crystalcove_pwm *pwm;
100	struct device *dev = pdev->dev.parent;
101	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
102
103	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
104	if (!pwm)
105		return -ENOMEM;
106
107	pwm->chip.dev = &pdev->dev;
108	pwm->chip.ops = &crc_pwm_ops;
109	pwm->chip.base = -1;
110	pwm->chip.npwm = 1;
111
112	/* get the PMIC regmap */
113	pwm->regmap = pmic->regmap;
114
115	platform_set_drvdata(pdev, pwm);
116
117	return pwmchip_add(&pwm->chip);
118}
119
120static int crystalcove_pwm_remove(struct platform_device *pdev)
121{
122	struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
123
124	return pwmchip_remove(&pwm->chip);
125}
126
127static struct platform_driver crystalcove_pwm_driver = {
128	.probe = crystalcove_pwm_probe,
129	.remove = crystalcove_pwm_remove,
130	.driver = {
131		.name = "crystal_cove_pwm",
132	},
133};
134
135builtin_platform_driver(crystalcove_pwm_driver);