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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * U300 GPIO module.
4 *
5 * Copyright (C) 2007-2012 ST-Ericsson AB
6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9 */
10#include <linux/module.h>
11#include <linux/interrupt.h>
12#include <linux/delay.h>
13#include <linux/errno.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/driver.h>
19#include <linux/slab.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include "pinctrl-coh901.h"
23
24#define U300_GPIO_PORT_STRIDE (0x30)
25/*
26 * Control Register 32bit (R/W)
27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
28 * gives the number of GPIO pins.
29 * bit 8-2 (mask 0x000001FC) contains the core version ID.
30 */
31#define U300_GPIO_CR (0x00)
32#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
33#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
34#define U300_GPIO_PXPDIR (0x04)
35#define U300_GPIO_PXPDOR (0x08)
36#define U300_GPIO_PXPCR (0x0C)
37#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
38#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
39#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
40#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
41#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
42#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
43#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
44#define U300_GPIO_PXPER (0x10)
45#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
46#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
47#define U300_GPIO_PXIEV (0x14)
48#define U300_GPIO_PXIEN (0x18)
49#define U300_GPIO_PXIFR (0x1C)
50#define U300_GPIO_PXICR (0x20)
51#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
52#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
53#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
54#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
55
56/* 8 bits per port, no version has more than 7 ports */
57#define U300_GPIO_NUM_PORTS 7
58#define U300_GPIO_PINS_PER_PORT 8
59#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
60
61struct u300_gpio_port {
62 struct u300_gpio *gpio;
63 char name[8];
64 int irq;
65 int number;
66 u8 toggle_edge_mode;
67};
68
69struct u300_gpio {
70 struct gpio_chip chip;
71 struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
72 struct clk *clk;
73 void __iomem *base;
74 struct device *dev;
75 u32 stride;
76 /* Register offsets */
77 u32 pcr;
78 u32 dor;
79 u32 dir;
80 u32 per;
81 u32 icr;
82 u32 ien;
83 u32 iev;
84};
85
86/*
87 * Macro to expand to read a specific register found in the "gpio"
88 * struct. It requires the struct u300_gpio *gpio variable to exist in
89 * its context. It calculates the port offset from the given pin
90 * offset, muliplies by the port stride and adds the register offset
91 * so it provides a pointer to the desired register.
92 */
93#define U300_PIN_REG(pin, reg) \
94 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
95
96/*
97 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
98 * register.
99 */
100#define U300_PIN_BIT(pin) \
101 (1 << (pin & 0x07))
102
103struct u300_gpio_confdata {
104 u16 bias_mode;
105 bool output;
106 int outval;
107};
108
109#define U300_FLOATING_INPUT { \
110 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
111 .output = false, \
112}
113
114#define U300_PULL_UP_INPUT { \
115 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
116 .output = false, \
117}
118
119#define U300_OUTPUT_LOW { \
120 .output = true, \
121 .outval = 0, \
122}
123
124#define U300_OUTPUT_HIGH { \
125 .output = true, \
126 .outval = 1, \
127}
128
129/* Initial configuration */
130static const struct u300_gpio_confdata __initconst
131bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
132 /* Port 0, pins 0-7 */
133 {
134 U300_FLOATING_INPUT,
135 U300_OUTPUT_HIGH,
136 U300_FLOATING_INPUT,
137 U300_OUTPUT_LOW,
138 U300_OUTPUT_LOW,
139 U300_OUTPUT_LOW,
140 U300_OUTPUT_LOW,
141 U300_OUTPUT_LOW,
142 },
143 /* Port 1, pins 0-7 */
144 {
145 U300_OUTPUT_LOW,
146 U300_OUTPUT_LOW,
147 U300_OUTPUT_LOW,
148 U300_PULL_UP_INPUT,
149 U300_FLOATING_INPUT,
150 U300_OUTPUT_HIGH,
151 U300_OUTPUT_LOW,
152 U300_OUTPUT_LOW,
153 },
154 /* Port 2, pins 0-7 */
155 {
156 U300_FLOATING_INPUT,
157 U300_FLOATING_INPUT,
158 U300_FLOATING_INPUT,
159 U300_FLOATING_INPUT,
160 U300_OUTPUT_LOW,
161 U300_PULL_UP_INPUT,
162 U300_OUTPUT_LOW,
163 U300_PULL_UP_INPUT,
164 },
165 /* Port 3, pins 0-7 */
166 {
167 U300_PULL_UP_INPUT,
168 U300_OUTPUT_LOW,
169 U300_FLOATING_INPUT,
170 U300_FLOATING_INPUT,
171 U300_FLOATING_INPUT,
172 U300_FLOATING_INPUT,
173 U300_FLOATING_INPUT,
174 U300_FLOATING_INPUT,
175 },
176 /* Port 4, pins 0-7 */
177 {
178 U300_FLOATING_INPUT,
179 U300_FLOATING_INPUT,
180 U300_FLOATING_INPUT,
181 U300_FLOATING_INPUT,
182 U300_FLOATING_INPUT,
183 U300_FLOATING_INPUT,
184 U300_FLOATING_INPUT,
185 U300_FLOATING_INPUT,
186 },
187 /* Port 5, pins 0-7 */
188 {
189 U300_FLOATING_INPUT,
190 U300_FLOATING_INPUT,
191 U300_FLOATING_INPUT,
192 U300_FLOATING_INPUT,
193 U300_FLOATING_INPUT,
194 U300_FLOATING_INPUT,
195 U300_FLOATING_INPUT,
196 U300_FLOATING_INPUT,
197 },
198 /* Port 6, pind 0-7 */
199 {
200 U300_FLOATING_INPUT,
201 U300_FLOATING_INPUT,
202 U300_FLOATING_INPUT,
203 U300_FLOATING_INPUT,
204 U300_FLOATING_INPUT,
205 U300_FLOATING_INPUT,
206 U300_FLOATING_INPUT,
207 U300_FLOATING_INPUT,
208 }
209};
210
211static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
212{
213 struct u300_gpio *gpio = gpiochip_get_data(chip);
214
215 return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
216}
217
218static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
219{
220 struct u300_gpio *gpio = gpiochip_get_data(chip);
221 unsigned long flags;
222 u32 val;
223
224 local_irq_save(flags);
225
226 val = readl(U300_PIN_REG(offset, dor));
227 if (value)
228 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
229 else
230 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
231
232 local_irq_restore(flags);
233}
234
235static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
236{
237 struct u300_gpio *gpio = gpiochip_get_data(chip);
238 unsigned long flags;
239 u32 val;
240
241 local_irq_save(flags);
242 val = readl(U300_PIN_REG(offset, pcr));
243 /* Mask out this pin, note 2 bits per setting */
244 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
245 writel(val, U300_PIN_REG(offset, pcr));
246 local_irq_restore(flags);
247 return 0;
248}
249
250static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
251 int value)
252{
253 struct u300_gpio *gpio = gpiochip_get_data(chip);
254 unsigned long flags;
255 u32 oldmode;
256 u32 val;
257
258 local_irq_save(flags);
259 val = readl(U300_PIN_REG(offset, pcr));
260 /*
261 * Drive mode must be set by the special mode set function, set
262 * push/pull mode by default if no mode has been selected.
263 */
264 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
265 ((offset & 0x07) << 1));
266 /* mode = 0 means input, else some mode is already set */
267 if (oldmode == 0) {
268 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
269 ((offset & 0x07) << 1));
270 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
271 << ((offset & 0x07) << 1));
272 writel(val, U300_PIN_REG(offset, pcr));
273 }
274 u300_gpio_set(chip, offset, value);
275 local_irq_restore(flags);
276 return 0;
277}
278
279/* Returning -EINVAL means "supported but not available" */
280int u300_gpio_config_get(struct gpio_chip *chip,
281 unsigned offset,
282 unsigned long *config)
283{
284 struct u300_gpio *gpio = gpiochip_get_data(chip);
285 enum pin_config_param param = (enum pin_config_param) *config;
286 bool biasmode;
287 u32 drmode;
288
289 /* One bit per pin, clamp to bool range */
290 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
291
292 /* Mask out the two bits for this pin and shift to bits 0,1 */
293 drmode = readl(U300_PIN_REG(offset, pcr));
294 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
295 drmode >>= ((offset & 0x07) << 1);
296
297 switch (param) {
298 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
299 *config = 0;
300 if (biasmode)
301 return 0;
302 else
303 return -EINVAL;
304 break;
305 case PIN_CONFIG_BIAS_PULL_UP:
306 *config = 0;
307 if (!biasmode)
308 return 0;
309 else
310 return -EINVAL;
311 break;
312 case PIN_CONFIG_DRIVE_PUSH_PULL:
313 *config = 0;
314 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
315 return 0;
316 else
317 return -EINVAL;
318 break;
319 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
320 *config = 0;
321 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
322 return 0;
323 else
324 return -EINVAL;
325 break;
326 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
327 *config = 0;
328 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
329 return 0;
330 else
331 return -EINVAL;
332 break;
333 default:
334 break;
335 }
336 return -ENOTSUPP;
337}
338
339int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
340 enum pin_config_param param)
341{
342 struct u300_gpio *gpio = gpiochip_get_data(chip);
343 unsigned long flags;
344 u32 val;
345
346 local_irq_save(flags);
347 switch (param) {
348 case PIN_CONFIG_BIAS_DISABLE:
349 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
350 val = readl(U300_PIN_REG(offset, per));
351 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
352 break;
353 case PIN_CONFIG_BIAS_PULL_UP:
354 val = readl(U300_PIN_REG(offset, per));
355 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
356 break;
357 case PIN_CONFIG_DRIVE_PUSH_PULL:
358 val = readl(U300_PIN_REG(offset, pcr));
359 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
360 << ((offset & 0x07) << 1));
361 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
362 << ((offset & 0x07) << 1));
363 writel(val, U300_PIN_REG(offset, pcr));
364 break;
365 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
366 val = readl(U300_PIN_REG(offset, pcr));
367 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
368 << ((offset & 0x07) << 1));
369 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
370 << ((offset & 0x07) << 1));
371 writel(val, U300_PIN_REG(offset, pcr));
372 break;
373 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
374 val = readl(U300_PIN_REG(offset, pcr));
375 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
376 << ((offset & 0x07) << 1));
377 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
378 << ((offset & 0x07) << 1));
379 writel(val, U300_PIN_REG(offset, pcr));
380 break;
381 default:
382 local_irq_restore(flags);
383 dev_err(gpio->dev, "illegal configuration requested\n");
384 return -EINVAL;
385 }
386 local_irq_restore(flags);
387 return 0;
388}
389
390static const struct gpio_chip u300_gpio_chip = {
391 .label = "u300-gpio-chip",
392 .owner = THIS_MODULE,
393 .request = gpiochip_generic_request,
394 .free = gpiochip_generic_free,
395 .get = u300_gpio_get,
396 .set = u300_gpio_set,
397 .direction_input = u300_gpio_direction_input,
398 .direction_output = u300_gpio_direction_output,
399};
400
401static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
402{
403 u32 val;
404
405 val = readl(U300_PIN_REG(offset, icr));
406 /* Set mode depending on state */
407 if (u300_gpio_get(&gpio->chip, offset)) {
408 /* High now, let's trigger on falling edge next then */
409 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
410 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
411 offset);
412 } else {
413 /* Low now, let's trigger on rising edge next then */
414 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
415 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
416 offset);
417 }
418}
419
420static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
421{
422 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
423 struct u300_gpio *gpio = gpiochip_get_data(chip);
424 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
425 int offset = d->hwirq;
426 u32 val;
427
428 if ((trigger & IRQF_TRIGGER_RISING) &&
429 (trigger & IRQF_TRIGGER_FALLING)) {
430 /*
431 * The GPIO block can only trigger on falling OR rising edges,
432 * not both. So we need to toggle the mode whenever the pin
433 * goes from one state to the other with a special state flag
434 */
435 dev_dbg(gpio->dev,
436 "trigger on both rising and falling edge on pin %d\n",
437 offset);
438 port->toggle_edge_mode |= U300_PIN_BIT(offset);
439 u300_toggle_trigger(gpio, offset);
440 } else if (trigger & IRQF_TRIGGER_RISING) {
441 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
442 offset);
443 val = readl(U300_PIN_REG(offset, icr));
444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
445 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
446 } else if (trigger & IRQF_TRIGGER_FALLING) {
447 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
448 offset);
449 val = readl(U300_PIN_REG(offset, icr));
450 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
451 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
452 }
453
454 return 0;
455}
456
457static void u300_gpio_irq_enable(struct irq_data *d)
458{
459 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
460 struct u300_gpio *gpio = gpiochip_get_data(chip);
461 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
462 int offset = d->hwirq;
463 u32 val;
464 unsigned long flags;
465
466 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
467 d->hwirq, port->name, offset);
468 local_irq_save(flags);
469 val = readl(U300_PIN_REG(offset, ien));
470 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
471 local_irq_restore(flags);
472}
473
474static void u300_gpio_irq_disable(struct irq_data *d)
475{
476 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
477 struct u300_gpio *gpio = gpiochip_get_data(chip);
478 int offset = d->hwirq;
479 u32 val;
480 unsigned long flags;
481
482 local_irq_save(flags);
483 val = readl(U300_PIN_REG(offset, ien));
484 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
485 local_irq_restore(flags);
486}
487
488static struct irq_chip u300_gpio_irqchip = {
489 .name = "u300-gpio-irqchip",
490 .irq_enable = u300_gpio_irq_enable,
491 .irq_disable = u300_gpio_irq_disable,
492 .irq_set_type = u300_gpio_irq_type,
493};
494
495static void u300_gpio_irq_handler(struct irq_desc *desc)
496{
497 unsigned int irq = irq_desc_get_irq(desc);
498 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
499 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
500 struct u300_gpio *gpio = gpiochip_get_data(chip);
501 struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
502 int pinoffset = port->number << 3; /* get the right stride */
503 unsigned long val;
504
505 chained_irq_enter(parent_chip, desc);
506
507 /* Read event register */
508 val = readl(U300_PIN_REG(pinoffset, iev));
509 /* Mask relevant bits */
510 val &= 0xFFU; /* 8 bits per port */
511 /* ACK IRQ (clear event) */
512 writel(val, U300_PIN_REG(pinoffset, iev));
513
514 /* Call IRQ handler */
515 if (val != 0) {
516 int irqoffset;
517
518 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
519 int offset = pinoffset + irqoffset;
520 int pin_irq = irq_find_mapping(chip->irq.domain, offset);
521
522 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
523 pin_irq, offset);
524 generic_handle_irq(pin_irq);
525 /*
526 * Triggering IRQ on both rising and falling edge
527 * needs mockery
528 */
529 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
530 u300_toggle_trigger(gpio, offset);
531 }
532 }
533
534 chained_irq_exit(parent_chip, desc);
535}
536
537static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
538 int offset,
539 const struct u300_gpio_confdata *conf)
540{
541 /* Set mode: input or output */
542 if (conf->output) {
543 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
544
545 /* Deactivate bias mode for output */
546 u300_gpio_config_set(&gpio->chip, offset,
547 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
548
549 /* Set drive mode for output */
550 u300_gpio_config_set(&gpio->chip, offset,
551 PIN_CONFIG_DRIVE_PUSH_PULL);
552
553 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
554 offset, conf->outval);
555 } else {
556 u300_gpio_direction_input(&gpio->chip, offset);
557
558 /* Always set output low on input pins */
559 u300_gpio_set(&gpio->chip, offset, 0);
560
561 /* Set bias mode for input */
562 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
563
564 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
565 offset, conf->bias_mode);
566 }
567}
568
569static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
570{
571 int i, j;
572
573 /* Write default config and values to all pins */
574 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
575 for (j = 0; j < 8; j++) {
576 const struct u300_gpio_confdata *conf;
577 int offset = (i*8) + j;
578
579 conf = &bs335_gpio_config[i][j];
580 u300_gpio_init_pin(gpio, offset, conf);
581 }
582 }
583}
584
585/*
586 * Here we map a GPIO in the local gpio_chip pin space to a pin in
587 * the local pinctrl pin space. The pin controller used is
588 * pinctrl-u300.
589 */
590struct coh901_pinpair {
591 unsigned int offset;
592 unsigned int pin_base;
593};
594
595#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
596
597static struct coh901_pinpair coh901_pintable[] = {
598 COH901_PINRANGE(10, 426),
599 COH901_PINRANGE(11, 180),
600 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
601 COH901_PINRANGE(13, 179),
602 COH901_PINRANGE(14, 178),
603 COH901_PINRANGE(16, 194),
604 COH901_PINRANGE(17, 193),
605 COH901_PINRANGE(18, 192),
606 COH901_PINRANGE(19, 191),
607 COH901_PINRANGE(20, 186),
608 COH901_PINRANGE(21, 185),
609 COH901_PINRANGE(22, 184),
610 COH901_PINRANGE(23, 183),
611 COH901_PINRANGE(24, 182),
612 COH901_PINRANGE(25, 181),
613};
614
615static int __init u300_gpio_probe(struct platform_device *pdev)
616{
617 struct u300_gpio *gpio;
618 struct gpio_irq_chip *girq;
619 int err = 0;
620 int portno;
621 u32 val;
622 u32 ifr;
623 int i;
624
625 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
626 if (gpio == NULL)
627 return -ENOMEM;
628
629 gpio->chip = u300_gpio_chip;
630 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
631 gpio->chip.parent = &pdev->dev;
632 gpio->chip.base = 0;
633 gpio->dev = &pdev->dev;
634
635 gpio->base = devm_platform_ioremap_resource(pdev, 0);
636 if (IS_ERR(gpio->base))
637 return PTR_ERR(gpio->base);
638
639 gpio->clk = devm_clk_get(gpio->dev, NULL);
640 if (IS_ERR(gpio->clk)) {
641 err = PTR_ERR(gpio->clk);
642 dev_err(gpio->dev, "could not get GPIO clock\n");
643 return err;
644 }
645
646 err = clk_prepare_enable(gpio->clk);
647 if (err) {
648 dev_err(gpio->dev, "could not enable GPIO clock\n");
649 return err;
650 }
651
652 dev_info(gpio->dev,
653 "initializing GPIO Controller COH 901 571/3\n");
654 gpio->stride = U300_GPIO_PORT_STRIDE;
655 gpio->pcr = U300_GPIO_PXPCR;
656 gpio->dor = U300_GPIO_PXPDOR;
657 gpio->dir = U300_GPIO_PXPDIR;
658 gpio->per = U300_GPIO_PXPER;
659 gpio->icr = U300_GPIO_PXICR;
660 gpio->ien = U300_GPIO_PXIEN;
661 gpio->iev = U300_GPIO_PXIEV;
662 ifr = U300_GPIO_PXIFR;
663
664 val = readl(gpio->base + U300_GPIO_CR);
665 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
666 "number of cores: %d totalling %d pins\n",
667 ((val & 0x000001FC) >> 2),
668 ((val & 0x0000FE00) >> 9),
669 ((val & 0x0000FE00) >> 9) * 8);
670 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
671 gpio->base + U300_GPIO_CR);
672 u300_gpio_init_coh901571(gpio);
673
674 girq = &gpio->chip.irq;
675 girq->chip = &u300_gpio_irqchip;
676 girq->parent_handler = u300_gpio_irq_handler;
677 girq->num_parents = U300_GPIO_NUM_PORTS;
678 girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
679 sizeof(*girq->parents),
680 GFP_KERNEL);
681 if (!girq->parents) {
682 err = -ENOMEM;
683 goto err_dis_clk;
684 }
685 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
686 struct u300_gpio_port *port = &gpio->ports[portno];
687
688 snprintf(port->name, 8, "gpio%d", portno);
689 port->number = portno;
690 port->gpio = gpio;
691
692 port->irq = platform_get_irq(pdev, portno);
693 girq->parents[portno] = port->irq;
694
695 /* Turns off irq force (test register) for this port */
696 writel(0x0, gpio->base + portno * gpio->stride + ifr);
697 }
698 girq->default_type = IRQ_TYPE_EDGE_FALLING;
699 girq->handler = handle_simple_irq;
700#ifdef CONFIG_OF_GPIO
701 gpio->chip.of_node = pdev->dev.of_node;
702#endif
703 err = gpiochip_add_data(&gpio->chip, gpio);
704 if (err) {
705 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
706 goto err_dis_clk;
707 }
708
709 /*
710 * Add pinctrl pin ranges, the pin controller must be registered
711 * at this point
712 */
713 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
714 struct coh901_pinpair *p = &coh901_pintable[i];
715
716 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
717 p->offset, p->pin_base, 1);
718 if (err)
719 goto err_no_range;
720 }
721
722 platform_set_drvdata(pdev, gpio);
723
724 return 0;
725
726err_no_range:
727 gpiochip_remove(&gpio->chip);
728err_dis_clk:
729 clk_disable_unprepare(gpio->clk);
730 dev_err(&pdev->dev, "module ERROR:%d\n", err);
731 return err;
732}
733
734static int __exit u300_gpio_remove(struct platform_device *pdev)
735{
736 struct u300_gpio *gpio = platform_get_drvdata(pdev);
737
738 /* Turn off the GPIO block */
739 writel(0x00000000U, gpio->base + U300_GPIO_CR);
740
741 gpiochip_remove(&gpio->chip);
742 clk_disable_unprepare(gpio->clk);
743 return 0;
744}
745
746static const struct of_device_id u300_gpio_match[] = {
747 { .compatible = "stericsson,gpio-coh901" },
748 {},
749};
750
751static struct platform_driver u300_gpio_driver = {
752 .driver = {
753 .name = "u300-gpio",
754 .of_match_table = u300_gpio_match,
755 },
756 .remove = __exit_p(u300_gpio_remove),
757};
758
759static int __init u300_gpio_init(void)
760{
761 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
762}
763
764static void __exit u300_gpio_exit(void)
765{
766 platform_driver_unregister(&u300_gpio_driver);
767}
768
769arch_initcall(u300_gpio_init);
770module_exit(u300_gpio_exit);
771
772MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
773MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
774MODULE_LICENSE("GPL");
1/*
2 * U300 GPIO module.
3 *
4 * Copyright (C) 2007-2011 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */
13#include <linux/module.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <linux/list.h>
24#include <linux/slab.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <mach/gpio-u300.h>
28#include "pinctrl-coh901.h"
29
30/*
31 * Register definitions for COH 901 335 variant
32 */
33#define U300_335_PORT_STRIDE (0x1C)
34/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
35#define U300_335_PXPDIR (0x00)
36#define U300_335_PXPDOR (0x00)
37/* Port X Pin Config Register 32bit (R/W) */
38#define U300_335_PXPCR (0x04)
39/* This register layout is the same in both blocks */
40#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
41#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
43#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
47/* Port X Interrupt Event Register 32bit (R/W) */
48#define U300_335_PXIEV (0x08)
49/* Port X Interrupt Enable Register 32bit (R/W) */
50#define U300_335_PXIEN (0x0C)
51/* Port X Interrupt Force Register 32bit (R/W) */
52#define U300_335_PXIFR (0x10)
53/* Port X Interrupt Config Register 32bit (R/W) */
54#define U300_335_PXICR (0x14)
55/* This register layout is the same in both blocks */
56#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
57#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
58#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
59#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
60/* Port X Pull-up Enable Register 32bit (R/W) */
61#define U300_335_PXPER (0x18)
62/* This register layout is the same in both blocks */
63#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
64#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
65/* Control Register 32bit (R/W) */
66#define U300_335_CR (0x54)
67#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
68
69/*
70 * Register definitions for COH 901 571 / 3 variant
71 */
72#define U300_571_PORT_STRIDE (0x30)
73/*
74 * Control Register 32bit (R/W)
75 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
76 * gives the number of GPIO pins.
77 * bit 8-2 (mask 0x000001FC) contains the core version ID.
78 */
79#define U300_571_CR (0x00)
80#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
81#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
82/*
83 * These registers have the same layout and function as the corresponding
84 * COH 901 335 registers, just at different offset.
85 */
86#define U300_571_PXPDIR (0x04)
87#define U300_571_PXPDOR (0x08)
88#define U300_571_PXPCR (0x0C)
89#define U300_571_PXPER (0x10)
90#define U300_571_PXIEV (0x14)
91#define U300_571_PXIEN (0x18)
92#define U300_571_PXIFR (0x1C)
93#define U300_571_PXICR (0x20)
94
95/* 8 bits per port, no version has more than 7 ports */
96#define U300_GPIO_PINS_PER_PORT 8
97#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
98
99struct u300_gpio {
100 struct gpio_chip chip;
101 struct list_head port_list;
102 struct clk *clk;
103 struct resource *memres;
104 void __iomem *base;
105 struct device *dev;
106 int irq_base;
107 u32 stride;
108 /* Register offsets */
109 u32 pcr;
110 u32 dor;
111 u32 dir;
112 u32 per;
113 u32 icr;
114 u32 ien;
115 u32 iev;
116};
117
118struct u300_gpio_port {
119 struct list_head node;
120 struct u300_gpio *gpio;
121 char name[8];
122 int irq;
123 int number;
124 u8 toggle_edge_mode;
125};
126
127/*
128 * Macro to expand to read a specific register found in the "gpio"
129 * struct. It requires the struct u300_gpio *gpio variable to exist in
130 * its context. It calculates the port offset from the given pin
131 * offset, muliplies by the port stride and adds the register offset
132 * so it provides a pointer to the desired register.
133 */
134#define U300_PIN_REG(pin, reg) \
135 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
136
137/*
138 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
139 * register.
140 */
141#define U300_PIN_BIT(pin) \
142 (1 << (pin & 0x07))
143
144struct u300_gpio_confdata {
145 u16 bias_mode;
146 bool output;
147 int outval;
148};
149
150/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
151#define BS335_GPIO_NUM_PORTS 7
152/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
153#define BS365_GPIO_NUM_PORTS 5
154
155#define U300_FLOATING_INPUT { \
156 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
157 .output = false, \
158}
159
160#define U300_PULL_UP_INPUT { \
161 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
162 .output = false, \
163}
164
165#define U300_OUTPUT_LOW { \
166 .output = true, \
167 .outval = 0, \
168}
169
170#define U300_OUTPUT_HIGH { \
171 .output = true, \
172 .outval = 1, \
173}
174
175
176/* Initial configuration */
177static const struct __initconst u300_gpio_confdata
178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
179 /* Port 0, pins 0-7 */
180 {
181 U300_FLOATING_INPUT,
182 U300_OUTPUT_HIGH,
183 U300_FLOATING_INPUT,
184 U300_OUTPUT_LOW,
185 U300_OUTPUT_LOW,
186 U300_OUTPUT_LOW,
187 U300_OUTPUT_LOW,
188 U300_OUTPUT_LOW,
189 },
190 /* Port 1, pins 0-7 */
191 {
192 U300_OUTPUT_LOW,
193 U300_OUTPUT_LOW,
194 U300_OUTPUT_LOW,
195 U300_PULL_UP_INPUT,
196 U300_FLOATING_INPUT,
197 U300_OUTPUT_HIGH,
198 U300_OUTPUT_LOW,
199 U300_OUTPUT_LOW,
200 },
201 /* Port 2, pins 0-7 */
202 {
203 U300_FLOATING_INPUT,
204 U300_FLOATING_INPUT,
205 U300_FLOATING_INPUT,
206 U300_FLOATING_INPUT,
207 U300_OUTPUT_LOW,
208 U300_PULL_UP_INPUT,
209 U300_OUTPUT_LOW,
210 U300_PULL_UP_INPUT,
211 },
212 /* Port 3, pins 0-7 */
213 {
214 U300_PULL_UP_INPUT,
215 U300_OUTPUT_LOW,
216 U300_FLOATING_INPUT,
217 U300_FLOATING_INPUT,
218 U300_FLOATING_INPUT,
219 U300_FLOATING_INPUT,
220 U300_FLOATING_INPUT,
221 U300_FLOATING_INPUT,
222 },
223 /* Port 4, pins 0-7 */
224 {
225 U300_FLOATING_INPUT,
226 U300_FLOATING_INPUT,
227 U300_FLOATING_INPUT,
228 U300_FLOATING_INPUT,
229 U300_FLOATING_INPUT,
230 U300_FLOATING_INPUT,
231 U300_FLOATING_INPUT,
232 U300_FLOATING_INPUT,
233 },
234 /* Port 5, pins 0-7 */
235 {
236 U300_FLOATING_INPUT,
237 U300_FLOATING_INPUT,
238 U300_FLOATING_INPUT,
239 U300_FLOATING_INPUT,
240 U300_FLOATING_INPUT,
241 U300_FLOATING_INPUT,
242 U300_FLOATING_INPUT,
243 U300_FLOATING_INPUT,
244 },
245 /* Port 6, pind 0-7 */
246 {
247 U300_FLOATING_INPUT,
248 U300_FLOATING_INPUT,
249 U300_FLOATING_INPUT,
250 U300_FLOATING_INPUT,
251 U300_FLOATING_INPUT,
252 U300_FLOATING_INPUT,
253 U300_FLOATING_INPUT,
254 U300_FLOATING_INPUT,
255 }
256};
257
258static const struct __initconst u300_gpio_confdata
259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260 /* Port 0, pins 0-7 */
261 {
262 U300_FLOATING_INPUT,
263 U300_OUTPUT_LOW,
264 U300_FLOATING_INPUT,
265 U300_OUTPUT_LOW,
266 U300_OUTPUT_LOW,
267 U300_OUTPUT_LOW,
268 U300_PULL_UP_INPUT,
269 U300_FLOATING_INPUT,
270 },
271 /* Port 1, pins 0-7 */
272 {
273 U300_OUTPUT_LOW,
274 U300_FLOATING_INPUT,
275 U300_OUTPUT_LOW,
276 U300_FLOATING_INPUT,
277 U300_FLOATING_INPUT,
278 U300_OUTPUT_HIGH,
279 U300_OUTPUT_LOW,
280 U300_OUTPUT_LOW,
281 },
282 /* Port 2, pins 0-7 */
283 {
284 U300_FLOATING_INPUT,
285 U300_PULL_UP_INPUT,
286 U300_OUTPUT_LOW,
287 U300_OUTPUT_LOW,
288 U300_PULL_UP_INPUT,
289 U300_PULL_UP_INPUT,
290 U300_PULL_UP_INPUT,
291 U300_PULL_UP_INPUT,
292 },
293 /* Port 3, pins 0-7 */
294 {
295 U300_PULL_UP_INPUT,
296 U300_PULL_UP_INPUT,
297 U300_PULL_UP_INPUT,
298 U300_PULL_UP_INPUT,
299 U300_PULL_UP_INPUT,
300 U300_PULL_UP_INPUT,
301 U300_PULL_UP_INPUT,
302 U300_PULL_UP_INPUT,
303 },
304 /* Port 4, pins 0-7 */
305 {
306 U300_PULL_UP_INPUT,
307 U300_PULL_UP_INPUT,
308 U300_PULL_UP_INPUT,
309 U300_PULL_UP_INPUT,
310 /* These 4 pins doesn't exist on DB3210 */
311 U300_OUTPUT_LOW,
312 U300_OUTPUT_LOW,
313 U300_OUTPUT_LOW,
314 U300_OUTPUT_LOW,
315 }
316};
317
318/**
319 * to_u300_gpio() - get the pointer to u300_gpio
320 * @chip: the gpio chip member of the structure u300_gpio
321 */
322static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
323{
324 return container_of(chip, struct u300_gpio, chip);
325}
326
327static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
328{
329 /*
330 * Map back to global GPIO space and request muxing, the direction
331 * parameter does not matter for this controller.
332 */
333 int gpio = chip->base + offset;
334
335 return pinctrl_request_gpio(gpio);
336}
337
338static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
339{
340 int gpio = chip->base + offset;
341
342 pinctrl_free_gpio(gpio);
343}
344
345static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
346{
347 struct u300_gpio *gpio = to_u300_gpio(chip);
348
349 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
350}
351
352static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
353{
354 struct u300_gpio *gpio = to_u300_gpio(chip);
355 unsigned long flags;
356 u32 val;
357
358 local_irq_save(flags);
359
360 val = readl(U300_PIN_REG(offset, dor));
361 if (value)
362 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
363 else
364 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
365
366 local_irq_restore(flags);
367}
368
369static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
370{
371 struct u300_gpio *gpio = to_u300_gpio(chip);
372 unsigned long flags;
373 u32 val;
374
375 local_irq_save(flags);
376 val = readl(U300_PIN_REG(offset, pcr));
377 /* Mask out this pin, note 2 bits per setting */
378 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
379 writel(val, U300_PIN_REG(offset, pcr));
380 local_irq_restore(flags);
381 return 0;
382}
383
384static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
385 int value)
386{
387 struct u300_gpio *gpio = to_u300_gpio(chip);
388 unsigned long flags;
389 u32 oldmode;
390 u32 val;
391
392 local_irq_save(flags);
393 val = readl(U300_PIN_REG(offset, pcr));
394 /*
395 * Drive mode must be set by the special mode set function, set
396 * push/pull mode by default if no mode has been selected.
397 */
398 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
399 ((offset & 0x07) << 1));
400 /* mode = 0 means input, else some mode is already set */
401 if (oldmode == 0) {
402 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
403 ((offset & 0x07) << 1));
404 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
405 << ((offset & 0x07) << 1));
406 writel(val, U300_PIN_REG(offset, pcr));
407 }
408 u300_gpio_set(chip, offset, value);
409 local_irq_restore(flags);
410 return 0;
411}
412
413static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
414{
415 struct u300_gpio *gpio = to_u300_gpio(chip);
416 int retirq = gpio->irq_base + offset;
417
418 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
419 retirq);
420 return retirq;
421}
422
423/* Returning -EINVAL means "supported but not available" */
424int u300_gpio_config_get(struct gpio_chip *chip,
425 unsigned offset,
426 unsigned long *config)
427{
428 struct u300_gpio *gpio = to_u300_gpio(chip);
429 enum pin_config_param param = (enum pin_config_param) *config;
430 bool biasmode;
431 u32 drmode;
432
433 /* One bit per pin, clamp to bool range */
434 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
435
436 /* Mask out the two bits for this pin and shift to bits 0,1 */
437 drmode = readl(U300_PIN_REG(offset, pcr));
438 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
439 drmode >>= ((offset & 0x07) << 1);
440
441 switch(param) {
442 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
443 *config = 0;
444 if (biasmode)
445 return 0;
446 else
447 return -EINVAL;
448 break;
449 case PIN_CONFIG_BIAS_PULL_UP:
450 *config = 0;
451 if (!biasmode)
452 return 0;
453 else
454 return -EINVAL;
455 break;
456 case PIN_CONFIG_DRIVE_PUSH_PULL:
457 *config = 0;
458 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
459 return 0;
460 else
461 return -EINVAL;
462 break;
463 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
464 *config = 0;
465 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
466 return 0;
467 else
468 return -EINVAL;
469 break;
470 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
471 *config = 0;
472 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
473 return 0;
474 else
475 return -EINVAL;
476 break;
477 default:
478 break;
479 }
480 return -ENOTSUPP;
481}
482
483int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
484 enum pin_config_param param)
485{
486 struct u300_gpio *gpio = to_u300_gpio(chip);
487 unsigned long flags;
488 u32 val;
489
490 local_irq_save(flags);
491 switch (param) {
492 case PIN_CONFIG_BIAS_DISABLE:
493 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
494 val = readl(U300_PIN_REG(offset, per));
495 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
496 break;
497 case PIN_CONFIG_BIAS_PULL_UP:
498 val = readl(U300_PIN_REG(offset, per));
499 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
500 break;
501 case PIN_CONFIG_DRIVE_PUSH_PULL:
502 val = readl(U300_PIN_REG(offset, pcr));
503 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
504 << ((offset & 0x07) << 1));
505 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
506 << ((offset & 0x07) << 1));
507 writel(val, U300_PIN_REG(offset, pcr));
508 break;
509 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
510 val = readl(U300_PIN_REG(offset, pcr));
511 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
512 << ((offset & 0x07) << 1));
513 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
514 << ((offset & 0x07) << 1));
515 writel(val, U300_PIN_REG(offset, pcr));
516 break;
517 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
518 val = readl(U300_PIN_REG(offset, pcr));
519 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
520 << ((offset & 0x07) << 1));
521 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
522 << ((offset & 0x07) << 1));
523 writel(val, U300_PIN_REG(offset, pcr));
524 break;
525 default:
526 local_irq_restore(flags);
527 dev_err(gpio->dev, "illegal configuration requested\n");
528 return -EINVAL;
529 }
530 local_irq_restore(flags);
531 return 0;
532}
533
534static struct gpio_chip u300_gpio_chip = {
535 .label = "u300-gpio-chip",
536 .owner = THIS_MODULE,
537 .request = u300_gpio_request,
538 .free = u300_gpio_free,
539 .get = u300_gpio_get,
540 .set = u300_gpio_set,
541 .direction_input = u300_gpio_direction_input,
542 .direction_output = u300_gpio_direction_output,
543 .to_irq = u300_gpio_to_irq,
544};
545
546static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
547{
548 u32 val;
549
550 val = readl(U300_PIN_REG(offset, icr));
551 /* Set mode depending on state */
552 if (u300_gpio_get(&gpio->chip, offset)) {
553 /* High now, let's trigger on falling edge next then */
554 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
555 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
556 offset);
557 } else {
558 /* Low now, let's trigger on rising edge next then */
559 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
560 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
561 offset);
562 }
563}
564
565static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
566{
567 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
568 struct u300_gpio *gpio = port->gpio;
569 int offset = d->irq - gpio->irq_base;
570 u32 val;
571
572 if ((trigger & IRQF_TRIGGER_RISING) &&
573 (trigger & IRQF_TRIGGER_FALLING)) {
574 /*
575 * The GPIO block can only trigger on falling OR rising edges,
576 * not both. So we need to toggle the mode whenever the pin
577 * goes from one state to the other with a special state flag
578 */
579 dev_dbg(gpio->dev,
580 "trigger on both rising and falling edge on pin %d\n",
581 offset);
582 port->toggle_edge_mode |= U300_PIN_BIT(offset);
583 u300_toggle_trigger(gpio, offset);
584 } else if (trigger & IRQF_TRIGGER_RISING) {
585 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
586 offset);
587 val = readl(U300_PIN_REG(offset, icr));
588 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
589 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
590 } else if (trigger & IRQF_TRIGGER_FALLING) {
591 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
592 offset);
593 val = readl(U300_PIN_REG(offset, icr));
594 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
595 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
596 }
597
598 return 0;
599}
600
601static void u300_gpio_irq_enable(struct irq_data *d)
602{
603 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
604 struct u300_gpio *gpio = port->gpio;
605 int offset = d->irq - gpio->irq_base;
606 u32 val;
607 unsigned long flags;
608
609 local_irq_save(flags);
610 val = readl(U300_PIN_REG(offset, ien));
611 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
612 local_irq_restore(flags);
613}
614
615static void u300_gpio_irq_disable(struct irq_data *d)
616{
617 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
618 struct u300_gpio *gpio = port->gpio;
619 int offset = d->irq - gpio->irq_base;
620 u32 val;
621 unsigned long flags;
622
623 local_irq_save(flags);
624 val = readl(U300_PIN_REG(offset, ien));
625 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
626 local_irq_restore(flags);
627}
628
629static struct irq_chip u300_gpio_irqchip = {
630 .name = "u300-gpio-irqchip",
631 .irq_enable = u300_gpio_irq_enable,
632 .irq_disable = u300_gpio_irq_disable,
633 .irq_set_type = u300_gpio_irq_type,
634
635};
636
637static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
638{
639 struct u300_gpio_port *port = irq_get_handler_data(irq);
640 struct u300_gpio *gpio = port->gpio;
641 int pinoffset = port->number << 3; /* get the right stride */
642 unsigned long val;
643
644 desc->irq_data.chip->irq_ack(&desc->irq_data);
645 /* Read event register */
646 val = readl(U300_PIN_REG(pinoffset, iev));
647 /* Mask relevant bits */
648 val &= 0xFFU; /* 8 bits per port */
649 /* ACK IRQ (clear event) */
650 writel(val, U300_PIN_REG(pinoffset, iev));
651
652 /* Call IRQ handler */
653 if (val != 0) {
654 int irqoffset;
655
656 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
657 int pin_irq = gpio->irq_base + (port->number << 3)
658 + irqoffset;
659 int offset = pinoffset + irqoffset;
660
661 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
662 pin_irq, offset);
663 generic_handle_irq(pin_irq);
664 /*
665 * Triggering IRQ on both rising and falling edge
666 * needs mockery
667 */
668 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
669 u300_toggle_trigger(gpio, offset);
670 }
671 }
672
673 desc->irq_data.chip->irq_unmask(&desc->irq_data);
674}
675
676static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
677 int offset,
678 const struct u300_gpio_confdata *conf)
679{
680 /* Set mode: input or output */
681 if (conf->output) {
682 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
683
684 /* Deactivate bias mode for output */
685 u300_gpio_config_set(&gpio->chip, offset,
686 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
687
688 /* Set drive mode for output */
689 u300_gpio_config_set(&gpio->chip, offset,
690 PIN_CONFIG_DRIVE_PUSH_PULL);
691
692 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
693 offset, conf->outval);
694 } else {
695 u300_gpio_direction_input(&gpio->chip, offset);
696
697 /* Always set output low on input pins */
698 u300_gpio_set(&gpio->chip, offset, 0);
699
700 /* Set bias mode for input */
701 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
702
703 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
704 offset, conf->bias_mode);
705 }
706}
707
708static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
709 struct u300_gpio_platform *plat)
710{
711 int i, j;
712
713 /* Write default config and values to all pins */
714 for (i = 0; i < plat->ports; i++) {
715 for (j = 0; j < 8; j++) {
716 const struct u300_gpio_confdata *conf;
717 int offset = (i*8) + j;
718
719 if (plat->variant == U300_GPIO_COH901571_3_BS335)
720 conf = &bs335_gpio_config[i][j];
721 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
722 conf = &bs365_gpio_config[i][j];
723 else
724 break;
725
726 u300_gpio_init_pin(gpio, offset, conf);
727 }
728 }
729}
730
731static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
732{
733 struct u300_gpio_port *port;
734 struct list_head *p, *n;
735
736 list_for_each_safe(p, n, &gpio->port_list) {
737 port = list_entry(p, struct u300_gpio_port, node);
738 list_del(&port->node);
739 kfree(port);
740 }
741}
742
743static int __init u300_gpio_probe(struct platform_device *pdev)
744{
745 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
746 struct u300_gpio *gpio;
747 int err = 0;
748 int portno;
749 u32 val;
750 u32 ifr;
751 int i;
752
753 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
754 if (gpio == NULL) {
755 dev_err(&pdev->dev, "failed to allocate memory\n");
756 return -ENOMEM;
757 }
758
759 gpio->chip = u300_gpio_chip;
760 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
761 gpio->irq_base = plat->gpio_irq_base;
762 gpio->chip.dev = &pdev->dev;
763 gpio->chip.base = plat->gpio_base;
764 gpio->dev = &pdev->dev;
765
766 /* Get GPIO clock */
767 gpio->clk = clk_get(gpio->dev, NULL);
768 if (IS_ERR(gpio->clk)) {
769 err = PTR_ERR(gpio->clk);
770 dev_err(gpio->dev, "could not get GPIO clock\n");
771 goto err_no_clk;
772 }
773 err = clk_enable(gpio->clk);
774 if (err) {
775 dev_err(gpio->dev, "could not enable GPIO clock\n");
776 goto err_no_clk_enable;
777 }
778
779 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
780 if (!gpio->memres) {
781 dev_err(gpio->dev, "could not get GPIO memory resource\n");
782 err = -ENODEV;
783 goto err_no_resource;
784 }
785
786 if (!request_mem_region(gpio->memres->start,
787 resource_size(gpio->memres),
788 "GPIO Controller")) {
789 err = -ENODEV;
790 goto err_no_ioregion;
791 }
792
793 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
794 if (!gpio->base) {
795 err = -ENOMEM;
796 goto err_no_ioremap;
797 }
798
799 if (plat->variant == U300_GPIO_COH901335) {
800 dev_info(gpio->dev,
801 "initializing GPIO Controller COH 901 335\n");
802 gpio->stride = U300_335_PORT_STRIDE;
803 gpio->pcr = U300_335_PXPCR;
804 gpio->dor = U300_335_PXPDOR;
805 gpio->dir = U300_335_PXPDIR;
806 gpio->per = U300_335_PXPER;
807 gpio->icr = U300_335_PXICR;
808 gpio->ien = U300_335_PXIEN;
809 gpio->iev = U300_335_PXIEV;
810 ifr = U300_335_PXIFR;
811
812 /* Turn on the GPIO block */
813 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
814 gpio->base + U300_335_CR);
815 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
816 plat->variant == U300_GPIO_COH901571_3_BS365) {
817 dev_info(gpio->dev,
818 "initializing GPIO Controller COH 901 571/3\n");
819 gpio->stride = U300_571_PORT_STRIDE;
820 gpio->pcr = U300_571_PXPCR;
821 gpio->dor = U300_571_PXPDOR;
822 gpio->dir = U300_571_PXPDIR;
823 gpio->per = U300_571_PXPER;
824 gpio->icr = U300_571_PXICR;
825 gpio->ien = U300_571_PXIEN;
826 gpio->iev = U300_571_PXIEV;
827 ifr = U300_571_PXIFR;
828
829 val = readl(gpio->base + U300_571_CR);
830 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
831 "number of cores: %d totalling %d pins\n",
832 ((val & 0x000001FC) >> 2),
833 ((val & 0x0000FE00) >> 9),
834 ((val & 0x0000FE00) >> 9) * 8);
835 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
836 gpio->base + U300_571_CR);
837 u300_gpio_init_coh901571(gpio, plat);
838 } else {
839 dev_err(gpio->dev, "unknown block variant\n");
840 err = -ENODEV;
841 goto err_unknown_variant;
842 }
843
844 /* Add each port with its IRQ separately */
845 INIT_LIST_HEAD(&gpio->port_list);
846 for (portno = 0 ; portno < plat->ports; portno++) {
847 struct u300_gpio_port *port =
848 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
849
850 if (!port) {
851 dev_err(gpio->dev, "out of memory\n");
852 err = -ENOMEM;
853 goto err_no_port;
854 }
855
856 snprintf(port->name, 8, "gpio%d", portno);
857 port->number = portno;
858 port->gpio = gpio;
859
860 port->irq = platform_get_irq_byname(pdev,
861 port->name);
862
863 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
864 port->name);
865
866 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
867 irq_set_handler_data(port->irq, port);
868
869 /* For each GPIO pin set the unique IRQ handler */
870 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
871 int irqno = gpio->irq_base + (portno << 3) + i;
872
873 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
874 irqno, port->name);
875 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
876 handle_simple_irq);
877 set_irq_flags(irqno, IRQF_VALID);
878 irq_set_chip_data(irqno, port);
879 }
880
881 /* Turns off irq force (test register) for this port */
882 writel(0x0, gpio->base + portno * gpio->stride + ifr);
883
884 list_add_tail(&port->node, &gpio->port_list);
885 }
886 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
887
888 err = gpiochip_add(&gpio->chip);
889 if (err) {
890 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
891 goto err_no_chip;
892 }
893
894 /* Spawn pin controller device as child of the GPIO, pass gpio chip */
895 plat->pinctrl_device->dev.platform_data = &gpio->chip;
896 err = platform_device_register(plat->pinctrl_device);
897 if (err)
898 goto err_no_pinctrl;
899
900 platform_set_drvdata(pdev, gpio);
901
902 return 0;
903
904err_no_pinctrl:
905 err = gpiochip_remove(&gpio->chip);
906err_no_chip:
907err_no_port:
908 u300_gpio_free_ports(gpio);
909err_unknown_variant:
910 iounmap(gpio->base);
911err_no_ioremap:
912 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
913err_no_ioregion:
914err_no_resource:
915 clk_disable(gpio->clk);
916err_no_clk_enable:
917 clk_put(gpio->clk);
918err_no_clk:
919 kfree(gpio);
920 dev_info(&pdev->dev, "module ERROR:%d\n", err);
921 return err;
922}
923
924static int __exit u300_gpio_remove(struct platform_device *pdev)
925{
926 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
927 struct u300_gpio *gpio = platform_get_drvdata(pdev);
928 int err;
929
930 /* Turn off the GPIO block */
931 if (plat->variant == U300_GPIO_COH901335)
932 writel(0x00000000U, gpio->base + U300_335_CR);
933 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
934 plat->variant == U300_GPIO_COH901571_3_BS365)
935 writel(0x00000000U, gpio->base + U300_571_CR);
936
937 err = gpiochip_remove(&gpio->chip);
938 if (err < 0) {
939 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
940 return err;
941 }
942 u300_gpio_free_ports(gpio);
943 iounmap(gpio->base);
944 release_mem_region(gpio->memres->start,
945 resource_size(gpio->memres));
946 clk_disable(gpio->clk);
947 clk_put(gpio->clk);
948 platform_set_drvdata(pdev, NULL);
949 kfree(gpio);
950 return 0;
951}
952
953static struct platform_driver u300_gpio_driver = {
954 .driver = {
955 .name = "u300-gpio",
956 },
957 .remove = __exit_p(u300_gpio_remove),
958};
959
960static int __init u300_gpio_init(void)
961{
962 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
963}
964
965static void __exit u300_gpio_exit(void)
966{
967 platform_driver_unregister(&u300_gpio_driver);
968}
969
970arch_initcall(u300_gpio_init);
971module_exit(u300_gpio_exit);
972
973MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
974MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
975MODULE_LICENSE("GPL");