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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DB8500 PRCM Unit driver
4 *
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
7 *
8 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
11 *
12 * U8500 PRCM Unit interface driver
13 */
14#include <linux/init.h>
15#include <linux/export.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/spinlock.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/mutex.h>
24#include <linux/completion.h>
25#include <linux/irq.h>
26#include <linux/jiffies.h>
27#include <linux/bitops.h>
28#include <linux/fs.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/platform_device.h>
33#include <linux/uaccess.h>
34#include <linux/mfd/core.h>
35#include <linux/mfd/dbx500-prcmu.h>
36#include <linux/mfd/abx500/ab8500.h>
37#include <linux/regulator/db8500-prcmu.h>
38#include <linux/regulator/machine.h>
39#include <linux/platform_data/ux500_wdt.h>
40#include "dbx500-prcmu-regs.h"
41
42/* Index of different voltages to be used when accessing AVSData */
43#define PRCM_AVS_BASE 0x2FC
44#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
45#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
46#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
47#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
48#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
49#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
50#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
51#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
52#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
53#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
54#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
55#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
56#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
57
58#define PRCM_AVS_VOLTAGE 0
59#define PRCM_AVS_VOLTAGE_MASK 0x3f
60#define PRCM_AVS_ISSLOWSTARTUP 6
61#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
62#define PRCM_AVS_ISMODEENABLE 7
63#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
64
65#define PRCM_BOOT_STATUS 0xFFF
66#define PRCM_ROMCODE_A2P 0xFFE
67#define PRCM_ROMCODE_P2A 0xFFD
68#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
69
70#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
71
72#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
73#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
74#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
75#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
76#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
77#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
78#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
79#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
80
81/* Req Mailboxes */
82#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
83#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
84#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
85#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
86#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
87#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
88
89/* Ack Mailboxes */
90#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
91#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
92#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
93#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
94#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
95#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
96
97/* Mailbox 0 headers */
98#define MB0H_POWER_STATE_TRANS 0
99#define MB0H_CONFIG_WAKEUPS_EXE 1
100#define MB0H_READ_WAKEUP_ACK 3
101#define MB0H_CONFIG_WAKEUPS_SLEEP 4
102
103#define MB0H_WAKEUP_EXE 2
104#define MB0H_WAKEUP_SLEEP 5
105
106/* Mailbox 0 REQs */
107#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
108#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
109#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
110#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
111#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
112#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
113
114/* Mailbox 0 ACKs */
115#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
116#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
117#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
118#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
119#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
120#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
121#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
122
123/* Mailbox 1 headers */
124#define MB1H_ARM_APE_OPP 0x0
125#define MB1H_RESET_MODEM 0x2
126#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
127#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
128#define MB1H_RELEASE_USB_WAKEUP 0x5
129#define MB1H_PLL_ON_OFF 0x6
130
131/* Mailbox 1 Requests */
132#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
133#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
134#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
135#define PLL_SOC0_OFF 0x1
136#define PLL_SOC0_ON 0x2
137#define PLL_SOC1_OFF 0x4
138#define PLL_SOC1_ON 0x8
139
140/* Mailbox 1 ACKs */
141#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
142#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
143#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
144#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
145
146/* Mailbox 2 headers */
147#define MB2H_DPS 0x0
148#define MB2H_AUTO_PWR 0x1
149
150/* Mailbox 2 REQs */
151#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
152#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
153#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
154#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
155#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
156#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
157#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
158#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
159#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
160#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
161
162/* Mailbox 2 ACKs */
163#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
164#define HWACC_PWR_ST_OK 0xFE
165
166/* Mailbox 3 headers */
167#define MB3H_ANC 0x0
168#define MB3H_SIDETONE 0x1
169#define MB3H_SYSCLK 0xE
170
171/* Mailbox 3 Requests */
172#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
173#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
174#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
175#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
176#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
177#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
178#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
179
180/* Mailbox 4 headers */
181#define MB4H_DDR_INIT 0x0
182#define MB4H_MEM_ST 0x1
183#define MB4H_HOTDOG 0x12
184#define MB4H_HOTMON 0x13
185#define MB4H_HOT_PERIOD 0x14
186#define MB4H_A9WDOG_CONF 0x16
187#define MB4H_A9WDOG_EN 0x17
188#define MB4H_A9WDOG_DIS 0x18
189#define MB4H_A9WDOG_LOAD 0x19
190#define MB4H_A9WDOG_KICK 0x20
191
192/* Mailbox 4 Requests */
193#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
194#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
195#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
196#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
197#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
198#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
199#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
200#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
201#define HOTMON_CONFIG_LOW BIT(0)
202#define HOTMON_CONFIG_HIGH BIT(1)
203#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
204#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
205#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
206#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
207#define A9WDOG_AUTO_OFF_EN BIT(7)
208#define A9WDOG_AUTO_OFF_DIS 0
209#define A9WDOG_ID_MASK 0xf
210
211/* Mailbox 5 Requests */
212#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
213#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
214#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
215#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
216#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
217#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
218#define PRCMU_I2C_STOP_EN BIT(3)
219
220/* Mailbox 5 ACKs */
221#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
222#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
223#define I2C_WR_OK 0x1
224#define I2C_RD_OK 0x2
225
226#define NUM_MB 8
227#define MBOX_BIT BIT
228#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
229
230/*
231 * Wakeups/IRQs
232 */
233
234#define WAKEUP_BIT_RTC BIT(0)
235#define WAKEUP_BIT_RTT0 BIT(1)
236#define WAKEUP_BIT_RTT1 BIT(2)
237#define WAKEUP_BIT_HSI0 BIT(3)
238#define WAKEUP_BIT_HSI1 BIT(4)
239#define WAKEUP_BIT_CA_WAKE BIT(5)
240#define WAKEUP_BIT_USB BIT(6)
241#define WAKEUP_BIT_ABB BIT(7)
242#define WAKEUP_BIT_ABB_FIFO BIT(8)
243#define WAKEUP_BIT_SYSCLK_OK BIT(9)
244#define WAKEUP_BIT_CA_SLEEP BIT(10)
245#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
246#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
247#define WAKEUP_BIT_ANC_OK BIT(13)
248#define WAKEUP_BIT_SW_ERROR BIT(14)
249#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
250#define WAKEUP_BIT_ARM BIT(17)
251#define WAKEUP_BIT_HOTMON_LOW BIT(18)
252#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
253#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
254#define WAKEUP_BIT_GPIO0 BIT(23)
255#define WAKEUP_BIT_GPIO1 BIT(24)
256#define WAKEUP_BIT_GPIO2 BIT(25)
257#define WAKEUP_BIT_GPIO3 BIT(26)
258#define WAKEUP_BIT_GPIO4 BIT(27)
259#define WAKEUP_BIT_GPIO5 BIT(28)
260#define WAKEUP_BIT_GPIO6 BIT(29)
261#define WAKEUP_BIT_GPIO7 BIT(30)
262#define WAKEUP_BIT_GPIO8 BIT(31)
263
264static struct {
265 bool valid;
266 struct prcmu_fw_version version;
267} fw_info;
268
269static struct irq_domain *db8500_irq_domain;
270
271/*
272 * This vector maps irq numbers to the bits in the bit field used in
273 * communication with the PRCMU firmware.
274 *
275 * The reason for having this is to keep the irq numbers contiguous even though
276 * the bits in the bit field are not. (The bits also have a tendency to move
277 * around, to further complicate matters.)
278 */
279#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
280#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
281
282#define IRQ_PRCMU_RTC 0
283#define IRQ_PRCMU_RTT0 1
284#define IRQ_PRCMU_RTT1 2
285#define IRQ_PRCMU_HSI0 3
286#define IRQ_PRCMU_HSI1 4
287#define IRQ_PRCMU_CA_WAKE 5
288#define IRQ_PRCMU_USB 6
289#define IRQ_PRCMU_ABB 7
290#define IRQ_PRCMU_ABB_FIFO 8
291#define IRQ_PRCMU_ARM 9
292#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
293#define IRQ_PRCMU_GPIO0 11
294#define IRQ_PRCMU_GPIO1 12
295#define IRQ_PRCMU_GPIO2 13
296#define IRQ_PRCMU_GPIO3 14
297#define IRQ_PRCMU_GPIO4 15
298#define IRQ_PRCMU_GPIO5 16
299#define IRQ_PRCMU_GPIO6 17
300#define IRQ_PRCMU_GPIO7 18
301#define IRQ_PRCMU_GPIO8 19
302#define IRQ_PRCMU_CA_SLEEP 20
303#define IRQ_PRCMU_HOTMON_LOW 21
304#define IRQ_PRCMU_HOTMON_HIGH 22
305#define NUM_PRCMU_WAKEUPS 23
306
307static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
308 IRQ_ENTRY(RTC),
309 IRQ_ENTRY(RTT0),
310 IRQ_ENTRY(RTT1),
311 IRQ_ENTRY(HSI0),
312 IRQ_ENTRY(HSI1),
313 IRQ_ENTRY(CA_WAKE),
314 IRQ_ENTRY(USB),
315 IRQ_ENTRY(ABB),
316 IRQ_ENTRY(ABB_FIFO),
317 IRQ_ENTRY(CA_SLEEP),
318 IRQ_ENTRY(ARM),
319 IRQ_ENTRY(HOTMON_LOW),
320 IRQ_ENTRY(HOTMON_HIGH),
321 IRQ_ENTRY(MODEM_SW_RESET_REQ),
322 IRQ_ENTRY(GPIO0),
323 IRQ_ENTRY(GPIO1),
324 IRQ_ENTRY(GPIO2),
325 IRQ_ENTRY(GPIO3),
326 IRQ_ENTRY(GPIO4),
327 IRQ_ENTRY(GPIO5),
328 IRQ_ENTRY(GPIO6),
329 IRQ_ENTRY(GPIO7),
330 IRQ_ENTRY(GPIO8)
331};
332
333#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
334#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
335static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
336 WAKEUP_ENTRY(RTC),
337 WAKEUP_ENTRY(RTT0),
338 WAKEUP_ENTRY(RTT1),
339 WAKEUP_ENTRY(HSI0),
340 WAKEUP_ENTRY(HSI1),
341 WAKEUP_ENTRY(USB),
342 WAKEUP_ENTRY(ABB),
343 WAKEUP_ENTRY(ABB_FIFO),
344 WAKEUP_ENTRY(ARM)
345};
346
347/*
348 * mb0_transfer - state needed for mailbox 0 communication.
349 * @lock: The transaction lock.
350 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
351 * the request data.
352 * @mask_work: Work structure used for (un)masking wakeup interrupts.
353 * @req: Request data that need to persist between requests.
354 */
355static struct {
356 spinlock_t lock;
357 spinlock_t dbb_irqs_lock;
358 struct work_struct mask_work;
359 struct mutex ac_wake_lock;
360 struct completion ac_wake_work;
361 struct {
362 u32 dbb_irqs;
363 u32 dbb_wakeups;
364 u32 abb_events;
365 } req;
366} mb0_transfer;
367
368/*
369 * mb1_transfer - state needed for mailbox 1 communication.
370 * @lock: The transaction lock.
371 * @work: The transaction completion structure.
372 * @ape_opp: The current APE OPP.
373 * @ack: Reply ("acknowledge") data.
374 */
375static struct {
376 struct mutex lock;
377 struct completion work;
378 u8 ape_opp;
379 struct {
380 u8 header;
381 u8 arm_opp;
382 u8 ape_opp;
383 u8 ape_voltage_status;
384 } ack;
385} mb1_transfer;
386
387/*
388 * mb2_transfer - state needed for mailbox 2 communication.
389 * @lock: The transaction lock.
390 * @work: The transaction completion structure.
391 * @auto_pm_lock: The autonomous power management configuration lock.
392 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
393 * @req: Request data that need to persist between requests.
394 * @ack: Reply ("acknowledge") data.
395 */
396static struct {
397 struct mutex lock;
398 struct completion work;
399 spinlock_t auto_pm_lock;
400 bool auto_pm_enabled;
401 struct {
402 u8 status;
403 } ack;
404} mb2_transfer;
405
406/*
407 * mb3_transfer - state needed for mailbox 3 communication.
408 * @lock: The request lock.
409 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
410 * @sysclk_work: Work structure used for sysclk requests.
411 */
412static struct {
413 spinlock_t lock;
414 struct mutex sysclk_lock;
415 struct completion sysclk_work;
416} mb3_transfer;
417
418/*
419 * mb4_transfer - state needed for mailbox 4 communication.
420 * @lock: The transaction lock.
421 * @work: The transaction completion structure.
422 */
423static struct {
424 struct mutex lock;
425 struct completion work;
426} mb4_transfer;
427
428/*
429 * mb5_transfer - state needed for mailbox 5 communication.
430 * @lock: The transaction lock.
431 * @work: The transaction completion structure.
432 * @ack: Reply ("acknowledge") data.
433 */
434static struct {
435 struct mutex lock;
436 struct completion work;
437 struct {
438 u8 status;
439 u8 value;
440 } ack;
441} mb5_transfer;
442
443static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
444
445/* Spinlocks */
446static DEFINE_SPINLOCK(prcmu_lock);
447static DEFINE_SPINLOCK(clkout_lock);
448
449/* Global var to runtime determine TCDM base for v2 or v1 */
450static __iomem void *tcdm_base;
451static __iomem void *prcmu_base;
452
453struct clk_mgt {
454 u32 offset;
455 u32 pllsw;
456 int branch;
457 bool clk38div;
458};
459
460enum {
461 PLL_RAW,
462 PLL_FIX,
463 PLL_DIV
464};
465
466static DEFINE_SPINLOCK(clk_mgt_lock);
467
468#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
469 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
470static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
471 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
472 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
476 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
478 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
485 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
488 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
489 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
492 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
493 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
494 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
496 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
499 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
500};
501
502struct dsiclk {
503 u32 divsel_mask;
504 u32 divsel_shift;
505 u32 divsel;
506};
507
508static struct dsiclk dsiclk[2] = {
509 {
510 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
511 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
513 },
514 {
515 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
516 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
518 }
519};
520
521struct dsiescclk {
522 u32 en;
523 u32 div_mask;
524 u32 div_shift;
525};
526
527static struct dsiescclk dsiescclk[3] = {
528 {
529 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
532 },
533 {
534 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
537 },
538 {
539 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
542 }
543};
544
545u32 db8500_prcmu_read(unsigned int reg)
546{
547 return readl(prcmu_base + reg);
548}
549
550void db8500_prcmu_write(unsigned int reg, u32 value)
551{
552 unsigned long flags;
553
554 spin_lock_irqsave(&prcmu_lock, flags);
555 writel(value, (prcmu_base + reg));
556 spin_unlock_irqrestore(&prcmu_lock, flags);
557}
558
559void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
560{
561 u32 val;
562 unsigned long flags;
563
564 spin_lock_irqsave(&prcmu_lock, flags);
565 val = readl(prcmu_base + reg);
566 val = ((val & ~mask) | (value & mask));
567 writel(val, (prcmu_base + reg));
568 spin_unlock_irqrestore(&prcmu_lock, flags);
569}
570
571struct prcmu_fw_version *prcmu_get_fw_version(void)
572{
573 return fw_info.valid ? &fw_info.version : NULL;
574}
575
576static bool prcmu_is_ulppll_disabled(void)
577{
578 struct prcmu_fw_version *ver;
579
580 ver = prcmu_get_fw_version();
581 return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
582}
583
584bool prcmu_has_arm_maxopp(void)
585{
586 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
587 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
588}
589
590/**
591 * prcmu_set_rc_a2p - This function is used to run few power state sequences
592 * @val: Value to be set, i.e. transition requested
593 * Returns: 0 on success, -EINVAL on invalid argument
594 *
595 * This function is used to run the following power state sequences -
596 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
597 */
598int prcmu_set_rc_a2p(enum romcode_write val)
599{
600 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
601 return -EINVAL;
602 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
603 return 0;
604}
605
606/**
607 * prcmu_get_rc_p2a - This function is used to get power state sequences
608 * Returns: the power transition that has last happened
609 *
610 * This function can return the following transitions-
611 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
612 */
613enum romcode_read prcmu_get_rc_p2a(void)
614{
615 return readb(tcdm_base + PRCM_ROMCODE_P2A);
616}
617
618/**
619 * prcmu_get_current_mode - Return the current XP70 power mode
620 * Returns: Returns the current AP(ARM) power mode: init,
621 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
622 */
623enum ap_pwrst prcmu_get_xp70_current_state(void)
624{
625 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
626}
627
628/**
629 * prcmu_config_clkout - Configure one of the programmable clock outputs.
630 * @clkout: The CLKOUT number (0 or 1).
631 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
632 * @div: The divider to be applied.
633 *
634 * Configures one of the programmable clock outputs (CLKOUTs).
635 * @div should be in the range [1,63] to request a configuration, or 0 to
636 * inform that the configuration is no longer requested.
637 */
638int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
639{
640 static int requests[2];
641 int r = 0;
642 unsigned long flags;
643 u32 val;
644 u32 bits;
645 u32 mask;
646 u32 div_mask;
647
648 BUG_ON(clkout > 1);
649 BUG_ON(div > 63);
650 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
651
652 if (!div && !requests[clkout])
653 return -EINVAL;
654
655 if (clkout == 0) {
656 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
657 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
658 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
659 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
660 } else {
661 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
662 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
663 PRCM_CLKOCR_CLK1TYPE);
664 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
665 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
666 }
667 bits &= mask;
668
669 spin_lock_irqsave(&clkout_lock, flags);
670
671 val = readl(PRCM_CLKOCR);
672 if (val & div_mask) {
673 if (div) {
674 if ((val & mask) != bits) {
675 r = -EBUSY;
676 goto unlock_and_return;
677 }
678 } else {
679 if ((val & mask & ~div_mask) != bits) {
680 r = -EINVAL;
681 goto unlock_and_return;
682 }
683 }
684 }
685 writel((bits | (val & ~mask)), PRCM_CLKOCR);
686 requests[clkout] += (div ? 1 : -1);
687
688unlock_and_return:
689 spin_unlock_irqrestore(&clkout_lock, flags);
690
691 return r;
692}
693
694int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
695{
696 unsigned long flags;
697
698 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
699
700 spin_lock_irqsave(&mb0_transfer.lock, flags);
701
702 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
703 cpu_relax();
704
705 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
706 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
707 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
708 writeb((keep_ulp_clk ? 1 : 0),
709 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
710 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
711 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
712
713 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
714
715 return 0;
716}
717
718u8 db8500_prcmu_get_power_state_result(void)
719{
720 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
721}
722
723/* This function should only be called while mb0_transfer.lock is held. */
724static void config_wakeups(void)
725{
726 const u8 header[2] = {
727 MB0H_CONFIG_WAKEUPS_EXE,
728 MB0H_CONFIG_WAKEUPS_SLEEP
729 };
730 static u32 last_dbb_events;
731 static u32 last_abb_events;
732 u32 dbb_events;
733 u32 abb_events;
734 unsigned int i;
735
736 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
737 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
738
739 abb_events = mb0_transfer.req.abb_events;
740
741 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
742 return;
743
744 for (i = 0; i < 2; i++) {
745 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
746 cpu_relax();
747 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
748 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
749 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
750 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
751 }
752 last_dbb_events = dbb_events;
753 last_abb_events = abb_events;
754}
755
756void db8500_prcmu_enable_wakeups(u32 wakeups)
757{
758 unsigned long flags;
759 u32 bits;
760 int i;
761
762 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
763
764 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
765 if (wakeups & BIT(i))
766 bits |= prcmu_wakeup_bit[i];
767 }
768
769 spin_lock_irqsave(&mb0_transfer.lock, flags);
770
771 mb0_transfer.req.dbb_wakeups = bits;
772 config_wakeups();
773
774 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
775}
776
777void db8500_prcmu_config_abb_event_readout(u32 abb_events)
778{
779 unsigned long flags;
780
781 spin_lock_irqsave(&mb0_transfer.lock, flags);
782
783 mb0_transfer.req.abb_events = abb_events;
784 config_wakeups();
785
786 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
787}
788
789void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
790{
791 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
792 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
793 else
794 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
795}
796
797/**
798 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
799 * @opp: The new ARM operating point to which transition is to be made
800 * Returns: 0 on success, non-zero on failure
801 *
802 * This function sets the the operating point of the ARM.
803 */
804int db8500_prcmu_set_arm_opp(u8 opp)
805{
806 int r;
807
808 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
809 return -EINVAL;
810
811 r = 0;
812
813 mutex_lock(&mb1_transfer.lock);
814
815 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
816 cpu_relax();
817
818 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
819 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
820 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
821
822 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
823 wait_for_completion(&mb1_transfer.work);
824
825 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
826 (mb1_transfer.ack.arm_opp != opp))
827 r = -EIO;
828
829 mutex_unlock(&mb1_transfer.lock);
830
831 return r;
832}
833
834/**
835 * db8500_prcmu_get_arm_opp - get the current ARM OPP
836 *
837 * Returns: the current ARM OPP
838 */
839int db8500_prcmu_get_arm_opp(void)
840{
841 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
842}
843
844/**
845 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
846 *
847 * Returns: the current DDR OPP
848 */
849int db8500_prcmu_get_ddr_opp(void)
850{
851 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
852}
853
854/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
855static void request_even_slower_clocks(bool enable)
856{
857 u32 clock_reg[] = {
858 PRCM_ACLK_MGT,
859 PRCM_DMACLK_MGT
860 };
861 unsigned long flags;
862 unsigned int i;
863
864 spin_lock_irqsave(&clk_mgt_lock, flags);
865
866 /* Grab the HW semaphore. */
867 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
868 cpu_relax();
869
870 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
871 u32 val;
872 u32 div;
873
874 val = readl(prcmu_base + clock_reg[i]);
875 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
876 if (enable) {
877 if ((div <= 1) || (div > 15)) {
878 pr_err("prcmu: Bad clock divider %d in %s\n",
879 div, __func__);
880 goto unlock_and_return;
881 }
882 div <<= 1;
883 } else {
884 if (div <= 2)
885 goto unlock_and_return;
886 div >>= 1;
887 }
888 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
889 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
890 writel(val, prcmu_base + clock_reg[i]);
891 }
892
893unlock_and_return:
894 /* Release the HW semaphore. */
895 writel(0, PRCM_SEM);
896
897 spin_unlock_irqrestore(&clk_mgt_lock, flags);
898}
899
900/**
901 * db8500_set_ape_opp - set the appropriate APE OPP
902 * @opp: The new APE operating point to which transition is to be made
903 * Returns: 0 on success, non-zero on failure
904 *
905 * This function sets the operating point of the APE.
906 */
907int db8500_prcmu_set_ape_opp(u8 opp)
908{
909 int r = 0;
910
911 if (opp == mb1_transfer.ape_opp)
912 return 0;
913
914 mutex_lock(&mb1_transfer.lock);
915
916 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
917 request_even_slower_clocks(false);
918
919 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
920 goto skip_message;
921
922 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
923 cpu_relax();
924
925 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
926 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
927 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
928 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
929
930 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
931 wait_for_completion(&mb1_transfer.work);
932
933 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
934 (mb1_transfer.ack.ape_opp != opp))
935 r = -EIO;
936
937skip_message:
938 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
939 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
940 request_even_slower_clocks(true);
941 if (!r)
942 mb1_transfer.ape_opp = opp;
943
944 mutex_unlock(&mb1_transfer.lock);
945
946 return r;
947}
948
949/**
950 * db8500_prcmu_get_ape_opp - get the current APE OPP
951 *
952 * Returns: the current APE OPP
953 */
954int db8500_prcmu_get_ape_opp(void)
955{
956 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
957}
958
959/**
960 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
961 * @enable: true to request the higher voltage, false to drop a request.
962 *
963 * Calls to this function to enable and disable requests must be balanced.
964 */
965int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
966{
967 int r = 0;
968 u8 header;
969 static unsigned int requests;
970
971 mutex_lock(&mb1_transfer.lock);
972
973 if (enable) {
974 if (0 != requests++)
975 goto unlock_and_return;
976 header = MB1H_REQUEST_APE_OPP_100_VOLT;
977 } else {
978 if (requests == 0) {
979 r = -EIO;
980 goto unlock_and_return;
981 } else if (1 != requests--) {
982 goto unlock_and_return;
983 }
984 header = MB1H_RELEASE_APE_OPP_100_VOLT;
985 }
986
987 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
988 cpu_relax();
989
990 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
991
992 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
993 wait_for_completion(&mb1_transfer.work);
994
995 if ((mb1_transfer.ack.header != header) ||
996 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
997 r = -EIO;
998
999unlock_and_return:
1000 mutex_unlock(&mb1_transfer.lock);
1001
1002 return r;
1003}
1004
1005/**
1006 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1007 *
1008 * This function releases the power state requirements of a USB wakeup.
1009 */
1010int prcmu_release_usb_wakeup_state(void)
1011{
1012 int r = 0;
1013
1014 mutex_lock(&mb1_transfer.lock);
1015
1016 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1017 cpu_relax();
1018
1019 writeb(MB1H_RELEASE_USB_WAKEUP,
1020 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1021
1022 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1023 wait_for_completion(&mb1_transfer.work);
1024
1025 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1026 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1027 r = -EIO;
1028
1029 mutex_unlock(&mb1_transfer.lock);
1030
1031 return r;
1032}
1033
1034static int request_pll(u8 clock, bool enable)
1035{
1036 int r = 0;
1037
1038 if (clock == PRCMU_PLLSOC0)
1039 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1040 else if (clock == PRCMU_PLLSOC1)
1041 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1042 else
1043 return -EINVAL;
1044
1045 mutex_lock(&mb1_transfer.lock);
1046
1047 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1048 cpu_relax();
1049
1050 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1051 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1052
1053 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1054 wait_for_completion(&mb1_transfer.work);
1055
1056 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1057 r = -EIO;
1058
1059 mutex_unlock(&mb1_transfer.lock);
1060
1061 return r;
1062}
1063
1064/**
1065 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1066 * @epod_id: The EPOD to set
1067 * @epod_state: The new EPOD state
1068 *
1069 * This function sets the state of a EPOD (power domain). It may not be called
1070 * from interrupt context.
1071 */
1072int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1073{
1074 int r = 0;
1075 bool ram_retention = false;
1076 int i;
1077
1078 /* check argument */
1079 BUG_ON(epod_id >= NUM_EPOD_ID);
1080
1081 /* set flag if retention is possible */
1082 switch (epod_id) {
1083 case EPOD_ID_SVAMMDSP:
1084 case EPOD_ID_SIAMMDSP:
1085 case EPOD_ID_ESRAM12:
1086 case EPOD_ID_ESRAM34:
1087 ram_retention = true;
1088 break;
1089 }
1090
1091 /* check argument */
1092 BUG_ON(epod_state > EPOD_STATE_ON);
1093 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1094
1095 /* get lock */
1096 mutex_lock(&mb2_transfer.lock);
1097
1098 /* wait for mailbox */
1099 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1100 cpu_relax();
1101
1102 /* fill in mailbox */
1103 for (i = 0; i < NUM_EPOD_ID; i++)
1104 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1105 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1106
1107 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1108
1109 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1110
1111 /*
1112 * The current firmware version does not handle errors correctly,
1113 * and we cannot recover if there is an error.
1114 * This is expected to change when the firmware is updated.
1115 */
1116 if (!wait_for_completion_timeout(&mb2_transfer.work,
1117 msecs_to_jiffies(20000))) {
1118 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1119 __func__);
1120 r = -EIO;
1121 goto unlock_and_return;
1122 }
1123
1124 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1125 r = -EIO;
1126
1127unlock_and_return:
1128 mutex_unlock(&mb2_transfer.lock);
1129 return r;
1130}
1131
1132/**
1133 * prcmu_configure_auto_pm - Configure autonomous power management.
1134 * @sleep: Configuration for ApSleep.
1135 * @idle: Configuration for ApIdle.
1136 */
1137void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1138 struct prcmu_auto_pm_config *idle)
1139{
1140 u32 sleep_cfg;
1141 u32 idle_cfg;
1142 unsigned long flags;
1143
1144 BUG_ON((sleep == NULL) || (idle == NULL));
1145
1146 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1147 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1148 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1149 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1150 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1151 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1152
1153 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1154 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1155 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1156 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1157 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1158 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1159
1160 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1161
1162 /*
1163 * The autonomous power management configuration is done through
1164 * fields in mailbox 2, but these fields are only used as shared
1165 * variables - i.e. there is no need to send a message.
1166 */
1167 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1168 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1169
1170 mb2_transfer.auto_pm_enabled =
1171 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1172 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1173 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1174 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1175
1176 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1177}
1178EXPORT_SYMBOL(prcmu_configure_auto_pm);
1179
1180bool prcmu_is_auto_pm_enabled(void)
1181{
1182 return mb2_transfer.auto_pm_enabled;
1183}
1184
1185static int request_sysclk(bool enable)
1186{
1187 int r;
1188 unsigned long flags;
1189
1190 r = 0;
1191
1192 mutex_lock(&mb3_transfer.sysclk_lock);
1193
1194 spin_lock_irqsave(&mb3_transfer.lock, flags);
1195
1196 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1197 cpu_relax();
1198
1199 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1200
1201 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1202 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1203
1204 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1205
1206 /*
1207 * The firmware only sends an ACK if we want to enable the
1208 * SysClk, and it succeeds.
1209 */
1210 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1211 msecs_to_jiffies(20000))) {
1212 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1213 __func__);
1214 r = -EIO;
1215 }
1216
1217 mutex_unlock(&mb3_transfer.sysclk_lock);
1218
1219 return r;
1220}
1221
1222static int request_timclk(bool enable)
1223{
1224 u32 val;
1225
1226 /*
1227 * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power)
1228 * PLL is disabled so we cannot use doze mode, this will
1229 * stop the clock on this firmware.
1230 */
1231 if (prcmu_is_ulppll_disabled())
1232 val = 0;
1233 else
1234 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1235
1236 if (!enable)
1237 val |= PRCM_TCR_STOP_TIMERS |
1238 PRCM_TCR_DOZE_MODE |
1239 PRCM_TCR_TENSEL_MASK;
1240
1241 writel(val, PRCM_TCR);
1242
1243 return 0;
1244}
1245
1246static int request_clock(u8 clock, bool enable)
1247{
1248 u32 val;
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&clk_mgt_lock, flags);
1252
1253 /* Grab the HW semaphore. */
1254 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1255 cpu_relax();
1256
1257 val = readl(prcmu_base + clk_mgt[clock].offset);
1258 if (enable) {
1259 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1260 } else {
1261 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1262 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1263 }
1264 writel(val, prcmu_base + clk_mgt[clock].offset);
1265
1266 /* Release the HW semaphore. */
1267 writel(0, PRCM_SEM);
1268
1269 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1270
1271 return 0;
1272}
1273
1274static int request_sga_clock(u8 clock, bool enable)
1275{
1276 u32 val;
1277 int ret;
1278
1279 if (enable) {
1280 val = readl(PRCM_CGATING_BYPASS);
1281 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1282 }
1283
1284 ret = request_clock(clock, enable);
1285
1286 if (!ret && !enable) {
1287 val = readl(PRCM_CGATING_BYPASS);
1288 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1289 }
1290
1291 return ret;
1292}
1293
1294static inline bool plldsi_locked(void)
1295{
1296 return (readl(PRCM_PLLDSI_LOCKP) &
1297 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1298 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1299 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1300 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1301}
1302
1303static int request_plldsi(bool enable)
1304{
1305 int r = 0;
1306 u32 val;
1307
1308 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1309 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1310 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1311
1312 val = readl(PRCM_PLLDSI_ENABLE);
1313 if (enable)
1314 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1315 else
1316 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1317 writel(val, PRCM_PLLDSI_ENABLE);
1318
1319 if (enable) {
1320 unsigned int i;
1321 bool locked = plldsi_locked();
1322
1323 for (i = 10; !locked && (i > 0); --i) {
1324 udelay(100);
1325 locked = plldsi_locked();
1326 }
1327 if (locked) {
1328 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1329 PRCM_APE_RESETN_SET);
1330 } else {
1331 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1332 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1333 PRCM_MMIP_LS_CLAMP_SET);
1334 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1335 writel(val, PRCM_PLLDSI_ENABLE);
1336 r = -EAGAIN;
1337 }
1338 } else {
1339 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1340 }
1341 return r;
1342}
1343
1344static int request_dsiclk(u8 n, bool enable)
1345{
1346 u32 val;
1347
1348 val = readl(PRCM_DSI_PLLOUT_SEL);
1349 val &= ~dsiclk[n].divsel_mask;
1350 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1351 dsiclk[n].divsel_shift);
1352 writel(val, PRCM_DSI_PLLOUT_SEL);
1353 return 0;
1354}
1355
1356static int request_dsiescclk(u8 n, bool enable)
1357{
1358 u32 val;
1359
1360 val = readl(PRCM_DSITVCLK_DIV);
1361 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1362 writel(val, PRCM_DSITVCLK_DIV);
1363 return 0;
1364}
1365
1366/**
1367 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1368 * @clock: The clock for which the request is made.
1369 * @enable: Whether the clock should be enabled (true) or disabled (false).
1370 *
1371 * This function should only be used by the clock implementation.
1372 * Do not use it from any other place!
1373 */
1374int db8500_prcmu_request_clock(u8 clock, bool enable)
1375{
1376 if (clock == PRCMU_SGACLK)
1377 return request_sga_clock(clock, enable);
1378 else if (clock < PRCMU_NUM_REG_CLOCKS)
1379 return request_clock(clock, enable);
1380 else if (clock == PRCMU_TIMCLK)
1381 return request_timclk(enable);
1382 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1383 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1384 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1385 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1386 else if (clock == PRCMU_PLLDSI)
1387 return request_plldsi(enable);
1388 else if (clock == PRCMU_SYSCLK)
1389 return request_sysclk(enable);
1390 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1391 return request_pll(clock, enable);
1392 else
1393 return -EINVAL;
1394}
1395
1396static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1397 int branch)
1398{
1399 u64 rate;
1400 u32 val;
1401 u32 d;
1402 u32 div = 1;
1403
1404 val = readl(reg);
1405
1406 rate = src_rate;
1407 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1408
1409 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1410 if (d > 1)
1411 div *= d;
1412
1413 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1414 if (d > 1)
1415 div *= d;
1416
1417 if (val & PRCM_PLL_FREQ_SELDIV2)
1418 div *= 2;
1419
1420 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1421 (val & PRCM_PLL_FREQ_DIV2EN) &&
1422 ((reg == PRCM_PLLSOC0_FREQ) ||
1423 (reg == PRCM_PLLARM_FREQ) ||
1424 (reg == PRCM_PLLDDR_FREQ))))
1425 div *= 2;
1426
1427 (void)do_div(rate, div);
1428
1429 return (unsigned long)rate;
1430}
1431
1432#define ROOT_CLOCK_RATE 38400000
1433
1434static unsigned long clock_rate(u8 clock)
1435{
1436 u32 val;
1437 u32 pllsw;
1438 unsigned long rate = ROOT_CLOCK_RATE;
1439
1440 val = readl(prcmu_base + clk_mgt[clock].offset);
1441
1442 if (val & PRCM_CLK_MGT_CLK38) {
1443 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1444 rate /= 2;
1445 return rate;
1446 }
1447
1448 val |= clk_mgt[clock].pllsw;
1449 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1450
1451 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1453 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1455 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1457 else
1458 return 0;
1459
1460 if ((clock == PRCMU_SGACLK) &&
1461 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1462 u64 r = (rate * 10);
1463
1464 (void)do_div(r, 25);
1465 return (unsigned long)r;
1466 }
1467 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1468 if (val)
1469 return rate / val;
1470 else
1471 return 0;
1472}
1473
1474static unsigned long armss_rate(void)
1475{
1476 u32 r;
1477 unsigned long rate;
1478
1479 r = readl(PRCM_ARM_CHGCLKREQ);
1480
1481 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1482 /* External ARMCLKFIX clock */
1483
1484 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1485
1486 /* Check PRCM_ARM_CHGCLKREQ divider */
1487 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1488 rate /= 2;
1489
1490 /* Check PRCM_ARMCLKFIX_MGT divider */
1491 r = readl(PRCM_ARMCLKFIX_MGT);
1492 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1493 rate /= r;
1494
1495 } else {/* ARM PLL */
1496 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1497 }
1498
1499 return rate;
1500}
1501
1502static unsigned long dsiclk_rate(u8 n)
1503{
1504 u32 divsel;
1505 u32 div = 1;
1506
1507 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1508 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1509
1510 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1511 divsel = dsiclk[n].divsel;
1512 else
1513 dsiclk[n].divsel = divsel;
1514
1515 switch (divsel) {
1516 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1517 div *= 2;
1518 fallthrough;
1519 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1520 div *= 2;
1521 fallthrough;
1522 case PRCM_DSI_PLLOUT_SEL_PHI:
1523 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1524 PLL_RAW) / div;
1525 default:
1526 return 0;
1527 }
1528}
1529
1530static unsigned long dsiescclk_rate(u8 n)
1531{
1532 u32 div;
1533
1534 div = readl(PRCM_DSITVCLK_DIV);
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1536 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1537}
1538
1539unsigned long prcmu_clock_rate(u8 clock)
1540{
1541 if (clock < PRCMU_NUM_REG_CLOCKS)
1542 return clock_rate(clock);
1543 else if (clock == PRCMU_TIMCLK)
1544 return prcmu_is_ulppll_disabled() ?
1545 32768 : ROOT_CLOCK_RATE / 16;
1546 else if (clock == PRCMU_SYSCLK)
1547 return ROOT_CLOCK_RATE;
1548 else if (clock == PRCMU_PLLSOC0)
1549 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1550 else if (clock == PRCMU_PLLSOC1)
1551 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1552 else if (clock == PRCMU_ARMSS)
1553 return armss_rate();
1554 else if (clock == PRCMU_PLLDDR)
1555 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1556 else if (clock == PRCMU_PLLDSI)
1557 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1558 PLL_RAW);
1559 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1560 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1561 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1562 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1563 else
1564 return 0;
1565}
1566
1567static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1568{
1569 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1570 return ROOT_CLOCK_RATE;
1571 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1572 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1573 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1574 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1575 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1576 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1577 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1578 else
1579 return 0;
1580}
1581
1582static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1583{
1584 u32 div;
1585
1586 div = (src_rate / rate);
1587 if (div == 0)
1588 return 1;
1589 if (rate < (src_rate / div))
1590 div++;
1591 return div;
1592}
1593
1594static long round_clock_rate(u8 clock, unsigned long rate)
1595{
1596 u32 val;
1597 u32 div;
1598 unsigned long src_rate;
1599 long rounded_rate;
1600
1601 val = readl(prcmu_base + clk_mgt[clock].offset);
1602 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1603 clk_mgt[clock].branch);
1604 div = clock_divider(src_rate, rate);
1605 if (val & PRCM_CLK_MGT_CLK38) {
1606 if (clk_mgt[clock].clk38div) {
1607 if (div > 2)
1608 div = 2;
1609 } else {
1610 div = 1;
1611 }
1612 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1613 u64 r = (src_rate * 10);
1614
1615 (void)do_div(r, 25);
1616 if (r <= rate)
1617 return (unsigned long)r;
1618 }
1619 rounded_rate = (src_rate / min(div, (u32)31));
1620
1621 return rounded_rate;
1622}
1623
1624static const unsigned long db8500_armss_freqs[] = {
1625 200000000,
1626 400000000,
1627 800000000,
1628 998400000
1629};
1630
1631/* The DB8520 has slightly higher ARMSS max frequency */
1632static const unsigned long db8520_armss_freqs[] = {
1633 200000000,
1634 400000000,
1635 800000000,
1636 1152000000
1637};
1638
1639
1640
1641static long round_armss_rate(unsigned long rate)
1642{
1643 unsigned long freq = 0;
1644 const unsigned long *freqs;
1645 int nfreqs;
1646 int i;
1647
1648 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1649 freqs = db8520_armss_freqs;
1650 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1651 } else {
1652 freqs = db8500_armss_freqs;
1653 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1654 }
1655
1656 /* Find the corresponding arm opp from the cpufreq table. */
1657 for (i = 0; i < nfreqs; i++) {
1658 freq = freqs[i];
1659 if (rate <= freq)
1660 break;
1661 }
1662
1663 /* Return the last valid value, even if a match was not found. */
1664 return freq;
1665}
1666
1667#define MIN_PLL_VCO_RATE 600000000ULL
1668#define MAX_PLL_VCO_RATE 1680640000ULL
1669
1670static long round_plldsi_rate(unsigned long rate)
1671{
1672 long rounded_rate = 0;
1673 unsigned long src_rate;
1674 unsigned long rem;
1675 u32 r;
1676
1677 src_rate = clock_rate(PRCMU_HDMICLK);
1678 rem = rate;
1679
1680 for (r = 7; (rem > 0) && (r > 0); r--) {
1681 u64 d;
1682
1683 d = (r * rate);
1684 (void)do_div(d, src_rate);
1685 if (d < 6)
1686 d = 6;
1687 else if (d > 255)
1688 d = 255;
1689 d *= src_rate;
1690 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1691 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1692 continue;
1693 (void)do_div(d, r);
1694 if (rate < d) {
1695 if (rounded_rate == 0)
1696 rounded_rate = (long)d;
1697 break;
1698 }
1699 if ((rate - d) < rem) {
1700 rem = (rate - d);
1701 rounded_rate = (long)d;
1702 }
1703 }
1704 return rounded_rate;
1705}
1706
1707static long round_dsiclk_rate(unsigned long rate)
1708{
1709 u32 div;
1710 unsigned long src_rate;
1711 long rounded_rate;
1712
1713 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1714 PLL_RAW);
1715 div = clock_divider(src_rate, rate);
1716 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1717
1718 return rounded_rate;
1719}
1720
1721static long round_dsiescclk_rate(unsigned long rate)
1722{
1723 u32 div;
1724 unsigned long src_rate;
1725 long rounded_rate;
1726
1727 src_rate = clock_rate(PRCMU_TVCLK);
1728 div = clock_divider(src_rate, rate);
1729 rounded_rate = (src_rate / min(div, (u32)255));
1730
1731 return rounded_rate;
1732}
1733
1734long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1735{
1736 if (clock < PRCMU_NUM_REG_CLOCKS)
1737 return round_clock_rate(clock, rate);
1738 else if (clock == PRCMU_ARMSS)
1739 return round_armss_rate(rate);
1740 else if (clock == PRCMU_PLLDSI)
1741 return round_plldsi_rate(rate);
1742 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1743 return round_dsiclk_rate(rate);
1744 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1745 return round_dsiescclk_rate(rate);
1746 else
1747 return (long)prcmu_clock_rate(clock);
1748}
1749
1750static void set_clock_rate(u8 clock, unsigned long rate)
1751{
1752 u32 val;
1753 u32 div;
1754 unsigned long src_rate;
1755 unsigned long flags;
1756
1757 spin_lock_irqsave(&clk_mgt_lock, flags);
1758
1759 /* Grab the HW semaphore. */
1760 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1761 cpu_relax();
1762
1763 val = readl(prcmu_base + clk_mgt[clock].offset);
1764 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1765 clk_mgt[clock].branch);
1766 div = clock_divider(src_rate, rate);
1767 if (val & PRCM_CLK_MGT_CLK38) {
1768 if (clk_mgt[clock].clk38div) {
1769 if (div > 1)
1770 val |= PRCM_CLK_MGT_CLK38DIV;
1771 else
1772 val &= ~PRCM_CLK_MGT_CLK38DIV;
1773 }
1774 } else if (clock == PRCMU_SGACLK) {
1775 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1776 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1777 if (div == 3) {
1778 u64 r = (src_rate * 10);
1779
1780 (void)do_div(r, 25);
1781 if (r <= rate) {
1782 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1783 div = 0;
1784 }
1785 }
1786 val |= min(div, (u32)31);
1787 } else {
1788 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1789 val |= min(div, (u32)31);
1790 }
1791 writel(val, prcmu_base + clk_mgt[clock].offset);
1792
1793 /* Release the HW semaphore. */
1794 writel(0, PRCM_SEM);
1795
1796 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1797}
1798
1799static int set_armss_rate(unsigned long rate)
1800{
1801 unsigned long freq;
1802 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1803 const unsigned long *freqs;
1804 int nfreqs;
1805 int i;
1806
1807 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1808 freqs = db8520_armss_freqs;
1809 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1810 } else {
1811 freqs = db8500_armss_freqs;
1812 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1813 }
1814
1815 /* Find the corresponding arm opp from the cpufreq table. */
1816 for (i = 0; i < nfreqs; i++) {
1817 freq = freqs[i];
1818 if (rate == freq)
1819 break;
1820 }
1821
1822 if (rate != freq)
1823 return -EINVAL;
1824
1825 /* Set the new arm opp. */
1826 pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1827 return db8500_prcmu_set_arm_opp(opps[i]);
1828}
1829
1830static int set_plldsi_rate(unsigned long rate)
1831{
1832 unsigned long src_rate;
1833 unsigned long rem;
1834 u32 pll_freq = 0;
1835 u32 r;
1836
1837 src_rate = clock_rate(PRCMU_HDMICLK);
1838 rem = rate;
1839
1840 for (r = 7; (rem > 0) && (r > 0); r--) {
1841 u64 d;
1842 u64 hwrate;
1843
1844 d = (r * rate);
1845 (void)do_div(d, src_rate);
1846 if (d < 6)
1847 d = 6;
1848 else if (d > 255)
1849 d = 255;
1850 hwrate = (d * src_rate);
1851 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1852 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1853 continue;
1854 (void)do_div(hwrate, r);
1855 if (rate < hwrate) {
1856 if (pll_freq == 0)
1857 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1858 (r << PRCM_PLL_FREQ_R_SHIFT));
1859 break;
1860 }
1861 if ((rate - hwrate) < rem) {
1862 rem = (rate - hwrate);
1863 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1864 (r << PRCM_PLL_FREQ_R_SHIFT));
1865 }
1866 }
1867 if (pll_freq == 0)
1868 return -EINVAL;
1869
1870 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1871 writel(pll_freq, PRCM_PLLDSI_FREQ);
1872
1873 return 0;
1874}
1875
1876static void set_dsiclk_rate(u8 n, unsigned long rate)
1877{
1878 u32 val;
1879 u32 div;
1880
1881 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1882 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1883
1884 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1885 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1886 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1887
1888 val = readl(PRCM_DSI_PLLOUT_SEL);
1889 val &= ~dsiclk[n].divsel_mask;
1890 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1891 writel(val, PRCM_DSI_PLLOUT_SEL);
1892}
1893
1894static void set_dsiescclk_rate(u8 n, unsigned long rate)
1895{
1896 u32 val;
1897 u32 div;
1898
1899 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1900 val = readl(PRCM_DSITVCLK_DIV);
1901 val &= ~dsiescclk[n].div_mask;
1902 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1903 writel(val, PRCM_DSITVCLK_DIV);
1904}
1905
1906int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1907{
1908 if (clock < PRCMU_NUM_REG_CLOCKS)
1909 set_clock_rate(clock, rate);
1910 else if (clock == PRCMU_ARMSS)
1911 return set_armss_rate(rate);
1912 else if (clock == PRCMU_PLLDSI)
1913 return set_plldsi_rate(rate);
1914 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1915 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1916 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1917 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1918 return 0;
1919}
1920
1921int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1922{
1923 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1924 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1925 return -EINVAL;
1926
1927 mutex_lock(&mb4_transfer.lock);
1928
1929 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1930 cpu_relax();
1931
1932 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1933 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
1934 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1935 writeb(DDR_PWR_STATE_ON,
1936 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1937 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1938
1939 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1940 wait_for_completion(&mb4_transfer.work);
1941
1942 mutex_unlock(&mb4_transfer.lock);
1943
1944 return 0;
1945}
1946
1947int db8500_prcmu_config_hotdog(u8 threshold)
1948{
1949 mutex_lock(&mb4_transfer.lock);
1950
1951 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1952 cpu_relax();
1953
1954 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1955 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1956
1957 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1958 wait_for_completion(&mb4_transfer.work);
1959
1960 mutex_unlock(&mb4_transfer.lock);
1961
1962 return 0;
1963}
1964
1965int db8500_prcmu_config_hotmon(u8 low, u8 high)
1966{
1967 mutex_lock(&mb4_transfer.lock);
1968
1969 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1970 cpu_relax();
1971
1972 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
1973 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
1974 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
1975 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
1976 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1977
1978 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1979 wait_for_completion(&mb4_transfer.work);
1980
1981 mutex_unlock(&mb4_transfer.lock);
1982
1983 return 0;
1984}
1985EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
1986
1987static int config_hot_period(u16 val)
1988{
1989 mutex_lock(&mb4_transfer.lock);
1990
1991 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1992 cpu_relax();
1993
1994 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
1995 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1996
1997 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1998 wait_for_completion(&mb4_transfer.work);
1999
2000 mutex_unlock(&mb4_transfer.lock);
2001
2002 return 0;
2003}
2004
2005int db8500_prcmu_start_temp_sense(u16 cycles32k)
2006{
2007 if (cycles32k == 0xFFFF)
2008 return -EINVAL;
2009
2010 return config_hot_period(cycles32k);
2011}
2012EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2013
2014int db8500_prcmu_stop_temp_sense(void)
2015{
2016 return config_hot_period(0xFFFF);
2017}
2018EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2019
2020static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2021{
2022
2023 mutex_lock(&mb4_transfer.lock);
2024
2025 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2026 cpu_relax();
2027
2028 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2029 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2030 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2031 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2032
2033 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2034
2035 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2036 wait_for_completion(&mb4_transfer.work);
2037
2038 mutex_unlock(&mb4_transfer.lock);
2039
2040 return 0;
2041
2042}
2043
2044int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2045{
2046 BUG_ON(num == 0 || num > 0xf);
2047 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2048 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2049 A9WDOG_AUTO_OFF_DIS);
2050}
2051EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2052
2053int db8500_prcmu_enable_a9wdog(u8 id)
2054{
2055 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2056}
2057EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2058
2059int db8500_prcmu_disable_a9wdog(u8 id)
2060{
2061 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2062}
2063EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2064
2065int db8500_prcmu_kick_a9wdog(u8 id)
2066{
2067 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2068}
2069EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2070
2071/*
2072 * timeout is 28 bit, in ms.
2073 */
2074int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2075{
2076 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2077 (id & A9WDOG_ID_MASK) |
2078 /*
2079 * Put the lowest 28 bits of timeout at
2080 * offset 4. Four first bits are used for id.
2081 */
2082 (u8)((timeout << 4) & 0xf0),
2083 (u8)((timeout >> 4) & 0xff),
2084 (u8)((timeout >> 12) & 0xff),
2085 (u8)((timeout >> 20) & 0xff));
2086}
2087EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2088
2089/**
2090 * prcmu_abb_read() - Read register value(s) from the ABB.
2091 * @slave: The I2C slave address.
2092 * @reg: The (start) register address.
2093 * @value: The read out value(s).
2094 * @size: The number of registers to read.
2095 *
2096 * Reads register value(s) from the ABB.
2097 * @size has to be 1 for the current firmware version.
2098 */
2099int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2100{
2101 int r;
2102
2103 if (size != 1)
2104 return -EINVAL;
2105
2106 mutex_lock(&mb5_transfer.lock);
2107
2108 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2109 cpu_relax();
2110
2111 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2112 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2113 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2114 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2115 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2116
2117 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2118
2119 if (!wait_for_completion_timeout(&mb5_transfer.work,
2120 msecs_to_jiffies(20000))) {
2121 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2122 __func__);
2123 r = -EIO;
2124 } else {
2125 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2126 }
2127
2128 if (!r)
2129 *value = mb5_transfer.ack.value;
2130
2131 mutex_unlock(&mb5_transfer.lock);
2132
2133 return r;
2134}
2135
2136/**
2137 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2138 * @slave: The I2C slave address.
2139 * @reg: The (start) register address.
2140 * @value: The value(s) to write.
2141 * @mask: The mask(s) to use.
2142 * @size: The number of registers to write.
2143 *
2144 * Writes masked register value(s) to the ABB.
2145 * For each @value, only the bits set to 1 in the corresponding @mask
2146 * will be written. The other bits are not changed.
2147 * @size has to be 1 for the current firmware version.
2148 */
2149int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2150{
2151 int r;
2152
2153 if (size != 1)
2154 return -EINVAL;
2155
2156 mutex_lock(&mb5_transfer.lock);
2157
2158 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2159 cpu_relax();
2160
2161 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2162 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2163 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2164 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2165 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2166
2167 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2168
2169 if (!wait_for_completion_timeout(&mb5_transfer.work,
2170 msecs_to_jiffies(20000))) {
2171 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2172 __func__);
2173 r = -EIO;
2174 } else {
2175 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2176 }
2177
2178 mutex_unlock(&mb5_transfer.lock);
2179
2180 return r;
2181}
2182
2183/**
2184 * prcmu_abb_write() - Write register value(s) to the ABB.
2185 * @slave: The I2C slave address.
2186 * @reg: The (start) register address.
2187 * @value: The value(s) to write.
2188 * @size: The number of registers to write.
2189 *
2190 * Writes register value(s) to the ABB.
2191 * @size has to be 1 for the current firmware version.
2192 */
2193int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2194{
2195 u8 mask = ~0;
2196
2197 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2198}
2199
2200/**
2201 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2202 */
2203int prcmu_ac_wake_req(void)
2204{
2205 u32 val;
2206 int ret = 0;
2207
2208 mutex_lock(&mb0_transfer.ac_wake_lock);
2209
2210 val = readl(PRCM_HOSTACCESS_REQ);
2211 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2212 goto unlock_and_return;
2213
2214 atomic_set(&ac_wake_req_state, 1);
2215
2216 /*
2217 * Force Modem Wake-up before hostaccess_req ping-pong.
2218 * It prevents Modem to enter in Sleep while acking the hostaccess
2219 * request. The 31us delay has been calculated by HWI.
2220 */
2221 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2222 writel(val, PRCM_HOSTACCESS_REQ);
2223
2224 udelay(31);
2225
2226 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2227 writel(val, PRCM_HOSTACCESS_REQ);
2228
2229 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2230 msecs_to_jiffies(5000))) {
2231 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2232 __func__);
2233 ret = -EFAULT;
2234 }
2235
2236unlock_and_return:
2237 mutex_unlock(&mb0_transfer.ac_wake_lock);
2238 return ret;
2239}
2240
2241/**
2242 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2243 */
2244void prcmu_ac_sleep_req(void)
2245{
2246 u32 val;
2247
2248 mutex_lock(&mb0_transfer.ac_wake_lock);
2249
2250 val = readl(PRCM_HOSTACCESS_REQ);
2251 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2252 goto unlock_and_return;
2253
2254 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2255 PRCM_HOSTACCESS_REQ);
2256
2257 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2258 msecs_to_jiffies(5000))) {
2259 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2260 __func__);
2261 }
2262
2263 atomic_set(&ac_wake_req_state, 0);
2264
2265unlock_and_return:
2266 mutex_unlock(&mb0_transfer.ac_wake_lock);
2267}
2268
2269bool db8500_prcmu_is_ac_wake_requested(void)
2270{
2271 return (atomic_read(&ac_wake_req_state) != 0);
2272}
2273
2274/**
2275 * db8500_prcmu_system_reset - System reset
2276 *
2277 * Saves the reset reason code and then sets the APE_SOFTRST register which
2278 * fires interrupt to fw
2279 *
2280 * @reset_code: The reason for system reset
2281 */
2282void db8500_prcmu_system_reset(u16 reset_code)
2283{
2284 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2285 writel(1, PRCM_APE_SOFTRST);
2286}
2287
2288/**
2289 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2290 *
2291 * Retrieves the reset reason code stored by prcmu_system_reset() before
2292 * last restart.
2293 */
2294u16 db8500_prcmu_get_reset_code(void)
2295{
2296 return readw(tcdm_base + PRCM_SW_RST_REASON);
2297}
2298
2299/**
2300 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2301 */
2302void db8500_prcmu_modem_reset(void)
2303{
2304 mutex_lock(&mb1_transfer.lock);
2305
2306 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2307 cpu_relax();
2308
2309 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2310 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2311 wait_for_completion(&mb1_transfer.work);
2312
2313 /*
2314 * No need to check return from PRCMU as modem should go in reset state
2315 * This state is already managed by upper layer
2316 */
2317
2318 mutex_unlock(&mb1_transfer.lock);
2319}
2320
2321static void ack_dbb_wakeup(void)
2322{
2323 unsigned long flags;
2324
2325 spin_lock_irqsave(&mb0_transfer.lock, flags);
2326
2327 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2328 cpu_relax();
2329
2330 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2331 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2332
2333 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2334}
2335
2336static inline void print_unknown_header_warning(u8 n, u8 header)
2337{
2338 pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2339 header, n);
2340}
2341
2342static bool read_mailbox_0(void)
2343{
2344 bool r;
2345 u32 ev;
2346 unsigned int n;
2347 u8 header;
2348
2349 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2350 switch (header) {
2351 case MB0H_WAKEUP_EXE:
2352 case MB0H_WAKEUP_SLEEP:
2353 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2354 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2355 else
2356 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2357
2358 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2359 complete(&mb0_transfer.ac_wake_work);
2360 if (ev & WAKEUP_BIT_SYSCLK_OK)
2361 complete(&mb3_transfer.sysclk_work);
2362
2363 ev &= mb0_transfer.req.dbb_irqs;
2364
2365 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2366 if (ev & prcmu_irq_bit[n])
2367 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2368 }
2369 r = true;
2370 break;
2371 default:
2372 print_unknown_header_warning(0, header);
2373 r = false;
2374 break;
2375 }
2376 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2377 return r;
2378}
2379
2380static bool read_mailbox_1(void)
2381{
2382 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2383 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2384 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2385 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2386 PRCM_ACK_MB1_CURRENT_APE_OPP);
2387 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2388 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2389 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2390 complete(&mb1_transfer.work);
2391 return false;
2392}
2393
2394static bool read_mailbox_2(void)
2395{
2396 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2397 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2398 complete(&mb2_transfer.work);
2399 return false;
2400}
2401
2402static bool read_mailbox_3(void)
2403{
2404 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2405 return false;
2406}
2407
2408static bool read_mailbox_4(void)
2409{
2410 u8 header;
2411 bool do_complete = true;
2412
2413 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2414 switch (header) {
2415 case MB4H_MEM_ST:
2416 case MB4H_HOTDOG:
2417 case MB4H_HOTMON:
2418 case MB4H_HOT_PERIOD:
2419 case MB4H_A9WDOG_CONF:
2420 case MB4H_A9WDOG_EN:
2421 case MB4H_A9WDOG_DIS:
2422 case MB4H_A9WDOG_LOAD:
2423 case MB4H_A9WDOG_KICK:
2424 break;
2425 default:
2426 print_unknown_header_warning(4, header);
2427 do_complete = false;
2428 break;
2429 }
2430
2431 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2432
2433 if (do_complete)
2434 complete(&mb4_transfer.work);
2435
2436 return false;
2437}
2438
2439static bool read_mailbox_5(void)
2440{
2441 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2442 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2443 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2444 complete(&mb5_transfer.work);
2445 return false;
2446}
2447
2448static bool read_mailbox_6(void)
2449{
2450 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2451 return false;
2452}
2453
2454static bool read_mailbox_7(void)
2455{
2456 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2457 return false;
2458}
2459
2460static bool (* const read_mailbox[NUM_MB])(void) = {
2461 read_mailbox_0,
2462 read_mailbox_1,
2463 read_mailbox_2,
2464 read_mailbox_3,
2465 read_mailbox_4,
2466 read_mailbox_5,
2467 read_mailbox_6,
2468 read_mailbox_7
2469};
2470
2471static irqreturn_t prcmu_irq_handler(int irq, void *data)
2472{
2473 u32 bits;
2474 u8 n;
2475 irqreturn_t r;
2476
2477 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2478 if (unlikely(!bits))
2479 return IRQ_NONE;
2480
2481 r = IRQ_HANDLED;
2482 for (n = 0; bits; n++) {
2483 if (bits & MBOX_BIT(n)) {
2484 bits -= MBOX_BIT(n);
2485 if (read_mailbox[n]())
2486 r = IRQ_WAKE_THREAD;
2487 }
2488 }
2489 return r;
2490}
2491
2492static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2493{
2494 ack_dbb_wakeup();
2495 return IRQ_HANDLED;
2496}
2497
2498static void prcmu_mask_work(struct work_struct *work)
2499{
2500 unsigned long flags;
2501
2502 spin_lock_irqsave(&mb0_transfer.lock, flags);
2503
2504 config_wakeups();
2505
2506 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2507}
2508
2509static void prcmu_irq_mask(struct irq_data *d)
2510{
2511 unsigned long flags;
2512
2513 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2514
2515 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2516
2517 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2518
2519 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2520 schedule_work(&mb0_transfer.mask_work);
2521}
2522
2523static void prcmu_irq_unmask(struct irq_data *d)
2524{
2525 unsigned long flags;
2526
2527 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2528
2529 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2530
2531 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2532
2533 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2534 schedule_work(&mb0_transfer.mask_work);
2535}
2536
2537static void noop(struct irq_data *d)
2538{
2539}
2540
2541static struct irq_chip prcmu_irq_chip = {
2542 .name = "prcmu",
2543 .irq_disable = prcmu_irq_mask,
2544 .irq_ack = noop,
2545 .irq_mask = prcmu_irq_mask,
2546 .irq_unmask = prcmu_irq_unmask,
2547};
2548
2549static char *fw_project_name(u32 project)
2550{
2551 switch (project) {
2552 case PRCMU_FW_PROJECT_U8500:
2553 return "U8500";
2554 case PRCMU_FW_PROJECT_U8400:
2555 return "U8400";
2556 case PRCMU_FW_PROJECT_U9500:
2557 return "U9500";
2558 case PRCMU_FW_PROJECT_U8500_MBB:
2559 return "U8500 MBB";
2560 case PRCMU_FW_PROJECT_U8500_C1:
2561 return "U8500 C1";
2562 case PRCMU_FW_PROJECT_U8500_C2:
2563 return "U8500 C2";
2564 case PRCMU_FW_PROJECT_U8500_C3:
2565 return "U8500 C3";
2566 case PRCMU_FW_PROJECT_U8500_C4:
2567 return "U8500 C4";
2568 case PRCMU_FW_PROJECT_U9500_MBL:
2569 return "U9500 MBL";
2570 case PRCMU_FW_PROJECT_U8500_MBL:
2571 return "U8500 MBL";
2572 case PRCMU_FW_PROJECT_U8500_MBL2:
2573 return "U8500 MBL2";
2574 case PRCMU_FW_PROJECT_U8520:
2575 return "U8520 MBL";
2576 case PRCMU_FW_PROJECT_U8420:
2577 return "U8420";
2578 case PRCMU_FW_PROJECT_U8420_SYSCLK:
2579 return "U8420-sysclk";
2580 case PRCMU_FW_PROJECT_U9540:
2581 return "U9540";
2582 case PRCMU_FW_PROJECT_A9420:
2583 return "A9420";
2584 case PRCMU_FW_PROJECT_L8540:
2585 return "L8540";
2586 case PRCMU_FW_PROJECT_L8580:
2587 return "L8580";
2588 default:
2589 return "Unknown";
2590 }
2591}
2592
2593static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2594 irq_hw_number_t hwirq)
2595{
2596 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2597 handle_simple_irq);
2598
2599 return 0;
2600}
2601
2602static const struct irq_domain_ops db8500_irq_ops = {
2603 .map = db8500_irq_map,
2604 .xlate = irq_domain_xlate_twocell,
2605};
2606
2607static int db8500_irq_init(struct device_node *np)
2608{
2609 int i;
2610
2611 db8500_irq_domain = irq_domain_add_simple(
2612 np, NUM_PRCMU_WAKEUPS, 0,
2613 &db8500_irq_ops, NULL);
2614
2615 if (!db8500_irq_domain) {
2616 pr_err("Failed to create irqdomain\n");
2617 return -ENOSYS;
2618 }
2619
2620 /* All wakeups will be used, so create mappings for all */
2621 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2622 irq_create_mapping(db8500_irq_domain, i);
2623
2624 return 0;
2625}
2626
2627static void dbx500_fw_version_init(struct device_node *np)
2628{
2629 void __iomem *tcpm_base;
2630 u32 version;
2631
2632 tcpm_base = of_iomap(np, 1);
2633 if (!tcpm_base) {
2634 pr_err("no prcmu tcpm mem region provided\n");
2635 return;
2636 }
2637
2638 version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET);
2639 fw_info.version.project = (version & 0xFF);
2640 fw_info.version.api_version = (version >> 8) & 0xFF;
2641 fw_info.version.func_version = (version >> 16) & 0xFF;
2642 fw_info.version.errata = (version >> 24) & 0xFF;
2643 strncpy(fw_info.version.project_name,
2644 fw_project_name(fw_info.version.project),
2645 PRCMU_FW_PROJECT_NAME_LEN);
2646 fw_info.valid = true;
2647 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2648 fw_info.version.project_name,
2649 fw_info.version.project,
2650 fw_info.version.api_version,
2651 fw_info.version.func_version,
2652 fw_info.version.errata);
2653 iounmap(tcpm_base);
2654}
2655
2656void __init db8500_prcmu_early_init(void)
2657{
2658 /*
2659 * This is a temporary remap to bring up the clocks. It is
2660 * subsequently replaces with a real remap. After the merge of
2661 * the mailbox subsystem all of this early code goes away, and the
2662 * clock driver can probe independently. An early initcall will
2663 * still be needed, but it can be diverted into drivers/clk/ux500.
2664 */
2665 struct device_node *np;
2666
2667 np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
2668 prcmu_base = of_iomap(np, 0);
2669 if (!prcmu_base) {
2670 of_node_put(np);
2671 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2672 return;
2673 }
2674 dbx500_fw_version_init(np);
2675 of_node_put(np);
2676
2677 spin_lock_init(&mb0_transfer.lock);
2678 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2679 mutex_init(&mb0_transfer.ac_wake_lock);
2680 init_completion(&mb0_transfer.ac_wake_work);
2681 mutex_init(&mb1_transfer.lock);
2682 init_completion(&mb1_transfer.work);
2683 mb1_transfer.ape_opp = APE_NO_CHANGE;
2684 mutex_init(&mb2_transfer.lock);
2685 init_completion(&mb2_transfer.work);
2686 spin_lock_init(&mb2_transfer.auto_pm_lock);
2687 spin_lock_init(&mb3_transfer.lock);
2688 mutex_init(&mb3_transfer.sysclk_lock);
2689 init_completion(&mb3_transfer.sysclk_work);
2690 mutex_init(&mb4_transfer.lock);
2691 init_completion(&mb4_transfer.work);
2692 mutex_init(&mb5_transfer.lock);
2693 init_completion(&mb5_transfer.work);
2694
2695 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2696}
2697
2698static void init_prcm_registers(void)
2699{
2700 u32 val;
2701
2702 val = readl(PRCM_A9PL_FORCE_CLKEN);
2703 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2704 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2705 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2706}
2707
2708/*
2709 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2710 */
2711static struct regulator_consumer_supply db8500_vape_consumers[] = {
2712 REGULATOR_SUPPLY("v-ape", NULL),
2713 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2714 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2715 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2716 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2717 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2718 /* "v-mmc" changed to "vcore" in the mainline kernel */
2719 REGULATOR_SUPPLY("vcore", "sdi0"),
2720 REGULATOR_SUPPLY("vcore", "sdi1"),
2721 REGULATOR_SUPPLY("vcore", "sdi2"),
2722 REGULATOR_SUPPLY("vcore", "sdi3"),
2723 REGULATOR_SUPPLY("vcore", "sdi4"),
2724 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2725 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2726 /* "v-uart" changed to "vcore" in the mainline kernel */
2727 REGULATOR_SUPPLY("vcore", "uart0"),
2728 REGULATOR_SUPPLY("vcore", "uart1"),
2729 REGULATOR_SUPPLY("vcore", "uart2"),
2730 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2731 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2732 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2733};
2734
2735static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2736 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2737 /* AV8100 regulator */
2738 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2739};
2740
2741static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2742 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2743 REGULATOR_SUPPLY("vsupply", "mcde"),
2744};
2745
2746/* SVA MMDSP regulator switch */
2747static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2748 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2749};
2750
2751/* SVA pipe regulator switch */
2752static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2753 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2754};
2755
2756/* SIA MMDSP regulator switch */
2757static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2758 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2759};
2760
2761/* SIA pipe regulator switch */
2762static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2763 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2764};
2765
2766static struct regulator_consumer_supply db8500_sga_consumers[] = {
2767 REGULATOR_SUPPLY("v-mali", NULL),
2768};
2769
2770/* ESRAM1 and 2 regulator switch */
2771static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2772 REGULATOR_SUPPLY("esram12", "cm_control"),
2773};
2774
2775/* ESRAM3 and 4 regulator switch */
2776static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2777 REGULATOR_SUPPLY("v-esram34", "mcde"),
2778 REGULATOR_SUPPLY("esram34", "cm_control"),
2779 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2780};
2781
2782static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2783 [DB8500_REGULATOR_VAPE] = {
2784 .constraints = {
2785 .name = "db8500-vape",
2786 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2787 .always_on = true,
2788 },
2789 .consumer_supplies = db8500_vape_consumers,
2790 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2791 },
2792 [DB8500_REGULATOR_VARM] = {
2793 .constraints = {
2794 .name = "db8500-varm",
2795 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2796 },
2797 },
2798 [DB8500_REGULATOR_VMODEM] = {
2799 .constraints = {
2800 .name = "db8500-vmodem",
2801 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2802 },
2803 },
2804 [DB8500_REGULATOR_VPLL] = {
2805 .constraints = {
2806 .name = "db8500-vpll",
2807 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2808 },
2809 },
2810 [DB8500_REGULATOR_VSMPS1] = {
2811 .constraints = {
2812 .name = "db8500-vsmps1",
2813 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2814 },
2815 },
2816 [DB8500_REGULATOR_VSMPS2] = {
2817 .constraints = {
2818 .name = "db8500-vsmps2",
2819 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2820 },
2821 .consumer_supplies = db8500_vsmps2_consumers,
2822 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2823 },
2824 [DB8500_REGULATOR_VSMPS3] = {
2825 .constraints = {
2826 .name = "db8500-vsmps3",
2827 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2828 },
2829 },
2830 [DB8500_REGULATOR_VRF1] = {
2831 .constraints = {
2832 .name = "db8500-vrf1",
2833 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2834 },
2835 },
2836 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2837 /* dependency to u8500-vape is handled outside regulator framework */
2838 .constraints = {
2839 .name = "db8500-sva-mmdsp",
2840 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2841 },
2842 .consumer_supplies = db8500_svammdsp_consumers,
2843 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2844 },
2845 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2846 .constraints = {
2847 /* "ret" means "retention" */
2848 .name = "db8500-sva-mmdsp-ret",
2849 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2850 },
2851 },
2852 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2853 /* dependency to u8500-vape is handled outside regulator framework */
2854 .constraints = {
2855 .name = "db8500-sva-pipe",
2856 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2857 },
2858 .consumer_supplies = db8500_svapipe_consumers,
2859 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2860 },
2861 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2862 /* dependency to u8500-vape is handled outside regulator framework */
2863 .constraints = {
2864 .name = "db8500-sia-mmdsp",
2865 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2866 },
2867 .consumer_supplies = db8500_siammdsp_consumers,
2868 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2869 },
2870 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2871 .constraints = {
2872 .name = "db8500-sia-mmdsp-ret",
2873 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2874 },
2875 },
2876 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2877 /* dependency to u8500-vape is handled outside regulator framework */
2878 .constraints = {
2879 .name = "db8500-sia-pipe",
2880 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2881 },
2882 .consumer_supplies = db8500_siapipe_consumers,
2883 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2884 },
2885 [DB8500_REGULATOR_SWITCH_SGA] = {
2886 .supply_regulator = "db8500-vape",
2887 .constraints = {
2888 .name = "db8500-sga",
2889 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890 },
2891 .consumer_supplies = db8500_sga_consumers,
2892 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2893
2894 },
2895 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2896 .supply_regulator = "db8500-vape",
2897 .constraints = {
2898 .name = "db8500-b2r2-mcde",
2899 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2900 },
2901 .consumer_supplies = db8500_b2r2_mcde_consumers,
2902 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2903 },
2904 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2905 /*
2906 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2907 * no need to hold Vape
2908 */
2909 .constraints = {
2910 .name = "db8500-esram12",
2911 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2912 },
2913 .consumer_supplies = db8500_esram12_consumers,
2914 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2915 },
2916 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2917 .constraints = {
2918 .name = "db8500-esram12-ret",
2919 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920 },
2921 },
2922 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2923 /*
2924 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2925 * no need to hold Vape
2926 */
2927 .constraints = {
2928 .name = "db8500-esram34",
2929 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2930 },
2931 .consumer_supplies = db8500_esram34_consumers,
2932 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2933 },
2934 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2935 .constraints = {
2936 .name = "db8500-esram34-ret",
2937 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2938 },
2939 },
2940};
2941
2942static struct ux500_wdt_data db8500_wdt_pdata = {
2943 .timeout = 600, /* 10 minutes */
2944 .has_28_bits_resolution = true,
2945};
2946
2947static const struct mfd_cell common_prcmu_devs[] = {
2948 {
2949 .name = "ux500_wdt",
2950 .platform_data = &db8500_wdt_pdata,
2951 .pdata_size = sizeof(db8500_wdt_pdata),
2952 .id = -1,
2953 },
2954};
2955
2956static const struct mfd_cell db8500_prcmu_devs[] = {
2957 OF_MFD_CELL("db8500-prcmu-regulators", NULL,
2958 &db8500_regulators, sizeof(db8500_regulators), 0,
2959 "stericsson,db8500-prcmu-regulator"),
2960 OF_MFD_CELL("cpuidle-dbx500",
2961 NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"),
2962 OF_MFD_CELL("db8500-thermal",
2963 NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
2964};
2965
2966static int db8500_prcmu_register_ab8500(struct device *parent)
2967{
2968 struct device_node *np;
2969 struct resource ab850x_resource;
2970 const struct mfd_cell ab8500_cell = {
2971 .name = "ab8500-core",
2972 .of_compatible = "stericsson,ab8500",
2973 .id = AB8500_VERSION_AB8500,
2974 .resources = &ab850x_resource,
2975 .num_resources = 1,
2976 };
2977 const struct mfd_cell ab8505_cell = {
2978 .name = "ab8505-core",
2979 .of_compatible = "stericsson,ab8505",
2980 .id = AB8500_VERSION_AB8505,
2981 .resources = &ab850x_resource,
2982 .num_resources = 1,
2983 };
2984 const struct mfd_cell *ab850x_cell;
2985
2986 if (!parent->of_node)
2987 return -ENODEV;
2988
2989 /* Look up the device node, sneak the IRQ out of it */
2990 for_each_child_of_node(parent->of_node, np) {
2991 if (of_device_is_compatible(np, ab8500_cell.of_compatible)) {
2992 ab850x_cell = &ab8500_cell;
2993 break;
2994 }
2995 if (of_device_is_compatible(np, ab8505_cell.of_compatible)) {
2996 ab850x_cell = &ab8505_cell;
2997 break;
2998 }
2999 }
3000 if (!np) {
3001 dev_info(parent, "could not find AB850X node in the device tree\n");
3002 return -ENODEV;
3003 }
3004 of_irq_to_resource_table(np, &ab850x_resource, 1);
3005
3006 return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL);
3007}
3008
3009static int db8500_prcmu_probe(struct platform_device *pdev)
3010{
3011 struct device_node *np = pdev->dev.of_node;
3012 int irq = 0, err = 0;
3013 struct resource *res;
3014
3015 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3016 if (!res) {
3017 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3018 return -EINVAL;
3019 }
3020 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3021 if (!prcmu_base) {
3022 dev_err(&pdev->dev,
3023 "failed to ioremap prcmu register memory\n");
3024 return -ENOMEM;
3025 }
3026 init_prcm_registers();
3027 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3028 if (!res) {
3029 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3030 return -EINVAL;
3031 }
3032 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3033 resource_size(res));
3034 if (!tcdm_base) {
3035 dev_err(&pdev->dev,
3036 "failed to ioremap prcmu-tcdm register memory\n");
3037 return -ENOMEM;
3038 }
3039
3040 /* Clean up the mailbox interrupts after pre-kernel code. */
3041 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3042
3043 irq = platform_get_irq(pdev, 0);
3044 if (irq <= 0)
3045 return irq;
3046
3047 err = request_threaded_irq(irq, prcmu_irq_handler,
3048 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3049 if (err < 0) {
3050 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3051 return err;
3052 }
3053
3054 db8500_irq_init(np);
3055
3056 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3057
3058 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3059 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3060 if (err) {
3061 pr_err("prcmu: Failed to add subdevices\n");
3062 return err;
3063 }
3064
3065 /* TODO: Remove restriction when clk definitions are available. */
3066 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3067 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3068 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3069 db8500_irq_domain);
3070 if (err) {
3071 mfd_remove_devices(&pdev->dev);
3072 pr_err("prcmu: Failed to add subdevices\n");
3073 return err;
3074 }
3075 }
3076
3077 err = db8500_prcmu_register_ab8500(&pdev->dev);
3078 if (err) {
3079 mfd_remove_devices(&pdev->dev);
3080 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3081 return err;
3082 }
3083
3084 pr_info("DB8500 PRCMU initialized\n");
3085 return err;
3086}
3087static const struct of_device_id db8500_prcmu_match[] = {
3088 { .compatible = "stericsson,db8500-prcmu"},
3089 { },
3090};
3091
3092static struct platform_driver db8500_prcmu_driver = {
3093 .driver = {
3094 .name = "db8500-prcmu",
3095 .of_match_table = db8500_prcmu_match,
3096 },
3097 .probe = db8500_prcmu_probe,
3098};
3099
3100static int __init db8500_prcmu_init(void)
3101{
3102 return platform_driver_register(&db8500_prcmu_driver);
3103}
3104core_initcall(db8500_prcmu_init);
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
9 *
10 * U8500 PRCM Unit interface driver
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/spinlock.h>
19#include <linux/io.h>
20#include <linux/slab.h>
21#include <linux/mutex.h>
22#include <linux/completion.h>
23#include <linux/irq.h>
24#include <linux/jiffies.h>
25#include <linux/bitops.h>
26#include <linux/fs.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
29#include <linux/mfd/core.h>
30#include <linux/mfd/dbx500-prcmu.h>
31#include <linux/regulator/db8500-prcmu.h>
32#include <linux/regulator/machine.h>
33#include <asm/hardware/gic.h>
34#include <mach/hardware.h>
35#include <mach/irqs.h>
36#include <mach/db8500-regs.h>
37#include <mach/id.h>
38#include "dbx500-prcmu-regs.h"
39
40/* Offset for the firmware version within the TCPM */
41#define PRCMU_FW_VERSION_OFFSET 0xA4
42
43/* Index of different voltages to be used when accessing AVSData */
44#define PRCM_AVS_BASE 0x2FC
45#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
46#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
47#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
48#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
49#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
50#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
51#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
52#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
53#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
54#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
55#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
56#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
57#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
58
59#define PRCM_AVS_VOLTAGE 0
60#define PRCM_AVS_VOLTAGE_MASK 0x3f
61#define PRCM_AVS_ISSLOWSTARTUP 6
62#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
63#define PRCM_AVS_ISMODEENABLE 7
64#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
65
66#define PRCM_BOOT_STATUS 0xFFF
67#define PRCM_ROMCODE_A2P 0xFFE
68#define PRCM_ROMCODE_P2A 0xFFD
69#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
70
71#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
72
73#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
74#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
75#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
76#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
77#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
78#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
79#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
80#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
81
82/* Req Mailboxes */
83#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
84#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
85#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
86#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
87#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
88#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
89
90/* Ack Mailboxes */
91#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
92#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
93#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
94#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
95#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
96#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
97
98/* Mailbox 0 headers */
99#define MB0H_POWER_STATE_TRANS 0
100#define MB0H_CONFIG_WAKEUPS_EXE 1
101#define MB0H_READ_WAKEUP_ACK 3
102#define MB0H_CONFIG_WAKEUPS_SLEEP 4
103
104#define MB0H_WAKEUP_EXE 2
105#define MB0H_WAKEUP_SLEEP 5
106
107/* Mailbox 0 REQs */
108#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
109#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
110#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
111#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
112#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
113#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
114
115/* Mailbox 0 ACKs */
116#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
117#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
118#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
119#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
120#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
121#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
122#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
123
124/* Mailbox 1 headers */
125#define MB1H_ARM_APE_OPP 0x0
126#define MB1H_RESET_MODEM 0x2
127#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
128#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
129#define MB1H_RELEASE_USB_WAKEUP 0x5
130#define MB1H_PLL_ON_OFF 0x6
131
132/* Mailbox 1 Requests */
133#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
134#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
135#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
136#define PLL_SOC0_OFF 0x1
137#define PLL_SOC0_ON 0x2
138#define PLL_SOC1_OFF 0x4
139#define PLL_SOC1_ON 0x8
140
141/* Mailbox 1 ACKs */
142#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
143#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
144#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
145#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
146
147/* Mailbox 2 headers */
148#define MB2H_DPS 0x0
149#define MB2H_AUTO_PWR 0x1
150
151/* Mailbox 2 REQs */
152#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
153#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
154#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
155#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
156#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
157#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
158#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
159#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
160#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
161#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
162
163/* Mailbox 2 ACKs */
164#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
165#define HWACC_PWR_ST_OK 0xFE
166
167/* Mailbox 3 headers */
168#define MB3H_ANC 0x0
169#define MB3H_SIDETONE 0x1
170#define MB3H_SYSCLK 0xE
171
172/* Mailbox 3 Requests */
173#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
174#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
175#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
176#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
177#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
178#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
179#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
180
181/* Mailbox 4 headers */
182#define MB4H_DDR_INIT 0x0
183#define MB4H_MEM_ST 0x1
184#define MB4H_HOTDOG 0x12
185#define MB4H_HOTMON 0x13
186#define MB4H_HOT_PERIOD 0x14
187#define MB4H_A9WDOG_CONF 0x16
188#define MB4H_A9WDOG_EN 0x17
189#define MB4H_A9WDOG_DIS 0x18
190#define MB4H_A9WDOG_LOAD 0x19
191#define MB4H_A9WDOG_KICK 0x20
192
193/* Mailbox 4 Requests */
194#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
195#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
196#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
197#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
198#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
199#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
200#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
201#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
202#define HOTMON_CONFIG_LOW BIT(0)
203#define HOTMON_CONFIG_HIGH BIT(1)
204#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
205#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
206#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
207#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
208#define A9WDOG_AUTO_OFF_EN BIT(7)
209#define A9WDOG_AUTO_OFF_DIS 0
210#define A9WDOG_ID_MASK 0xf
211
212/* Mailbox 5 Requests */
213#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
214#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
215#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
216#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
217#define PRCMU_I2C_WRITE(slave) \
218 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
219#define PRCMU_I2C_READ(slave) \
220 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
221#define PRCMU_I2C_STOP_EN BIT(3)
222
223/* Mailbox 5 ACKs */
224#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
225#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
226#define I2C_WR_OK 0x1
227#define I2C_RD_OK 0x2
228
229#define NUM_MB 8
230#define MBOX_BIT BIT
231#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
232
233/*
234 * Wakeups/IRQs
235 */
236
237#define WAKEUP_BIT_RTC BIT(0)
238#define WAKEUP_BIT_RTT0 BIT(1)
239#define WAKEUP_BIT_RTT1 BIT(2)
240#define WAKEUP_BIT_HSI0 BIT(3)
241#define WAKEUP_BIT_HSI1 BIT(4)
242#define WAKEUP_BIT_CA_WAKE BIT(5)
243#define WAKEUP_BIT_USB BIT(6)
244#define WAKEUP_BIT_ABB BIT(7)
245#define WAKEUP_BIT_ABB_FIFO BIT(8)
246#define WAKEUP_BIT_SYSCLK_OK BIT(9)
247#define WAKEUP_BIT_CA_SLEEP BIT(10)
248#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
249#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
250#define WAKEUP_BIT_ANC_OK BIT(13)
251#define WAKEUP_BIT_SW_ERROR BIT(14)
252#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
253#define WAKEUP_BIT_ARM BIT(17)
254#define WAKEUP_BIT_HOTMON_LOW BIT(18)
255#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
256#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
257#define WAKEUP_BIT_GPIO0 BIT(23)
258#define WAKEUP_BIT_GPIO1 BIT(24)
259#define WAKEUP_BIT_GPIO2 BIT(25)
260#define WAKEUP_BIT_GPIO3 BIT(26)
261#define WAKEUP_BIT_GPIO4 BIT(27)
262#define WAKEUP_BIT_GPIO5 BIT(28)
263#define WAKEUP_BIT_GPIO6 BIT(29)
264#define WAKEUP_BIT_GPIO7 BIT(30)
265#define WAKEUP_BIT_GPIO8 BIT(31)
266
267static struct {
268 bool valid;
269 struct prcmu_fw_version version;
270} fw_info;
271
272/*
273 * This vector maps irq numbers to the bits in the bit field used in
274 * communication with the PRCMU firmware.
275 *
276 * The reason for having this is to keep the irq numbers contiguous even though
277 * the bits in the bit field are not. (The bits also have a tendency to move
278 * around, to further complicate matters.)
279 */
280#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
281#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
283 IRQ_ENTRY(RTC),
284 IRQ_ENTRY(RTT0),
285 IRQ_ENTRY(RTT1),
286 IRQ_ENTRY(HSI0),
287 IRQ_ENTRY(HSI1),
288 IRQ_ENTRY(CA_WAKE),
289 IRQ_ENTRY(USB),
290 IRQ_ENTRY(ABB),
291 IRQ_ENTRY(ABB_FIFO),
292 IRQ_ENTRY(CA_SLEEP),
293 IRQ_ENTRY(ARM),
294 IRQ_ENTRY(HOTMON_LOW),
295 IRQ_ENTRY(HOTMON_HIGH),
296 IRQ_ENTRY(MODEM_SW_RESET_REQ),
297 IRQ_ENTRY(GPIO0),
298 IRQ_ENTRY(GPIO1),
299 IRQ_ENTRY(GPIO2),
300 IRQ_ENTRY(GPIO3),
301 IRQ_ENTRY(GPIO4),
302 IRQ_ENTRY(GPIO5),
303 IRQ_ENTRY(GPIO6),
304 IRQ_ENTRY(GPIO7),
305 IRQ_ENTRY(GPIO8)
306};
307
308#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
309#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
310static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
311 WAKEUP_ENTRY(RTC),
312 WAKEUP_ENTRY(RTT0),
313 WAKEUP_ENTRY(RTT1),
314 WAKEUP_ENTRY(HSI0),
315 WAKEUP_ENTRY(HSI1),
316 WAKEUP_ENTRY(USB),
317 WAKEUP_ENTRY(ABB),
318 WAKEUP_ENTRY(ABB_FIFO),
319 WAKEUP_ENTRY(ARM)
320};
321
322/*
323 * mb0_transfer - state needed for mailbox 0 communication.
324 * @lock: The transaction lock.
325 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
326 * the request data.
327 * @mask_work: Work structure used for (un)masking wakeup interrupts.
328 * @req: Request data that need to persist between requests.
329 */
330static struct {
331 spinlock_t lock;
332 spinlock_t dbb_irqs_lock;
333 struct work_struct mask_work;
334 struct mutex ac_wake_lock;
335 struct completion ac_wake_work;
336 struct {
337 u32 dbb_irqs;
338 u32 dbb_wakeups;
339 u32 abb_events;
340 } req;
341} mb0_transfer;
342
343/*
344 * mb1_transfer - state needed for mailbox 1 communication.
345 * @lock: The transaction lock.
346 * @work: The transaction completion structure.
347 * @ape_opp: The current APE OPP.
348 * @ack: Reply ("acknowledge") data.
349 */
350static struct {
351 struct mutex lock;
352 struct completion work;
353 u8 ape_opp;
354 struct {
355 u8 header;
356 u8 arm_opp;
357 u8 ape_opp;
358 u8 ape_voltage_status;
359 } ack;
360} mb1_transfer;
361
362/*
363 * mb2_transfer - state needed for mailbox 2 communication.
364 * @lock: The transaction lock.
365 * @work: The transaction completion structure.
366 * @auto_pm_lock: The autonomous power management configuration lock.
367 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
368 * @req: Request data that need to persist between requests.
369 * @ack: Reply ("acknowledge") data.
370 */
371static struct {
372 struct mutex lock;
373 struct completion work;
374 spinlock_t auto_pm_lock;
375 bool auto_pm_enabled;
376 struct {
377 u8 status;
378 } ack;
379} mb2_transfer;
380
381/*
382 * mb3_transfer - state needed for mailbox 3 communication.
383 * @lock: The request lock.
384 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
385 * @sysclk_work: Work structure used for sysclk requests.
386 */
387static struct {
388 spinlock_t lock;
389 struct mutex sysclk_lock;
390 struct completion sysclk_work;
391} mb3_transfer;
392
393/*
394 * mb4_transfer - state needed for mailbox 4 communication.
395 * @lock: The transaction lock.
396 * @work: The transaction completion structure.
397 */
398static struct {
399 struct mutex lock;
400 struct completion work;
401} mb4_transfer;
402
403/*
404 * mb5_transfer - state needed for mailbox 5 communication.
405 * @lock: The transaction lock.
406 * @work: The transaction completion structure.
407 * @ack: Reply ("acknowledge") data.
408 */
409static struct {
410 struct mutex lock;
411 struct completion work;
412 struct {
413 u8 status;
414 u8 value;
415 } ack;
416} mb5_transfer;
417
418static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
419
420/* Spinlocks */
421static DEFINE_SPINLOCK(prcmu_lock);
422static DEFINE_SPINLOCK(clkout_lock);
423
424/* Global var to runtime determine TCDM base for v2 or v1 */
425static __iomem void *tcdm_base;
426
427struct clk_mgt {
428 void __iomem *reg;
429 u32 pllsw;
430 int branch;
431 bool clk38div;
432};
433
434enum {
435 PLL_RAW,
436 PLL_FIX,
437 PLL_DIV
438};
439
440static DEFINE_SPINLOCK(clk_mgt_lock);
441
442#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
443 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
444struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
445 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
446 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
447 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
448 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
449 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
450 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
451 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
452 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
453 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
454 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
455 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
456 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
457 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
458 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
459 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
460 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
461 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
462 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
463 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
464 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
465 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
466 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
467 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
468 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
469 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
470 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
471 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
474};
475
476struct dsiclk {
477 u32 divsel_mask;
478 u32 divsel_shift;
479 u32 divsel;
480};
481
482static struct dsiclk dsiclk[2] = {
483 {
484 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
485 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
486 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
487 },
488 {
489 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
490 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
491 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
492 }
493};
494
495struct dsiescclk {
496 u32 en;
497 u32 div_mask;
498 u32 div_shift;
499};
500
501static struct dsiescclk dsiescclk[3] = {
502 {
503 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
504 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
505 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
506 },
507 {
508 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
509 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
510 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
511 },
512 {
513 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
514 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
515 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
516 }
517};
518
519/*
520* Used by MCDE to setup all necessary PRCMU registers
521*/
522#define PRCMU_RESET_DSIPLL 0x00004000
523#define PRCMU_UNCLAMP_DSIPLL 0x00400800
524
525#define PRCMU_CLK_PLL_DIV_SHIFT 0
526#define PRCMU_CLK_PLL_SW_SHIFT 5
527#define PRCMU_CLK_38 (1 << 9)
528#define PRCMU_CLK_38_SRC (1 << 10)
529#define PRCMU_CLK_38_DIV (1 << 11)
530
531/* PLLDIV=12, PLLSW=4 (PLLDDR) */
532#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
533
534/* DPI 50000000 Hz */
535#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
536 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
537#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
538
539/* D=101, N=1, R=4, SELDIV2=0 */
540#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
541
542#define PRCMU_ENABLE_PLLDSI 0x00000001
543#define PRCMU_DISABLE_PLLDSI 0x00000000
544#define PRCMU_RELEASE_RESET_DSS 0x0000400C
545#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
546/* ESC clk, div0=1, div1=1, div2=3 */
547#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
548#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
549#define PRCMU_DSI_RESET_SW 0x00000007
550
551#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
552
553int db8500_prcmu_enable_dsipll(void)
554{
555 int i;
556
557 /* Clear DSIPLL_RESETN */
558 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
559 /* Unclamp DSIPLL in/out */
560 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
561
562 /* Set DSI PLL FREQ */
563 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
564 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
565 /* Enable Escape clocks */
566 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
567
568 /* Start DSI PLL */
569 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
570 /* Reset DSI PLL */
571 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
572 for (i = 0; i < 10; i++) {
573 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
574 == PRCMU_PLLDSI_LOCKP_LOCKED)
575 break;
576 udelay(100);
577 }
578 /* Set DSIPLL_RESETN */
579 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
580 return 0;
581}
582
583int db8500_prcmu_disable_dsipll(void)
584{
585 /* Disable dsi pll */
586 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
587 /* Disable escapeclock */
588 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
589 return 0;
590}
591
592int db8500_prcmu_set_display_clocks(void)
593{
594 unsigned long flags;
595
596 spin_lock_irqsave(&clk_mgt_lock, flags);
597
598 /* Grab the HW semaphore. */
599 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
600 cpu_relax();
601
602 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
603 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
604 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
605
606 /* Release the HW semaphore. */
607 writel(0, PRCM_SEM);
608
609 spin_unlock_irqrestore(&clk_mgt_lock, flags);
610
611 return 0;
612}
613
614u32 db8500_prcmu_read(unsigned int reg)
615{
616 return readl(_PRCMU_BASE + reg);
617}
618
619void db8500_prcmu_write(unsigned int reg, u32 value)
620{
621 unsigned long flags;
622
623 spin_lock_irqsave(&prcmu_lock, flags);
624 writel(value, (_PRCMU_BASE + reg));
625 spin_unlock_irqrestore(&prcmu_lock, flags);
626}
627
628void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
629{
630 u32 val;
631 unsigned long flags;
632
633 spin_lock_irqsave(&prcmu_lock, flags);
634 val = readl(_PRCMU_BASE + reg);
635 val = ((val & ~mask) | (value & mask));
636 writel(val, (_PRCMU_BASE + reg));
637 spin_unlock_irqrestore(&prcmu_lock, flags);
638}
639
640struct prcmu_fw_version *prcmu_get_fw_version(void)
641{
642 return fw_info.valid ? &fw_info.version : NULL;
643}
644
645bool prcmu_has_arm_maxopp(void)
646{
647 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
648 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
649}
650
651/**
652 * prcmu_get_boot_status - PRCMU boot status checking
653 * Returns: the current PRCMU boot status
654 */
655int prcmu_get_boot_status(void)
656{
657 return readb(tcdm_base + PRCM_BOOT_STATUS);
658}
659
660/**
661 * prcmu_set_rc_a2p - This function is used to run few power state sequences
662 * @val: Value to be set, i.e. transition requested
663 * Returns: 0 on success, -EINVAL on invalid argument
664 *
665 * This function is used to run the following power state sequences -
666 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
667 */
668int prcmu_set_rc_a2p(enum romcode_write val)
669{
670 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
671 return -EINVAL;
672 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
673 return 0;
674}
675
676/**
677 * prcmu_get_rc_p2a - This function is used to get power state sequences
678 * Returns: the power transition that has last happened
679 *
680 * This function can return the following transitions-
681 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
682 */
683enum romcode_read prcmu_get_rc_p2a(void)
684{
685 return readb(tcdm_base + PRCM_ROMCODE_P2A);
686}
687
688/**
689 * prcmu_get_current_mode - Return the current XP70 power mode
690 * Returns: Returns the current AP(ARM) power mode: init,
691 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
692 */
693enum ap_pwrst prcmu_get_xp70_current_state(void)
694{
695 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
696}
697
698/**
699 * prcmu_config_clkout - Configure one of the programmable clock outputs.
700 * @clkout: The CLKOUT number (0 or 1).
701 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
702 * @div: The divider to be applied.
703 *
704 * Configures one of the programmable clock outputs (CLKOUTs).
705 * @div should be in the range [1,63] to request a configuration, or 0 to
706 * inform that the configuration is no longer requested.
707 */
708int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
709{
710 static int requests[2];
711 int r = 0;
712 unsigned long flags;
713 u32 val;
714 u32 bits;
715 u32 mask;
716 u32 div_mask;
717
718 BUG_ON(clkout > 1);
719 BUG_ON(div > 63);
720 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
721
722 if (!div && !requests[clkout])
723 return -EINVAL;
724
725 switch (clkout) {
726 case 0:
727 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
728 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
729 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
730 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
731 break;
732 case 1:
733 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
734 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
735 PRCM_CLKOCR_CLK1TYPE);
736 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
737 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
738 break;
739 }
740 bits &= mask;
741
742 spin_lock_irqsave(&clkout_lock, flags);
743
744 val = readl(PRCM_CLKOCR);
745 if (val & div_mask) {
746 if (div) {
747 if ((val & mask) != bits) {
748 r = -EBUSY;
749 goto unlock_and_return;
750 }
751 } else {
752 if ((val & mask & ~div_mask) != bits) {
753 r = -EINVAL;
754 goto unlock_and_return;
755 }
756 }
757 }
758 writel((bits | (val & ~mask)), PRCM_CLKOCR);
759 requests[clkout] += (div ? 1 : -1);
760
761unlock_and_return:
762 spin_unlock_irqrestore(&clkout_lock, flags);
763
764 return r;
765}
766
767int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
768{
769 unsigned long flags;
770
771 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
772
773 spin_lock_irqsave(&mb0_transfer.lock, flags);
774
775 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
776 cpu_relax();
777
778 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
779 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
780 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
781 writeb((keep_ulp_clk ? 1 : 0),
782 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
783 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
784 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
785
786 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
787
788 return 0;
789}
790
791u8 db8500_prcmu_get_power_state_result(void)
792{
793 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
794}
795
796/* This function decouple the gic from the prcmu */
797int db8500_prcmu_gic_decouple(void)
798{
799 u32 val = readl(PRCM_A9_MASK_REQ);
800
801 /* Set bit 0 register value to 1 */
802 writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
803 PRCM_A9_MASK_REQ);
804
805 /* Make sure the register is updated */
806 readl(PRCM_A9_MASK_REQ);
807
808 /* Wait a few cycles for the gic mask completion */
809 udelay(1);
810
811 return 0;
812}
813
814/* This function recouple the gic with the prcmu */
815int db8500_prcmu_gic_recouple(void)
816{
817 u32 val = readl(PRCM_A9_MASK_REQ);
818
819 /* Set bit 0 register value to 0 */
820 writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
821
822 return 0;
823}
824
825#define PRCMU_GIC_NUMBER_REGS 5
826
827/*
828 * This function checks if there are pending irq on the gic. It only
829 * makes sense if the gic has been decoupled before with the
830 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
831 * disables the forwarding of the interrupt to any CPU interface. It
832 * does not prevent the interrupt from changing state, for example
833 * becoming pending, or active and pending if it is already
834 * active. Hence, we have to check the interrupt is pending *and* is
835 * active.
836 */
837bool db8500_prcmu_gic_pending_irq(void)
838{
839 u32 pr; /* Pending register */
840 u32 er; /* Enable register */
841 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
842 int i;
843
844 /* 5 registers. STI & PPI not skipped */
845 for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
846
847 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
848 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
849
850 if (pr & er)
851 return true; /* There is a pending interrupt */
852 }
853
854 return false;
855}
856
857/*
858 * This function checks if there are pending interrupt on the
859 * prcmu which has been delegated to monitor the irqs with the
860 * db8500_prcmu_copy_gic_settings function.
861 */
862bool db8500_prcmu_pending_irq(void)
863{
864 u32 it, im;
865 int i;
866
867 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
868 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
869 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
870 if (it & im)
871 return true; /* There is a pending interrupt */
872 }
873
874 return false;
875}
876
877/*
878 * This function checks if the specified cpu is in in WFI. It's usage
879 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
880 * function. Of course passing smp_processor_id() to this function will
881 * always return false...
882 */
883bool db8500_prcmu_is_cpu_in_wfi(int cpu)
884{
885 return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
886 PRCM_ARM_WFI_STANDBY_WFI0;
887}
888
889/*
890 * This function copies the gic SPI settings to the prcmu in order to
891 * monitor them and abort/finish the retention/off sequence or state.
892 */
893int db8500_prcmu_copy_gic_settings(void)
894{
895 u32 er; /* Enable register */
896 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
897 int i;
898
899 /* We skip the STI and PPI */
900 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
901 er = readl_relaxed(dist_base +
902 GIC_DIST_ENABLE_SET + (i + 1) * 4);
903 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
904 }
905
906 return 0;
907}
908
909/* This function should only be called while mb0_transfer.lock is held. */
910static void config_wakeups(void)
911{
912 const u8 header[2] = {
913 MB0H_CONFIG_WAKEUPS_EXE,
914 MB0H_CONFIG_WAKEUPS_SLEEP
915 };
916 static u32 last_dbb_events;
917 static u32 last_abb_events;
918 u32 dbb_events;
919 u32 abb_events;
920 unsigned int i;
921
922 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
923 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
924
925 abb_events = mb0_transfer.req.abb_events;
926
927 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
928 return;
929
930 for (i = 0; i < 2; i++) {
931 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
932 cpu_relax();
933 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
934 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
935 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
936 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
937 }
938 last_dbb_events = dbb_events;
939 last_abb_events = abb_events;
940}
941
942void db8500_prcmu_enable_wakeups(u32 wakeups)
943{
944 unsigned long flags;
945 u32 bits;
946 int i;
947
948 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
949
950 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
951 if (wakeups & BIT(i))
952 bits |= prcmu_wakeup_bit[i];
953 }
954
955 spin_lock_irqsave(&mb0_transfer.lock, flags);
956
957 mb0_transfer.req.dbb_wakeups = bits;
958 config_wakeups();
959
960 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
961}
962
963void db8500_prcmu_config_abb_event_readout(u32 abb_events)
964{
965 unsigned long flags;
966
967 spin_lock_irqsave(&mb0_transfer.lock, flags);
968
969 mb0_transfer.req.abb_events = abb_events;
970 config_wakeups();
971
972 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
973}
974
975void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
976{
977 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
978 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
979 else
980 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
981}
982
983/**
984 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
985 * @opp: The new ARM operating point to which transition is to be made
986 * Returns: 0 on success, non-zero on failure
987 *
988 * This function sets the the operating point of the ARM.
989 */
990int db8500_prcmu_set_arm_opp(u8 opp)
991{
992 int r;
993
994 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
995 return -EINVAL;
996
997 r = 0;
998
999 mutex_lock(&mb1_transfer.lock);
1000
1001 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1002 cpu_relax();
1003
1004 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1005 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1006 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1007
1008 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1009 wait_for_completion(&mb1_transfer.work);
1010
1011 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1012 (mb1_transfer.ack.arm_opp != opp))
1013 r = -EIO;
1014
1015 mutex_unlock(&mb1_transfer.lock);
1016
1017 return r;
1018}
1019
1020/**
1021 * db8500_prcmu_get_arm_opp - get the current ARM OPP
1022 *
1023 * Returns: the current ARM OPP
1024 */
1025int db8500_prcmu_get_arm_opp(void)
1026{
1027 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1028}
1029
1030/**
1031 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1032 *
1033 * Returns: the current DDR OPP
1034 */
1035int db8500_prcmu_get_ddr_opp(void)
1036{
1037 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1038}
1039
1040/**
1041 * db8500_set_ddr_opp - set the appropriate DDR OPP
1042 * @opp: The new DDR operating point to which transition is to be made
1043 * Returns: 0 on success, non-zero on failure
1044 *
1045 * This function sets the operating point of the DDR.
1046 */
1047int db8500_prcmu_set_ddr_opp(u8 opp)
1048{
1049 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1050 return -EINVAL;
1051 /* Changing the DDR OPP can hang the hardware pre-v21 */
1052 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1053 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1054
1055 return 0;
1056}
1057
1058/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1059static void request_even_slower_clocks(bool enable)
1060{
1061 void __iomem *clock_reg[] = {
1062 PRCM_ACLK_MGT,
1063 PRCM_DMACLK_MGT
1064 };
1065 unsigned long flags;
1066 unsigned int i;
1067
1068 spin_lock_irqsave(&clk_mgt_lock, flags);
1069
1070 /* Grab the HW semaphore. */
1071 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1072 cpu_relax();
1073
1074 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1075 u32 val;
1076 u32 div;
1077
1078 val = readl(clock_reg[i]);
1079 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1080 if (enable) {
1081 if ((div <= 1) || (div > 15)) {
1082 pr_err("prcmu: Bad clock divider %d in %s\n",
1083 div, __func__);
1084 goto unlock_and_return;
1085 }
1086 div <<= 1;
1087 } else {
1088 if (div <= 2)
1089 goto unlock_and_return;
1090 div >>= 1;
1091 }
1092 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1093 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1094 writel(val, clock_reg[i]);
1095 }
1096
1097unlock_and_return:
1098 /* Release the HW semaphore. */
1099 writel(0, PRCM_SEM);
1100
1101 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1102}
1103
1104/**
1105 * db8500_set_ape_opp - set the appropriate APE OPP
1106 * @opp: The new APE operating point to which transition is to be made
1107 * Returns: 0 on success, non-zero on failure
1108 *
1109 * This function sets the operating point of the APE.
1110 */
1111int db8500_prcmu_set_ape_opp(u8 opp)
1112{
1113 int r = 0;
1114
1115 if (opp == mb1_transfer.ape_opp)
1116 return 0;
1117
1118 mutex_lock(&mb1_transfer.lock);
1119
1120 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1121 request_even_slower_clocks(false);
1122
1123 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1124 goto skip_message;
1125
1126 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1127 cpu_relax();
1128
1129 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1130 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1131 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1132 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1133
1134 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1135 wait_for_completion(&mb1_transfer.work);
1136
1137 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1138 (mb1_transfer.ack.ape_opp != opp))
1139 r = -EIO;
1140
1141skip_message:
1142 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1143 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1144 request_even_slower_clocks(true);
1145 if (!r)
1146 mb1_transfer.ape_opp = opp;
1147
1148 mutex_unlock(&mb1_transfer.lock);
1149
1150 return r;
1151}
1152
1153/**
1154 * db8500_prcmu_get_ape_opp - get the current APE OPP
1155 *
1156 * Returns: the current APE OPP
1157 */
1158int db8500_prcmu_get_ape_opp(void)
1159{
1160 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1161}
1162
1163/**
1164 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1165 * @enable: true to request the higher voltage, false to drop a request.
1166 *
1167 * Calls to this function to enable and disable requests must be balanced.
1168 */
1169int prcmu_request_ape_opp_100_voltage(bool enable)
1170{
1171 int r = 0;
1172 u8 header;
1173 static unsigned int requests;
1174
1175 mutex_lock(&mb1_transfer.lock);
1176
1177 if (enable) {
1178 if (0 != requests++)
1179 goto unlock_and_return;
1180 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1181 } else {
1182 if (requests == 0) {
1183 r = -EIO;
1184 goto unlock_and_return;
1185 } else if (1 != requests--) {
1186 goto unlock_and_return;
1187 }
1188 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1189 }
1190
1191 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1192 cpu_relax();
1193
1194 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1195
1196 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1197 wait_for_completion(&mb1_transfer.work);
1198
1199 if ((mb1_transfer.ack.header != header) ||
1200 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1201 r = -EIO;
1202
1203unlock_and_return:
1204 mutex_unlock(&mb1_transfer.lock);
1205
1206 return r;
1207}
1208
1209/**
1210 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1211 *
1212 * This function releases the power state requirements of a USB wakeup.
1213 */
1214int prcmu_release_usb_wakeup_state(void)
1215{
1216 int r = 0;
1217
1218 mutex_lock(&mb1_transfer.lock);
1219
1220 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1221 cpu_relax();
1222
1223 writeb(MB1H_RELEASE_USB_WAKEUP,
1224 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1225
1226 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1227 wait_for_completion(&mb1_transfer.work);
1228
1229 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1230 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1231 r = -EIO;
1232
1233 mutex_unlock(&mb1_transfer.lock);
1234
1235 return r;
1236}
1237
1238static int request_pll(u8 clock, bool enable)
1239{
1240 int r = 0;
1241
1242 if (clock == PRCMU_PLLSOC0)
1243 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1244 else if (clock == PRCMU_PLLSOC1)
1245 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1246 else
1247 return -EINVAL;
1248
1249 mutex_lock(&mb1_transfer.lock);
1250
1251 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1252 cpu_relax();
1253
1254 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1255 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1256
1257 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1258 wait_for_completion(&mb1_transfer.work);
1259
1260 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1261 r = -EIO;
1262
1263 mutex_unlock(&mb1_transfer.lock);
1264
1265 return r;
1266}
1267
1268/**
1269 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1270 * @epod_id: The EPOD to set
1271 * @epod_state: The new EPOD state
1272 *
1273 * This function sets the state of a EPOD (power domain). It may not be called
1274 * from interrupt context.
1275 */
1276int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1277{
1278 int r = 0;
1279 bool ram_retention = false;
1280 int i;
1281
1282 /* check argument */
1283 BUG_ON(epod_id >= NUM_EPOD_ID);
1284
1285 /* set flag if retention is possible */
1286 switch (epod_id) {
1287 case EPOD_ID_SVAMMDSP:
1288 case EPOD_ID_SIAMMDSP:
1289 case EPOD_ID_ESRAM12:
1290 case EPOD_ID_ESRAM34:
1291 ram_retention = true;
1292 break;
1293 }
1294
1295 /* check argument */
1296 BUG_ON(epod_state > EPOD_STATE_ON);
1297 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1298
1299 /* get lock */
1300 mutex_lock(&mb2_transfer.lock);
1301
1302 /* wait for mailbox */
1303 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1304 cpu_relax();
1305
1306 /* fill in mailbox */
1307 for (i = 0; i < NUM_EPOD_ID; i++)
1308 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1309 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1310
1311 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1312
1313 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1314
1315 /*
1316 * The current firmware version does not handle errors correctly,
1317 * and we cannot recover if there is an error.
1318 * This is expected to change when the firmware is updated.
1319 */
1320 if (!wait_for_completion_timeout(&mb2_transfer.work,
1321 msecs_to_jiffies(20000))) {
1322 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1323 __func__);
1324 r = -EIO;
1325 goto unlock_and_return;
1326 }
1327
1328 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1329 r = -EIO;
1330
1331unlock_and_return:
1332 mutex_unlock(&mb2_transfer.lock);
1333 return r;
1334}
1335
1336/**
1337 * prcmu_configure_auto_pm - Configure autonomous power management.
1338 * @sleep: Configuration for ApSleep.
1339 * @idle: Configuration for ApIdle.
1340 */
1341void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1342 struct prcmu_auto_pm_config *idle)
1343{
1344 u32 sleep_cfg;
1345 u32 idle_cfg;
1346 unsigned long flags;
1347
1348 BUG_ON((sleep == NULL) || (idle == NULL));
1349
1350 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1351 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1352 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1353 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1354 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1355 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1356
1357 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1358 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1359 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1360 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1361 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1362 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1363
1364 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1365
1366 /*
1367 * The autonomous power management configuration is done through
1368 * fields in mailbox 2, but these fields are only used as shared
1369 * variables - i.e. there is no need to send a message.
1370 */
1371 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1372 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1373
1374 mb2_transfer.auto_pm_enabled =
1375 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1376 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1377 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1378 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1379
1380 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1381}
1382EXPORT_SYMBOL(prcmu_configure_auto_pm);
1383
1384bool prcmu_is_auto_pm_enabled(void)
1385{
1386 return mb2_transfer.auto_pm_enabled;
1387}
1388
1389static int request_sysclk(bool enable)
1390{
1391 int r;
1392 unsigned long flags;
1393
1394 r = 0;
1395
1396 mutex_lock(&mb3_transfer.sysclk_lock);
1397
1398 spin_lock_irqsave(&mb3_transfer.lock, flags);
1399
1400 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1401 cpu_relax();
1402
1403 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1404
1405 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1406 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1407
1408 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1409
1410 /*
1411 * The firmware only sends an ACK if we want to enable the
1412 * SysClk, and it succeeds.
1413 */
1414 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1415 msecs_to_jiffies(20000))) {
1416 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1417 __func__);
1418 r = -EIO;
1419 }
1420
1421 mutex_unlock(&mb3_transfer.sysclk_lock);
1422
1423 return r;
1424}
1425
1426static int request_timclk(bool enable)
1427{
1428 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1429
1430 if (!enable)
1431 val |= PRCM_TCR_STOP_TIMERS;
1432 writel(val, PRCM_TCR);
1433
1434 return 0;
1435}
1436
1437static int request_clock(u8 clock, bool enable)
1438{
1439 u32 val;
1440 unsigned long flags;
1441
1442 spin_lock_irqsave(&clk_mgt_lock, flags);
1443
1444 /* Grab the HW semaphore. */
1445 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1446 cpu_relax();
1447
1448 val = readl(clk_mgt[clock].reg);
1449 if (enable) {
1450 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1451 } else {
1452 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1453 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1454 }
1455 writel(val, clk_mgt[clock].reg);
1456
1457 /* Release the HW semaphore. */
1458 writel(0, PRCM_SEM);
1459
1460 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1461
1462 return 0;
1463}
1464
1465static int request_sga_clock(u8 clock, bool enable)
1466{
1467 u32 val;
1468 int ret;
1469
1470 if (enable) {
1471 val = readl(PRCM_CGATING_BYPASS);
1472 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1473 }
1474
1475 ret = request_clock(clock, enable);
1476
1477 if (!ret && !enable) {
1478 val = readl(PRCM_CGATING_BYPASS);
1479 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1480 }
1481
1482 return ret;
1483}
1484
1485static inline bool plldsi_locked(void)
1486{
1487 return (readl(PRCM_PLLDSI_LOCKP) &
1488 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1489 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1490 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1491 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1492}
1493
1494static int request_plldsi(bool enable)
1495{
1496 int r = 0;
1497 u32 val;
1498
1499 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1500 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1501 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1502
1503 val = readl(PRCM_PLLDSI_ENABLE);
1504 if (enable)
1505 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1506 else
1507 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1508 writel(val, PRCM_PLLDSI_ENABLE);
1509
1510 if (enable) {
1511 unsigned int i;
1512 bool locked = plldsi_locked();
1513
1514 for (i = 10; !locked && (i > 0); --i) {
1515 udelay(100);
1516 locked = plldsi_locked();
1517 }
1518 if (locked) {
1519 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1520 PRCM_APE_RESETN_SET);
1521 } else {
1522 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1523 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1524 PRCM_MMIP_LS_CLAMP_SET);
1525 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1526 writel(val, PRCM_PLLDSI_ENABLE);
1527 r = -EAGAIN;
1528 }
1529 } else {
1530 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1531 }
1532 return r;
1533}
1534
1535static int request_dsiclk(u8 n, bool enable)
1536{
1537 u32 val;
1538
1539 val = readl(PRCM_DSI_PLLOUT_SEL);
1540 val &= ~dsiclk[n].divsel_mask;
1541 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1542 dsiclk[n].divsel_shift);
1543 writel(val, PRCM_DSI_PLLOUT_SEL);
1544 return 0;
1545}
1546
1547static int request_dsiescclk(u8 n, bool enable)
1548{
1549 u32 val;
1550
1551 val = readl(PRCM_DSITVCLK_DIV);
1552 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1553 writel(val, PRCM_DSITVCLK_DIV);
1554 return 0;
1555}
1556
1557/**
1558 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1559 * @clock: The clock for which the request is made.
1560 * @enable: Whether the clock should be enabled (true) or disabled (false).
1561 *
1562 * This function should only be used by the clock implementation.
1563 * Do not use it from any other place!
1564 */
1565int db8500_prcmu_request_clock(u8 clock, bool enable)
1566{
1567 if (clock == PRCMU_SGACLK)
1568 return request_sga_clock(clock, enable);
1569 else if (clock < PRCMU_NUM_REG_CLOCKS)
1570 return request_clock(clock, enable);
1571 else if (clock == PRCMU_TIMCLK)
1572 return request_timclk(enable);
1573 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1574 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1575 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1576 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1577 else if (clock == PRCMU_PLLDSI)
1578 return request_plldsi(enable);
1579 else if (clock == PRCMU_SYSCLK)
1580 return request_sysclk(enable);
1581 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1582 return request_pll(clock, enable);
1583 else
1584 return -EINVAL;
1585}
1586
1587static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1588 int branch)
1589{
1590 u64 rate;
1591 u32 val;
1592 u32 d;
1593 u32 div = 1;
1594
1595 val = readl(reg);
1596
1597 rate = src_rate;
1598 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1599
1600 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1601 if (d > 1)
1602 div *= d;
1603
1604 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1605 if (d > 1)
1606 div *= d;
1607
1608 if (val & PRCM_PLL_FREQ_SELDIV2)
1609 div *= 2;
1610
1611 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1612 (val & PRCM_PLL_FREQ_DIV2EN) &&
1613 ((reg == PRCM_PLLSOC0_FREQ) ||
1614 (reg == PRCM_PLLDDR_FREQ))))
1615 div *= 2;
1616
1617 (void)do_div(rate, div);
1618
1619 return (unsigned long)rate;
1620}
1621
1622#define ROOT_CLOCK_RATE 38400000
1623
1624static unsigned long clock_rate(u8 clock)
1625{
1626 u32 val;
1627 u32 pllsw;
1628 unsigned long rate = ROOT_CLOCK_RATE;
1629
1630 val = readl(clk_mgt[clock].reg);
1631
1632 if (val & PRCM_CLK_MGT_CLK38) {
1633 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1634 rate /= 2;
1635 return rate;
1636 }
1637
1638 val |= clk_mgt[clock].pllsw;
1639 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1640
1641 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1642 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1643 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1644 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1645 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1646 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1647 else
1648 return 0;
1649
1650 if ((clock == PRCMU_SGACLK) &&
1651 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1652 u64 r = (rate * 10);
1653
1654 (void)do_div(r, 25);
1655 return (unsigned long)r;
1656 }
1657 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1658 if (val)
1659 return rate / val;
1660 else
1661 return 0;
1662}
1663
1664static unsigned long dsiclk_rate(u8 n)
1665{
1666 u32 divsel;
1667 u32 div = 1;
1668
1669 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1670 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1671
1672 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1673 divsel = dsiclk[n].divsel;
1674
1675 switch (divsel) {
1676 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1677 div *= 2;
1678 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1679 div *= 2;
1680 case PRCM_DSI_PLLOUT_SEL_PHI:
1681 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1682 PLL_RAW) / div;
1683 default:
1684 return 0;
1685 }
1686}
1687
1688static unsigned long dsiescclk_rate(u8 n)
1689{
1690 u32 div;
1691
1692 div = readl(PRCM_DSITVCLK_DIV);
1693 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1694 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1695}
1696
1697unsigned long prcmu_clock_rate(u8 clock)
1698{
1699 if (clock < PRCMU_NUM_REG_CLOCKS)
1700 return clock_rate(clock);
1701 else if (clock == PRCMU_TIMCLK)
1702 return ROOT_CLOCK_RATE / 16;
1703 else if (clock == PRCMU_SYSCLK)
1704 return ROOT_CLOCK_RATE;
1705 else if (clock == PRCMU_PLLSOC0)
1706 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1707 else if (clock == PRCMU_PLLSOC1)
1708 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1709 else if (clock == PRCMU_PLLDDR)
1710 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1711 else if (clock == PRCMU_PLLDSI)
1712 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1713 PLL_RAW);
1714 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1715 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1716 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1717 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1718 else
1719 return 0;
1720}
1721
1722static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1723{
1724 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1725 return ROOT_CLOCK_RATE;
1726 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1727 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1728 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1729 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1730 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1731 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1732 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1733 else
1734 return 0;
1735}
1736
1737static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1738{
1739 u32 div;
1740
1741 div = (src_rate / rate);
1742 if (div == 0)
1743 return 1;
1744 if (rate < (src_rate / div))
1745 div++;
1746 return div;
1747}
1748
1749static long round_clock_rate(u8 clock, unsigned long rate)
1750{
1751 u32 val;
1752 u32 div;
1753 unsigned long src_rate;
1754 long rounded_rate;
1755
1756 val = readl(clk_mgt[clock].reg);
1757 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1758 clk_mgt[clock].branch);
1759 div = clock_divider(src_rate, rate);
1760 if (val & PRCM_CLK_MGT_CLK38) {
1761 if (clk_mgt[clock].clk38div) {
1762 if (div > 2)
1763 div = 2;
1764 } else {
1765 div = 1;
1766 }
1767 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1768 u64 r = (src_rate * 10);
1769
1770 (void)do_div(r, 25);
1771 if (r <= rate)
1772 return (unsigned long)r;
1773 }
1774 rounded_rate = (src_rate / min(div, (u32)31));
1775
1776 return rounded_rate;
1777}
1778
1779#define MIN_PLL_VCO_RATE 600000000ULL
1780#define MAX_PLL_VCO_RATE 1680640000ULL
1781
1782static long round_plldsi_rate(unsigned long rate)
1783{
1784 long rounded_rate = 0;
1785 unsigned long src_rate;
1786 unsigned long rem;
1787 u32 r;
1788
1789 src_rate = clock_rate(PRCMU_HDMICLK);
1790 rem = rate;
1791
1792 for (r = 7; (rem > 0) && (r > 0); r--) {
1793 u64 d;
1794
1795 d = (r * rate);
1796 (void)do_div(d, src_rate);
1797 if (d < 6)
1798 d = 6;
1799 else if (d > 255)
1800 d = 255;
1801 d *= src_rate;
1802 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1803 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1804 continue;
1805 (void)do_div(d, r);
1806 if (rate < d) {
1807 if (rounded_rate == 0)
1808 rounded_rate = (long)d;
1809 break;
1810 }
1811 if ((rate - d) < rem) {
1812 rem = (rate - d);
1813 rounded_rate = (long)d;
1814 }
1815 }
1816 return rounded_rate;
1817}
1818
1819static long round_dsiclk_rate(unsigned long rate)
1820{
1821 u32 div;
1822 unsigned long src_rate;
1823 long rounded_rate;
1824
1825 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1826 PLL_RAW);
1827 div = clock_divider(src_rate, rate);
1828 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1829
1830 return rounded_rate;
1831}
1832
1833static long round_dsiescclk_rate(unsigned long rate)
1834{
1835 u32 div;
1836 unsigned long src_rate;
1837 long rounded_rate;
1838
1839 src_rate = clock_rate(PRCMU_TVCLK);
1840 div = clock_divider(src_rate, rate);
1841 rounded_rate = (src_rate / min(div, (u32)255));
1842
1843 return rounded_rate;
1844}
1845
1846long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1847{
1848 if (clock < PRCMU_NUM_REG_CLOCKS)
1849 return round_clock_rate(clock, rate);
1850 else if (clock == PRCMU_PLLDSI)
1851 return round_plldsi_rate(rate);
1852 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1853 return round_dsiclk_rate(rate);
1854 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1855 return round_dsiescclk_rate(rate);
1856 else
1857 return (long)prcmu_clock_rate(clock);
1858}
1859
1860static void set_clock_rate(u8 clock, unsigned long rate)
1861{
1862 u32 val;
1863 u32 div;
1864 unsigned long src_rate;
1865 unsigned long flags;
1866
1867 spin_lock_irqsave(&clk_mgt_lock, flags);
1868
1869 /* Grab the HW semaphore. */
1870 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1871 cpu_relax();
1872
1873 val = readl(clk_mgt[clock].reg);
1874 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1875 clk_mgt[clock].branch);
1876 div = clock_divider(src_rate, rate);
1877 if (val & PRCM_CLK_MGT_CLK38) {
1878 if (clk_mgt[clock].clk38div) {
1879 if (div > 1)
1880 val |= PRCM_CLK_MGT_CLK38DIV;
1881 else
1882 val &= ~PRCM_CLK_MGT_CLK38DIV;
1883 }
1884 } else if (clock == PRCMU_SGACLK) {
1885 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1886 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1887 if (div == 3) {
1888 u64 r = (src_rate * 10);
1889
1890 (void)do_div(r, 25);
1891 if (r <= rate) {
1892 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1893 div = 0;
1894 }
1895 }
1896 val |= min(div, (u32)31);
1897 } else {
1898 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1899 val |= min(div, (u32)31);
1900 }
1901 writel(val, clk_mgt[clock].reg);
1902
1903 /* Release the HW semaphore. */
1904 writel(0, PRCM_SEM);
1905
1906 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1907}
1908
1909static int set_plldsi_rate(unsigned long rate)
1910{
1911 unsigned long src_rate;
1912 unsigned long rem;
1913 u32 pll_freq = 0;
1914 u32 r;
1915
1916 src_rate = clock_rate(PRCMU_HDMICLK);
1917 rem = rate;
1918
1919 for (r = 7; (rem > 0) && (r > 0); r--) {
1920 u64 d;
1921 u64 hwrate;
1922
1923 d = (r * rate);
1924 (void)do_div(d, src_rate);
1925 if (d < 6)
1926 d = 6;
1927 else if (d > 255)
1928 d = 255;
1929 hwrate = (d * src_rate);
1930 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1931 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1932 continue;
1933 (void)do_div(hwrate, r);
1934 if (rate < hwrate) {
1935 if (pll_freq == 0)
1936 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1937 (r << PRCM_PLL_FREQ_R_SHIFT));
1938 break;
1939 }
1940 if ((rate - hwrate) < rem) {
1941 rem = (rate - hwrate);
1942 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1943 (r << PRCM_PLL_FREQ_R_SHIFT));
1944 }
1945 }
1946 if (pll_freq == 0)
1947 return -EINVAL;
1948
1949 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1950 writel(pll_freq, PRCM_PLLDSI_FREQ);
1951
1952 return 0;
1953}
1954
1955static void set_dsiclk_rate(u8 n, unsigned long rate)
1956{
1957 u32 val;
1958 u32 div;
1959
1960 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1961 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1962
1963 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1964 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1965 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1966
1967 val = readl(PRCM_DSI_PLLOUT_SEL);
1968 val &= ~dsiclk[n].divsel_mask;
1969 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1970 writel(val, PRCM_DSI_PLLOUT_SEL);
1971}
1972
1973static void set_dsiescclk_rate(u8 n, unsigned long rate)
1974{
1975 u32 val;
1976 u32 div;
1977
1978 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1979 val = readl(PRCM_DSITVCLK_DIV);
1980 val &= ~dsiescclk[n].div_mask;
1981 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1982 writel(val, PRCM_DSITVCLK_DIV);
1983}
1984
1985int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1986{
1987 if (clock < PRCMU_NUM_REG_CLOCKS)
1988 set_clock_rate(clock, rate);
1989 else if (clock == PRCMU_PLLDSI)
1990 return set_plldsi_rate(rate);
1991 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1992 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1993 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1994 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1995 return 0;
1996}
1997
1998int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1999{
2000 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2001 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2002 return -EINVAL;
2003
2004 mutex_lock(&mb4_transfer.lock);
2005
2006 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2007 cpu_relax();
2008
2009 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2010 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2011 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2012 writeb(DDR_PWR_STATE_ON,
2013 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2014 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2015
2016 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2017 wait_for_completion(&mb4_transfer.work);
2018
2019 mutex_unlock(&mb4_transfer.lock);
2020
2021 return 0;
2022}
2023
2024int db8500_prcmu_config_hotdog(u8 threshold)
2025{
2026 mutex_lock(&mb4_transfer.lock);
2027
2028 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2029 cpu_relax();
2030
2031 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2032 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2033
2034 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2035 wait_for_completion(&mb4_transfer.work);
2036
2037 mutex_unlock(&mb4_transfer.lock);
2038
2039 return 0;
2040}
2041
2042int db8500_prcmu_config_hotmon(u8 low, u8 high)
2043{
2044 mutex_lock(&mb4_transfer.lock);
2045
2046 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2047 cpu_relax();
2048
2049 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2050 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2051 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2052 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2053 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2054
2055 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2056 wait_for_completion(&mb4_transfer.work);
2057
2058 mutex_unlock(&mb4_transfer.lock);
2059
2060 return 0;
2061}
2062
2063static int config_hot_period(u16 val)
2064{
2065 mutex_lock(&mb4_transfer.lock);
2066
2067 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2068 cpu_relax();
2069
2070 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2071 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2072
2073 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2074 wait_for_completion(&mb4_transfer.work);
2075
2076 mutex_unlock(&mb4_transfer.lock);
2077
2078 return 0;
2079}
2080
2081int db8500_prcmu_start_temp_sense(u16 cycles32k)
2082{
2083 if (cycles32k == 0xFFFF)
2084 return -EINVAL;
2085
2086 return config_hot_period(cycles32k);
2087}
2088
2089int db8500_prcmu_stop_temp_sense(void)
2090{
2091 return config_hot_period(0xFFFF);
2092}
2093
2094static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2095{
2096
2097 mutex_lock(&mb4_transfer.lock);
2098
2099 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2100 cpu_relax();
2101
2102 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2103 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2104 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2105 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2106
2107 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2108
2109 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2110 wait_for_completion(&mb4_transfer.work);
2111
2112 mutex_unlock(&mb4_transfer.lock);
2113
2114 return 0;
2115
2116}
2117
2118int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2119{
2120 BUG_ON(num == 0 || num > 0xf);
2121 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2122 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2123 A9WDOG_AUTO_OFF_DIS);
2124}
2125
2126int db8500_prcmu_enable_a9wdog(u8 id)
2127{
2128 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2129}
2130
2131int db8500_prcmu_disable_a9wdog(u8 id)
2132{
2133 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2134}
2135
2136int db8500_prcmu_kick_a9wdog(u8 id)
2137{
2138 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2139}
2140
2141/*
2142 * timeout is 28 bit, in ms.
2143 */
2144int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2145{
2146 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2147 (id & A9WDOG_ID_MASK) |
2148 /*
2149 * Put the lowest 28 bits of timeout at
2150 * offset 4. Four first bits are used for id.
2151 */
2152 (u8)((timeout << 4) & 0xf0),
2153 (u8)((timeout >> 4) & 0xff),
2154 (u8)((timeout >> 12) & 0xff),
2155 (u8)((timeout >> 20) & 0xff));
2156}
2157
2158/**
2159 * prcmu_abb_read() - Read register value(s) from the ABB.
2160 * @slave: The I2C slave address.
2161 * @reg: The (start) register address.
2162 * @value: The read out value(s).
2163 * @size: The number of registers to read.
2164 *
2165 * Reads register value(s) from the ABB.
2166 * @size has to be 1 for the current firmware version.
2167 */
2168int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2169{
2170 int r;
2171
2172 if (size != 1)
2173 return -EINVAL;
2174
2175 mutex_lock(&mb5_transfer.lock);
2176
2177 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2178 cpu_relax();
2179
2180 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2181 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2182 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2183 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2184 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2185
2186 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2187
2188 if (!wait_for_completion_timeout(&mb5_transfer.work,
2189 msecs_to_jiffies(20000))) {
2190 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2191 __func__);
2192 r = -EIO;
2193 } else {
2194 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2195 }
2196
2197 if (!r)
2198 *value = mb5_transfer.ack.value;
2199
2200 mutex_unlock(&mb5_transfer.lock);
2201
2202 return r;
2203}
2204
2205/**
2206 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2207 * @slave: The I2C slave address.
2208 * @reg: The (start) register address.
2209 * @value: The value(s) to write.
2210 * @mask: The mask(s) to use.
2211 * @size: The number of registers to write.
2212 *
2213 * Writes masked register value(s) to the ABB.
2214 * For each @value, only the bits set to 1 in the corresponding @mask
2215 * will be written. The other bits are not changed.
2216 * @size has to be 1 for the current firmware version.
2217 */
2218int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2219{
2220 int r;
2221
2222 if (size != 1)
2223 return -EINVAL;
2224
2225 mutex_lock(&mb5_transfer.lock);
2226
2227 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2228 cpu_relax();
2229
2230 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2231 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2232 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2233 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2234 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2235
2236 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2237
2238 if (!wait_for_completion_timeout(&mb5_transfer.work,
2239 msecs_to_jiffies(20000))) {
2240 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2241 __func__);
2242 r = -EIO;
2243 } else {
2244 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2245 }
2246
2247 mutex_unlock(&mb5_transfer.lock);
2248
2249 return r;
2250}
2251
2252/**
2253 * prcmu_abb_write() - Write register value(s) to the ABB.
2254 * @slave: The I2C slave address.
2255 * @reg: The (start) register address.
2256 * @value: The value(s) to write.
2257 * @size: The number of registers to write.
2258 *
2259 * Writes register value(s) to the ABB.
2260 * @size has to be 1 for the current firmware version.
2261 */
2262int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2263{
2264 u8 mask = ~0;
2265
2266 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2267}
2268
2269/**
2270 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2271 */
2272void prcmu_ac_wake_req(void)
2273{
2274 u32 val;
2275 u32 status;
2276
2277 mutex_lock(&mb0_transfer.ac_wake_lock);
2278
2279 val = readl(PRCM_HOSTACCESS_REQ);
2280 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2281 goto unlock_and_return;
2282
2283 atomic_set(&ac_wake_req_state, 1);
2284
2285retry:
2286 writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ);
2287
2288 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2289 msecs_to_jiffies(5000))) {
2290 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2291 __func__);
2292 goto unlock_and_return;
2293 }
2294
2295 /*
2296 * The modem can generate an AC_WAKE_ACK, and then still go to sleep.
2297 * As a workaround, we wait, and then check that the modem is indeed
2298 * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS
2299 * register, which may not be the whole truth).
2300 */
2301 udelay(400);
2302 status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2));
2303 if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE |
2304 PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) {
2305 pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n",
2306 __func__, status);
2307 udelay(1200);
2308 writel(val, PRCM_HOSTACCESS_REQ);
2309 if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2310 msecs_to_jiffies(5000)))
2311 goto retry;
2312 pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n",
2313 __func__);
2314 }
2315
2316unlock_and_return:
2317 mutex_unlock(&mb0_transfer.ac_wake_lock);
2318}
2319
2320/**
2321 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2322 */
2323void prcmu_ac_sleep_req()
2324{
2325 u32 val;
2326
2327 mutex_lock(&mb0_transfer.ac_wake_lock);
2328
2329 val = readl(PRCM_HOSTACCESS_REQ);
2330 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2331 goto unlock_and_return;
2332
2333 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2334 PRCM_HOSTACCESS_REQ);
2335
2336 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2337 msecs_to_jiffies(5000))) {
2338 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2339 __func__);
2340 }
2341
2342 atomic_set(&ac_wake_req_state, 0);
2343
2344unlock_and_return:
2345 mutex_unlock(&mb0_transfer.ac_wake_lock);
2346}
2347
2348bool db8500_prcmu_is_ac_wake_requested(void)
2349{
2350 return (atomic_read(&ac_wake_req_state) != 0);
2351}
2352
2353/**
2354 * db8500_prcmu_system_reset - System reset
2355 *
2356 * Saves the reset reason code and then sets the APE_SOFTRST register which
2357 * fires interrupt to fw
2358 */
2359void db8500_prcmu_system_reset(u16 reset_code)
2360{
2361 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2362 writel(1, PRCM_APE_SOFTRST);
2363}
2364
2365/**
2366 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2367 *
2368 * Retrieves the reset reason code stored by prcmu_system_reset() before
2369 * last restart.
2370 */
2371u16 db8500_prcmu_get_reset_code(void)
2372{
2373 return readw(tcdm_base + PRCM_SW_RST_REASON);
2374}
2375
2376/**
2377 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2378 */
2379void db8500_prcmu_modem_reset(void)
2380{
2381 mutex_lock(&mb1_transfer.lock);
2382
2383 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2384 cpu_relax();
2385
2386 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2387 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2388 wait_for_completion(&mb1_transfer.work);
2389
2390 /*
2391 * No need to check return from PRCMU as modem should go in reset state
2392 * This state is already managed by upper layer
2393 */
2394
2395 mutex_unlock(&mb1_transfer.lock);
2396}
2397
2398static void ack_dbb_wakeup(void)
2399{
2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&mb0_transfer.lock, flags);
2403
2404 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2405 cpu_relax();
2406
2407 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2408 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2409
2410 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2411}
2412
2413static inline void print_unknown_header_warning(u8 n, u8 header)
2414{
2415 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2416 header, n);
2417}
2418
2419static bool read_mailbox_0(void)
2420{
2421 bool r;
2422 u32 ev;
2423 unsigned int n;
2424 u8 header;
2425
2426 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2427 switch (header) {
2428 case MB0H_WAKEUP_EXE:
2429 case MB0H_WAKEUP_SLEEP:
2430 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2431 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2432 else
2433 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2434
2435 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2436 complete(&mb0_transfer.ac_wake_work);
2437 if (ev & WAKEUP_BIT_SYSCLK_OK)
2438 complete(&mb3_transfer.sysclk_work);
2439
2440 ev &= mb0_transfer.req.dbb_irqs;
2441
2442 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2443 if (ev & prcmu_irq_bit[n])
2444 generic_handle_irq(IRQ_PRCMU_BASE + n);
2445 }
2446 r = true;
2447 break;
2448 default:
2449 print_unknown_header_warning(0, header);
2450 r = false;
2451 break;
2452 }
2453 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2454 return r;
2455}
2456
2457static bool read_mailbox_1(void)
2458{
2459 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2460 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2461 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2462 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2463 PRCM_ACK_MB1_CURRENT_APE_OPP);
2464 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2465 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2466 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2467 complete(&mb1_transfer.work);
2468 return false;
2469}
2470
2471static bool read_mailbox_2(void)
2472{
2473 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2474 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2475 complete(&mb2_transfer.work);
2476 return false;
2477}
2478
2479static bool read_mailbox_3(void)
2480{
2481 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2482 return false;
2483}
2484
2485static bool read_mailbox_4(void)
2486{
2487 u8 header;
2488 bool do_complete = true;
2489
2490 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2491 switch (header) {
2492 case MB4H_MEM_ST:
2493 case MB4H_HOTDOG:
2494 case MB4H_HOTMON:
2495 case MB4H_HOT_PERIOD:
2496 case MB4H_A9WDOG_CONF:
2497 case MB4H_A9WDOG_EN:
2498 case MB4H_A9WDOG_DIS:
2499 case MB4H_A9WDOG_LOAD:
2500 case MB4H_A9WDOG_KICK:
2501 break;
2502 default:
2503 print_unknown_header_warning(4, header);
2504 do_complete = false;
2505 break;
2506 }
2507
2508 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2509
2510 if (do_complete)
2511 complete(&mb4_transfer.work);
2512
2513 return false;
2514}
2515
2516static bool read_mailbox_5(void)
2517{
2518 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2519 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2520 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2521 complete(&mb5_transfer.work);
2522 return false;
2523}
2524
2525static bool read_mailbox_6(void)
2526{
2527 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2528 return false;
2529}
2530
2531static bool read_mailbox_7(void)
2532{
2533 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2534 return false;
2535}
2536
2537static bool (* const read_mailbox[NUM_MB])(void) = {
2538 read_mailbox_0,
2539 read_mailbox_1,
2540 read_mailbox_2,
2541 read_mailbox_3,
2542 read_mailbox_4,
2543 read_mailbox_5,
2544 read_mailbox_6,
2545 read_mailbox_7
2546};
2547
2548static irqreturn_t prcmu_irq_handler(int irq, void *data)
2549{
2550 u32 bits;
2551 u8 n;
2552 irqreturn_t r;
2553
2554 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2555 if (unlikely(!bits))
2556 return IRQ_NONE;
2557
2558 r = IRQ_HANDLED;
2559 for (n = 0; bits; n++) {
2560 if (bits & MBOX_BIT(n)) {
2561 bits -= MBOX_BIT(n);
2562 if (read_mailbox[n]())
2563 r = IRQ_WAKE_THREAD;
2564 }
2565 }
2566 return r;
2567}
2568
2569static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2570{
2571 ack_dbb_wakeup();
2572 return IRQ_HANDLED;
2573}
2574
2575static void prcmu_mask_work(struct work_struct *work)
2576{
2577 unsigned long flags;
2578
2579 spin_lock_irqsave(&mb0_transfer.lock, flags);
2580
2581 config_wakeups();
2582
2583 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2584}
2585
2586static void prcmu_irq_mask(struct irq_data *d)
2587{
2588 unsigned long flags;
2589
2590 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2591
2592 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2593
2594 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2595
2596 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2597 schedule_work(&mb0_transfer.mask_work);
2598}
2599
2600static void prcmu_irq_unmask(struct irq_data *d)
2601{
2602 unsigned long flags;
2603
2604 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2605
2606 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
2607
2608 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2609
2610 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2611 schedule_work(&mb0_transfer.mask_work);
2612}
2613
2614static void noop(struct irq_data *d)
2615{
2616}
2617
2618static struct irq_chip prcmu_irq_chip = {
2619 .name = "prcmu",
2620 .irq_disable = prcmu_irq_mask,
2621 .irq_ack = noop,
2622 .irq_mask = prcmu_irq_mask,
2623 .irq_unmask = prcmu_irq_unmask,
2624};
2625
2626static char *fw_project_name(u8 project)
2627{
2628 switch (project) {
2629 case PRCMU_FW_PROJECT_U8500:
2630 return "U8500";
2631 case PRCMU_FW_PROJECT_U8500_C2:
2632 return "U8500 C2";
2633 case PRCMU_FW_PROJECT_U9500:
2634 return "U9500";
2635 case PRCMU_FW_PROJECT_U9500_C2:
2636 return "U9500 C2";
2637 case PRCMU_FW_PROJECT_U8520:
2638 return "U8520";
2639 case PRCMU_FW_PROJECT_U8420:
2640 return "U8420";
2641 default:
2642 return "Unknown";
2643 }
2644}
2645
2646void __init db8500_prcmu_early_init(void)
2647{
2648 unsigned int i;
2649 if (cpu_is_u8500v2()) {
2650 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2651
2652 if (tcpm_base != NULL) {
2653 u32 version;
2654 version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
2655 fw_info.version.project = version & 0xFF;
2656 fw_info.version.api_version = (version >> 8) & 0xFF;
2657 fw_info.version.func_version = (version >> 16) & 0xFF;
2658 fw_info.version.errata = (version >> 24) & 0xFF;
2659 fw_info.valid = true;
2660 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2661 fw_project_name(fw_info.version.project),
2662 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2663 (version >> 24) & 0xFF);
2664 iounmap(tcpm_base);
2665 }
2666
2667 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2668 } else {
2669 pr_err("prcmu: Unsupported chip version\n");
2670 BUG();
2671 }
2672
2673 spin_lock_init(&mb0_transfer.lock);
2674 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2675 mutex_init(&mb0_transfer.ac_wake_lock);
2676 init_completion(&mb0_transfer.ac_wake_work);
2677 mutex_init(&mb1_transfer.lock);
2678 init_completion(&mb1_transfer.work);
2679 mb1_transfer.ape_opp = APE_NO_CHANGE;
2680 mutex_init(&mb2_transfer.lock);
2681 init_completion(&mb2_transfer.work);
2682 spin_lock_init(&mb2_transfer.auto_pm_lock);
2683 spin_lock_init(&mb3_transfer.lock);
2684 mutex_init(&mb3_transfer.sysclk_lock);
2685 init_completion(&mb3_transfer.sysclk_work);
2686 mutex_init(&mb4_transfer.lock);
2687 init_completion(&mb4_transfer.work);
2688 mutex_init(&mb5_transfer.lock);
2689 init_completion(&mb5_transfer.work);
2690
2691 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2692
2693 /* Initalize irqs. */
2694 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
2695 unsigned int irq;
2696
2697 irq = IRQ_PRCMU_BASE + i;
2698 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
2699 handle_simple_irq);
2700 set_irq_flags(irq, IRQF_VALID);
2701 }
2702}
2703
2704static void __init init_prcm_registers(void)
2705{
2706 u32 val;
2707
2708 val = readl(PRCM_A9PL_FORCE_CLKEN);
2709 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2710 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2711 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2712}
2713
2714/*
2715 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2716 */
2717static struct regulator_consumer_supply db8500_vape_consumers[] = {
2718 REGULATOR_SUPPLY("v-ape", NULL),
2719 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2720 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2721 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2722 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2723 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2724 /* "v-mmc" changed to "vcore" in the mainline kernel */
2725 REGULATOR_SUPPLY("vcore", "sdi0"),
2726 REGULATOR_SUPPLY("vcore", "sdi1"),
2727 REGULATOR_SUPPLY("vcore", "sdi2"),
2728 REGULATOR_SUPPLY("vcore", "sdi3"),
2729 REGULATOR_SUPPLY("vcore", "sdi4"),
2730 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2731 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2732 /* "v-uart" changed to "vcore" in the mainline kernel */
2733 REGULATOR_SUPPLY("vcore", "uart0"),
2734 REGULATOR_SUPPLY("vcore", "uart1"),
2735 REGULATOR_SUPPLY("vcore", "uart2"),
2736 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2737 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2738 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2739};
2740
2741static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2742 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2743 /* AV8100 regulator */
2744 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2745};
2746
2747static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2748 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2749 REGULATOR_SUPPLY("vsupply", "mcde"),
2750};
2751
2752/* SVA MMDSP regulator switch */
2753static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2754 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2755};
2756
2757/* SVA pipe regulator switch */
2758static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2759 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2760};
2761
2762/* SIA MMDSP regulator switch */
2763static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2764 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2765};
2766
2767/* SIA pipe regulator switch */
2768static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2769 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2770};
2771
2772static struct regulator_consumer_supply db8500_sga_consumers[] = {
2773 REGULATOR_SUPPLY("v-mali", NULL),
2774};
2775
2776/* ESRAM1 and 2 regulator switch */
2777static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2778 REGULATOR_SUPPLY("esram12", "cm_control"),
2779};
2780
2781/* ESRAM3 and 4 regulator switch */
2782static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2783 REGULATOR_SUPPLY("v-esram34", "mcde"),
2784 REGULATOR_SUPPLY("esram34", "cm_control"),
2785 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2786};
2787
2788static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2789 [DB8500_REGULATOR_VAPE] = {
2790 .constraints = {
2791 .name = "db8500-vape",
2792 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2793 .always_on = true,
2794 },
2795 .consumer_supplies = db8500_vape_consumers,
2796 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2797 },
2798 [DB8500_REGULATOR_VARM] = {
2799 .constraints = {
2800 .name = "db8500-varm",
2801 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2802 },
2803 },
2804 [DB8500_REGULATOR_VMODEM] = {
2805 .constraints = {
2806 .name = "db8500-vmodem",
2807 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2808 },
2809 },
2810 [DB8500_REGULATOR_VPLL] = {
2811 .constraints = {
2812 .name = "db8500-vpll",
2813 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2814 },
2815 },
2816 [DB8500_REGULATOR_VSMPS1] = {
2817 .constraints = {
2818 .name = "db8500-vsmps1",
2819 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2820 },
2821 },
2822 [DB8500_REGULATOR_VSMPS2] = {
2823 .constraints = {
2824 .name = "db8500-vsmps2",
2825 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2826 },
2827 .consumer_supplies = db8500_vsmps2_consumers,
2828 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2829 },
2830 [DB8500_REGULATOR_VSMPS3] = {
2831 .constraints = {
2832 .name = "db8500-vsmps3",
2833 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2834 },
2835 },
2836 [DB8500_REGULATOR_VRF1] = {
2837 .constraints = {
2838 .name = "db8500-vrf1",
2839 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2840 },
2841 },
2842 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2843 /* dependency to u8500-vape is handled outside regulator framework */
2844 .constraints = {
2845 .name = "db8500-sva-mmdsp",
2846 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2847 },
2848 .consumer_supplies = db8500_svammdsp_consumers,
2849 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2850 },
2851 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2852 .constraints = {
2853 /* "ret" means "retention" */
2854 .name = "db8500-sva-mmdsp-ret",
2855 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2856 },
2857 },
2858 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2859 /* dependency to u8500-vape is handled outside regulator framework */
2860 .constraints = {
2861 .name = "db8500-sva-pipe",
2862 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2863 },
2864 .consumer_supplies = db8500_svapipe_consumers,
2865 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2866 },
2867 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2868 /* dependency to u8500-vape is handled outside regulator framework */
2869 .constraints = {
2870 .name = "db8500-sia-mmdsp",
2871 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2872 },
2873 .consumer_supplies = db8500_siammdsp_consumers,
2874 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2875 },
2876 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2877 .constraints = {
2878 .name = "db8500-sia-mmdsp-ret",
2879 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2880 },
2881 },
2882 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2883 /* dependency to u8500-vape is handled outside regulator framework */
2884 .constraints = {
2885 .name = "db8500-sia-pipe",
2886 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2887 },
2888 .consumer_supplies = db8500_siapipe_consumers,
2889 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2890 },
2891 [DB8500_REGULATOR_SWITCH_SGA] = {
2892 .supply_regulator = "db8500-vape",
2893 .constraints = {
2894 .name = "db8500-sga",
2895 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2896 },
2897 .consumer_supplies = db8500_sga_consumers,
2898 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2899
2900 },
2901 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2902 .supply_regulator = "db8500-vape",
2903 .constraints = {
2904 .name = "db8500-b2r2-mcde",
2905 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2906 },
2907 .consumer_supplies = db8500_b2r2_mcde_consumers,
2908 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2909 },
2910 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2911 /*
2912 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2913 * no need to hold Vape
2914 */
2915 .constraints = {
2916 .name = "db8500-esram12",
2917 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2918 },
2919 .consumer_supplies = db8500_esram12_consumers,
2920 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2921 },
2922 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2923 .constraints = {
2924 .name = "db8500-esram12-ret",
2925 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2926 },
2927 },
2928 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2929 /*
2930 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2931 * no need to hold Vape
2932 */
2933 .constraints = {
2934 .name = "db8500-esram34",
2935 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936 },
2937 .consumer_supplies = db8500_esram34_consumers,
2938 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
2939 },
2940 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2941 .constraints = {
2942 .name = "db8500-esram34-ret",
2943 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2944 },
2945 },
2946};
2947
2948static struct mfd_cell db8500_prcmu_devs[] = {
2949 {
2950 .name = "db8500-prcmu-regulators",
2951 .platform_data = &db8500_regulators,
2952 .pdata_size = sizeof(db8500_regulators),
2953 },
2954 {
2955 .name = "cpufreq-u8500",
2956 },
2957};
2958
2959/**
2960 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
2961 *
2962 */
2963static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
2964{
2965 struct device_node *np = pdev->dev.of_node;
2966 int irq = 0, err = 0;
2967
2968 if (ux500_is_svp())
2969 return -ENODEV;
2970
2971 init_prcm_registers();
2972
2973 /* Clean up the mailbox interrupts after pre-kernel code. */
2974 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
2975
2976 if (np)
2977 irq = platform_get_irq(pdev, 0);
2978
2979 if (!np || irq <= 0)
2980 irq = IRQ_DB8500_PRCMU1;
2981
2982 err = request_threaded_irq(irq, prcmu_irq_handler,
2983 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
2984 if (err < 0) {
2985 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
2986 err = -EBUSY;
2987 goto no_irq_return;
2988 }
2989
2990 if (cpu_is_u8500v20_or_later())
2991 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
2992
2993 if (!np) {
2994 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
2995 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0);
2996 if (err) {
2997 pr_err("prcmu: Failed to add subdevices\n");
2998 return err;
2999 }
3000 }
3001
3002 pr_info("DB8500 PRCMU initialized\n");
3003
3004no_irq_return:
3005 return err;
3006}
3007
3008static struct platform_driver db8500_prcmu_driver = {
3009 .driver = {
3010 .name = "db8500-prcmu",
3011 .owner = THIS_MODULE,
3012 },
3013 .probe = db8500_prcmu_probe,
3014};
3015
3016static int __init db8500_prcmu_init(void)
3017{
3018 return platform_driver_register(&db8500_prcmu_driver);
3019}
3020
3021arch_initcall(db8500_prcmu_init);
3022
3023MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3024MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3025MODULE_LICENSE("GPL v2");