Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * offload engine driver for the Intel Xscale series of i/o processors
4 * Copyright © 2006, Intel Corporation.
5 */
6
7/*
8 * This driver supports the asynchrounous DMA copy and RAID engines available
9 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/prefetch.h>
20#include <linux/memory.h>
21#include <linux/ioport.h>
22#include <linux/raid/pq.h>
23#include <linux/slab.h>
24
25#include "iop-adma.h"
26#include "dmaengine.h"
27
28#define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
29#define to_iop_adma_device(dev) \
30 container_of(dev, struct iop_adma_device, common)
31#define tx_to_iop_adma_slot(tx) \
32 container_of(tx, struct iop_adma_desc_slot, async_tx)
33
34/**
35 * iop_adma_free_slots - flags descriptor slots for reuse
36 * @slot: Slot to free
37 * Caller must hold &iop_chan->lock while calling this function
38 */
39static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
40{
41 int stride = slot->slots_per_op;
42
43 while (stride--) {
44 slot->slots_per_op = 0;
45 slot = list_entry(slot->slot_node.next,
46 struct iop_adma_desc_slot,
47 slot_node);
48 }
49}
50
51static dma_cookie_t
52iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
53 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
54{
55 struct dma_async_tx_descriptor *tx = &desc->async_tx;
56
57 BUG_ON(tx->cookie < 0);
58 if (tx->cookie > 0) {
59 cookie = tx->cookie;
60 tx->cookie = 0;
61
62 /* call the callback (must not sleep or submit new
63 * operations to this channel)
64 */
65 dmaengine_desc_get_callback_invoke(tx, NULL);
66
67 dma_descriptor_unmap(tx);
68 if (desc->group_head)
69 desc->group_head = NULL;
70 }
71
72 /* run dependent operations */
73 dma_run_dependencies(tx);
74
75 return cookie;
76}
77
78static int
79iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
80 struct iop_adma_chan *iop_chan)
81{
82 /* the client is allowed to attach dependent operations
83 * until 'ack' is set
84 */
85 if (!async_tx_test_ack(&desc->async_tx))
86 return 0;
87
88 /* leave the last descriptor in the chain
89 * so we can append to it
90 */
91 if (desc->chain_node.next == &iop_chan->chain)
92 return 1;
93
94 dev_dbg(iop_chan->device->common.dev,
95 "\tfree slot: %d slots_per_op: %d\n",
96 desc->idx, desc->slots_per_op);
97
98 list_del(&desc->chain_node);
99 iop_adma_free_slots(desc);
100
101 return 0;
102}
103
104static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
105{
106 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
107 dma_cookie_t cookie = 0;
108 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
109 int busy = iop_chan_is_busy(iop_chan);
110 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
111
112 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
113 /* free completed slots from the chain starting with
114 * the oldest descriptor
115 */
116 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
117 chain_node) {
118 pr_debug("\tcookie: %d slot: %d busy: %d "
119 "this_desc: %pad next_desc: %#llx ack: %d\n",
120 iter->async_tx.cookie, iter->idx, busy,
121 &iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter),
122 async_tx_test_ack(&iter->async_tx));
123 prefetch(_iter);
124 prefetch(&_iter->async_tx);
125
126 /* do not advance past the current descriptor loaded into the
127 * hardware channel, subsequent descriptors are either in
128 * process or have not been submitted
129 */
130 if (seen_current)
131 break;
132
133 /* stop the search if we reach the current descriptor and the
134 * channel is busy, or if it appears that the current descriptor
135 * needs to be re-read (i.e. has been appended to)
136 */
137 if (iter->async_tx.phys == current_desc) {
138 BUG_ON(seen_current++);
139 if (busy || iop_desc_get_next_desc(iter))
140 break;
141 }
142
143 /* detect the start of a group transaction */
144 if (!slot_cnt && !slots_per_op) {
145 slot_cnt = iter->slot_cnt;
146 slots_per_op = iter->slots_per_op;
147 if (slot_cnt <= slots_per_op) {
148 slot_cnt = 0;
149 slots_per_op = 0;
150 }
151 }
152
153 if (slot_cnt) {
154 pr_debug("\tgroup++\n");
155 if (!grp_start)
156 grp_start = iter;
157 slot_cnt -= slots_per_op;
158 }
159
160 /* all the members of a group are complete */
161 if (slots_per_op != 0 && slot_cnt == 0) {
162 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
163 int end_of_chain = 0;
164 pr_debug("\tgroup end\n");
165
166 /* collect the total results */
167 if (grp_start->xor_check_result) {
168 u32 zero_sum_result = 0;
169 slot_cnt = grp_start->slot_cnt;
170 grp_iter = grp_start;
171
172 list_for_each_entry_from(grp_iter,
173 &iop_chan->chain, chain_node) {
174 zero_sum_result |=
175 iop_desc_get_zero_result(grp_iter);
176 pr_debug("\titer%d result: %d\n",
177 grp_iter->idx, zero_sum_result);
178 slot_cnt -= slots_per_op;
179 if (slot_cnt == 0)
180 break;
181 }
182 pr_debug("\tgrp_start->xor_check_result: %p\n",
183 grp_start->xor_check_result);
184 *grp_start->xor_check_result = zero_sum_result;
185 }
186
187 /* clean up the group */
188 slot_cnt = grp_start->slot_cnt;
189 grp_iter = grp_start;
190 list_for_each_entry_safe_from(grp_iter, _grp_iter,
191 &iop_chan->chain, chain_node) {
192 cookie = iop_adma_run_tx_complete_actions(
193 grp_iter, iop_chan, cookie);
194
195 slot_cnt -= slots_per_op;
196 end_of_chain = iop_adma_clean_slot(grp_iter,
197 iop_chan);
198
199 if (slot_cnt == 0 || end_of_chain)
200 break;
201 }
202
203 /* the group should be complete at this point */
204 BUG_ON(slot_cnt);
205
206 slots_per_op = 0;
207 grp_start = NULL;
208 if (end_of_chain)
209 break;
210 else
211 continue;
212 } else if (slots_per_op) /* wait for group completion */
213 continue;
214
215 /* write back zero sum results (single descriptor case) */
216 if (iter->xor_check_result && iter->async_tx.cookie)
217 *iter->xor_check_result =
218 iop_desc_get_zero_result(iter);
219
220 cookie = iop_adma_run_tx_complete_actions(
221 iter, iop_chan, cookie);
222
223 if (iop_adma_clean_slot(iter, iop_chan))
224 break;
225 }
226
227 if (cookie > 0) {
228 iop_chan->common.completed_cookie = cookie;
229 pr_debug("\tcompleted cookie %d\n", cookie);
230 }
231}
232
233static void
234iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
235{
236 spin_lock_bh(&iop_chan->lock);
237 __iop_adma_slot_cleanup(iop_chan);
238 spin_unlock_bh(&iop_chan->lock);
239}
240
241static void iop_adma_tasklet(unsigned long data)
242{
243 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
244
245 /* lockdep will flag depedency submissions as potentially
246 * recursive locking, this is not the case as a dependency
247 * submission will never recurse a channels submit routine.
248 * There are checks in async_tx.c to prevent this.
249 */
250 spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
251 __iop_adma_slot_cleanup(iop_chan);
252 spin_unlock(&iop_chan->lock);
253}
254
255static struct iop_adma_desc_slot *
256iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
257 int slots_per_op)
258{
259 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
260 LIST_HEAD(chain);
261 int slots_found, retry = 0;
262
263 /* start search from the last allocated descrtiptor
264 * if a contiguous allocation can not be found start searching
265 * from the beginning of the list
266 */
267retry:
268 slots_found = 0;
269 if (retry == 0)
270 iter = iop_chan->last_used;
271 else
272 iter = list_entry(&iop_chan->all_slots,
273 struct iop_adma_desc_slot,
274 slot_node);
275
276 list_for_each_entry_safe_continue(
277 iter, _iter, &iop_chan->all_slots, slot_node) {
278 prefetch(_iter);
279 prefetch(&_iter->async_tx);
280 if (iter->slots_per_op) {
281 /* give up after finding the first busy slot
282 * on the second pass through the list
283 */
284 if (retry)
285 break;
286
287 slots_found = 0;
288 continue;
289 }
290
291 /* start the allocation if the slot is correctly aligned */
292 if (!slots_found++) {
293 if (iop_desc_is_aligned(iter, slots_per_op))
294 alloc_start = iter;
295 else {
296 slots_found = 0;
297 continue;
298 }
299 }
300
301 if (slots_found == num_slots) {
302 struct iop_adma_desc_slot *alloc_tail = NULL;
303 struct iop_adma_desc_slot *last_used = NULL;
304 iter = alloc_start;
305 while (num_slots) {
306 int i;
307 dev_dbg(iop_chan->device->common.dev,
308 "allocated slot: %d "
309 "(desc %p phys: %#llx) slots_per_op %d\n",
310 iter->idx, iter->hw_desc,
311 (u64)iter->async_tx.phys, slots_per_op);
312
313 /* pre-ack all but the last descriptor */
314 if (num_slots != slots_per_op)
315 async_tx_ack(&iter->async_tx);
316
317 list_add_tail(&iter->chain_node, &chain);
318 alloc_tail = iter;
319 iter->async_tx.cookie = 0;
320 iter->slot_cnt = num_slots;
321 iter->xor_check_result = NULL;
322 for (i = 0; i < slots_per_op; i++) {
323 iter->slots_per_op = slots_per_op - i;
324 last_used = iter;
325 iter = list_entry(iter->slot_node.next,
326 struct iop_adma_desc_slot,
327 slot_node);
328 }
329 num_slots -= slots_per_op;
330 }
331 alloc_tail->group_head = alloc_start;
332 alloc_tail->async_tx.cookie = -EBUSY;
333 list_splice(&chain, &alloc_tail->tx_list);
334 iop_chan->last_used = last_used;
335 iop_desc_clear_next_desc(alloc_start);
336 iop_desc_clear_next_desc(alloc_tail);
337 return alloc_tail;
338 }
339 }
340 if (!retry++)
341 goto retry;
342
343 /* perform direct reclaim if the allocation fails */
344 __iop_adma_slot_cleanup(iop_chan);
345
346 return NULL;
347}
348
349static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
350{
351 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
352 iop_chan->pending);
353
354 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
355 iop_chan->pending = 0;
356 iop_chan_append(iop_chan);
357 }
358}
359
360static dma_cookie_t
361iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
362{
363 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
364 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
365 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
366 int slot_cnt;
367 dma_cookie_t cookie;
368 dma_addr_t next_dma;
369
370 grp_start = sw_desc->group_head;
371 slot_cnt = grp_start->slot_cnt;
372
373 spin_lock_bh(&iop_chan->lock);
374 cookie = dma_cookie_assign(tx);
375
376 old_chain_tail = list_entry(iop_chan->chain.prev,
377 struct iop_adma_desc_slot, chain_node);
378 list_splice_init(&sw_desc->tx_list,
379 &old_chain_tail->chain_node);
380
381 /* fix up the hardware chain */
382 next_dma = grp_start->async_tx.phys;
383 iop_desc_set_next_desc(old_chain_tail, next_dma);
384 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
385
386 /* check for pre-chained descriptors */
387 iop_paranoia(iop_desc_get_next_desc(sw_desc));
388
389 /* increment the pending count by the number of slots
390 * memcpy operations have a 1:1 (slot:operation) relation
391 * other operations are heavier and will pop the threshold
392 * more often.
393 */
394 iop_chan->pending += slot_cnt;
395 iop_adma_check_threshold(iop_chan);
396 spin_unlock_bh(&iop_chan->lock);
397
398 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
399 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
400
401 return cookie;
402}
403
404static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
405static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
406
407/**
408 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
409 * @chan: allocate descriptor resources for this channel
410 *
411 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
412 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
413 * greater than 2x the number slots needed to satisfy a device->max_xor
414 * request.
415 * */
416static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
417{
418 char *hw_desc;
419 int idx;
420 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
421 struct iop_adma_desc_slot *slot = NULL;
422 int init = iop_chan->slots_allocated ? 0 : 1;
423 struct iop_adma_platform_data *plat_data =
424 dev_get_platdata(&iop_chan->device->pdev->dev);
425 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
426
427 /* Allocate descriptor slots */
428 do {
429 idx = iop_chan->slots_allocated;
430 if (idx == num_descs_in_pool)
431 break;
432
433 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
434 if (!slot) {
435 printk(KERN_INFO "IOP ADMA Channel only initialized"
436 " %d descriptor slots", idx);
437 break;
438 }
439 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
440 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
441
442 dma_async_tx_descriptor_init(&slot->async_tx, chan);
443 slot->async_tx.tx_submit = iop_adma_tx_submit;
444 INIT_LIST_HEAD(&slot->tx_list);
445 INIT_LIST_HEAD(&slot->chain_node);
446 INIT_LIST_HEAD(&slot->slot_node);
447 hw_desc = (char *) iop_chan->device->dma_desc_pool;
448 slot->async_tx.phys =
449 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
450 slot->idx = idx;
451
452 spin_lock_bh(&iop_chan->lock);
453 iop_chan->slots_allocated++;
454 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
455 spin_unlock_bh(&iop_chan->lock);
456 } while (iop_chan->slots_allocated < num_descs_in_pool);
457
458 if (idx && !iop_chan->last_used)
459 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
460 struct iop_adma_desc_slot,
461 slot_node);
462
463 dev_dbg(iop_chan->device->common.dev,
464 "allocated %d descriptor slots last_used: %p\n",
465 iop_chan->slots_allocated, iop_chan->last_used);
466
467 /* initialize the channel and the chain with a null operation */
468 if (init) {
469 if (dma_has_cap(DMA_MEMCPY,
470 iop_chan->device->common.cap_mask))
471 iop_chan_start_null_memcpy(iop_chan);
472 else if (dma_has_cap(DMA_XOR,
473 iop_chan->device->common.cap_mask))
474 iop_chan_start_null_xor(iop_chan);
475 else
476 BUG();
477 }
478
479 return (idx > 0) ? idx : -ENOMEM;
480}
481
482static struct dma_async_tx_descriptor *
483iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
484{
485 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
486 struct iop_adma_desc_slot *sw_desc, *grp_start;
487 int slot_cnt, slots_per_op;
488
489 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
490
491 spin_lock_bh(&iop_chan->lock);
492 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
493 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
494 if (sw_desc) {
495 grp_start = sw_desc->group_head;
496 iop_desc_init_interrupt(grp_start, iop_chan);
497 sw_desc->async_tx.flags = flags;
498 }
499 spin_unlock_bh(&iop_chan->lock);
500
501 return sw_desc ? &sw_desc->async_tx : NULL;
502}
503
504static struct dma_async_tx_descriptor *
505iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
506 dma_addr_t dma_src, size_t len, unsigned long flags)
507{
508 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
509 struct iop_adma_desc_slot *sw_desc, *grp_start;
510 int slot_cnt, slots_per_op;
511
512 if (unlikely(!len))
513 return NULL;
514 BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT);
515
516 dev_dbg(iop_chan->device->common.dev, "%s len: %zu\n",
517 __func__, len);
518
519 spin_lock_bh(&iop_chan->lock);
520 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
521 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
522 if (sw_desc) {
523 grp_start = sw_desc->group_head;
524 iop_desc_init_memcpy(grp_start, flags);
525 iop_desc_set_byte_count(grp_start, iop_chan, len);
526 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
527 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
528 sw_desc->async_tx.flags = flags;
529 }
530 spin_unlock_bh(&iop_chan->lock);
531
532 return sw_desc ? &sw_desc->async_tx : NULL;
533}
534
535static struct dma_async_tx_descriptor *
536iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
537 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
538 unsigned long flags)
539{
540 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
541 struct iop_adma_desc_slot *sw_desc, *grp_start;
542 int slot_cnt, slots_per_op;
543
544 if (unlikely(!len))
545 return NULL;
546 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
547
548 dev_dbg(iop_chan->device->common.dev,
549 "%s src_cnt: %d len: %zu flags: %lx\n",
550 __func__, src_cnt, len, flags);
551
552 spin_lock_bh(&iop_chan->lock);
553 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
554 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
555 if (sw_desc) {
556 grp_start = sw_desc->group_head;
557 iop_desc_init_xor(grp_start, src_cnt, flags);
558 iop_desc_set_byte_count(grp_start, iop_chan, len);
559 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
560 sw_desc->async_tx.flags = flags;
561 while (src_cnt--)
562 iop_desc_set_xor_src_addr(grp_start, src_cnt,
563 dma_src[src_cnt]);
564 }
565 spin_unlock_bh(&iop_chan->lock);
566
567 return sw_desc ? &sw_desc->async_tx : NULL;
568}
569
570static struct dma_async_tx_descriptor *
571iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
572 unsigned int src_cnt, size_t len, u32 *result,
573 unsigned long flags)
574{
575 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
576 struct iop_adma_desc_slot *sw_desc, *grp_start;
577 int slot_cnt, slots_per_op;
578
579 if (unlikely(!len))
580 return NULL;
581
582 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n",
583 __func__, src_cnt, len);
584
585 spin_lock_bh(&iop_chan->lock);
586 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
587 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
588 if (sw_desc) {
589 grp_start = sw_desc->group_head;
590 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
591 iop_desc_set_zero_sum_byte_count(grp_start, len);
592 grp_start->xor_check_result = result;
593 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
594 __func__, grp_start->xor_check_result);
595 sw_desc->async_tx.flags = flags;
596 while (src_cnt--)
597 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
598 dma_src[src_cnt]);
599 }
600 spin_unlock_bh(&iop_chan->lock);
601
602 return sw_desc ? &sw_desc->async_tx : NULL;
603}
604
605static struct dma_async_tx_descriptor *
606iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
607 unsigned int src_cnt, const unsigned char *scf, size_t len,
608 unsigned long flags)
609{
610 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
611 struct iop_adma_desc_slot *sw_desc, *g;
612 int slot_cnt, slots_per_op;
613 int continue_srcs;
614
615 if (unlikely(!len))
616 return NULL;
617 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
618
619 dev_dbg(iop_chan->device->common.dev,
620 "%s src_cnt: %d len: %zu flags: %lx\n",
621 __func__, src_cnt, len, flags);
622
623 if (dmaf_p_disabled_continue(flags))
624 continue_srcs = 1+src_cnt;
625 else if (dmaf_continue(flags))
626 continue_srcs = 3+src_cnt;
627 else
628 continue_srcs = 0+src_cnt;
629
630 spin_lock_bh(&iop_chan->lock);
631 slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
632 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
633 if (sw_desc) {
634 int i;
635
636 g = sw_desc->group_head;
637 iop_desc_set_byte_count(g, iop_chan, len);
638
639 /* even if P is disabled its destination address (bits
640 * [3:0]) must match Q. It is ok if P points to an
641 * invalid address, it won't be written.
642 */
643 if (flags & DMA_PREP_PQ_DISABLE_P)
644 dst[0] = dst[1] & 0x7;
645
646 iop_desc_set_pq_addr(g, dst);
647 sw_desc->async_tx.flags = flags;
648 for (i = 0; i < src_cnt; i++)
649 iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
650
651 /* if we are continuing a previous operation factor in
652 * the old p and q values, see the comment for dma_maxpq
653 * in include/linux/dmaengine.h
654 */
655 if (dmaf_p_disabled_continue(flags))
656 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
657 else if (dmaf_continue(flags)) {
658 iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
659 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
660 iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
661 }
662 iop_desc_init_pq(g, i, flags);
663 }
664 spin_unlock_bh(&iop_chan->lock);
665
666 return sw_desc ? &sw_desc->async_tx : NULL;
667}
668
669static struct dma_async_tx_descriptor *
670iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
671 unsigned int src_cnt, const unsigned char *scf,
672 size_t len, enum sum_check_flags *pqres,
673 unsigned long flags)
674{
675 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
676 struct iop_adma_desc_slot *sw_desc, *g;
677 int slot_cnt, slots_per_op;
678
679 if (unlikely(!len))
680 return NULL;
681 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
682
683 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n",
684 __func__, src_cnt, len);
685
686 spin_lock_bh(&iop_chan->lock);
687 slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
688 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
689 if (sw_desc) {
690 /* for validate operations p and q are tagged onto the
691 * end of the source list
692 */
693 int pq_idx = src_cnt;
694
695 g = sw_desc->group_head;
696 iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
697 iop_desc_set_pq_zero_sum_byte_count(g, len);
698 g->pq_check_result = pqres;
699 pr_debug("\t%s: g->pq_check_result: %p\n",
700 __func__, g->pq_check_result);
701 sw_desc->async_tx.flags = flags;
702 while (src_cnt--)
703 iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
704 src[src_cnt],
705 scf[src_cnt]);
706 iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
707 }
708 spin_unlock_bh(&iop_chan->lock);
709
710 return sw_desc ? &sw_desc->async_tx : NULL;
711}
712
713static void iop_adma_free_chan_resources(struct dma_chan *chan)
714{
715 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
716 struct iop_adma_desc_slot *iter, *_iter;
717 int in_use_descs = 0;
718
719 iop_adma_slot_cleanup(iop_chan);
720
721 spin_lock_bh(&iop_chan->lock);
722 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
723 chain_node) {
724 in_use_descs++;
725 list_del(&iter->chain_node);
726 }
727 list_for_each_entry_safe_reverse(
728 iter, _iter, &iop_chan->all_slots, slot_node) {
729 list_del(&iter->slot_node);
730 kfree(iter);
731 iop_chan->slots_allocated--;
732 }
733 iop_chan->last_used = NULL;
734
735 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
736 __func__, iop_chan->slots_allocated);
737 spin_unlock_bh(&iop_chan->lock);
738
739 /* one is ok since we left it on there on purpose */
740 if (in_use_descs > 1)
741 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
742 in_use_descs - 1);
743}
744
745/**
746 * iop_adma_status - poll the status of an ADMA transaction
747 * @chan: ADMA channel handle
748 * @cookie: ADMA transaction identifier
749 * @txstate: a holder for the current state of the channel or NULL
750 */
751static enum dma_status iop_adma_status(struct dma_chan *chan,
752 dma_cookie_t cookie,
753 struct dma_tx_state *txstate)
754{
755 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
756 int ret;
757
758 ret = dma_cookie_status(chan, cookie, txstate);
759 if (ret == DMA_COMPLETE)
760 return ret;
761
762 iop_adma_slot_cleanup(iop_chan);
763
764 return dma_cookie_status(chan, cookie, txstate);
765}
766
767static irqreturn_t iop_adma_eot_handler(int irq, void *data)
768{
769 struct iop_adma_chan *chan = data;
770
771 dev_dbg(chan->device->common.dev, "%s\n", __func__);
772
773 tasklet_schedule(&chan->irq_tasklet);
774
775 iop_adma_device_clear_eot_status(chan);
776
777 return IRQ_HANDLED;
778}
779
780static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
781{
782 struct iop_adma_chan *chan = data;
783
784 dev_dbg(chan->device->common.dev, "%s\n", __func__);
785
786 tasklet_schedule(&chan->irq_tasklet);
787
788 iop_adma_device_clear_eoc_status(chan);
789
790 return IRQ_HANDLED;
791}
792
793static irqreturn_t iop_adma_err_handler(int irq, void *data)
794{
795 struct iop_adma_chan *chan = data;
796 unsigned long status = iop_chan_get_status(chan);
797
798 dev_err(chan->device->common.dev,
799 "error ( %s%s%s%s%s%s%s)\n",
800 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
801 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
802 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
803 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
804 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
805 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
806 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
807
808 iop_adma_device_clear_err_status(chan);
809
810 BUG();
811
812 return IRQ_HANDLED;
813}
814
815static void iop_adma_issue_pending(struct dma_chan *chan)
816{
817 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
818
819 if (iop_chan->pending) {
820 iop_chan->pending = 0;
821 iop_chan_append(iop_chan);
822 }
823}
824
825/*
826 * Perform a transaction to verify the HW works.
827 */
828#define IOP_ADMA_TEST_SIZE 2000
829
830static int iop_adma_memcpy_self_test(struct iop_adma_device *device)
831{
832 int i;
833 void *src, *dest;
834 dma_addr_t src_dma, dest_dma;
835 struct dma_chan *dma_chan;
836 dma_cookie_t cookie;
837 struct dma_async_tx_descriptor *tx;
838 int err = 0;
839 struct iop_adma_chan *iop_chan;
840
841 dev_dbg(device->common.dev, "%s\n", __func__);
842
843 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
844 if (!src)
845 return -ENOMEM;
846 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
847 if (!dest) {
848 kfree(src);
849 return -ENOMEM;
850 }
851
852 /* Fill in src buffer */
853 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
854 ((u8 *) src)[i] = (u8)i;
855
856 /* Start copy, using first DMA channel */
857 dma_chan = container_of(device->common.channels.next,
858 struct dma_chan,
859 device_node);
860 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
861 err = -ENODEV;
862 goto out;
863 }
864
865 dest_dma = dma_map_single(dma_chan->device->dev, dest,
866 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
867 src_dma = dma_map_single(dma_chan->device->dev, src,
868 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
869 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
870 IOP_ADMA_TEST_SIZE,
871 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
872
873 cookie = iop_adma_tx_submit(tx);
874 iop_adma_issue_pending(dma_chan);
875 msleep(1);
876
877 if (iop_adma_status(dma_chan, cookie, NULL) !=
878 DMA_COMPLETE) {
879 dev_err(dma_chan->device->dev,
880 "Self-test copy timed out, disabling\n");
881 err = -ENODEV;
882 goto free_resources;
883 }
884
885 iop_chan = to_iop_adma_chan(dma_chan);
886 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
887 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
888 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
889 dev_err(dma_chan->device->dev,
890 "Self-test copy failed compare, disabling\n");
891 err = -ENODEV;
892 goto free_resources;
893 }
894
895free_resources:
896 iop_adma_free_chan_resources(dma_chan);
897out:
898 kfree(src);
899 kfree(dest);
900 return err;
901}
902
903#define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
904static int
905iop_adma_xor_val_self_test(struct iop_adma_device *device)
906{
907 int i, src_idx;
908 struct page *dest;
909 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
910 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
911 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
912 dma_addr_t dest_dma;
913 struct dma_async_tx_descriptor *tx;
914 struct dma_chan *dma_chan;
915 dma_cookie_t cookie;
916 u8 cmp_byte = 0;
917 u32 cmp_word;
918 u32 zero_sum_result;
919 int err = 0;
920 struct iop_adma_chan *iop_chan;
921
922 dev_dbg(device->common.dev, "%s\n", __func__);
923
924 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
925 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
926 if (!xor_srcs[src_idx]) {
927 while (src_idx--)
928 __free_page(xor_srcs[src_idx]);
929 return -ENOMEM;
930 }
931 }
932
933 dest = alloc_page(GFP_KERNEL);
934 if (!dest) {
935 while (src_idx--)
936 __free_page(xor_srcs[src_idx]);
937 return -ENOMEM;
938 }
939
940 /* Fill in src buffers */
941 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
942 u8 *ptr = page_address(xor_srcs[src_idx]);
943 for (i = 0; i < PAGE_SIZE; i++)
944 ptr[i] = (1 << src_idx);
945 }
946
947 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
948 cmp_byte ^= (u8) (1 << src_idx);
949
950 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
951 (cmp_byte << 8) | cmp_byte;
952
953 memset(page_address(dest), 0, PAGE_SIZE);
954
955 dma_chan = container_of(device->common.channels.next,
956 struct dma_chan,
957 device_node);
958 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
959 err = -ENODEV;
960 goto out;
961 }
962
963 /* test xor */
964 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
965 PAGE_SIZE, DMA_FROM_DEVICE);
966 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
967 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
968 0, PAGE_SIZE, DMA_TO_DEVICE);
969 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
970 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
971 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
972
973 cookie = iop_adma_tx_submit(tx);
974 iop_adma_issue_pending(dma_chan);
975 msleep(8);
976
977 if (iop_adma_status(dma_chan, cookie, NULL) !=
978 DMA_COMPLETE) {
979 dev_err(dma_chan->device->dev,
980 "Self-test xor timed out, disabling\n");
981 err = -ENODEV;
982 goto free_resources;
983 }
984
985 iop_chan = to_iop_adma_chan(dma_chan);
986 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
987 PAGE_SIZE, DMA_FROM_DEVICE);
988 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
989 u32 *ptr = page_address(dest);
990 if (ptr[i] != cmp_word) {
991 dev_err(dma_chan->device->dev,
992 "Self-test xor failed compare, disabling\n");
993 err = -ENODEV;
994 goto free_resources;
995 }
996 }
997 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
998 PAGE_SIZE, DMA_TO_DEVICE);
999
1000 /* skip zero sum if the capability is not present */
1001 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1002 goto free_resources;
1003
1004 /* zero sum the sources with the destintation page */
1005 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1006 zero_sum_srcs[i] = xor_srcs[i];
1007 zero_sum_srcs[i] = dest;
1008
1009 zero_sum_result = 1;
1010
1011 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1012 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1013 zero_sum_srcs[i], 0, PAGE_SIZE,
1014 DMA_TO_DEVICE);
1015 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1016 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1017 &zero_sum_result,
1018 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1019
1020 cookie = iop_adma_tx_submit(tx);
1021 iop_adma_issue_pending(dma_chan);
1022 msleep(8);
1023
1024 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1025 dev_err(dma_chan->device->dev,
1026 "Self-test zero sum timed out, disabling\n");
1027 err = -ENODEV;
1028 goto free_resources;
1029 }
1030
1031 if (zero_sum_result != 0) {
1032 dev_err(dma_chan->device->dev,
1033 "Self-test zero sum failed compare, disabling\n");
1034 err = -ENODEV;
1035 goto free_resources;
1036 }
1037
1038 /* test for non-zero parity sum */
1039 zero_sum_result = 0;
1040 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1041 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1042 zero_sum_srcs[i], 0, PAGE_SIZE,
1043 DMA_TO_DEVICE);
1044 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1045 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1046 &zero_sum_result,
1047 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1048
1049 cookie = iop_adma_tx_submit(tx);
1050 iop_adma_issue_pending(dma_chan);
1051 msleep(8);
1052
1053 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1054 dev_err(dma_chan->device->dev,
1055 "Self-test non-zero sum timed out, disabling\n");
1056 err = -ENODEV;
1057 goto free_resources;
1058 }
1059
1060 if (zero_sum_result != 1) {
1061 dev_err(dma_chan->device->dev,
1062 "Self-test non-zero sum failed compare, disabling\n");
1063 err = -ENODEV;
1064 goto free_resources;
1065 }
1066
1067free_resources:
1068 iop_adma_free_chan_resources(dma_chan);
1069out:
1070 src_idx = IOP_ADMA_NUM_SRC_TEST;
1071 while (src_idx--)
1072 __free_page(xor_srcs[src_idx]);
1073 __free_page(dest);
1074 return err;
1075}
1076
1077#ifdef CONFIG_RAID6_PQ
1078static int
1079iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
1080{
1081 /* combined sources, software pq results, and extra hw pq results */
1082 struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2];
1083 /* ptr to the extra hw pq buffers defined above */
1084 struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
1085 /* address conversion buffers (dma_map / page_address) */
1086 void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
1087 dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
1088 dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST];
1089
1090 int i;
1091 struct dma_async_tx_descriptor *tx;
1092 struct dma_chan *dma_chan;
1093 dma_cookie_t cookie;
1094 u32 zero_sum_result;
1095 int err = 0;
1096 struct device *dev;
1097
1098 dev_dbg(device->common.dev, "%s\n", __func__);
1099
1100 for (i = 0; i < ARRAY_SIZE(pq); i++) {
1101 pq[i] = alloc_page(GFP_KERNEL);
1102 if (!pq[i]) {
1103 while (i--)
1104 __free_page(pq[i]);
1105 return -ENOMEM;
1106 }
1107 }
1108
1109 /* Fill in src buffers */
1110 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) {
1111 pq_sw[i] = page_address(pq[i]);
1112 memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE);
1113 }
1114 pq_sw[i] = page_address(pq[i]);
1115 pq_sw[i+1] = page_address(pq[i+1]);
1116
1117 dma_chan = container_of(device->common.channels.next,
1118 struct dma_chan,
1119 device_node);
1120 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1121 err = -ENODEV;
1122 goto out;
1123 }
1124
1125 dev = dma_chan->device->dev;
1126
1127 /* initialize the dests */
1128 memset(page_address(pq_hw[0]), 0 , PAGE_SIZE);
1129 memset(page_address(pq_hw[1]), 0 , PAGE_SIZE);
1130
1131 /* test pq */
1132 pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1133 pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1134 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1135 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1136 DMA_TO_DEVICE);
1137
1138 tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src,
1139 IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp,
1140 PAGE_SIZE,
1141 DMA_PREP_INTERRUPT |
1142 DMA_CTRL_ACK);
1143
1144 cookie = iop_adma_tx_submit(tx);
1145 iop_adma_issue_pending(dma_chan);
1146 msleep(8);
1147
1148 if (iop_adma_status(dma_chan, cookie, NULL) !=
1149 DMA_COMPLETE) {
1150 dev_err(dev, "Self-test pq timed out, disabling\n");
1151 err = -ENODEV;
1152 goto free_resources;
1153 }
1154
1155 raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw);
1156
1157 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST],
1158 page_address(pq_hw[0]), PAGE_SIZE) != 0) {
1159 dev_err(dev, "Self-test p failed compare, disabling\n");
1160 err = -ENODEV;
1161 goto free_resources;
1162 }
1163 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1],
1164 page_address(pq_hw[1]), PAGE_SIZE) != 0) {
1165 dev_err(dev, "Self-test q failed compare, disabling\n");
1166 err = -ENODEV;
1167 goto free_resources;
1168 }
1169
1170 /* test correct zero sum using the software generated pq values */
1171 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1172 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1173 DMA_TO_DEVICE);
1174
1175 zero_sum_result = ~0;
1176 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1177 pq_src, IOP_ADMA_NUM_SRC_TEST,
1178 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1179 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1180
1181 cookie = iop_adma_tx_submit(tx);
1182 iop_adma_issue_pending(dma_chan);
1183 msleep(8);
1184
1185 if (iop_adma_status(dma_chan, cookie, NULL) !=
1186 DMA_COMPLETE) {
1187 dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n");
1188 err = -ENODEV;
1189 goto free_resources;
1190 }
1191
1192 if (zero_sum_result != 0) {
1193 dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n",
1194 zero_sum_result);
1195 err = -ENODEV;
1196 goto free_resources;
1197 }
1198
1199 /* test incorrect zero sum */
1200 i = IOP_ADMA_NUM_SRC_TEST;
1201 memset(pq_sw[i] + 100, 0, 100);
1202 memset(pq_sw[i+1] + 200, 0, 200);
1203 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1204 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1205 DMA_TO_DEVICE);
1206
1207 zero_sum_result = 0;
1208 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1209 pq_src, IOP_ADMA_NUM_SRC_TEST,
1210 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1211 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1212
1213 cookie = iop_adma_tx_submit(tx);
1214 iop_adma_issue_pending(dma_chan);
1215 msleep(8);
1216
1217 if (iop_adma_status(dma_chan, cookie, NULL) !=
1218 DMA_COMPLETE) {
1219 dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n");
1220 err = -ENODEV;
1221 goto free_resources;
1222 }
1223
1224 if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) {
1225 dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n",
1226 zero_sum_result);
1227 err = -ENODEV;
1228 goto free_resources;
1229 }
1230
1231free_resources:
1232 iop_adma_free_chan_resources(dma_chan);
1233out:
1234 i = ARRAY_SIZE(pq);
1235 while (i--)
1236 __free_page(pq[i]);
1237 return err;
1238}
1239#endif
1240
1241static int iop_adma_remove(struct platform_device *dev)
1242{
1243 struct iop_adma_device *device = platform_get_drvdata(dev);
1244 struct dma_chan *chan, *_chan;
1245 struct iop_adma_chan *iop_chan;
1246 struct iop_adma_platform_data *plat_data = dev_get_platdata(&dev->dev);
1247
1248 dma_async_device_unregister(&device->common);
1249
1250 dma_free_coherent(&dev->dev, plat_data->pool_size,
1251 device->dma_desc_pool_virt, device->dma_desc_pool);
1252
1253 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1254 device_node) {
1255 iop_chan = to_iop_adma_chan(chan);
1256 list_del(&chan->device_node);
1257 kfree(iop_chan);
1258 }
1259 kfree(device);
1260
1261 return 0;
1262}
1263
1264static int iop_adma_probe(struct platform_device *pdev)
1265{
1266 struct resource *res;
1267 int ret = 0, i;
1268 struct iop_adma_device *adev;
1269 struct iop_adma_chan *iop_chan;
1270 struct dma_device *dma_dev;
1271 struct iop_adma_platform_data *plat_data = dev_get_platdata(&pdev->dev);
1272
1273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1274 if (!res)
1275 return -ENODEV;
1276
1277 if (!devm_request_mem_region(&pdev->dev, res->start,
1278 resource_size(res), pdev->name))
1279 return -EBUSY;
1280
1281 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1282 if (!adev)
1283 return -ENOMEM;
1284 dma_dev = &adev->common;
1285
1286 /* allocate coherent memory for hardware descriptors
1287 * note: writecombine gives slightly better performance, but
1288 * requires that we explicitly flush the writes
1289 */
1290 adev->dma_desc_pool_virt = dma_alloc_wc(&pdev->dev,
1291 plat_data->pool_size,
1292 &adev->dma_desc_pool,
1293 GFP_KERNEL);
1294 if (!adev->dma_desc_pool_virt) {
1295 ret = -ENOMEM;
1296 goto err_free_adev;
1297 }
1298
1299 dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %p\n",
1300 __func__, adev->dma_desc_pool_virt,
1301 (void *) adev->dma_desc_pool);
1302
1303 adev->id = plat_data->hw_id;
1304
1305 /* discover transaction capabilites from the platform data */
1306 dma_dev->cap_mask = plat_data->cap_mask;
1307
1308 adev->pdev = pdev;
1309 platform_set_drvdata(pdev, adev);
1310
1311 INIT_LIST_HEAD(&dma_dev->channels);
1312
1313 /* set base routines */
1314 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1315 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1316 dma_dev->device_tx_status = iop_adma_status;
1317 dma_dev->device_issue_pending = iop_adma_issue_pending;
1318 dma_dev->dev = &pdev->dev;
1319
1320 /* set prep routines based on capability */
1321 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1322 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1323 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1324 dma_dev->max_xor = iop_adma_get_max_xor();
1325 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1326 }
1327 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1328 dma_dev->device_prep_dma_xor_val =
1329 iop_adma_prep_dma_xor_val;
1330 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1331 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1332 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1333 }
1334 if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1335 dma_dev->device_prep_dma_pq_val =
1336 iop_adma_prep_dma_pq_val;
1337 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1338 dma_dev->device_prep_dma_interrupt =
1339 iop_adma_prep_dma_interrupt;
1340
1341 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1342 if (!iop_chan) {
1343 ret = -ENOMEM;
1344 goto err_free_dma;
1345 }
1346 iop_chan->device = adev;
1347
1348 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1349 resource_size(res));
1350 if (!iop_chan->mmr_base) {
1351 ret = -ENOMEM;
1352 goto err_free_iop_chan;
1353 }
1354 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1355 iop_chan);
1356
1357 /* clear errors before enabling interrupts */
1358 iop_adma_device_clear_err_status(iop_chan);
1359
1360 for (i = 0; i < 3; i++) {
1361 static const irq_handler_t handler[] = {
1362 iop_adma_eot_handler,
1363 iop_adma_eoc_handler,
1364 iop_adma_err_handler
1365 };
1366 int irq = platform_get_irq(pdev, i);
1367 if (irq < 0) {
1368 ret = -ENXIO;
1369 goto err_free_iop_chan;
1370 } else {
1371 ret = devm_request_irq(&pdev->dev, irq,
1372 handler[i], 0, pdev->name, iop_chan);
1373 if (ret)
1374 goto err_free_iop_chan;
1375 }
1376 }
1377
1378 spin_lock_init(&iop_chan->lock);
1379 INIT_LIST_HEAD(&iop_chan->chain);
1380 INIT_LIST_HEAD(&iop_chan->all_slots);
1381 iop_chan->common.device = dma_dev;
1382 dma_cookie_init(&iop_chan->common);
1383 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1384
1385 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1386 ret = iop_adma_memcpy_self_test(adev);
1387 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1388 if (ret)
1389 goto err_free_iop_chan;
1390 }
1391
1392 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1393 ret = iop_adma_xor_val_self_test(adev);
1394 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1395 if (ret)
1396 goto err_free_iop_chan;
1397 }
1398
1399 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
1400 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
1401 #ifdef CONFIG_RAID6_PQ
1402 ret = iop_adma_pq_zero_sum_self_test(adev);
1403 dev_dbg(&pdev->dev, "pq self test returned %d\n", ret);
1404 #else
1405 /* can not test raid6, so do not publish capability */
1406 dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
1407 dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
1408 ret = 0;
1409 #endif
1410 if (ret)
1411 goto err_free_iop_chan;
1412 }
1413
1414 dev_info(&pdev->dev, "Intel(R) IOP: ( %s%s%s%s%s%s)\n",
1415 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1416 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1417 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1418 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1419 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1420 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1421
1422 dma_async_device_register(dma_dev);
1423 goto out;
1424
1425 err_free_iop_chan:
1426 kfree(iop_chan);
1427 err_free_dma:
1428 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1429 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1430 err_free_adev:
1431 kfree(adev);
1432 out:
1433 return ret;
1434}
1435
1436static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1437{
1438 struct iop_adma_desc_slot *sw_desc, *grp_start;
1439 dma_cookie_t cookie;
1440 int slot_cnt, slots_per_op;
1441
1442 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1443
1444 spin_lock_bh(&iop_chan->lock);
1445 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1446 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1447 if (sw_desc) {
1448 grp_start = sw_desc->group_head;
1449
1450 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1451 async_tx_ack(&sw_desc->async_tx);
1452 iop_desc_init_memcpy(grp_start, 0);
1453 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1454 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1455 iop_desc_set_memcpy_src_addr(grp_start, 0);
1456
1457 cookie = dma_cookie_assign(&sw_desc->async_tx);
1458
1459 /* initialize the completed cookie to be less than
1460 * the most recently used cookie
1461 */
1462 iop_chan->common.completed_cookie = cookie - 1;
1463
1464 /* channel should not be busy */
1465 BUG_ON(iop_chan_is_busy(iop_chan));
1466
1467 /* clear any prior error-status bits */
1468 iop_adma_device_clear_err_status(iop_chan);
1469
1470 /* disable operation */
1471 iop_chan_disable(iop_chan);
1472
1473 /* set the descriptor address */
1474 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1475
1476 /* 1/ don't add pre-chained descriptors
1477 * 2/ dummy read to flush next_desc write
1478 */
1479 BUG_ON(iop_desc_get_next_desc(sw_desc));
1480
1481 /* run the descriptor */
1482 iop_chan_enable(iop_chan);
1483 } else
1484 dev_err(iop_chan->device->common.dev,
1485 "failed to allocate null descriptor\n");
1486 spin_unlock_bh(&iop_chan->lock);
1487}
1488
1489static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1490{
1491 struct iop_adma_desc_slot *sw_desc, *grp_start;
1492 dma_cookie_t cookie;
1493 int slot_cnt, slots_per_op;
1494
1495 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1496
1497 spin_lock_bh(&iop_chan->lock);
1498 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1499 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1500 if (sw_desc) {
1501 grp_start = sw_desc->group_head;
1502 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1503 async_tx_ack(&sw_desc->async_tx);
1504 iop_desc_init_null_xor(grp_start, 2, 0);
1505 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1506 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1507 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1508 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1509
1510 cookie = dma_cookie_assign(&sw_desc->async_tx);
1511
1512 /* initialize the completed cookie to be less than
1513 * the most recently used cookie
1514 */
1515 iop_chan->common.completed_cookie = cookie - 1;
1516
1517 /* channel should not be busy */
1518 BUG_ON(iop_chan_is_busy(iop_chan));
1519
1520 /* clear any prior error-status bits */
1521 iop_adma_device_clear_err_status(iop_chan);
1522
1523 /* disable operation */
1524 iop_chan_disable(iop_chan);
1525
1526 /* set the descriptor address */
1527 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1528
1529 /* 1/ don't add pre-chained descriptors
1530 * 2/ dummy read to flush next_desc write
1531 */
1532 BUG_ON(iop_desc_get_next_desc(sw_desc));
1533
1534 /* run the descriptor */
1535 iop_chan_enable(iop_chan);
1536 } else
1537 dev_err(iop_chan->device->common.dev,
1538 "failed to allocate null descriptor\n");
1539 spin_unlock_bh(&iop_chan->lock);
1540}
1541
1542static struct platform_driver iop_adma_driver = {
1543 .probe = iop_adma_probe,
1544 .remove = iop_adma_remove,
1545 .driver = {
1546 .name = "iop-adma",
1547 },
1548};
1549
1550module_platform_driver(iop_adma_driver);
1551
1552MODULE_AUTHOR("Intel Corporation");
1553MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1554MODULE_LICENSE("GPL");
1555MODULE_ALIAS("platform:iop-adma");
1/*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20/*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/spinlock.h>
30#include <linux/interrupt.h>
31#include <linux/platform_device.h>
32#include <linux/memory.h>
33#include <linux/ioport.h>
34#include <linux/raid/pq.h>
35#include <linux/slab.h>
36
37#include <mach/adma.h>
38
39#include "dmaengine.h"
40
41#define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
42#define to_iop_adma_device(dev) \
43 container_of(dev, struct iop_adma_device, common)
44#define tx_to_iop_adma_slot(tx) \
45 container_of(tx, struct iop_adma_desc_slot, async_tx)
46
47/**
48 * iop_adma_free_slots - flags descriptor slots for reuse
49 * @slot: Slot to free
50 * Caller must hold &iop_chan->lock while calling this function
51 */
52static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
53{
54 int stride = slot->slots_per_op;
55
56 while (stride--) {
57 slot->slots_per_op = 0;
58 slot = list_entry(slot->slot_node.next,
59 struct iop_adma_desc_slot,
60 slot_node);
61 }
62}
63
64static void
65iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
66{
67 struct dma_async_tx_descriptor *tx = &desc->async_tx;
68 struct iop_adma_desc_slot *unmap = desc->group_head;
69 struct device *dev = &iop_chan->device->pdev->dev;
70 u32 len = unmap->unmap_len;
71 enum dma_ctrl_flags flags = tx->flags;
72 u32 src_cnt;
73 dma_addr_t addr;
74 dma_addr_t dest;
75
76 src_cnt = unmap->unmap_src_cnt;
77 dest = iop_desc_get_dest_addr(unmap, iop_chan);
78 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
79 enum dma_data_direction dir;
80
81 if (src_cnt > 1) /* is xor? */
82 dir = DMA_BIDIRECTIONAL;
83 else
84 dir = DMA_FROM_DEVICE;
85
86 dma_unmap_page(dev, dest, len, dir);
87 }
88
89 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
90 while (src_cnt--) {
91 addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt);
92 if (addr == dest)
93 continue;
94 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
95 }
96 }
97 desc->group_head = NULL;
98}
99
100static void
101iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
102{
103 struct dma_async_tx_descriptor *tx = &desc->async_tx;
104 struct iop_adma_desc_slot *unmap = desc->group_head;
105 struct device *dev = &iop_chan->device->pdev->dev;
106 u32 len = unmap->unmap_len;
107 enum dma_ctrl_flags flags = tx->flags;
108 u32 src_cnt = unmap->unmap_src_cnt;
109 dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan);
110 dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan);
111 int i;
112
113 if (tx->flags & DMA_PREP_CONTINUE)
114 src_cnt -= 3;
115
116 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) {
117 dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL);
118 dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL);
119 }
120
121 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
122 dma_addr_t addr;
123
124 for (i = 0; i < src_cnt; i++) {
125 addr = iop_desc_get_src_addr(unmap, iop_chan, i);
126 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
127 }
128 if (desc->pq_check_result) {
129 dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE);
130 dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE);
131 }
132 }
133
134 desc->group_head = NULL;
135}
136
137
138static dma_cookie_t
139iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
140 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
141{
142 struct dma_async_tx_descriptor *tx = &desc->async_tx;
143
144 BUG_ON(tx->cookie < 0);
145 if (tx->cookie > 0) {
146 cookie = tx->cookie;
147 tx->cookie = 0;
148
149 /* call the callback (must not sleep or submit new
150 * operations to this channel)
151 */
152 if (tx->callback)
153 tx->callback(tx->callback_param);
154
155 /* unmap dma addresses
156 * (unmap_single vs unmap_page?)
157 */
158 if (desc->group_head && desc->unmap_len) {
159 if (iop_desc_is_pq(desc))
160 iop_desc_unmap_pq(iop_chan, desc);
161 else
162 iop_desc_unmap(iop_chan, desc);
163 }
164 }
165
166 /* run dependent operations */
167 dma_run_dependencies(tx);
168
169 return cookie;
170}
171
172static int
173iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
174 struct iop_adma_chan *iop_chan)
175{
176 /* the client is allowed to attach dependent operations
177 * until 'ack' is set
178 */
179 if (!async_tx_test_ack(&desc->async_tx))
180 return 0;
181
182 /* leave the last descriptor in the chain
183 * so we can append to it
184 */
185 if (desc->chain_node.next == &iop_chan->chain)
186 return 1;
187
188 dev_dbg(iop_chan->device->common.dev,
189 "\tfree slot: %d slots_per_op: %d\n",
190 desc->idx, desc->slots_per_op);
191
192 list_del(&desc->chain_node);
193 iop_adma_free_slots(desc);
194
195 return 0;
196}
197
198static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
199{
200 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
201 dma_cookie_t cookie = 0;
202 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
203 int busy = iop_chan_is_busy(iop_chan);
204 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
205
206 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
207 /* free completed slots from the chain starting with
208 * the oldest descriptor
209 */
210 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
211 chain_node) {
212 pr_debug("\tcookie: %d slot: %d busy: %d "
213 "this_desc: %#x next_desc: %#x ack: %d\n",
214 iter->async_tx.cookie, iter->idx, busy,
215 iter->async_tx.phys, iop_desc_get_next_desc(iter),
216 async_tx_test_ack(&iter->async_tx));
217 prefetch(_iter);
218 prefetch(&_iter->async_tx);
219
220 /* do not advance past the current descriptor loaded into the
221 * hardware channel, subsequent descriptors are either in
222 * process or have not been submitted
223 */
224 if (seen_current)
225 break;
226
227 /* stop the search if we reach the current descriptor and the
228 * channel is busy, or if it appears that the current descriptor
229 * needs to be re-read (i.e. has been appended to)
230 */
231 if (iter->async_tx.phys == current_desc) {
232 BUG_ON(seen_current++);
233 if (busy || iop_desc_get_next_desc(iter))
234 break;
235 }
236
237 /* detect the start of a group transaction */
238 if (!slot_cnt && !slots_per_op) {
239 slot_cnt = iter->slot_cnt;
240 slots_per_op = iter->slots_per_op;
241 if (slot_cnt <= slots_per_op) {
242 slot_cnt = 0;
243 slots_per_op = 0;
244 }
245 }
246
247 if (slot_cnt) {
248 pr_debug("\tgroup++\n");
249 if (!grp_start)
250 grp_start = iter;
251 slot_cnt -= slots_per_op;
252 }
253
254 /* all the members of a group are complete */
255 if (slots_per_op != 0 && slot_cnt == 0) {
256 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
257 int end_of_chain = 0;
258 pr_debug("\tgroup end\n");
259
260 /* collect the total results */
261 if (grp_start->xor_check_result) {
262 u32 zero_sum_result = 0;
263 slot_cnt = grp_start->slot_cnt;
264 grp_iter = grp_start;
265
266 list_for_each_entry_from(grp_iter,
267 &iop_chan->chain, chain_node) {
268 zero_sum_result |=
269 iop_desc_get_zero_result(grp_iter);
270 pr_debug("\titer%d result: %d\n",
271 grp_iter->idx, zero_sum_result);
272 slot_cnt -= slots_per_op;
273 if (slot_cnt == 0)
274 break;
275 }
276 pr_debug("\tgrp_start->xor_check_result: %p\n",
277 grp_start->xor_check_result);
278 *grp_start->xor_check_result = zero_sum_result;
279 }
280
281 /* clean up the group */
282 slot_cnt = grp_start->slot_cnt;
283 grp_iter = grp_start;
284 list_for_each_entry_safe_from(grp_iter, _grp_iter,
285 &iop_chan->chain, chain_node) {
286 cookie = iop_adma_run_tx_complete_actions(
287 grp_iter, iop_chan, cookie);
288
289 slot_cnt -= slots_per_op;
290 end_of_chain = iop_adma_clean_slot(grp_iter,
291 iop_chan);
292
293 if (slot_cnt == 0 || end_of_chain)
294 break;
295 }
296
297 /* the group should be complete at this point */
298 BUG_ON(slot_cnt);
299
300 slots_per_op = 0;
301 grp_start = NULL;
302 if (end_of_chain)
303 break;
304 else
305 continue;
306 } else if (slots_per_op) /* wait for group completion */
307 continue;
308
309 /* write back zero sum results (single descriptor case) */
310 if (iter->xor_check_result && iter->async_tx.cookie)
311 *iter->xor_check_result =
312 iop_desc_get_zero_result(iter);
313
314 cookie = iop_adma_run_tx_complete_actions(
315 iter, iop_chan, cookie);
316
317 if (iop_adma_clean_slot(iter, iop_chan))
318 break;
319 }
320
321 if (cookie > 0) {
322 iop_chan->common.completed_cookie = cookie;
323 pr_debug("\tcompleted cookie %d\n", cookie);
324 }
325}
326
327static void
328iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
329{
330 spin_lock_bh(&iop_chan->lock);
331 __iop_adma_slot_cleanup(iop_chan);
332 spin_unlock_bh(&iop_chan->lock);
333}
334
335static void iop_adma_tasklet(unsigned long data)
336{
337 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
338
339 /* lockdep will flag depedency submissions as potentially
340 * recursive locking, this is not the case as a dependency
341 * submission will never recurse a channels submit routine.
342 * There are checks in async_tx.c to prevent this.
343 */
344 spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
345 __iop_adma_slot_cleanup(iop_chan);
346 spin_unlock(&iop_chan->lock);
347}
348
349static struct iop_adma_desc_slot *
350iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
351 int slots_per_op)
352{
353 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
354 LIST_HEAD(chain);
355 int slots_found, retry = 0;
356
357 /* start search from the last allocated descrtiptor
358 * if a contiguous allocation can not be found start searching
359 * from the beginning of the list
360 */
361retry:
362 slots_found = 0;
363 if (retry == 0)
364 iter = iop_chan->last_used;
365 else
366 iter = list_entry(&iop_chan->all_slots,
367 struct iop_adma_desc_slot,
368 slot_node);
369
370 list_for_each_entry_safe_continue(
371 iter, _iter, &iop_chan->all_slots, slot_node) {
372 prefetch(_iter);
373 prefetch(&_iter->async_tx);
374 if (iter->slots_per_op) {
375 /* give up after finding the first busy slot
376 * on the second pass through the list
377 */
378 if (retry)
379 break;
380
381 slots_found = 0;
382 continue;
383 }
384
385 /* start the allocation if the slot is correctly aligned */
386 if (!slots_found++) {
387 if (iop_desc_is_aligned(iter, slots_per_op))
388 alloc_start = iter;
389 else {
390 slots_found = 0;
391 continue;
392 }
393 }
394
395 if (slots_found == num_slots) {
396 struct iop_adma_desc_slot *alloc_tail = NULL;
397 struct iop_adma_desc_slot *last_used = NULL;
398 iter = alloc_start;
399 while (num_slots) {
400 int i;
401 dev_dbg(iop_chan->device->common.dev,
402 "allocated slot: %d "
403 "(desc %p phys: %#x) slots_per_op %d\n",
404 iter->idx, iter->hw_desc,
405 iter->async_tx.phys, slots_per_op);
406
407 /* pre-ack all but the last descriptor */
408 if (num_slots != slots_per_op)
409 async_tx_ack(&iter->async_tx);
410
411 list_add_tail(&iter->chain_node, &chain);
412 alloc_tail = iter;
413 iter->async_tx.cookie = 0;
414 iter->slot_cnt = num_slots;
415 iter->xor_check_result = NULL;
416 for (i = 0; i < slots_per_op; i++) {
417 iter->slots_per_op = slots_per_op - i;
418 last_used = iter;
419 iter = list_entry(iter->slot_node.next,
420 struct iop_adma_desc_slot,
421 slot_node);
422 }
423 num_slots -= slots_per_op;
424 }
425 alloc_tail->group_head = alloc_start;
426 alloc_tail->async_tx.cookie = -EBUSY;
427 list_splice(&chain, &alloc_tail->tx_list);
428 iop_chan->last_used = last_used;
429 iop_desc_clear_next_desc(alloc_start);
430 iop_desc_clear_next_desc(alloc_tail);
431 return alloc_tail;
432 }
433 }
434 if (!retry++)
435 goto retry;
436
437 /* perform direct reclaim if the allocation fails */
438 __iop_adma_slot_cleanup(iop_chan);
439
440 return NULL;
441}
442
443static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
444{
445 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
446 iop_chan->pending);
447
448 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
449 iop_chan->pending = 0;
450 iop_chan_append(iop_chan);
451 }
452}
453
454static dma_cookie_t
455iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
456{
457 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
458 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
459 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
460 int slot_cnt;
461 int slots_per_op;
462 dma_cookie_t cookie;
463 dma_addr_t next_dma;
464
465 grp_start = sw_desc->group_head;
466 slot_cnt = grp_start->slot_cnt;
467 slots_per_op = grp_start->slots_per_op;
468
469 spin_lock_bh(&iop_chan->lock);
470 cookie = dma_cookie_assign(tx);
471
472 old_chain_tail = list_entry(iop_chan->chain.prev,
473 struct iop_adma_desc_slot, chain_node);
474 list_splice_init(&sw_desc->tx_list,
475 &old_chain_tail->chain_node);
476
477 /* fix up the hardware chain */
478 next_dma = grp_start->async_tx.phys;
479 iop_desc_set_next_desc(old_chain_tail, next_dma);
480 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
481
482 /* check for pre-chained descriptors */
483 iop_paranoia(iop_desc_get_next_desc(sw_desc));
484
485 /* increment the pending count by the number of slots
486 * memcpy operations have a 1:1 (slot:operation) relation
487 * other operations are heavier and will pop the threshold
488 * more often.
489 */
490 iop_chan->pending += slot_cnt;
491 iop_adma_check_threshold(iop_chan);
492 spin_unlock_bh(&iop_chan->lock);
493
494 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
495 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
496
497 return cookie;
498}
499
500static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
501static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
502
503/**
504 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
505 * @chan - allocate descriptor resources for this channel
506 * @client - current client requesting the channel be ready for requests
507 *
508 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
509 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
510 * greater than 2x the number slots needed to satisfy a device->max_xor
511 * request.
512 * */
513static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
514{
515 char *hw_desc;
516 int idx;
517 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
518 struct iop_adma_desc_slot *slot = NULL;
519 int init = iop_chan->slots_allocated ? 0 : 1;
520 struct iop_adma_platform_data *plat_data =
521 iop_chan->device->pdev->dev.platform_data;
522 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
523
524 /* Allocate descriptor slots */
525 do {
526 idx = iop_chan->slots_allocated;
527 if (idx == num_descs_in_pool)
528 break;
529
530 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
531 if (!slot) {
532 printk(KERN_INFO "IOP ADMA Channel only initialized"
533 " %d descriptor slots", idx);
534 break;
535 }
536 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
537 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
538
539 dma_async_tx_descriptor_init(&slot->async_tx, chan);
540 slot->async_tx.tx_submit = iop_adma_tx_submit;
541 INIT_LIST_HEAD(&slot->tx_list);
542 INIT_LIST_HEAD(&slot->chain_node);
543 INIT_LIST_HEAD(&slot->slot_node);
544 hw_desc = (char *) iop_chan->device->dma_desc_pool;
545 slot->async_tx.phys =
546 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
547 slot->idx = idx;
548
549 spin_lock_bh(&iop_chan->lock);
550 iop_chan->slots_allocated++;
551 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
552 spin_unlock_bh(&iop_chan->lock);
553 } while (iop_chan->slots_allocated < num_descs_in_pool);
554
555 if (idx && !iop_chan->last_used)
556 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
557 struct iop_adma_desc_slot,
558 slot_node);
559
560 dev_dbg(iop_chan->device->common.dev,
561 "allocated %d descriptor slots last_used: %p\n",
562 iop_chan->slots_allocated, iop_chan->last_used);
563
564 /* initialize the channel and the chain with a null operation */
565 if (init) {
566 if (dma_has_cap(DMA_MEMCPY,
567 iop_chan->device->common.cap_mask))
568 iop_chan_start_null_memcpy(iop_chan);
569 else if (dma_has_cap(DMA_XOR,
570 iop_chan->device->common.cap_mask))
571 iop_chan_start_null_xor(iop_chan);
572 else
573 BUG();
574 }
575
576 return (idx > 0) ? idx : -ENOMEM;
577}
578
579static struct dma_async_tx_descriptor *
580iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
581{
582 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
583 struct iop_adma_desc_slot *sw_desc, *grp_start;
584 int slot_cnt, slots_per_op;
585
586 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
587
588 spin_lock_bh(&iop_chan->lock);
589 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
590 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
591 if (sw_desc) {
592 grp_start = sw_desc->group_head;
593 iop_desc_init_interrupt(grp_start, iop_chan);
594 grp_start->unmap_len = 0;
595 sw_desc->async_tx.flags = flags;
596 }
597 spin_unlock_bh(&iop_chan->lock);
598
599 return sw_desc ? &sw_desc->async_tx : NULL;
600}
601
602static struct dma_async_tx_descriptor *
603iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
604 dma_addr_t dma_src, size_t len, unsigned long flags)
605{
606 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
607 struct iop_adma_desc_slot *sw_desc, *grp_start;
608 int slot_cnt, slots_per_op;
609
610 if (unlikely(!len))
611 return NULL;
612 BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT);
613
614 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
615 __func__, len);
616
617 spin_lock_bh(&iop_chan->lock);
618 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
619 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
620 if (sw_desc) {
621 grp_start = sw_desc->group_head;
622 iop_desc_init_memcpy(grp_start, flags);
623 iop_desc_set_byte_count(grp_start, iop_chan, len);
624 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
625 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
626 sw_desc->unmap_src_cnt = 1;
627 sw_desc->unmap_len = len;
628 sw_desc->async_tx.flags = flags;
629 }
630 spin_unlock_bh(&iop_chan->lock);
631
632 return sw_desc ? &sw_desc->async_tx : NULL;
633}
634
635static struct dma_async_tx_descriptor *
636iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
637 int value, size_t len, unsigned long flags)
638{
639 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
640 struct iop_adma_desc_slot *sw_desc, *grp_start;
641 int slot_cnt, slots_per_op;
642
643 if (unlikely(!len))
644 return NULL;
645 BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT);
646
647 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
648 __func__, len);
649
650 spin_lock_bh(&iop_chan->lock);
651 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
652 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
653 if (sw_desc) {
654 grp_start = sw_desc->group_head;
655 iop_desc_init_memset(grp_start, flags);
656 iop_desc_set_byte_count(grp_start, iop_chan, len);
657 iop_desc_set_block_fill_val(grp_start, value);
658 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
659 sw_desc->unmap_src_cnt = 1;
660 sw_desc->unmap_len = len;
661 sw_desc->async_tx.flags = flags;
662 }
663 spin_unlock_bh(&iop_chan->lock);
664
665 return sw_desc ? &sw_desc->async_tx : NULL;
666}
667
668static struct dma_async_tx_descriptor *
669iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
670 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
671 unsigned long flags)
672{
673 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
674 struct iop_adma_desc_slot *sw_desc, *grp_start;
675 int slot_cnt, slots_per_op;
676
677 if (unlikely(!len))
678 return NULL;
679 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
680
681 dev_dbg(iop_chan->device->common.dev,
682 "%s src_cnt: %d len: %u flags: %lx\n",
683 __func__, src_cnt, len, flags);
684
685 spin_lock_bh(&iop_chan->lock);
686 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
687 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
688 if (sw_desc) {
689 grp_start = sw_desc->group_head;
690 iop_desc_init_xor(grp_start, src_cnt, flags);
691 iop_desc_set_byte_count(grp_start, iop_chan, len);
692 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
693 sw_desc->unmap_src_cnt = src_cnt;
694 sw_desc->unmap_len = len;
695 sw_desc->async_tx.flags = flags;
696 while (src_cnt--)
697 iop_desc_set_xor_src_addr(grp_start, src_cnt,
698 dma_src[src_cnt]);
699 }
700 spin_unlock_bh(&iop_chan->lock);
701
702 return sw_desc ? &sw_desc->async_tx : NULL;
703}
704
705static struct dma_async_tx_descriptor *
706iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
707 unsigned int src_cnt, size_t len, u32 *result,
708 unsigned long flags)
709{
710 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
711 struct iop_adma_desc_slot *sw_desc, *grp_start;
712 int slot_cnt, slots_per_op;
713
714 if (unlikely(!len))
715 return NULL;
716
717 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
718 __func__, src_cnt, len);
719
720 spin_lock_bh(&iop_chan->lock);
721 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
722 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
723 if (sw_desc) {
724 grp_start = sw_desc->group_head;
725 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
726 iop_desc_set_zero_sum_byte_count(grp_start, len);
727 grp_start->xor_check_result = result;
728 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
729 __func__, grp_start->xor_check_result);
730 sw_desc->unmap_src_cnt = src_cnt;
731 sw_desc->unmap_len = len;
732 sw_desc->async_tx.flags = flags;
733 while (src_cnt--)
734 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
735 dma_src[src_cnt]);
736 }
737 spin_unlock_bh(&iop_chan->lock);
738
739 return sw_desc ? &sw_desc->async_tx : NULL;
740}
741
742static struct dma_async_tx_descriptor *
743iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
744 unsigned int src_cnt, const unsigned char *scf, size_t len,
745 unsigned long flags)
746{
747 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
748 struct iop_adma_desc_slot *sw_desc, *g;
749 int slot_cnt, slots_per_op;
750 int continue_srcs;
751
752 if (unlikely(!len))
753 return NULL;
754 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
755
756 dev_dbg(iop_chan->device->common.dev,
757 "%s src_cnt: %d len: %u flags: %lx\n",
758 __func__, src_cnt, len, flags);
759
760 if (dmaf_p_disabled_continue(flags))
761 continue_srcs = 1+src_cnt;
762 else if (dmaf_continue(flags))
763 continue_srcs = 3+src_cnt;
764 else
765 continue_srcs = 0+src_cnt;
766
767 spin_lock_bh(&iop_chan->lock);
768 slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
769 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
770 if (sw_desc) {
771 int i;
772
773 g = sw_desc->group_head;
774 iop_desc_set_byte_count(g, iop_chan, len);
775
776 /* even if P is disabled its destination address (bits
777 * [3:0]) must match Q. It is ok if P points to an
778 * invalid address, it won't be written.
779 */
780 if (flags & DMA_PREP_PQ_DISABLE_P)
781 dst[0] = dst[1] & 0x7;
782
783 iop_desc_set_pq_addr(g, dst);
784 sw_desc->unmap_src_cnt = src_cnt;
785 sw_desc->unmap_len = len;
786 sw_desc->async_tx.flags = flags;
787 for (i = 0; i < src_cnt; i++)
788 iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
789
790 /* if we are continuing a previous operation factor in
791 * the old p and q values, see the comment for dma_maxpq
792 * in include/linux/dmaengine.h
793 */
794 if (dmaf_p_disabled_continue(flags))
795 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
796 else if (dmaf_continue(flags)) {
797 iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
798 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
799 iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
800 }
801 iop_desc_init_pq(g, i, flags);
802 }
803 spin_unlock_bh(&iop_chan->lock);
804
805 return sw_desc ? &sw_desc->async_tx : NULL;
806}
807
808static struct dma_async_tx_descriptor *
809iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
810 unsigned int src_cnt, const unsigned char *scf,
811 size_t len, enum sum_check_flags *pqres,
812 unsigned long flags)
813{
814 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
815 struct iop_adma_desc_slot *sw_desc, *g;
816 int slot_cnt, slots_per_op;
817
818 if (unlikely(!len))
819 return NULL;
820 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
821
822 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
823 __func__, src_cnt, len);
824
825 spin_lock_bh(&iop_chan->lock);
826 slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
827 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
828 if (sw_desc) {
829 /* for validate operations p and q are tagged onto the
830 * end of the source list
831 */
832 int pq_idx = src_cnt;
833
834 g = sw_desc->group_head;
835 iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
836 iop_desc_set_pq_zero_sum_byte_count(g, len);
837 g->pq_check_result = pqres;
838 pr_debug("\t%s: g->pq_check_result: %p\n",
839 __func__, g->pq_check_result);
840 sw_desc->unmap_src_cnt = src_cnt+2;
841 sw_desc->unmap_len = len;
842 sw_desc->async_tx.flags = flags;
843 while (src_cnt--)
844 iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
845 src[src_cnt],
846 scf[src_cnt]);
847 iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
848 }
849 spin_unlock_bh(&iop_chan->lock);
850
851 return sw_desc ? &sw_desc->async_tx : NULL;
852}
853
854static void iop_adma_free_chan_resources(struct dma_chan *chan)
855{
856 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
857 struct iop_adma_desc_slot *iter, *_iter;
858 int in_use_descs = 0;
859
860 iop_adma_slot_cleanup(iop_chan);
861
862 spin_lock_bh(&iop_chan->lock);
863 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
864 chain_node) {
865 in_use_descs++;
866 list_del(&iter->chain_node);
867 }
868 list_for_each_entry_safe_reverse(
869 iter, _iter, &iop_chan->all_slots, slot_node) {
870 list_del(&iter->slot_node);
871 kfree(iter);
872 iop_chan->slots_allocated--;
873 }
874 iop_chan->last_used = NULL;
875
876 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
877 __func__, iop_chan->slots_allocated);
878 spin_unlock_bh(&iop_chan->lock);
879
880 /* one is ok since we left it on there on purpose */
881 if (in_use_descs > 1)
882 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
883 in_use_descs - 1);
884}
885
886/**
887 * iop_adma_status - poll the status of an ADMA transaction
888 * @chan: ADMA channel handle
889 * @cookie: ADMA transaction identifier
890 * @txstate: a holder for the current state of the channel or NULL
891 */
892static enum dma_status iop_adma_status(struct dma_chan *chan,
893 dma_cookie_t cookie,
894 struct dma_tx_state *txstate)
895{
896 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
897 int ret;
898
899 ret = dma_cookie_status(chan, cookie, txstate);
900 if (ret == DMA_SUCCESS)
901 return ret;
902
903 iop_adma_slot_cleanup(iop_chan);
904
905 return dma_cookie_status(chan, cookie, txstate);
906}
907
908static irqreturn_t iop_adma_eot_handler(int irq, void *data)
909{
910 struct iop_adma_chan *chan = data;
911
912 dev_dbg(chan->device->common.dev, "%s\n", __func__);
913
914 tasklet_schedule(&chan->irq_tasklet);
915
916 iop_adma_device_clear_eot_status(chan);
917
918 return IRQ_HANDLED;
919}
920
921static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
922{
923 struct iop_adma_chan *chan = data;
924
925 dev_dbg(chan->device->common.dev, "%s\n", __func__);
926
927 tasklet_schedule(&chan->irq_tasklet);
928
929 iop_adma_device_clear_eoc_status(chan);
930
931 return IRQ_HANDLED;
932}
933
934static irqreturn_t iop_adma_err_handler(int irq, void *data)
935{
936 struct iop_adma_chan *chan = data;
937 unsigned long status = iop_chan_get_status(chan);
938
939 dev_printk(KERN_ERR, chan->device->common.dev,
940 "error ( %s%s%s%s%s%s%s)\n",
941 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
942 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
943 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
944 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
945 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
946 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
947 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
948
949 iop_adma_device_clear_err_status(chan);
950
951 BUG();
952
953 return IRQ_HANDLED;
954}
955
956static void iop_adma_issue_pending(struct dma_chan *chan)
957{
958 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
959
960 if (iop_chan->pending) {
961 iop_chan->pending = 0;
962 iop_chan_append(iop_chan);
963 }
964}
965
966/*
967 * Perform a transaction to verify the HW works.
968 */
969#define IOP_ADMA_TEST_SIZE 2000
970
971static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
972{
973 int i;
974 void *src, *dest;
975 dma_addr_t src_dma, dest_dma;
976 struct dma_chan *dma_chan;
977 dma_cookie_t cookie;
978 struct dma_async_tx_descriptor *tx;
979 int err = 0;
980 struct iop_adma_chan *iop_chan;
981
982 dev_dbg(device->common.dev, "%s\n", __func__);
983
984 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
985 if (!src)
986 return -ENOMEM;
987 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
988 if (!dest) {
989 kfree(src);
990 return -ENOMEM;
991 }
992
993 /* Fill in src buffer */
994 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
995 ((u8 *) src)[i] = (u8)i;
996
997 /* Start copy, using first DMA channel */
998 dma_chan = container_of(device->common.channels.next,
999 struct dma_chan,
1000 device_node);
1001 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1002 err = -ENODEV;
1003 goto out;
1004 }
1005
1006 dest_dma = dma_map_single(dma_chan->device->dev, dest,
1007 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1008 src_dma = dma_map_single(dma_chan->device->dev, src,
1009 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
1010 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
1011 IOP_ADMA_TEST_SIZE,
1012 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1013
1014 cookie = iop_adma_tx_submit(tx);
1015 iop_adma_issue_pending(dma_chan);
1016 msleep(1);
1017
1018 if (iop_adma_status(dma_chan, cookie, NULL) !=
1019 DMA_SUCCESS) {
1020 dev_printk(KERN_ERR, dma_chan->device->dev,
1021 "Self-test copy timed out, disabling\n");
1022 err = -ENODEV;
1023 goto free_resources;
1024 }
1025
1026 iop_chan = to_iop_adma_chan(dma_chan);
1027 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1028 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1029 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
1030 dev_printk(KERN_ERR, dma_chan->device->dev,
1031 "Self-test copy failed compare, disabling\n");
1032 err = -ENODEV;
1033 goto free_resources;
1034 }
1035
1036free_resources:
1037 iop_adma_free_chan_resources(dma_chan);
1038out:
1039 kfree(src);
1040 kfree(dest);
1041 return err;
1042}
1043
1044#define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
1045static int __devinit
1046iop_adma_xor_val_self_test(struct iop_adma_device *device)
1047{
1048 int i, src_idx;
1049 struct page *dest;
1050 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
1051 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1052 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1053 dma_addr_t dma_addr, dest_dma;
1054 struct dma_async_tx_descriptor *tx;
1055 struct dma_chan *dma_chan;
1056 dma_cookie_t cookie;
1057 u8 cmp_byte = 0;
1058 u32 cmp_word;
1059 u32 zero_sum_result;
1060 int err = 0;
1061 struct iop_adma_chan *iop_chan;
1062
1063 dev_dbg(device->common.dev, "%s\n", __func__);
1064
1065 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1066 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1067 if (!xor_srcs[src_idx]) {
1068 while (src_idx--)
1069 __free_page(xor_srcs[src_idx]);
1070 return -ENOMEM;
1071 }
1072 }
1073
1074 dest = alloc_page(GFP_KERNEL);
1075 if (!dest) {
1076 while (src_idx--)
1077 __free_page(xor_srcs[src_idx]);
1078 return -ENOMEM;
1079 }
1080
1081 /* Fill in src buffers */
1082 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1083 u8 *ptr = page_address(xor_srcs[src_idx]);
1084 for (i = 0; i < PAGE_SIZE; i++)
1085 ptr[i] = (1 << src_idx);
1086 }
1087
1088 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
1089 cmp_byte ^= (u8) (1 << src_idx);
1090
1091 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1092 (cmp_byte << 8) | cmp_byte;
1093
1094 memset(page_address(dest), 0, PAGE_SIZE);
1095
1096 dma_chan = container_of(device->common.channels.next,
1097 struct dma_chan,
1098 device_node);
1099 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1100 err = -ENODEV;
1101 goto out;
1102 }
1103
1104 /* test xor */
1105 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
1106 PAGE_SIZE, DMA_FROM_DEVICE);
1107 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1108 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1109 0, PAGE_SIZE, DMA_TO_DEVICE);
1110 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1111 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
1112 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1113
1114 cookie = iop_adma_tx_submit(tx);
1115 iop_adma_issue_pending(dma_chan);
1116 msleep(8);
1117
1118 if (iop_adma_status(dma_chan, cookie, NULL) !=
1119 DMA_SUCCESS) {
1120 dev_printk(KERN_ERR, dma_chan->device->dev,
1121 "Self-test xor timed out, disabling\n");
1122 err = -ENODEV;
1123 goto free_resources;
1124 }
1125
1126 iop_chan = to_iop_adma_chan(dma_chan);
1127 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1128 PAGE_SIZE, DMA_FROM_DEVICE);
1129 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1130 u32 *ptr = page_address(dest);
1131 if (ptr[i] != cmp_word) {
1132 dev_printk(KERN_ERR, dma_chan->device->dev,
1133 "Self-test xor failed compare, disabling\n");
1134 err = -ENODEV;
1135 goto free_resources;
1136 }
1137 }
1138 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1139 PAGE_SIZE, DMA_TO_DEVICE);
1140
1141 /* skip zero sum if the capability is not present */
1142 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1143 goto free_resources;
1144
1145 /* zero sum the sources with the destintation page */
1146 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1147 zero_sum_srcs[i] = xor_srcs[i];
1148 zero_sum_srcs[i] = dest;
1149
1150 zero_sum_result = 1;
1151
1152 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1153 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1154 zero_sum_srcs[i], 0, PAGE_SIZE,
1155 DMA_TO_DEVICE);
1156 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1157 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1158 &zero_sum_result,
1159 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1160
1161 cookie = iop_adma_tx_submit(tx);
1162 iop_adma_issue_pending(dma_chan);
1163 msleep(8);
1164
1165 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1166 dev_printk(KERN_ERR, dma_chan->device->dev,
1167 "Self-test zero sum timed out, disabling\n");
1168 err = -ENODEV;
1169 goto free_resources;
1170 }
1171
1172 if (zero_sum_result != 0) {
1173 dev_printk(KERN_ERR, dma_chan->device->dev,
1174 "Self-test zero sum failed compare, disabling\n");
1175 err = -ENODEV;
1176 goto free_resources;
1177 }
1178
1179 /* test memset */
1180 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1181 PAGE_SIZE, DMA_FROM_DEVICE);
1182 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1183 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1184
1185 cookie = iop_adma_tx_submit(tx);
1186 iop_adma_issue_pending(dma_chan);
1187 msleep(8);
1188
1189 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1190 dev_printk(KERN_ERR, dma_chan->device->dev,
1191 "Self-test memset timed out, disabling\n");
1192 err = -ENODEV;
1193 goto free_resources;
1194 }
1195
1196 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1197 u32 *ptr = page_address(dest);
1198 if (ptr[i]) {
1199 dev_printk(KERN_ERR, dma_chan->device->dev,
1200 "Self-test memset failed compare, disabling\n");
1201 err = -ENODEV;
1202 goto free_resources;
1203 }
1204 }
1205
1206 /* test for non-zero parity sum */
1207 zero_sum_result = 0;
1208 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1209 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1210 zero_sum_srcs[i], 0, PAGE_SIZE,
1211 DMA_TO_DEVICE);
1212 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1213 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1214 &zero_sum_result,
1215 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1216
1217 cookie = iop_adma_tx_submit(tx);
1218 iop_adma_issue_pending(dma_chan);
1219 msleep(8);
1220
1221 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
1222 dev_printk(KERN_ERR, dma_chan->device->dev,
1223 "Self-test non-zero sum timed out, disabling\n");
1224 err = -ENODEV;
1225 goto free_resources;
1226 }
1227
1228 if (zero_sum_result != 1) {
1229 dev_printk(KERN_ERR, dma_chan->device->dev,
1230 "Self-test non-zero sum failed compare, disabling\n");
1231 err = -ENODEV;
1232 goto free_resources;
1233 }
1234
1235free_resources:
1236 iop_adma_free_chan_resources(dma_chan);
1237out:
1238 src_idx = IOP_ADMA_NUM_SRC_TEST;
1239 while (src_idx--)
1240 __free_page(xor_srcs[src_idx]);
1241 __free_page(dest);
1242 return err;
1243}
1244
1245#ifdef CONFIG_RAID6_PQ
1246static int __devinit
1247iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
1248{
1249 /* combined sources, software pq results, and extra hw pq results */
1250 struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2];
1251 /* ptr to the extra hw pq buffers defined above */
1252 struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
1253 /* address conversion buffers (dma_map / page_address) */
1254 void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
1255 dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
1256 dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST];
1257
1258 int i;
1259 struct dma_async_tx_descriptor *tx;
1260 struct dma_chan *dma_chan;
1261 dma_cookie_t cookie;
1262 u32 zero_sum_result;
1263 int err = 0;
1264 struct device *dev;
1265
1266 dev_dbg(device->common.dev, "%s\n", __func__);
1267
1268 for (i = 0; i < ARRAY_SIZE(pq); i++) {
1269 pq[i] = alloc_page(GFP_KERNEL);
1270 if (!pq[i]) {
1271 while (i--)
1272 __free_page(pq[i]);
1273 return -ENOMEM;
1274 }
1275 }
1276
1277 /* Fill in src buffers */
1278 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) {
1279 pq_sw[i] = page_address(pq[i]);
1280 memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE);
1281 }
1282 pq_sw[i] = page_address(pq[i]);
1283 pq_sw[i+1] = page_address(pq[i+1]);
1284
1285 dma_chan = container_of(device->common.channels.next,
1286 struct dma_chan,
1287 device_node);
1288 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1289 err = -ENODEV;
1290 goto out;
1291 }
1292
1293 dev = dma_chan->device->dev;
1294
1295 /* initialize the dests */
1296 memset(page_address(pq_hw[0]), 0 , PAGE_SIZE);
1297 memset(page_address(pq_hw[1]), 0 , PAGE_SIZE);
1298
1299 /* test pq */
1300 pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1301 pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1302 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1303 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1304 DMA_TO_DEVICE);
1305
1306 tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src,
1307 IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp,
1308 PAGE_SIZE,
1309 DMA_PREP_INTERRUPT |
1310 DMA_CTRL_ACK);
1311
1312 cookie = iop_adma_tx_submit(tx);
1313 iop_adma_issue_pending(dma_chan);
1314 msleep(8);
1315
1316 if (iop_adma_status(dma_chan, cookie, NULL) !=
1317 DMA_SUCCESS) {
1318 dev_err(dev, "Self-test pq timed out, disabling\n");
1319 err = -ENODEV;
1320 goto free_resources;
1321 }
1322
1323 raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw);
1324
1325 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST],
1326 page_address(pq_hw[0]), PAGE_SIZE) != 0) {
1327 dev_err(dev, "Self-test p failed compare, disabling\n");
1328 err = -ENODEV;
1329 goto free_resources;
1330 }
1331 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1],
1332 page_address(pq_hw[1]), PAGE_SIZE) != 0) {
1333 dev_err(dev, "Self-test q failed compare, disabling\n");
1334 err = -ENODEV;
1335 goto free_resources;
1336 }
1337
1338 /* test correct zero sum using the software generated pq values */
1339 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1340 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1341 DMA_TO_DEVICE);
1342
1343 zero_sum_result = ~0;
1344 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1345 pq_src, IOP_ADMA_NUM_SRC_TEST,
1346 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1347 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1348
1349 cookie = iop_adma_tx_submit(tx);
1350 iop_adma_issue_pending(dma_chan);
1351 msleep(8);
1352
1353 if (iop_adma_status(dma_chan, cookie, NULL) !=
1354 DMA_SUCCESS) {
1355 dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n");
1356 err = -ENODEV;
1357 goto free_resources;
1358 }
1359
1360 if (zero_sum_result != 0) {
1361 dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n",
1362 zero_sum_result);
1363 err = -ENODEV;
1364 goto free_resources;
1365 }
1366
1367 /* test incorrect zero sum */
1368 i = IOP_ADMA_NUM_SRC_TEST;
1369 memset(pq_sw[i] + 100, 0, 100);
1370 memset(pq_sw[i+1] + 200, 0, 200);
1371 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1372 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1373 DMA_TO_DEVICE);
1374
1375 zero_sum_result = 0;
1376 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1377 pq_src, IOP_ADMA_NUM_SRC_TEST,
1378 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1379 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1380
1381 cookie = iop_adma_tx_submit(tx);
1382 iop_adma_issue_pending(dma_chan);
1383 msleep(8);
1384
1385 if (iop_adma_status(dma_chan, cookie, NULL) !=
1386 DMA_SUCCESS) {
1387 dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n");
1388 err = -ENODEV;
1389 goto free_resources;
1390 }
1391
1392 if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) {
1393 dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n",
1394 zero_sum_result);
1395 err = -ENODEV;
1396 goto free_resources;
1397 }
1398
1399free_resources:
1400 iop_adma_free_chan_resources(dma_chan);
1401out:
1402 i = ARRAY_SIZE(pq);
1403 while (i--)
1404 __free_page(pq[i]);
1405 return err;
1406}
1407#endif
1408
1409static int __devexit iop_adma_remove(struct platform_device *dev)
1410{
1411 struct iop_adma_device *device = platform_get_drvdata(dev);
1412 struct dma_chan *chan, *_chan;
1413 struct iop_adma_chan *iop_chan;
1414 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1415
1416 dma_async_device_unregister(&device->common);
1417
1418 dma_free_coherent(&dev->dev, plat_data->pool_size,
1419 device->dma_desc_pool_virt, device->dma_desc_pool);
1420
1421 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1422 device_node) {
1423 iop_chan = to_iop_adma_chan(chan);
1424 list_del(&chan->device_node);
1425 kfree(iop_chan);
1426 }
1427 kfree(device);
1428
1429 return 0;
1430}
1431
1432static int __devinit iop_adma_probe(struct platform_device *pdev)
1433{
1434 struct resource *res;
1435 int ret = 0, i;
1436 struct iop_adma_device *adev;
1437 struct iop_adma_chan *iop_chan;
1438 struct dma_device *dma_dev;
1439 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1440
1441 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1442 if (!res)
1443 return -ENODEV;
1444
1445 if (!devm_request_mem_region(&pdev->dev, res->start,
1446 resource_size(res), pdev->name))
1447 return -EBUSY;
1448
1449 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1450 if (!adev)
1451 return -ENOMEM;
1452 dma_dev = &adev->common;
1453
1454 /* allocate coherent memory for hardware descriptors
1455 * note: writecombine gives slightly better performance, but
1456 * requires that we explicitly flush the writes
1457 */
1458 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1459 plat_data->pool_size,
1460 &adev->dma_desc_pool,
1461 GFP_KERNEL)) == NULL) {
1462 ret = -ENOMEM;
1463 goto err_free_adev;
1464 }
1465
1466 dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %p\n",
1467 __func__, adev->dma_desc_pool_virt,
1468 (void *) adev->dma_desc_pool);
1469
1470 adev->id = plat_data->hw_id;
1471
1472 /* discover transaction capabilites from the platform data */
1473 dma_dev->cap_mask = plat_data->cap_mask;
1474
1475 adev->pdev = pdev;
1476 platform_set_drvdata(pdev, adev);
1477
1478 INIT_LIST_HEAD(&dma_dev->channels);
1479
1480 /* set base routines */
1481 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1482 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1483 dma_dev->device_tx_status = iop_adma_status;
1484 dma_dev->device_issue_pending = iop_adma_issue_pending;
1485 dma_dev->dev = &pdev->dev;
1486
1487 /* set prep routines based on capability */
1488 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1489 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1490 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1491 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1492 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1493 dma_dev->max_xor = iop_adma_get_max_xor();
1494 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1495 }
1496 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1497 dma_dev->device_prep_dma_xor_val =
1498 iop_adma_prep_dma_xor_val;
1499 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1500 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1501 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1502 }
1503 if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1504 dma_dev->device_prep_dma_pq_val =
1505 iop_adma_prep_dma_pq_val;
1506 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1507 dma_dev->device_prep_dma_interrupt =
1508 iop_adma_prep_dma_interrupt;
1509
1510 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1511 if (!iop_chan) {
1512 ret = -ENOMEM;
1513 goto err_free_dma;
1514 }
1515 iop_chan->device = adev;
1516
1517 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1518 resource_size(res));
1519 if (!iop_chan->mmr_base) {
1520 ret = -ENOMEM;
1521 goto err_free_iop_chan;
1522 }
1523 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1524 iop_chan);
1525
1526 /* clear errors before enabling interrupts */
1527 iop_adma_device_clear_err_status(iop_chan);
1528
1529 for (i = 0; i < 3; i++) {
1530 irq_handler_t handler[] = { iop_adma_eot_handler,
1531 iop_adma_eoc_handler,
1532 iop_adma_err_handler };
1533 int irq = platform_get_irq(pdev, i);
1534 if (irq < 0) {
1535 ret = -ENXIO;
1536 goto err_free_iop_chan;
1537 } else {
1538 ret = devm_request_irq(&pdev->dev, irq,
1539 handler[i], 0, pdev->name, iop_chan);
1540 if (ret)
1541 goto err_free_iop_chan;
1542 }
1543 }
1544
1545 spin_lock_init(&iop_chan->lock);
1546 INIT_LIST_HEAD(&iop_chan->chain);
1547 INIT_LIST_HEAD(&iop_chan->all_slots);
1548 iop_chan->common.device = dma_dev;
1549 dma_cookie_init(&iop_chan->common);
1550 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1551
1552 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1553 ret = iop_adma_memcpy_self_test(adev);
1554 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1555 if (ret)
1556 goto err_free_iop_chan;
1557 }
1558
1559 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1560 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1561 ret = iop_adma_xor_val_self_test(adev);
1562 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1563 if (ret)
1564 goto err_free_iop_chan;
1565 }
1566
1567 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
1568 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
1569 #ifdef CONFIG_RAID6_PQ
1570 ret = iop_adma_pq_zero_sum_self_test(adev);
1571 dev_dbg(&pdev->dev, "pq self test returned %d\n", ret);
1572 #else
1573 /* can not test raid6, so do not publish capability */
1574 dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
1575 dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
1576 ret = 0;
1577 #endif
1578 if (ret)
1579 goto err_free_iop_chan;
1580 }
1581
1582 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1583 "( %s%s%s%s%s%s%s)\n",
1584 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1585 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1586 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1587 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1588 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1589 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1590 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1591
1592 dma_async_device_register(dma_dev);
1593 goto out;
1594
1595 err_free_iop_chan:
1596 kfree(iop_chan);
1597 err_free_dma:
1598 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1599 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1600 err_free_adev:
1601 kfree(adev);
1602 out:
1603 return ret;
1604}
1605
1606static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1607{
1608 struct iop_adma_desc_slot *sw_desc, *grp_start;
1609 dma_cookie_t cookie;
1610 int slot_cnt, slots_per_op;
1611
1612 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1613
1614 spin_lock_bh(&iop_chan->lock);
1615 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1616 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1617 if (sw_desc) {
1618 grp_start = sw_desc->group_head;
1619
1620 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1621 async_tx_ack(&sw_desc->async_tx);
1622 iop_desc_init_memcpy(grp_start, 0);
1623 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1624 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1625 iop_desc_set_memcpy_src_addr(grp_start, 0);
1626
1627 cookie = dma_cookie_assign(&sw_desc->async_tx);
1628
1629 /* initialize the completed cookie to be less than
1630 * the most recently used cookie
1631 */
1632 iop_chan->common.completed_cookie = cookie - 1;
1633
1634 /* channel should not be busy */
1635 BUG_ON(iop_chan_is_busy(iop_chan));
1636
1637 /* clear any prior error-status bits */
1638 iop_adma_device_clear_err_status(iop_chan);
1639
1640 /* disable operation */
1641 iop_chan_disable(iop_chan);
1642
1643 /* set the descriptor address */
1644 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1645
1646 /* 1/ don't add pre-chained descriptors
1647 * 2/ dummy read to flush next_desc write
1648 */
1649 BUG_ON(iop_desc_get_next_desc(sw_desc));
1650
1651 /* run the descriptor */
1652 iop_chan_enable(iop_chan);
1653 } else
1654 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1655 "failed to allocate null descriptor\n");
1656 spin_unlock_bh(&iop_chan->lock);
1657}
1658
1659static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1660{
1661 struct iop_adma_desc_slot *sw_desc, *grp_start;
1662 dma_cookie_t cookie;
1663 int slot_cnt, slots_per_op;
1664
1665 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1666
1667 spin_lock_bh(&iop_chan->lock);
1668 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1669 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1670 if (sw_desc) {
1671 grp_start = sw_desc->group_head;
1672 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
1673 async_tx_ack(&sw_desc->async_tx);
1674 iop_desc_init_null_xor(grp_start, 2, 0);
1675 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1676 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1677 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1678 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1679
1680 cookie = dma_cookie_assign(&sw_desc->async_tx);
1681
1682 /* initialize the completed cookie to be less than
1683 * the most recently used cookie
1684 */
1685 iop_chan->common.completed_cookie = cookie - 1;
1686
1687 /* channel should not be busy */
1688 BUG_ON(iop_chan_is_busy(iop_chan));
1689
1690 /* clear any prior error-status bits */
1691 iop_adma_device_clear_err_status(iop_chan);
1692
1693 /* disable operation */
1694 iop_chan_disable(iop_chan);
1695
1696 /* set the descriptor address */
1697 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1698
1699 /* 1/ don't add pre-chained descriptors
1700 * 2/ dummy read to flush next_desc write
1701 */
1702 BUG_ON(iop_desc_get_next_desc(sw_desc));
1703
1704 /* run the descriptor */
1705 iop_chan_enable(iop_chan);
1706 } else
1707 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1708 "failed to allocate null descriptor\n");
1709 spin_unlock_bh(&iop_chan->lock);
1710}
1711
1712static struct platform_driver iop_adma_driver = {
1713 .probe = iop_adma_probe,
1714 .remove = __devexit_p(iop_adma_remove),
1715 .driver = {
1716 .owner = THIS_MODULE,
1717 .name = "iop-adma",
1718 },
1719};
1720
1721module_platform_driver(iop_adma_driver);
1722
1723MODULE_AUTHOR("Intel Corporation");
1724MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1725MODULE_LICENSE("GPL");
1726MODULE_ALIAS("platform:iop-adma");