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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
8 * Copyright (C) 2008 Thiemo Seufer
9 * Copyright (C) 2012 MIPS Technologies, Inc.
10 */
11#include <linux/kernel.h>
12#include <linux/sched.h>
13#include <linux/smp.h>
14#include <linux/mm.h>
15#include <linux/proc_fs.h>
16
17#include <asm/bugs.h>
18#include <asm/cacheops.h>
19#include <asm/cpu-type.h>
20#include <asm/inst.h>
21#include <asm/io.h>
22#include <asm/page.h>
23#include <asm/prefetch.h>
24#include <asm/bootinfo.h>
25#include <asm/mipsregs.h>
26#include <asm/mmu_context.h>
27#include <asm/cpu.h>
28#include <asm/war.h>
29
30#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
31#include <asm/sibyte/sb1250.h>
32#include <asm/sibyte/sb1250_regs.h>
33#include <asm/sibyte/sb1250_dma.h>
34#endif
35
36#include <asm/uasm.h>
37
38/* Registers used in the assembled routines. */
39#define ZERO 0
40#define AT 2
41#define A0 4
42#define A1 5
43#define A2 6
44#define T0 8
45#define T1 9
46#define T2 10
47#define T3 11
48#define T9 25
49#define RA 31
50
51/* Handle labels (which must be positive integers). */
52enum label_id {
53 label_clear_nopref = 1,
54 label_clear_pref,
55 label_copy_nopref,
56 label_copy_pref_both,
57 label_copy_pref_store,
58};
59
60UASM_L_LA(_clear_nopref)
61UASM_L_LA(_clear_pref)
62UASM_L_LA(_copy_nopref)
63UASM_L_LA(_copy_pref_both)
64UASM_L_LA(_copy_pref_store)
65
66/* We need one branch and therefore one relocation per target label. */
67static struct uasm_label labels[5];
68static struct uasm_reloc relocs[5];
69
70#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
71#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
72
73/*
74 * R6 has a limited offset of the pref instruction.
75 * Skip it if the offset is more than 9 bits.
76 */
77#define _uasm_i_pref(a, b, c, d) \
78do { \
79 if (cpu_has_mips_r6) { \
80 if (c <= 0xff && c >= -0x100) \
81 uasm_i_pref(a, b, c, d);\
82 } else { \
83 uasm_i_pref(a, b, c, d); \
84 } \
85} while(0)
86
87static int pref_bias_clear_store;
88static int pref_bias_copy_load;
89static int pref_bias_copy_store;
90
91static u32 pref_src_mode;
92static u32 pref_dst_mode;
93
94static int clear_word_size;
95static int copy_word_size;
96
97static int half_clear_loop_size;
98static int half_copy_loop_size;
99
100static int cache_line_size;
101#define cache_line_mask() (cache_line_size - 1)
102
103static inline void
104pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
105{
106 if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
107 if (off > 0x7fff) {
108 uasm_i_lui(buf, T9, uasm_rel_hi(off));
109 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
110 } else
111 uasm_i_addiu(buf, T9, ZERO, off);
112 uasm_i_daddu(buf, reg1, reg2, T9);
113 } else {
114 if (off > 0x7fff) {
115 uasm_i_lui(buf, T9, uasm_rel_hi(off));
116 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
117 UASM_i_ADDU(buf, reg1, reg2, T9);
118 } else
119 UASM_i_ADDIU(buf, reg1, reg2, off);
120 }
121}
122
123static void set_prefetch_parameters(void)
124{
125 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
126 clear_word_size = 8;
127 else
128 clear_word_size = 4;
129
130 if (cpu_has_64bit_gp_regs)
131 copy_word_size = 8;
132 else
133 copy_word_size = 4;
134
135 /*
136 * The pref's used here are using "streaming" hints, which cause the
137 * copied data to be kicked out of the cache sooner. A page copy often
138 * ends up copying a lot more data than is commonly used, so this seems
139 * to make sense in terms of reducing cache pollution, but I've no real
140 * performance data to back this up.
141 */
142 if (cpu_has_prefetch) {
143 /*
144 * XXX: Most prefetch bias values in here are based on
145 * guesswork.
146 */
147 cache_line_size = cpu_dcache_line_size();
148 switch (current_cpu_type()) {
149 case CPU_R5500:
150 case CPU_TX49XX:
151 /* These processors only support the Pref_Load. */
152 pref_bias_copy_load = 256;
153 break;
154
155 case CPU_R10000:
156 case CPU_R12000:
157 case CPU_R14000:
158 case CPU_R16000:
159 /*
160 * Those values have been experimentally tuned for an
161 * Origin 200.
162 */
163 pref_bias_clear_store = 512;
164 pref_bias_copy_load = 256;
165 pref_bias_copy_store = 256;
166 pref_src_mode = Pref_LoadStreamed;
167 pref_dst_mode = Pref_StoreStreamed;
168 break;
169
170 case CPU_SB1:
171 case CPU_SB1A:
172 pref_bias_clear_store = 128;
173 pref_bias_copy_load = 128;
174 pref_bias_copy_store = 128;
175 /*
176 * SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed
177 * hints are broken.
178 */
179 if (current_cpu_type() == CPU_SB1 &&
180 (current_cpu_data.processor_id & 0xff) < 0x02) {
181 pref_src_mode = Pref_Load;
182 pref_dst_mode = Pref_Store;
183 } else {
184 pref_src_mode = Pref_LoadStreamed;
185 pref_dst_mode = Pref_StoreStreamed;
186 }
187 break;
188
189 case CPU_LOONGSON64:
190 /* Loongson-3 only support the Pref_Load/Pref_Store. */
191 pref_bias_clear_store = 128;
192 pref_bias_copy_load = 128;
193 pref_bias_copy_store = 128;
194 pref_src_mode = Pref_Load;
195 pref_dst_mode = Pref_Store;
196 break;
197
198 default:
199 pref_bias_clear_store = 128;
200 pref_bias_copy_load = 256;
201 pref_bias_copy_store = 128;
202 pref_src_mode = Pref_LoadStreamed;
203 if (cpu_has_mips_r6)
204 /*
205 * Bit 30 (Pref_PrepareForStore) has been
206 * removed from MIPS R6. Use bit 5
207 * (Pref_StoreStreamed).
208 */
209 pref_dst_mode = Pref_StoreStreamed;
210 else
211 pref_dst_mode = Pref_PrepareForStore;
212 break;
213 }
214 } else {
215 if (cpu_has_cache_cdex_s)
216 cache_line_size = cpu_scache_line_size();
217 else if (cpu_has_cache_cdex_p)
218 cache_line_size = cpu_dcache_line_size();
219 }
220 /*
221 * Too much unrolling will overflow the available space in
222 * clear_space_array / copy_page_array.
223 */
224 half_clear_loop_size = min(16 * clear_word_size,
225 max(cache_line_size >> 1,
226 4 * clear_word_size));
227 half_copy_loop_size = min(16 * copy_word_size,
228 max(cache_line_size >> 1,
229 4 * copy_word_size));
230}
231
232static void build_clear_store(u32 **buf, int off)
233{
234 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
235 uasm_i_sd(buf, ZERO, off, A0);
236 } else {
237 uasm_i_sw(buf, ZERO, off, A0);
238 }
239}
240
241static inline void build_clear_pref(u32 **buf, int off)
242{
243 if (off & cache_line_mask())
244 return;
245
246 if (pref_bias_clear_store) {
247 _uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
248 A0);
249 } else if (cache_line_size == (half_clear_loop_size << 1)) {
250 if (cpu_has_cache_cdex_s) {
251 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
252 } else if (cpu_has_cache_cdex_p) {
253 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
254 uasm_i_nop(buf);
255 uasm_i_nop(buf);
256 uasm_i_nop(buf);
257 uasm_i_nop(buf);
258 }
259
260 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
261 uasm_i_lw(buf, ZERO, ZERO, AT);
262
263 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
264 }
265 }
266}
267
268extern u32 __clear_page_start;
269extern u32 __clear_page_end;
270extern u32 __copy_page_start;
271extern u32 __copy_page_end;
272
273void build_clear_page(void)
274{
275 int off;
276 u32 *buf = &__clear_page_start;
277 struct uasm_label *l = labels;
278 struct uasm_reloc *r = relocs;
279 int i;
280 static atomic_t run_once = ATOMIC_INIT(0);
281
282 if (atomic_xchg(&run_once, 1)) {
283 return;
284 }
285
286 memset(labels, 0, sizeof(labels));
287 memset(relocs, 0, sizeof(relocs));
288
289 set_prefetch_parameters();
290
291 /*
292 * This algorithm makes the following assumptions:
293 * - The prefetch bias is a multiple of 2 words.
294 * - The prefetch bias is less than one page.
295 */
296 BUG_ON(pref_bias_clear_store % (2 * clear_word_size));
297 BUG_ON(PAGE_SIZE < pref_bias_clear_store);
298
299 off = PAGE_SIZE - pref_bias_clear_store;
300 if (off > 0xffff || !pref_bias_clear_store)
301 pg_addiu(&buf, A2, A0, off);
302 else
303 uasm_i_ori(&buf, A2, A0, off);
304
305 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
306 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
307
308 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
309 * cache_line_size : 0;
310 while (off) {
311 build_clear_pref(&buf, -off);
312 off -= cache_line_size;
313 }
314 uasm_l_clear_pref(&l, buf);
315 do {
316 build_clear_pref(&buf, off);
317 build_clear_store(&buf, off);
318 off += clear_word_size;
319 } while (off < half_clear_loop_size);
320 pg_addiu(&buf, A0, A0, 2 * off);
321 off = -off;
322 do {
323 build_clear_pref(&buf, off);
324 if (off == -clear_word_size)
325 uasm_il_bne(&buf, &r, A0, A2, label_clear_pref);
326 build_clear_store(&buf, off);
327 off += clear_word_size;
328 } while (off < 0);
329
330 if (pref_bias_clear_store) {
331 pg_addiu(&buf, A2, A0, pref_bias_clear_store);
332 uasm_l_clear_nopref(&l, buf);
333 off = 0;
334 do {
335 build_clear_store(&buf, off);
336 off += clear_word_size;
337 } while (off < half_clear_loop_size);
338 pg_addiu(&buf, A0, A0, 2 * off);
339 off = -off;
340 do {
341 if (off == -clear_word_size)
342 uasm_il_bne(&buf, &r, A0, A2,
343 label_clear_nopref);
344 build_clear_store(&buf, off);
345 off += clear_word_size;
346 } while (off < 0);
347 }
348
349 uasm_i_jr(&buf, RA);
350 uasm_i_nop(&buf);
351
352 BUG_ON(buf > &__clear_page_end);
353
354 uasm_resolve_relocs(relocs, labels);
355
356 pr_debug("Synthesized clear page handler (%u instructions).\n",
357 (u32)(buf - &__clear_page_start));
358
359 pr_debug("\t.set push\n");
360 pr_debug("\t.set noreorder\n");
361 for (i = 0; i < (buf - &__clear_page_start); i++)
362 pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
363 pr_debug("\t.set pop\n");
364}
365
366static void build_copy_load(u32 **buf, int reg, int off)
367{
368 if (cpu_has_64bit_gp_regs) {
369 uasm_i_ld(buf, reg, off, A1);
370 } else {
371 uasm_i_lw(buf, reg, off, A1);
372 }
373}
374
375static void build_copy_store(u32 **buf, int reg, int off)
376{
377 if (cpu_has_64bit_gp_regs) {
378 uasm_i_sd(buf, reg, off, A0);
379 } else {
380 uasm_i_sw(buf, reg, off, A0);
381 }
382}
383
384static inline void build_copy_load_pref(u32 **buf, int off)
385{
386 if (off & cache_line_mask())
387 return;
388
389 if (pref_bias_copy_load)
390 _uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1);
391}
392
393static inline void build_copy_store_pref(u32 **buf, int off)
394{
395 if (off & cache_line_mask())
396 return;
397
398 if (pref_bias_copy_store) {
399 _uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
400 A0);
401 } else if (cache_line_size == (half_copy_loop_size << 1)) {
402 if (cpu_has_cache_cdex_s) {
403 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
404 } else if (cpu_has_cache_cdex_p) {
405 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
406 uasm_i_nop(buf);
407 uasm_i_nop(buf);
408 uasm_i_nop(buf);
409 uasm_i_nop(buf);
410 }
411
412 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
413 uasm_i_lw(buf, ZERO, ZERO, AT);
414
415 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
416 }
417 }
418}
419
420void build_copy_page(void)
421{
422 int off;
423 u32 *buf = &__copy_page_start;
424 struct uasm_label *l = labels;
425 struct uasm_reloc *r = relocs;
426 int i;
427 static atomic_t run_once = ATOMIC_INIT(0);
428
429 if (atomic_xchg(&run_once, 1)) {
430 return;
431 }
432
433 memset(labels, 0, sizeof(labels));
434 memset(relocs, 0, sizeof(relocs));
435
436 set_prefetch_parameters();
437
438 /*
439 * This algorithm makes the following assumptions:
440 * - All prefetch biases are multiples of 8 words.
441 * - The prefetch biases are less than one page.
442 * - The store prefetch bias isn't greater than the load
443 * prefetch bias.
444 */
445 BUG_ON(pref_bias_copy_load % (8 * copy_word_size));
446 BUG_ON(pref_bias_copy_store % (8 * copy_word_size));
447 BUG_ON(PAGE_SIZE < pref_bias_copy_load);
448 BUG_ON(pref_bias_copy_store > pref_bias_copy_load);
449
450 off = PAGE_SIZE - pref_bias_copy_load;
451 if (off > 0xffff || !pref_bias_copy_load)
452 pg_addiu(&buf, A2, A0, off);
453 else
454 uasm_i_ori(&buf, A2, A0, off);
455
456 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
457 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
458
459 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
460 cache_line_size : 0;
461 while (off) {
462 build_copy_load_pref(&buf, -off);
463 off -= cache_line_size;
464 }
465 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *
466 cache_line_size : 0;
467 while (off) {
468 build_copy_store_pref(&buf, -off);
469 off -= cache_line_size;
470 }
471 uasm_l_copy_pref_both(&l, buf);
472 do {
473 build_copy_load_pref(&buf, off);
474 build_copy_load(&buf, T0, off);
475 build_copy_load_pref(&buf, off + copy_word_size);
476 build_copy_load(&buf, T1, off + copy_word_size);
477 build_copy_load_pref(&buf, off + 2 * copy_word_size);
478 build_copy_load(&buf, T2, off + 2 * copy_word_size);
479 build_copy_load_pref(&buf, off + 3 * copy_word_size);
480 build_copy_load(&buf, T3, off + 3 * copy_word_size);
481 build_copy_store_pref(&buf, off);
482 build_copy_store(&buf, T0, off);
483 build_copy_store_pref(&buf, off + copy_word_size);
484 build_copy_store(&buf, T1, off + copy_word_size);
485 build_copy_store_pref(&buf, off + 2 * copy_word_size);
486 build_copy_store(&buf, T2, off + 2 * copy_word_size);
487 build_copy_store_pref(&buf, off + 3 * copy_word_size);
488 build_copy_store(&buf, T3, off + 3 * copy_word_size);
489 off += 4 * copy_word_size;
490 } while (off < half_copy_loop_size);
491 pg_addiu(&buf, A1, A1, 2 * off);
492 pg_addiu(&buf, A0, A0, 2 * off);
493 off = -off;
494 do {
495 build_copy_load_pref(&buf, off);
496 build_copy_load(&buf, T0, off);
497 build_copy_load_pref(&buf, off + copy_word_size);
498 build_copy_load(&buf, T1, off + copy_word_size);
499 build_copy_load_pref(&buf, off + 2 * copy_word_size);
500 build_copy_load(&buf, T2, off + 2 * copy_word_size);
501 build_copy_load_pref(&buf, off + 3 * copy_word_size);
502 build_copy_load(&buf, T3, off + 3 * copy_word_size);
503 build_copy_store_pref(&buf, off);
504 build_copy_store(&buf, T0, off);
505 build_copy_store_pref(&buf, off + copy_word_size);
506 build_copy_store(&buf, T1, off + copy_word_size);
507 build_copy_store_pref(&buf, off + 2 * copy_word_size);
508 build_copy_store(&buf, T2, off + 2 * copy_word_size);
509 build_copy_store_pref(&buf, off + 3 * copy_word_size);
510 if (off == -(4 * copy_word_size))
511 uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both);
512 build_copy_store(&buf, T3, off + 3 * copy_word_size);
513 off += 4 * copy_word_size;
514 } while (off < 0);
515
516 if (pref_bias_copy_load - pref_bias_copy_store) {
517 pg_addiu(&buf, A2, A0,
518 pref_bias_copy_load - pref_bias_copy_store);
519 uasm_l_copy_pref_store(&l, buf);
520 off = 0;
521 do {
522 build_copy_load(&buf, T0, off);
523 build_copy_load(&buf, T1, off + copy_word_size);
524 build_copy_load(&buf, T2, off + 2 * copy_word_size);
525 build_copy_load(&buf, T3, off + 3 * copy_word_size);
526 build_copy_store_pref(&buf, off);
527 build_copy_store(&buf, T0, off);
528 build_copy_store_pref(&buf, off + copy_word_size);
529 build_copy_store(&buf, T1, off + copy_word_size);
530 build_copy_store_pref(&buf, off + 2 * copy_word_size);
531 build_copy_store(&buf, T2, off + 2 * copy_word_size);
532 build_copy_store_pref(&buf, off + 3 * copy_word_size);
533 build_copy_store(&buf, T3, off + 3 * copy_word_size);
534 off += 4 * copy_word_size;
535 } while (off < half_copy_loop_size);
536 pg_addiu(&buf, A1, A1, 2 * off);
537 pg_addiu(&buf, A0, A0, 2 * off);
538 off = -off;
539 do {
540 build_copy_load(&buf, T0, off);
541 build_copy_load(&buf, T1, off + copy_word_size);
542 build_copy_load(&buf, T2, off + 2 * copy_word_size);
543 build_copy_load(&buf, T3, off + 3 * copy_word_size);
544 build_copy_store_pref(&buf, off);
545 build_copy_store(&buf, T0, off);
546 build_copy_store_pref(&buf, off + copy_word_size);
547 build_copy_store(&buf, T1, off + copy_word_size);
548 build_copy_store_pref(&buf, off + 2 * copy_word_size);
549 build_copy_store(&buf, T2, off + 2 * copy_word_size);
550 build_copy_store_pref(&buf, off + 3 * copy_word_size);
551 if (off == -(4 * copy_word_size))
552 uasm_il_bne(&buf, &r, A2, A0,
553 label_copy_pref_store);
554 build_copy_store(&buf, T3, off + 3 * copy_word_size);
555 off += 4 * copy_word_size;
556 } while (off < 0);
557 }
558
559 if (pref_bias_copy_store) {
560 pg_addiu(&buf, A2, A0, pref_bias_copy_store);
561 uasm_l_copy_nopref(&l, buf);
562 off = 0;
563 do {
564 build_copy_load(&buf, T0, off);
565 build_copy_load(&buf, T1, off + copy_word_size);
566 build_copy_load(&buf, T2, off + 2 * copy_word_size);
567 build_copy_load(&buf, T3, off + 3 * copy_word_size);
568 build_copy_store(&buf, T0, off);
569 build_copy_store(&buf, T1, off + copy_word_size);
570 build_copy_store(&buf, T2, off + 2 * copy_word_size);
571 build_copy_store(&buf, T3, off + 3 * copy_word_size);
572 off += 4 * copy_word_size;
573 } while (off < half_copy_loop_size);
574 pg_addiu(&buf, A1, A1, 2 * off);
575 pg_addiu(&buf, A0, A0, 2 * off);
576 off = -off;
577 do {
578 build_copy_load(&buf, T0, off);
579 build_copy_load(&buf, T1, off + copy_word_size);
580 build_copy_load(&buf, T2, off + 2 * copy_word_size);
581 build_copy_load(&buf, T3, off + 3 * copy_word_size);
582 build_copy_store(&buf, T0, off);
583 build_copy_store(&buf, T1, off + copy_word_size);
584 build_copy_store(&buf, T2, off + 2 * copy_word_size);
585 if (off == -(4 * copy_word_size))
586 uasm_il_bne(&buf, &r, A2, A0,
587 label_copy_nopref);
588 build_copy_store(&buf, T3, off + 3 * copy_word_size);
589 off += 4 * copy_word_size;
590 } while (off < 0);
591 }
592
593 uasm_i_jr(&buf, RA);
594 uasm_i_nop(&buf);
595
596 BUG_ON(buf > &__copy_page_end);
597
598 uasm_resolve_relocs(relocs, labels);
599
600 pr_debug("Synthesized copy page handler (%u instructions).\n",
601 (u32)(buf - &__copy_page_start));
602
603 pr_debug("\t.set push\n");
604 pr_debug("\t.set noreorder\n");
605 for (i = 0; i < (buf - &__copy_page_start); i++)
606 pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
607 pr_debug("\t.set pop\n");
608}
609
610#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
611extern void clear_page_cpu(void *page);
612extern void copy_page_cpu(void *to, void *from);
613
614/*
615 * Pad descriptors to cacheline, since each is exclusively owned by a
616 * particular CPU.
617 */
618struct dmadscr {
619 u64 dscr_a;
620 u64 dscr_b;
621 u64 pad_a;
622 u64 pad_b;
623} ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS];
624
625void clear_page(void *page)
626{
627 u64 to_phys = CPHYSADDR((unsigned long)page);
628 unsigned int cpu = smp_processor_id();
629
630 /* if the page is not in KSEG0, use old way */
631 if ((long)KSEGX((unsigned long)page) != (long)CKSEG0)
632 return clear_page_cpu(page);
633
634 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
635 M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
636 page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
637 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
638
639 /*
640 * Don't really want to do it this way, but there's no
641 * reliable way to delay completion detection.
642 */
643 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
644 & M_DM_DSCR_BASE_INTERRUPT))
645 ;
646 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
647}
648EXPORT_SYMBOL(clear_page);
649
650void copy_page(void *to, void *from)
651{
652 u64 from_phys = CPHYSADDR((unsigned long)from);
653 u64 to_phys = CPHYSADDR((unsigned long)to);
654 unsigned int cpu = smp_processor_id();
655
656 /* if any page is not in KSEG0, use old way */
657 if ((long)KSEGX((unsigned long)to) != (long)CKSEG0
658 || (long)KSEGX((unsigned long)from) != (long)CKSEG0)
659 return copy_page_cpu(to, from);
660
661 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
662 M_DM_DSCRA_INTERRUPT;
663 page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
664 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
665
666 /*
667 * Don't really want to do it this way, but there's no
668 * reliable way to delay completion detection.
669 */
670 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
671 & M_DM_DSCR_BASE_INTERRUPT))
672 ;
673 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
674}
675EXPORT_SYMBOL(copy_page);
676
677#endif /* CONFIG_SIBYTE_DMA_PAGEOPS */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
8 * Copyright (C) 2008 Thiemo Seufer
9 * Copyright (C) 2012 MIPS Technologies, Inc.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15#include <linux/mm.h>
16#include <linux/module.h>
17#include <linux/proc_fs.h>
18
19#include <asm/bugs.h>
20#include <asm/cacheops.h>
21#include <asm/inst.h>
22#include <asm/io.h>
23#include <asm/page.h>
24#include <asm/pgtable.h>
25#include <asm/prefetch.h>
26#include <asm/bootinfo.h>
27#include <asm/mipsregs.h>
28#include <asm/mmu_context.h>
29#include <asm/cpu.h>
30#include <asm/war.h>
31
32#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
33#include <asm/sibyte/sb1250.h>
34#include <asm/sibyte/sb1250_regs.h>
35#include <asm/sibyte/sb1250_dma.h>
36#endif
37
38#include <asm/uasm.h>
39
40/* Registers used in the assembled routines. */
41#define ZERO 0
42#define AT 2
43#define A0 4
44#define A1 5
45#define A2 6
46#define T0 8
47#define T1 9
48#define T2 10
49#define T3 11
50#define T9 25
51#define RA 31
52
53/* Handle labels (which must be positive integers). */
54enum label_id {
55 label_clear_nopref = 1,
56 label_clear_pref,
57 label_copy_nopref,
58 label_copy_pref_both,
59 label_copy_pref_store,
60};
61
62UASM_L_LA(_clear_nopref)
63UASM_L_LA(_clear_pref)
64UASM_L_LA(_copy_nopref)
65UASM_L_LA(_copy_pref_both)
66UASM_L_LA(_copy_pref_store)
67
68/* We need one branch and therefore one relocation per target label. */
69static struct uasm_label __cpuinitdata labels[5];
70static struct uasm_reloc __cpuinitdata relocs[5];
71
72#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
73#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
74
75static int pref_bias_clear_store __cpuinitdata;
76static int pref_bias_copy_load __cpuinitdata;
77static int pref_bias_copy_store __cpuinitdata;
78
79static u32 pref_src_mode __cpuinitdata;
80static u32 pref_dst_mode __cpuinitdata;
81
82static int clear_word_size __cpuinitdata;
83static int copy_word_size __cpuinitdata;
84
85static int half_clear_loop_size __cpuinitdata;
86static int half_copy_loop_size __cpuinitdata;
87
88static int cache_line_size __cpuinitdata;
89#define cache_line_mask() (cache_line_size - 1)
90
91static inline void __cpuinit
92pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
93{
94 if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
95 if (off > 0x7fff) {
96 uasm_i_lui(buf, T9, uasm_rel_hi(off));
97 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
98 } else
99 uasm_i_addiu(buf, T9, ZERO, off);
100 uasm_i_daddu(buf, reg1, reg2, T9);
101 } else {
102 if (off > 0x7fff) {
103 uasm_i_lui(buf, T9, uasm_rel_hi(off));
104 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
105 UASM_i_ADDU(buf, reg1, reg2, T9);
106 } else
107 UASM_i_ADDIU(buf, reg1, reg2, off);
108 }
109}
110
111static void __cpuinit set_prefetch_parameters(void)
112{
113 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg)
114 clear_word_size = 8;
115 else
116 clear_word_size = 4;
117
118 if (cpu_has_64bit_gp_regs)
119 copy_word_size = 8;
120 else
121 copy_word_size = 4;
122
123 /*
124 * The pref's used here are using "streaming" hints, which cause the
125 * copied data to be kicked out of the cache sooner. A page copy often
126 * ends up copying a lot more data than is commonly used, so this seems
127 * to make sense in terms of reducing cache pollution, but I've no real
128 * performance data to back this up.
129 */
130 if (cpu_has_prefetch) {
131 /*
132 * XXX: Most prefetch bias values in here are based on
133 * guesswork.
134 */
135 cache_line_size = cpu_dcache_line_size();
136 switch (current_cpu_type()) {
137 case CPU_R5500:
138 case CPU_TX49XX:
139 /* These processors only support the Pref_Load. */
140 pref_bias_copy_load = 256;
141 break;
142
143 case CPU_RM9000:
144 /*
145 * As a workaround for erratum G105 which make the
146 * PrepareForStore hint unusable we fall back to
147 * StoreRetained on the RM9000. Once it is known which
148 * versions of the RM9000 we'll be able to condition-
149 * alize this.
150 */
151
152 case CPU_R10000:
153 case CPU_R12000:
154 case CPU_R14000:
155 /*
156 * Those values have been experimentally tuned for an
157 * Origin 200.
158 */
159 pref_bias_clear_store = 512;
160 pref_bias_copy_load = 256;
161 pref_bias_copy_store = 256;
162 pref_src_mode = Pref_LoadStreamed;
163 pref_dst_mode = Pref_StoreStreamed;
164 break;
165
166 case CPU_SB1:
167 case CPU_SB1A:
168 pref_bias_clear_store = 128;
169 pref_bias_copy_load = 128;
170 pref_bias_copy_store = 128;
171 /*
172 * SB1 pass1 Pref_LoadStreamed/Pref_StoreStreamed
173 * hints are broken.
174 */
175 if (current_cpu_type() == CPU_SB1 &&
176 (current_cpu_data.processor_id & 0xff) < 0x02) {
177 pref_src_mode = Pref_Load;
178 pref_dst_mode = Pref_Store;
179 } else {
180 pref_src_mode = Pref_LoadStreamed;
181 pref_dst_mode = Pref_StoreStreamed;
182 }
183 break;
184
185 default:
186 pref_bias_clear_store = 128;
187 pref_bias_copy_load = 256;
188 pref_bias_copy_store = 128;
189 pref_src_mode = Pref_LoadStreamed;
190 pref_dst_mode = Pref_PrepareForStore;
191 break;
192 }
193 } else {
194 if (cpu_has_cache_cdex_s)
195 cache_line_size = cpu_scache_line_size();
196 else if (cpu_has_cache_cdex_p)
197 cache_line_size = cpu_dcache_line_size();
198 }
199 /*
200 * Too much unrolling will overflow the available space in
201 * clear_space_array / copy_page_array.
202 */
203 half_clear_loop_size = min(16 * clear_word_size,
204 max(cache_line_size >> 1,
205 4 * clear_word_size));
206 half_copy_loop_size = min(16 * copy_word_size,
207 max(cache_line_size >> 1,
208 4 * copy_word_size));
209}
210
211static void __cpuinit build_clear_store(u32 **buf, int off)
212{
213 if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) {
214 uasm_i_sd(buf, ZERO, off, A0);
215 } else {
216 uasm_i_sw(buf, ZERO, off, A0);
217 }
218}
219
220static inline void __cpuinit build_clear_pref(u32 **buf, int off)
221{
222 if (off & cache_line_mask())
223 return;
224
225 if (pref_bias_clear_store) {
226 uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
227 A0);
228 } else if (cache_line_size == (half_clear_loop_size << 1)) {
229 if (cpu_has_cache_cdex_s) {
230 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
231 } else if (cpu_has_cache_cdex_p) {
232 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
233 uasm_i_nop(buf);
234 uasm_i_nop(buf);
235 uasm_i_nop(buf);
236 uasm_i_nop(buf);
237 }
238
239 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
240 uasm_i_lw(buf, ZERO, ZERO, AT);
241
242 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
243 }
244 }
245}
246
247extern u32 __clear_page_start;
248extern u32 __clear_page_end;
249extern u32 __copy_page_start;
250extern u32 __copy_page_end;
251
252void __cpuinit build_clear_page(void)
253{
254 int off;
255 u32 *buf = &__clear_page_start;
256 struct uasm_label *l = labels;
257 struct uasm_reloc *r = relocs;
258 int i;
259
260 memset(labels, 0, sizeof(labels));
261 memset(relocs, 0, sizeof(relocs));
262
263 set_prefetch_parameters();
264
265 /*
266 * This algorithm makes the following assumptions:
267 * - The prefetch bias is a multiple of 2 words.
268 * - The prefetch bias is less than one page.
269 */
270 BUG_ON(pref_bias_clear_store % (2 * clear_word_size));
271 BUG_ON(PAGE_SIZE < pref_bias_clear_store);
272
273 off = PAGE_SIZE - pref_bias_clear_store;
274 if (off > 0xffff || !pref_bias_clear_store)
275 pg_addiu(&buf, A2, A0, off);
276 else
277 uasm_i_ori(&buf, A2, A0, off);
278
279 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
280 uasm_i_lui(&buf, AT, 0xa000);
281
282 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
283 * cache_line_size : 0;
284 while (off) {
285 build_clear_pref(&buf, -off);
286 off -= cache_line_size;
287 }
288 uasm_l_clear_pref(&l, buf);
289 do {
290 build_clear_pref(&buf, off);
291 build_clear_store(&buf, off);
292 off += clear_word_size;
293 } while (off < half_clear_loop_size);
294 pg_addiu(&buf, A0, A0, 2 * off);
295 off = -off;
296 do {
297 build_clear_pref(&buf, off);
298 if (off == -clear_word_size)
299 uasm_il_bne(&buf, &r, A0, A2, label_clear_pref);
300 build_clear_store(&buf, off);
301 off += clear_word_size;
302 } while (off < 0);
303
304 if (pref_bias_clear_store) {
305 pg_addiu(&buf, A2, A0, pref_bias_clear_store);
306 uasm_l_clear_nopref(&l, buf);
307 off = 0;
308 do {
309 build_clear_store(&buf, off);
310 off += clear_word_size;
311 } while (off < half_clear_loop_size);
312 pg_addiu(&buf, A0, A0, 2 * off);
313 off = -off;
314 do {
315 if (off == -clear_word_size)
316 uasm_il_bne(&buf, &r, A0, A2,
317 label_clear_nopref);
318 build_clear_store(&buf, off);
319 off += clear_word_size;
320 } while (off < 0);
321 }
322
323 uasm_i_jr(&buf, RA);
324 uasm_i_nop(&buf);
325
326 BUG_ON(buf > &__clear_page_end);
327
328 uasm_resolve_relocs(relocs, labels);
329
330 pr_debug("Synthesized clear page handler (%u instructions).\n",
331 (u32)(buf - &__clear_page_start));
332
333 pr_debug("\t.set push\n");
334 pr_debug("\t.set noreorder\n");
335 for (i = 0; i < (buf - &__clear_page_start); i++)
336 pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
337 pr_debug("\t.set pop\n");
338}
339
340static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
341{
342 if (cpu_has_64bit_gp_regs) {
343 uasm_i_ld(buf, reg, off, A1);
344 } else {
345 uasm_i_lw(buf, reg, off, A1);
346 }
347}
348
349static void __cpuinit build_copy_store(u32 **buf, int reg, int off)
350{
351 if (cpu_has_64bit_gp_regs) {
352 uasm_i_sd(buf, reg, off, A0);
353 } else {
354 uasm_i_sw(buf, reg, off, A0);
355 }
356}
357
358static inline void build_copy_load_pref(u32 **buf, int off)
359{
360 if (off & cache_line_mask())
361 return;
362
363 if (pref_bias_copy_load)
364 uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1);
365}
366
367static inline void build_copy_store_pref(u32 **buf, int off)
368{
369 if (off & cache_line_mask())
370 return;
371
372 if (pref_bias_copy_store) {
373 uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
374 A0);
375 } else if (cache_line_size == (half_copy_loop_size << 1)) {
376 if (cpu_has_cache_cdex_s) {
377 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
378 } else if (cpu_has_cache_cdex_p) {
379 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
380 uasm_i_nop(buf);
381 uasm_i_nop(buf);
382 uasm_i_nop(buf);
383 uasm_i_nop(buf);
384 }
385
386 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
387 uasm_i_lw(buf, ZERO, ZERO, AT);
388
389 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
390 }
391 }
392}
393
394void __cpuinit build_copy_page(void)
395{
396 int off;
397 u32 *buf = &__copy_page_start;
398 struct uasm_label *l = labels;
399 struct uasm_reloc *r = relocs;
400 int i;
401
402 memset(labels, 0, sizeof(labels));
403 memset(relocs, 0, sizeof(relocs));
404
405 set_prefetch_parameters();
406
407 /*
408 * This algorithm makes the following assumptions:
409 * - All prefetch biases are multiples of 8 words.
410 * - The prefetch biases are less than one page.
411 * - The store prefetch bias isn't greater than the load
412 * prefetch bias.
413 */
414 BUG_ON(pref_bias_copy_load % (8 * copy_word_size));
415 BUG_ON(pref_bias_copy_store % (8 * copy_word_size));
416 BUG_ON(PAGE_SIZE < pref_bias_copy_load);
417 BUG_ON(pref_bias_copy_store > pref_bias_copy_load);
418
419 off = PAGE_SIZE - pref_bias_copy_load;
420 if (off > 0xffff || !pref_bias_copy_load)
421 pg_addiu(&buf, A2, A0, off);
422 else
423 uasm_i_ori(&buf, A2, A0, off);
424
425 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
426 uasm_i_lui(&buf, AT, 0xa000);
427
428 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
429 cache_line_size : 0;
430 while (off) {
431 build_copy_load_pref(&buf, -off);
432 off -= cache_line_size;
433 }
434 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *
435 cache_line_size : 0;
436 while (off) {
437 build_copy_store_pref(&buf, -off);
438 off -= cache_line_size;
439 }
440 uasm_l_copy_pref_both(&l, buf);
441 do {
442 build_copy_load_pref(&buf, off);
443 build_copy_load(&buf, T0, off);
444 build_copy_load_pref(&buf, off + copy_word_size);
445 build_copy_load(&buf, T1, off + copy_word_size);
446 build_copy_load_pref(&buf, off + 2 * copy_word_size);
447 build_copy_load(&buf, T2, off + 2 * copy_word_size);
448 build_copy_load_pref(&buf, off + 3 * copy_word_size);
449 build_copy_load(&buf, T3, off + 3 * copy_word_size);
450 build_copy_store_pref(&buf, off);
451 build_copy_store(&buf, T0, off);
452 build_copy_store_pref(&buf, off + copy_word_size);
453 build_copy_store(&buf, T1, off + copy_word_size);
454 build_copy_store_pref(&buf, off + 2 * copy_word_size);
455 build_copy_store(&buf, T2, off + 2 * copy_word_size);
456 build_copy_store_pref(&buf, off + 3 * copy_word_size);
457 build_copy_store(&buf, T3, off + 3 * copy_word_size);
458 off += 4 * copy_word_size;
459 } while (off < half_copy_loop_size);
460 pg_addiu(&buf, A1, A1, 2 * off);
461 pg_addiu(&buf, A0, A0, 2 * off);
462 off = -off;
463 do {
464 build_copy_load_pref(&buf, off);
465 build_copy_load(&buf, T0, off);
466 build_copy_load_pref(&buf, off + copy_word_size);
467 build_copy_load(&buf, T1, off + copy_word_size);
468 build_copy_load_pref(&buf, off + 2 * copy_word_size);
469 build_copy_load(&buf, T2, off + 2 * copy_word_size);
470 build_copy_load_pref(&buf, off + 3 * copy_word_size);
471 build_copy_load(&buf, T3, off + 3 * copy_word_size);
472 build_copy_store_pref(&buf, off);
473 build_copy_store(&buf, T0, off);
474 build_copy_store_pref(&buf, off + copy_word_size);
475 build_copy_store(&buf, T1, off + copy_word_size);
476 build_copy_store_pref(&buf, off + 2 * copy_word_size);
477 build_copy_store(&buf, T2, off + 2 * copy_word_size);
478 build_copy_store_pref(&buf, off + 3 * copy_word_size);
479 if (off == -(4 * copy_word_size))
480 uasm_il_bne(&buf, &r, A2, A0, label_copy_pref_both);
481 build_copy_store(&buf, T3, off + 3 * copy_word_size);
482 off += 4 * copy_word_size;
483 } while (off < 0);
484
485 if (pref_bias_copy_load - pref_bias_copy_store) {
486 pg_addiu(&buf, A2, A0,
487 pref_bias_copy_load - pref_bias_copy_store);
488 uasm_l_copy_pref_store(&l, buf);
489 off = 0;
490 do {
491 build_copy_load(&buf, T0, off);
492 build_copy_load(&buf, T1, off + copy_word_size);
493 build_copy_load(&buf, T2, off + 2 * copy_word_size);
494 build_copy_load(&buf, T3, off + 3 * copy_word_size);
495 build_copy_store_pref(&buf, off);
496 build_copy_store(&buf, T0, off);
497 build_copy_store_pref(&buf, off + copy_word_size);
498 build_copy_store(&buf, T1, off + copy_word_size);
499 build_copy_store_pref(&buf, off + 2 * copy_word_size);
500 build_copy_store(&buf, T2, off + 2 * copy_word_size);
501 build_copy_store_pref(&buf, off + 3 * copy_word_size);
502 build_copy_store(&buf, T3, off + 3 * copy_word_size);
503 off += 4 * copy_word_size;
504 } while (off < half_copy_loop_size);
505 pg_addiu(&buf, A1, A1, 2 * off);
506 pg_addiu(&buf, A0, A0, 2 * off);
507 off = -off;
508 do {
509 build_copy_load(&buf, T0, off);
510 build_copy_load(&buf, T1, off + copy_word_size);
511 build_copy_load(&buf, T2, off + 2 * copy_word_size);
512 build_copy_load(&buf, T3, off + 3 * copy_word_size);
513 build_copy_store_pref(&buf, off);
514 build_copy_store(&buf, T0, off);
515 build_copy_store_pref(&buf, off + copy_word_size);
516 build_copy_store(&buf, T1, off + copy_word_size);
517 build_copy_store_pref(&buf, off + 2 * copy_word_size);
518 build_copy_store(&buf, T2, off + 2 * copy_word_size);
519 build_copy_store_pref(&buf, off + 3 * copy_word_size);
520 if (off == -(4 * copy_word_size))
521 uasm_il_bne(&buf, &r, A2, A0,
522 label_copy_pref_store);
523 build_copy_store(&buf, T3, off + 3 * copy_word_size);
524 off += 4 * copy_word_size;
525 } while (off < 0);
526 }
527
528 if (pref_bias_copy_store) {
529 pg_addiu(&buf, A2, A0, pref_bias_copy_store);
530 uasm_l_copy_nopref(&l, buf);
531 off = 0;
532 do {
533 build_copy_load(&buf, T0, off);
534 build_copy_load(&buf, T1, off + copy_word_size);
535 build_copy_load(&buf, T2, off + 2 * copy_word_size);
536 build_copy_load(&buf, T3, off + 3 * copy_word_size);
537 build_copy_store(&buf, T0, off);
538 build_copy_store(&buf, T1, off + copy_word_size);
539 build_copy_store(&buf, T2, off + 2 * copy_word_size);
540 build_copy_store(&buf, T3, off + 3 * copy_word_size);
541 off += 4 * copy_word_size;
542 } while (off < half_copy_loop_size);
543 pg_addiu(&buf, A1, A1, 2 * off);
544 pg_addiu(&buf, A0, A0, 2 * off);
545 off = -off;
546 do {
547 build_copy_load(&buf, T0, off);
548 build_copy_load(&buf, T1, off + copy_word_size);
549 build_copy_load(&buf, T2, off + 2 * copy_word_size);
550 build_copy_load(&buf, T3, off + 3 * copy_word_size);
551 build_copy_store(&buf, T0, off);
552 build_copy_store(&buf, T1, off + copy_word_size);
553 build_copy_store(&buf, T2, off + 2 * copy_word_size);
554 if (off == -(4 * copy_word_size))
555 uasm_il_bne(&buf, &r, A2, A0,
556 label_copy_nopref);
557 build_copy_store(&buf, T3, off + 3 * copy_word_size);
558 off += 4 * copy_word_size;
559 } while (off < 0);
560 }
561
562 uasm_i_jr(&buf, RA);
563 uasm_i_nop(&buf);
564
565 BUG_ON(buf > &__copy_page_end);
566
567 uasm_resolve_relocs(relocs, labels);
568
569 pr_debug("Synthesized copy page handler (%u instructions).\n",
570 (u32)(buf - &__copy_page_start));
571
572 pr_debug("\t.set push\n");
573 pr_debug("\t.set noreorder\n");
574 for (i = 0; i < (buf - &__copy_page_start); i++)
575 pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
576 pr_debug("\t.set pop\n");
577}
578
579#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
580extern void clear_page_cpu(void *page);
581extern void copy_page_cpu(void *to, void *from);
582
583/*
584 * Pad descriptors to cacheline, since each is exclusively owned by a
585 * particular CPU.
586 */
587struct dmadscr {
588 u64 dscr_a;
589 u64 dscr_b;
590 u64 pad_a;
591 u64 pad_b;
592} ____cacheline_aligned_in_smp page_descr[DM_NUM_CHANNELS];
593
594void sb1_dma_init(void)
595{
596 int i;
597
598 for (i = 0; i < DM_NUM_CHANNELS; i++) {
599 const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) |
600 V_DM_DSCR_BASE_RINGSZ(1);
601 void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
602
603 __raw_writeq(base_val, base_reg);
604 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
605 __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg);
606 }
607}
608
609void clear_page(void *page)
610{
611 u64 to_phys = CPHYSADDR((unsigned long)page);
612 unsigned int cpu = smp_processor_id();
613
614 /* if the page is not in KSEG0, use old way */
615 if ((long)KSEGX((unsigned long)page) != (long)CKSEG0)
616 return clear_page_cpu(page);
617
618 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
619 M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
620 page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
621 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
622
623 /*
624 * Don't really want to do it this way, but there's no
625 * reliable way to delay completion detection.
626 */
627 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
628 & M_DM_DSCR_BASE_INTERRUPT))
629 ;
630 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
631}
632
633void copy_page(void *to, void *from)
634{
635 u64 from_phys = CPHYSADDR((unsigned long)from);
636 u64 to_phys = CPHYSADDR((unsigned long)to);
637 unsigned int cpu = smp_processor_id();
638
639 /* if any page is not in KSEG0, use old way */
640 if ((long)KSEGX((unsigned long)to) != (long)CKSEG0
641 || (long)KSEGX((unsigned long)from) != (long)CKSEG0)
642 return copy_page_cpu(to, from);
643
644 page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
645 M_DM_DSCRA_INTERRUPT;
646 page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
647 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
648
649 /*
650 * Don't really want to do it this way, but there's no
651 * reliable way to delay completion detection.
652 */
653 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
654 & M_DM_DSCR_BASE_INTERRUPT))
655 ;
656 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
657}
658
659#endif /* CONFIG_SIBYTE_DMA_PAGEOPS */