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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* -*- linux-c -*- *
3 *
4 * ALSA driver for the digigram lx6464es interface
5 * low-level interface
6 *
7 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
8 */
9
10#ifndef LX_CORE_H
11#define LX_CORE_H
12
13#include <linux/interrupt.h>
14
15#include "lx_defs.h"
16
17#define REG_CRM_NUMBER 12
18
19struct lx6464es;
20
21/* low-level register access */
22
23/* dsp register access */
24enum {
25 eReg_BASE,
26 eReg_CSM,
27 eReg_CRM1,
28 eReg_CRM2,
29 eReg_CRM3,
30 eReg_CRM4,
31 eReg_CRM5,
32 eReg_CRM6,
33 eReg_CRM7,
34 eReg_CRM8,
35 eReg_CRM9,
36 eReg_CRM10,
37 eReg_CRM11,
38 eReg_CRM12,
39
40 eReg_ICR,
41 eReg_CVR,
42 eReg_ISR,
43 eReg_RXHTXH,
44 eReg_RXMTXM,
45 eReg_RHLTXL,
46 eReg_RESETDSP,
47
48 eReg_CSUF,
49 eReg_CSES,
50 eReg_CRESMSB,
51 eReg_CRESLSB,
52 eReg_ADMACESMSB,
53 eReg_ADMACESLSB,
54 eReg_CONFES,
55
56 eMaxPortLx
57};
58
59unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
60void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
61
62/* plx register access */
63enum {
64 ePLX_PCICR,
65
66 ePLX_MBOX0,
67 ePLX_MBOX1,
68 ePLX_MBOX2,
69 ePLX_MBOX3,
70 ePLX_MBOX4,
71 ePLX_MBOX5,
72 ePLX_MBOX6,
73 ePLX_MBOX7,
74
75 ePLX_L2PCIDB,
76 ePLX_IRQCS,
77 ePLX_CHIPSC,
78
79 eMaxPort
80};
81
82unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
83void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
84
85/* rhm */
86struct lx_rmh {
87 u16 cmd_len; /* length of the command to send (WORDs) */
88 u16 stat_len; /* length of the status received (WORDs) */
89 u16 dsp_stat; /* status type, RMP_SSIZE_XXX */
90 u16 cmd_idx; /* index of the command */
91 u32 cmd[REG_CRM_NUMBER];
92 u32 stat[REG_CRM_NUMBER];
93};
94
95
96/* low-level dsp access */
97int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version);
98int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq);
99int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran);
100int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data);
101int lx_dsp_get_mac(struct lx6464es *chip);
102
103
104/* low-level pipe handling */
105int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
106 int channels);
107int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture);
108int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
109 u64 *rsample_count);
110int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate);
111int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture);
112int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture);
113int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture);
114
115int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture);
116int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture);
117
118/* low-level stream handling */
119int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
120 u32 pipe, int is_capture);
121int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
122 int *rstate);
123int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
124 u64 *r_bytepos);
125
126int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
127 int is_capture, enum stream_state_t state);
128
129static inline int lx_stream_start(struct lx6464es *chip, u32 pipe,
130 int is_capture)
131{
132 snd_printdd("->lx_stream_start\n");
133 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN);
134}
135
136static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe,
137 int is_capture)
138{
139 snd_printdd("->lx_stream_pause\n");
140 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE);
141}
142
143static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe,
144 int is_capture)
145{
146 snd_printdd("->lx_stream_stop\n");
147 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP);
148}
149
150/* low-level buffer handling */
151int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
152 u32 *r_needed, u32 *r_freed, u32 *size_array);
153int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
154 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
155 u32 *r_buffer_index);
156int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
157 u32 *r_buffer_size);
158int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
159 u32 buffer_index);
160
161/* low-level gain/peak handling */
162int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute);
163int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
164 u32 *r_levels);
165
166
167/* interrupt handling */
168irqreturn_t lx_interrupt(int irq, void *dev_id);
169irqreturn_t lx_threaded_irq(int irq, void *dev_id);
170void lx_irq_enable(struct lx6464es *chip);
171void lx_irq_disable(struct lx6464es *chip);
172
173
174/* Stream Format Header Defines (for LIN and IEEE754) */
175#define HEADER_FMT_BASE HEADER_FMT_BASE_LIN
176#define HEADER_FMT_BASE_LIN 0xFED00000
177#define HEADER_FMT_BASE_FLOAT 0xFAD00000
178#define HEADER_FMT_MONO 0x00000080 /* bit 23 in header_lo. WARNING: old
179 * bit 22 is ignored in float
180 * format */
181#define HEADER_FMT_INTEL 0x00008000
182#define HEADER_FMT_16BITS 0x00002000
183#define HEADER_FMT_24BITS 0x00004000
184#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.
185 * */
186#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less
187 * then 32k.*/
188
189
190#define BIT_FMP_HEADER 23
191#define BIT_FMP_SD 22
192#define BIT_FMP_MULTICHANNEL 19
193
194#define START_STATE 1
195#define PAUSE_STATE 0
196
197
198
199
200
201/* from PcxAll_e.h */
202/* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */
203#define START_PAUSE_IMMEDIATE 0
204#define START_PAUSE_ON_SYNCHRO 1
205#define START_PAUSE_ON_TIME_CODE 2
206
207
208/* Pipe / Stream state */
209#define START_STATE 1
210#define PAUSE_STATE 0
211
212static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high)
213{
214 *r_low = (u32)(ptr & 0xffffffff);
215#if BITS_PER_LONG == 32
216 *r_high = 0;
217#else
218 *r_high = (u32)((u64)ptr>>32);
219#endif
220}
221
222#endif /* LX_CORE_H */
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * low-level interface
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX_CORE_H
26#define LX_CORE_H
27
28#include <linux/interrupt.h>
29
30#include "lx_defs.h"
31
32#define REG_CRM_NUMBER 12
33
34struct lx6464es;
35
36/* low-level register access */
37
38/* dsp register access */
39enum {
40 eReg_BASE,
41 eReg_CSM,
42 eReg_CRM1,
43 eReg_CRM2,
44 eReg_CRM3,
45 eReg_CRM4,
46 eReg_CRM5,
47 eReg_CRM6,
48 eReg_CRM7,
49 eReg_CRM8,
50 eReg_CRM9,
51 eReg_CRM10,
52 eReg_CRM11,
53 eReg_CRM12,
54
55 eReg_ICR,
56 eReg_CVR,
57 eReg_ISR,
58 eReg_RXHTXH,
59 eReg_RXMTXM,
60 eReg_RHLTXL,
61 eReg_RESETDSP,
62
63 eReg_CSUF,
64 eReg_CSES,
65 eReg_CRESMSB,
66 eReg_CRESLSB,
67 eReg_ADMACESMSB,
68 eReg_ADMACESLSB,
69 eReg_CONFES,
70
71 eMaxPortLx
72};
73
74unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
75void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
76
77/* plx register access */
78enum {
79 ePLX_PCICR,
80
81 ePLX_MBOX0,
82 ePLX_MBOX1,
83 ePLX_MBOX2,
84 ePLX_MBOX3,
85 ePLX_MBOX4,
86 ePLX_MBOX5,
87 ePLX_MBOX6,
88 ePLX_MBOX7,
89
90 ePLX_L2PCIDB,
91 ePLX_IRQCS,
92 ePLX_CHIPSC,
93
94 eMaxPort
95};
96
97unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
98void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
99
100/* rhm */
101struct lx_rmh {
102 u16 cmd_len; /* length of the command to send (WORDs) */
103 u16 stat_len; /* length of the status received (WORDs) */
104 u16 dsp_stat; /* status type, RMP_SSIZE_XXX */
105 u16 cmd_idx; /* index of the command */
106 u32 cmd[REG_CRM_NUMBER];
107 u32 stat[REG_CRM_NUMBER];
108};
109
110
111/* low-level dsp access */
112int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version);
113int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq);
114int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran);
115int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data);
116int lx_dsp_get_mac(struct lx6464es *chip);
117
118
119/* low-level pipe handling */
120int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
121 int channels);
122int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture);
123int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
124 u64 *rsample_count);
125int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate);
126int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture);
127int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture);
128int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture);
129
130int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture);
131int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture);
132
133/* low-level stream handling */
134int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
135 u32 pipe, int is_capture);
136int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
137 int *rstate);
138int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
139 u64 *r_bytepos);
140
141int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
142 int is_capture, enum stream_state_t state);
143
144static inline int lx_stream_start(struct lx6464es *chip, u32 pipe,
145 int is_capture)
146{
147 snd_printdd("->lx_stream_start\n");
148 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN);
149}
150
151static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe,
152 int is_capture)
153{
154 snd_printdd("->lx_stream_pause\n");
155 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE);
156}
157
158static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe,
159 int is_capture)
160{
161 snd_printdd("->lx_stream_stop\n");
162 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP);
163}
164
165/* low-level buffer handling */
166int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
167 u32 *r_needed, u32 *r_freed, u32 *size_array);
168int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
169 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
170 u32 *r_buffer_index);
171int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
172 u32 *r_buffer_size);
173int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
174 u32 buffer_index);
175
176/* low-level gain/peak handling */
177int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute);
178int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
179 u32 *r_levels);
180
181
182/* interrupt handling */
183irqreturn_t lx_interrupt(int irq, void *dev_id);
184void lx_irq_enable(struct lx6464es *chip);
185void lx_irq_disable(struct lx6464es *chip);
186
187void lx_tasklet_capture(unsigned long data);
188void lx_tasklet_playback(unsigned long data);
189
190
191/* Stream Format Header Defines (for LIN and IEEE754) */
192#define HEADER_FMT_BASE HEADER_FMT_BASE_LIN
193#define HEADER_FMT_BASE_LIN 0xFED00000
194#define HEADER_FMT_BASE_FLOAT 0xFAD00000
195#define HEADER_FMT_MONO 0x00000080 /* bit 23 in header_lo. WARNING: old
196 * bit 22 is ignored in float
197 * format */
198#define HEADER_FMT_INTEL 0x00008000
199#define HEADER_FMT_16BITS 0x00002000
200#define HEADER_FMT_24BITS 0x00004000
201#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.
202 * */
203#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less
204 * then 32k.*/
205
206
207#define BIT_FMP_HEADER 23
208#define BIT_FMP_SD 22
209#define BIT_FMP_MULTICHANNEL 19
210
211#define START_STATE 1
212#define PAUSE_STATE 0
213
214
215
216
217
218/* from PcxAll_e.h */
219/* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */
220#define START_PAUSE_IMMEDIATE 0
221#define START_PAUSE_ON_SYNCHRO 1
222#define START_PAUSE_ON_TIME_CODE 2
223
224
225/* Pipe / Stream state */
226#define START_STATE 1
227#define PAUSE_STATE 0
228
229static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high)
230{
231 *r_low = (u32)(ptr & 0xffffffff);
232#if BITS_PER_LONG == 32
233 *r_high = 0;
234#else
235 *r_high = (u32)((u64)ptr>>32);
236#endif
237}
238
239#endif /* LX_CORE_H */