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1// SPDX-License-Identifier: GPL-2.0-only
2/* drivers/rtc/rtc-s3c.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * Copyright (c) 2004,2006 Simtec Electronics
8 * Ben Dooks, <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C2410/S3C2440/S3C24XX Internal RTC Driver
12*/
13
14#include <linux/module.h>
15#include <linux/fs.h>
16#include <linux/string.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/rtc.h>
21#include <linux/bcd.h>
22#include <linux/clk.h>
23#include <linux/log2.h>
24#include <linux/slab.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/uaccess.h>
28#include <linux/io.h>
29
30#include <asm/irq.h>
31#include "rtc-s3c.h"
32
33struct s3c_rtc {
34 struct device *dev;
35 struct rtc_device *rtc;
36
37 void __iomem *base;
38 struct clk *rtc_clk;
39 struct clk *rtc_src_clk;
40 bool alarm_enabled;
41
42 const struct s3c_rtc_data *data;
43
44 int irq_alarm;
45 int irq_tick;
46
47 spinlock_t pie_lock;
48 spinlock_t alarm_lock;
49
50 int ticnt_save;
51 int ticnt_en_save;
52 bool wake_en;
53};
54
55struct s3c_rtc_data {
56 int max_user_freq;
57 bool needs_src_clk;
58
59 void (*irq_handler) (struct s3c_rtc *info, int mask);
60 void (*set_freq) (struct s3c_rtc *info, int freq);
61 void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq);
62 void (*select_tick_clk) (struct s3c_rtc *info);
63 void (*save_tick_cnt) (struct s3c_rtc *info);
64 void (*restore_tick_cnt) (struct s3c_rtc *info);
65 void (*enable) (struct s3c_rtc *info);
66 void (*disable) (struct s3c_rtc *info);
67};
68
69static int s3c_rtc_enable_clk(struct s3c_rtc *info)
70{
71 int ret;
72
73 ret = clk_enable(info->rtc_clk);
74 if (ret)
75 return ret;
76
77 if (info->data->needs_src_clk) {
78 ret = clk_enable(info->rtc_src_clk);
79 if (ret) {
80 clk_disable(info->rtc_clk);
81 return ret;
82 }
83 }
84 return 0;
85}
86
87static void s3c_rtc_disable_clk(struct s3c_rtc *info)
88{
89 if (info->data->needs_src_clk)
90 clk_disable(info->rtc_src_clk);
91 clk_disable(info->rtc_clk);
92}
93
94/* IRQ Handlers */
95static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
96{
97 struct s3c_rtc *info = (struct s3c_rtc *)id;
98
99 if (info->data->irq_handler)
100 info->data->irq_handler(info, S3C2410_INTP_TIC);
101
102 return IRQ_HANDLED;
103}
104
105static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
106{
107 struct s3c_rtc *info = (struct s3c_rtc *)id;
108
109 if (info->data->irq_handler)
110 info->data->irq_handler(info, S3C2410_INTP_ALM);
111
112 return IRQ_HANDLED;
113}
114
115/* Update control registers */
116static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
117{
118 struct s3c_rtc *info = dev_get_drvdata(dev);
119 unsigned long flags;
120 unsigned int tmp;
121 int ret;
122
123 dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled);
124
125 ret = s3c_rtc_enable_clk(info);
126 if (ret)
127 return ret;
128
129 tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
130
131 if (enabled)
132 tmp |= S3C2410_RTCALM_ALMEN;
133
134 writeb(tmp, info->base + S3C2410_RTCALM);
135
136 spin_lock_irqsave(&info->alarm_lock, flags);
137
138 if (info->alarm_enabled && !enabled)
139 s3c_rtc_disable_clk(info);
140 else if (!info->alarm_enabled && enabled)
141 ret = s3c_rtc_enable_clk(info);
142
143 info->alarm_enabled = enabled;
144 spin_unlock_irqrestore(&info->alarm_lock, flags);
145
146 s3c_rtc_disable_clk(info);
147
148 return ret;
149}
150
151/* Set RTC frequency */
152static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq)
153{
154 int ret;
155
156 if (!is_power_of_2(freq))
157 return -EINVAL;
158
159 ret = s3c_rtc_enable_clk(info);
160 if (ret)
161 return ret;
162 spin_lock_irq(&info->pie_lock);
163
164 if (info->data->set_freq)
165 info->data->set_freq(info, freq);
166
167 spin_unlock_irq(&info->pie_lock);
168 s3c_rtc_disable_clk(info);
169
170 return 0;
171}
172
173/* Time read/write */
174static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
175{
176 struct s3c_rtc *info = dev_get_drvdata(dev);
177 unsigned int have_retried = 0;
178 int ret;
179
180 ret = s3c_rtc_enable_clk(info);
181 if (ret)
182 return ret;
183
184retry_get_time:
185 rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN);
186 rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR);
187 rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE);
188 rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON);
189 rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR);
190 rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC);
191
192 /* the only way to work out whether the system was mid-update
193 * when we read it is to check the second counter, and if it
194 * is zero, then we re-try the entire read
195 */
196
197 if (rtc_tm->tm_sec == 0 && !have_retried) {
198 have_retried = 1;
199 goto retry_get_time;
200 }
201
202 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
203 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
204 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
205 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
206 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
207 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
208
209 s3c_rtc_disable_clk(info);
210
211 rtc_tm->tm_year += 100;
212 rtc_tm->tm_mon -= 1;
213
214 dev_dbg(dev, "read time %ptR\n", rtc_tm);
215 return 0;
216}
217
218static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
219{
220 struct s3c_rtc *info = dev_get_drvdata(dev);
221 int year = tm->tm_year - 100;
222 int ret;
223
224 dev_dbg(dev, "set time %ptR\n", tm);
225
226 /* we get around y2k by simply not supporting it */
227
228 if (year < 0 || year >= 100) {
229 dev_err(dev, "rtc only supports 100 years\n");
230 return -EINVAL;
231 }
232
233 ret = s3c_rtc_enable_clk(info);
234 if (ret)
235 return ret;
236
237 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC);
238 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN);
239 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR);
240 writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE);
241 writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON);
242 writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR);
243
244 s3c_rtc_disable_clk(info);
245
246 return 0;
247}
248
249static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
250{
251 struct s3c_rtc *info = dev_get_drvdata(dev);
252 struct rtc_time *alm_tm = &alrm->time;
253 unsigned int alm_en;
254 int ret;
255
256 ret = s3c_rtc_enable_clk(info);
257 if (ret)
258 return ret;
259
260 alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC);
261 alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN);
262 alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR);
263 alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON);
264 alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE);
265 alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR);
266
267 alm_en = readb(info->base + S3C2410_RTCALM);
268
269 s3c_rtc_disable_clk(info);
270
271 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
272
273 dev_dbg(dev, "read alarm %d, %ptR\n", alm_en, alm_tm);
274
275 /* decode the alarm enable field */
276 if (alm_en & S3C2410_RTCALM_SECEN)
277 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
278
279 if (alm_en & S3C2410_RTCALM_MINEN)
280 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
281
282 if (alm_en & S3C2410_RTCALM_HOUREN)
283 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
284
285 if (alm_en & S3C2410_RTCALM_DAYEN)
286 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
287
288 if (alm_en & S3C2410_RTCALM_MONEN) {
289 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
290 alm_tm->tm_mon -= 1;
291 }
292
293 if (alm_en & S3C2410_RTCALM_YEAREN)
294 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
295
296 return 0;
297}
298
299static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
300{
301 struct s3c_rtc *info = dev_get_drvdata(dev);
302 struct rtc_time *tm = &alrm->time;
303 unsigned int alrm_en;
304 int ret;
305
306 dev_dbg(dev, "s3c_rtc_setalarm: %d, %ptR\n", alrm->enabled, tm);
307
308 ret = s3c_rtc_enable_clk(info);
309 if (ret)
310 return ret;
311
312 alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
313 writeb(0x00, info->base + S3C2410_RTCALM);
314
315 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
316 alrm_en |= S3C2410_RTCALM_SECEN;
317 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC);
318 }
319
320 if (tm->tm_min < 60 && tm->tm_min >= 0) {
321 alrm_en |= S3C2410_RTCALM_MINEN;
322 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN);
323 }
324
325 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
326 alrm_en |= S3C2410_RTCALM_HOUREN;
327 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR);
328 }
329
330 if (tm->tm_mon < 12 && tm->tm_mon >= 0) {
331 alrm_en |= S3C2410_RTCALM_MONEN;
332 writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON);
333 }
334
335 if (tm->tm_mday <= 31 && tm->tm_mday >= 1) {
336 alrm_en |= S3C2410_RTCALM_DAYEN;
337 writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE);
338 }
339
340 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
341
342 writeb(alrm_en, info->base + S3C2410_RTCALM);
343
344 s3c_rtc_setaie(dev, alrm->enabled);
345
346 s3c_rtc_disable_clk(info);
347
348 return 0;
349}
350
351static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
352{
353 struct s3c_rtc *info = dev_get_drvdata(dev);
354 int ret;
355
356 ret = s3c_rtc_enable_clk(info);
357 if (ret)
358 return ret;
359
360 if (info->data->enable_tick)
361 info->data->enable_tick(info, seq);
362
363 s3c_rtc_disable_clk(info);
364
365 return 0;
366}
367
368static const struct rtc_class_ops s3c_rtcops = {
369 .read_time = s3c_rtc_gettime,
370 .set_time = s3c_rtc_settime,
371 .read_alarm = s3c_rtc_getalarm,
372 .set_alarm = s3c_rtc_setalarm,
373 .proc = s3c_rtc_proc,
374 .alarm_irq_enable = s3c_rtc_setaie,
375};
376
377static void s3c24xx_rtc_enable(struct s3c_rtc *info)
378{
379 unsigned int con, tmp;
380
381 con = readw(info->base + S3C2410_RTCCON);
382 /* re-enable the device, and check it is ok */
383 if ((con & S3C2410_RTCCON_RTCEN) == 0) {
384 dev_info(info->dev, "rtc disabled, re-enabling\n");
385
386 tmp = readw(info->base + S3C2410_RTCCON);
387 writew(tmp | S3C2410_RTCCON_RTCEN, info->base + S3C2410_RTCCON);
388 }
389
390 if (con & S3C2410_RTCCON_CNTSEL) {
391 dev_info(info->dev, "removing RTCCON_CNTSEL\n");
392
393 tmp = readw(info->base + S3C2410_RTCCON);
394 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
395 info->base + S3C2410_RTCCON);
396 }
397
398 if (con & S3C2410_RTCCON_CLKRST) {
399 dev_info(info->dev, "removing RTCCON_CLKRST\n");
400
401 tmp = readw(info->base + S3C2410_RTCCON);
402 writew(tmp & ~S3C2410_RTCCON_CLKRST,
403 info->base + S3C2410_RTCCON);
404 }
405}
406
407static void s3c24xx_rtc_disable(struct s3c_rtc *info)
408{
409 unsigned int con;
410
411 con = readw(info->base + S3C2410_RTCCON);
412 con &= ~S3C2410_RTCCON_RTCEN;
413 writew(con, info->base + S3C2410_RTCCON);
414
415 con = readb(info->base + S3C2410_TICNT);
416 con &= ~S3C2410_TICNT_ENABLE;
417 writeb(con, info->base + S3C2410_TICNT);
418}
419
420static void s3c6410_rtc_disable(struct s3c_rtc *info)
421{
422 unsigned int con;
423
424 con = readw(info->base + S3C2410_RTCCON);
425 con &= ~S3C64XX_RTCCON_TICEN;
426 con &= ~S3C2410_RTCCON_RTCEN;
427 writew(con, info->base + S3C2410_RTCCON);
428}
429
430static int s3c_rtc_remove(struct platform_device *pdev)
431{
432 struct s3c_rtc *info = platform_get_drvdata(pdev);
433
434 s3c_rtc_setaie(info->dev, 0);
435
436 if (info->data->needs_src_clk)
437 clk_unprepare(info->rtc_src_clk);
438 clk_unprepare(info->rtc_clk);
439
440 return 0;
441}
442
443static int s3c_rtc_probe(struct platform_device *pdev)
444{
445 struct s3c_rtc *info = NULL;
446 struct rtc_time rtc_tm;
447 int ret;
448
449 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
450 if (!info)
451 return -ENOMEM;
452
453 /* find the IRQs */
454 info->irq_tick = platform_get_irq(pdev, 1);
455 if (info->irq_tick < 0)
456 return info->irq_tick;
457
458 info->dev = &pdev->dev;
459 info->data = of_device_get_match_data(&pdev->dev);
460 if (!info->data) {
461 dev_err(&pdev->dev, "failed getting s3c_rtc_data\n");
462 return -EINVAL;
463 }
464 spin_lock_init(&info->pie_lock);
465 spin_lock_init(&info->alarm_lock);
466
467 platform_set_drvdata(pdev, info);
468
469 info->irq_alarm = platform_get_irq(pdev, 0);
470 if (info->irq_alarm < 0)
471 return info->irq_alarm;
472
473 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
474 info->irq_tick, info->irq_alarm);
475
476 /* get the memory region */
477 info->base = devm_platform_ioremap_resource(pdev, 0);
478 if (IS_ERR(info->base))
479 return PTR_ERR(info->base);
480
481 info->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
482 if (IS_ERR(info->rtc_clk)) {
483 ret = PTR_ERR(info->rtc_clk);
484 if (ret != -EPROBE_DEFER)
485 dev_err(&pdev->dev, "failed to find rtc clock\n");
486 else
487 dev_dbg(&pdev->dev, "probe deferred due to missing rtc clk\n");
488 return ret;
489 }
490 ret = clk_prepare_enable(info->rtc_clk);
491 if (ret)
492 return ret;
493
494 if (info->data->needs_src_clk) {
495 info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src");
496 if (IS_ERR(info->rtc_src_clk)) {
497 ret = PTR_ERR(info->rtc_src_clk);
498 if (ret != -EPROBE_DEFER)
499 dev_err(&pdev->dev,
500 "failed to find rtc source clock\n");
501 else
502 dev_dbg(&pdev->dev,
503 "probe deferred due to missing rtc src clk\n");
504 goto err_src_clk;
505 }
506 ret = clk_prepare_enable(info->rtc_src_clk);
507 if (ret)
508 goto err_src_clk;
509 }
510
511 /* check to see if everything is setup correctly */
512 if (info->data->enable)
513 info->data->enable(info);
514
515 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
516 readw(info->base + S3C2410_RTCCON));
517
518 device_init_wakeup(&pdev->dev, 1);
519
520 /* Check RTC Time */
521 if (s3c_rtc_gettime(&pdev->dev, &rtc_tm)) {
522 rtc_tm.tm_year = 100;
523 rtc_tm.tm_mon = 0;
524 rtc_tm.tm_mday = 1;
525 rtc_tm.tm_hour = 0;
526 rtc_tm.tm_min = 0;
527 rtc_tm.tm_sec = 0;
528
529 s3c_rtc_settime(&pdev->dev, &rtc_tm);
530
531 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
532 }
533
534 /* register RTC and exit */
535 info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
536 THIS_MODULE);
537 if (IS_ERR(info->rtc)) {
538 dev_err(&pdev->dev, "cannot attach rtc\n");
539 ret = PTR_ERR(info->rtc);
540 goto err_nortc;
541 }
542
543 ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq,
544 0, "s3c2410-rtc alarm", info);
545 if (ret) {
546 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret);
547 goto err_nortc;
548 }
549
550 ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq,
551 0, "s3c2410-rtc tick", info);
552 if (ret) {
553 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret);
554 goto err_nortc;
555 }
556
557 if (info->data->select_tick_clk)
558 info->data->select_tick_clk(info);
559
560 s3c_rtc_setfreq(info, 1);
561
562 s3c_rtc_disable_clk(info);
563
564 return 0;
565
566err_nortc:
567 if (info->data->disable)
568 info->data->disable(info);
569
570 if (info->data->needs_src_clk)
571 clk_disable_unprepare(info->rtc_src_clk);
572err_src_clk:
573 clk_disable_unprepare(info->rtc_clk);
574
575 return ret;
576}
577
578#ifdef CONFIG_PM_SLEEP
579
580static int s3c_rtc_suspend(struct device *dev)
581{
582 struct s3c_rtc *info = dev_get_drvdata(dev);
583 int ret;
584
585 ret = s3c_rtc_enable_clk(info);
586 if (ret)
587 return ret;
588
589 /* save TICNT for anyone using periodic interrupts */
590 if (info->data->save_tick_cnt)
591 info->data->save_tick_cnt(info);
592
593 if (info->data->disable)
594 info->data->disable(info);
595
596 if (device_may_wakeup(dev) && !info->wake_en) {
597 if (enable_irq_wake(info->irq_alarm) == 0)
598 info->wake_en = true;
599 else
600 dev_err(dev, "enable_irq_wake failed\n");
601 }
602
603 return 0;
604}
605
606static int s3c_rtc_resume(struct device *dev)
607{
608 struct s3c_rtc *info = dev_get_drvdata(dev);
609
610 if (info->data->enable)
611 info->data->enable(info);
612
613 if (info->data->restore_tick_cnt)
614 info->data->restore_tick_cnt(info);
615
616 s3c_rtc_disable_clk(info);
617
618 if (device_may_wakeup(dev) && info->wake_en) {
619 disable_irq_wake(info->irq_alarm);
620 info->wake_en = false;
621 }
622
623 return 0;
624}
625#endif
626static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
627
628static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask)
629{
630 rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
631}
632
633static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask)
634{
635 rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
636 writeb(mask, info->base + S3C2410_INTP);
637}
638
639static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq)
640{
641 unsigned int tmp = 0;
642 int val;
643
644 tmp = readb(info->base + S3C2410_TICNT);
645 tmp &= S3C2410_TICNT_ENABLE;
646
647 val = (info->rtc->max_user_freq / freq) - 1;
648 tmp |= val;
649
650 writel(tmp, info->base + S3C2410_TICNT);
651}
652
653static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq)
654{
655 unsigned int tmp = 0;
656 int val;
657
658 tmp = readb(info->base + S3C2410_TICNT);
659 tmp &= S3C2410_TICNT_ENABLE;
660
661 val = (info->rtc->max_user_freq / freq) - 1;
662
663 tmp |= S3C2443_TICNT_PART(val);
664 writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
665
666 writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2);
667
668 writel(tmp, info->base + S3C2410_TICNT);
669}
670
671static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq)
672{
673 unsigned int tmp = 0;
674 int val;
675
676 tmp = readb(info->base + S3C2410_TICNT);
677 tmp &= S3C2410_TICNT_ENABLE;
678
679 val = (info->rtc->max_user_freq / freq) - 1;
680
681 tmp |= S3C2443_TICNT_PART(val);
682 writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
683
684 writel(tmp, info->base + S3C2410_TICNT);
685}
686
687static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq)
688{
689 int val;
690
691 val = (info->rtc->max_user_freq / freq) - 1;
692 writel(val, info->base + S3C2410_TICNT);
693}
694
695static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq)
696{
697 unsigned int ticnt;
698
699 ticnt = readb(info->base + S3C2410_TICNT);
700 ticnt &= S3C2410_TICNT_ENABLE;
701
702 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
703}
704
705static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info)
706{
707 unsigned int con;
708
709 con = readw(info->base + S3C2410_RTCCON);
710 con |= S3C2443_RTCCON_TICSEL;
711 writew(con, info->base + S3C2410_RTCCON);
712}
713
714static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq)
715{
716 unsigned int ticnt;
717
718 ticnt = readw(info->base + S3C2410_RTCCON);
719 ticnt &= S3C64XX_RTCCON_TICEN;
720
721 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
722}
723
724static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info)
725{
726 info->ticnt_save = readb(info->base + S3C2410_TICNT);
727}
728
729static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info)
730{
731 writeb(info->ticnt_save, info->base + S3C2410_TICNT);
732}
733
734static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info)
735{
736 info->ticnt_en_save = readw(info->base + S3C2410_RTCCON);
737 info->ticnt_en_save &= S3C64XX_RTCCON_TICEN;
738 info->ticnt_save = readl(info->base + S3C2410_TICNT);
739}
740
741static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info)
742{
743 unsigned int con;
744
745 writel(info->ticnt_save, info->base + S3C2410_TICNT);
746 if (info->ticnt_en_save) {
747 con = readw(info->base + S3C2410_RTCCON);
748 writew(con | info->ticnt_en_save, info->base + S3C2410_RTCCON);
749 }
750}
751
752static struct s3c_rtc_data const s3c2410_rtc_data = {
753 .max_user_freq = 128,
754 .irq_handler = s3c24xx_rtc_irq,
755 .set_freq = s3c2410_rtc_setfreq,
756 .enable_tick = s3c24xx_rtc_enable_tick,
757 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
758 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
759 .enable = s3c24xx_rtc_enable,
760 .disable = s3c24xx_rtc_disable,
761};
762
763static struct s3c_rtc_data const s3c2416_rtc_data = {
764 .max_user_freq = 32768,
765 .irq_handler = s3c24xx_rtc_irq,
766 .set_freq = s3c2416_rtc_setfreq,
767 .enable_tick = s3c24xx_rtc_enable_tick,
768 .select_tick_clk = s3c2416_rtc_select_tick_clk,
769 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
770 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
771 .enable = s3c24xx_rtc_enable,
772 .disable = s3c24xx_rtc_disable,
773};
774
775static struct s3c_rtc_data const s3c2443_rtc_data = {
776 .max_user_freq = 32768,
777 .irq_handler = s3c24xx_rtc_irq,
778 .set_freq = s3c2443_rtc_setfreq,
779 .enable_tick = s3c24xx_rtc_enable_tick,
780 .select_tick_clk = s3c2416_rtc_select_tick_clk,
781 .save_tick_cnt = s3c24xx_rtc_save_tick_cnt,
782 .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt,
783 .enable = s3c24xx_rtc_enable,
784 .disable = s3c24xx_rtc_disable,
785};
786
787static struct s3c_rtc_data const s3c6410_rtc_data = {
788 .max_user_freq = 32768,
789 .needs_src_clk = true,
790 .irq_handler = s3c6410_rtc_irq,
791 .set_freq = s3c6410_rtc_setfreq,
792 .enable_tick = s3c6410_rtc_enable_tick,
793 .save_tick_cnt = s3c6410_rtc_save_tick_cnt,
794 .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt,
795 .enable = s3c24xx_rtc_enable,
796 .disable = s3c6410_rtc_disable,
797};
798
799static const struct of_device_id s3c_rtc_dt_match[] = {
800 {
801 .compatible = "samsung,s3c2410-rtc",
802 .data = &s3c2410_rtc_data,
803 }, {
804 .compatible = "samsung,s3c2416-rtc",
805 .data = &s3c2416_rtc_data,
806 }, {
807 .compatible = "samsung,s3c2443-rtc",
808 .data = &s3c2443_rtc_data,
809 }, {
810 .compatible = "samsung,s3c6410-rtc",
811 .data = &s3c6410_rtc_data,
812 }, {
813 .compatible = "samsung,exynos3250-rtc",
814 .data = &s3c6410_rtc_data,
815 },
816 { /* sentinel */ },
817};
818MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
819
820static struct platform_driver s3c_rtc_driver = {
821 .probe = s3c_rtc_probe,
822 .remove = s3c_rtc_remove,
823 .driver = {
824 .name = "s3c-rtc",
825 .pm = &s3c_rtc_pm_ops,
826 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
827 },
828};
829module_platform_driver(s3c_rtc_driver);
830
831MODULE_DESCRIPTION("Samsung S3C RTC Driver");
832MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
833MODULE_LICENSE("GPL");
834MODULE_ALIAS("platform:s3c2410-rtc");
1/* drivers/rtc/rtc-s3c.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright (c) 2004,2006 Simtec Electronics
7 * Ben Dooks, <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S3C2410/S3C2440/S3C24XX Internal RTC Driver
15*/
16
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/bcd.h>
25#include <linux/clk.h>
26#include <linux/log2.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/uaccess.h>
30#include <linux/io.h>
31
32#include <asm/irq.h>
33#include "rtc-s3c.h"
34
35enum s3c_cpu_type {
36 TYPE_S3C2410,
37 TYPE_S3C2416,
38 TYPE_S3C2443,
39 TYPE_S3C64XX,
40};
41
42struct s3c_rtc_drv_data {
43 int cpu_type;
44};
45
46/* I have yet to find an S3C implementation with more than one
47 * of these rtc blocks in */
48
49static struct clk *rtc_clk;
50static void __iomem *s3c_rtc_base;
51static int s3c_rtc_alarmno;
52static int s3c_rtc_tickno;
53static enum s3c_cpu_type s3c_rtc_cpu_type;
54
55static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
56
57static void s3c_rtc_alarm_clk_enable(bool enable)
58{
59 static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
60 static bool alarm_clk_enabled;
61 unsigned long irq_flags;
62
63 spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
64 if (enable) {
65 if (!alarm_clk_enabled) {
66 clk_enable(rtc_clk);
67 alarm_clk_enabled = true;
68 }
69 } else {
70 if (alarm_clk_enabled) {
71 clk_disable(rtc_clk);
72 alarm_clk_enabled = false;
73 }
74 }
75 spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
76}
77
78/* IRQ Handlers */
79
80static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
81{
82 struct rtc_device *rdev = id;
83
84 clk_enable(rtc_clk);
85 rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
86
87 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
88 writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
89
90 clk_disable(rtc_clk);
91
92 s3c_rtc_alarm_clk_enable(false);
93
94 return IRQ_HANDLED;
95}
96
97static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
98{
99 struct rtc_device *rdev = id;
100
101 clk_enable(rtc_clk);
102 rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
103
104 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
105 writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
106
107 clk_disable(rtc_clk);
108 return IRQ_HANDLED;
109}
110
111/* Update control registers */
112static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
113{
114 unsigned int tmp;
115
116 dev_dbg(dev, "%s: aie=%d\n", __func__, enabled);
117
118 clk_enable(rtc_clk);
119 tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
120
121 if (enabled)
122 tmp |= S3C2410_RTCALM_ALMEN;
123
124 writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
125 clk_disable(rtc_clk);
126
127 s3c_rtc_alarm_clk_enable(enabled);
128
129 return 0;
130}
131
132static int s3c_rtc_setfreq(struct device *dev, int freq)
133{
134 struct platform_device *pdev = to_platform_device(dev);
135 struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
136 unsigned int tmp = 0;
137 int val;
138
139 if (!is_power_of_2(freq))
140 return -EINVAL;
141
142 clk_enable(rtc_clk);
143 spin_lock_irq(&s3c_rtc_pie_lock);
144
145 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
146 tmp = readb(s3c_rtc_base + S3C2410_TICNT);
147 tmp &= S3C2410_TICNT_ENABLE;
148 }
149
150 val = (rtc_dev->max_user_freq / freq) - 1;
151
152 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
153 tmp |= S3C2443_TICNT_PART(val);
154 writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
155
156 if (s3c_rtc_cpu_type == TYPE_S3C2416)
157 writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
158 } else {
159 tmp |= val;
160 }
161
162 writel(tmp, s3c_rtc_base + S3C2410_TICNT);
163 spin_unlock_irq(&s3c_rtc_pie_lock);
164 clk_disable(rtc_clk);
165
166 return 0;
167}
168
169/* Time read/write */
170
171static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
172{
173 unsigned int have_retried = 0;
174 void __iomem *base = s3c_rtc_base;
175
176 clk_enable(rtc_clk);
177 retry_get_time:
178 rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
179 rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
180 rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
181 rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
182 rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
183 rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
184
185 /* the only way to work out whether the system was mid-update
186 * when we read it is to check the second counter, and if it
187 * is zero, then we re-try the entire read
188 */
189
190 if (rtc_tm->tm_sec == 0 && !have_retried) {
191 have_retried = 1;
192 goto retry_get_time;
193 }
194
195 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
196 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
197 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
198 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
199 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
200 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
201
202 rtc_tm->tm_year += 100;
203
204 dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
205 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
206 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
207
208 rtc_tm->tm_mon -= 1;
209
210 clk_disable(rtc_clk);
211 return rtc_valid_tm(rtc_tm);
212}
213
214static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
215{
216 void __iomem *base = s3c_rtc_base;
217 int year = tm->tm_year - 100;
218
219 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
220 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
221 tm->tm_hour, tm->tm_min, tm->tm_sec);
222
223 /* we get around y2k by simply not supporting it */
224
225 if (year < 0 || year >= 100) {
226 dev_err(dev, "rtc only supports 100 years\n");
227 return -EINVAL;
228 }
229
230 clk_enable(rtc_clk);
231 writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
232 writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
233 writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
234 writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
235 writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
236 writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
237 clk_disable(rtc_clk);
238
239 return 0;
240}
241
242static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
243{
244 struct rtc_time *alm_tm = &alrm->time;
245 void __iomem *base = s3c_rtc_base;
246 unsigned int alm_en;
247
248 clk_enable(rtc_clk);
249 alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
250 alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
251 alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
252 alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
253 alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
254 alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
255
256 alm_en = readb(base + S3C2410_RTCALM);
257
258 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
259
260 dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
261 alm_en,
262 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
263 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
264
265
266 /* decode the alarm enable field */
267
268 if (alm_en & S3C2410_RTCALM_SECEN)
269 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
270 else
271 alm_tm->tm_sec = -1;
272
273 if (alm_en & S3C2410_RTCALM_MINEN)
274 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
275 else
276 alm_tm->tm_min = -1;
277
278 if (alm_en & S3C2410_RTCALM_HOUREN)
279 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
280 else
281 alm_tm->tm_hour = -1;
282
283 if (alm_en & S3C2410_RTCALM_DAYEN)
284 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
285 else
286 alm_tm->tm_mday = -1;
287
288 if (alm_en & S3C2410_RTCALM_MONEN) {
289 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
290 alm_tm->tm_mon -= 1;
291 } else {
292 alm_tm->tm_mon = -1;
293 }
294
295 if (alm_en & S3C2410_RTCALM_YEAREN)
296 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
297 else
298 alm_tm->tm_year = -1;
299
300 clk_disable(rtc_clk);
301 return 0;
302}
303
304static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
305{
306 struct rtc_time *tm = &alrm->time;
307 void __iomem *base = s3c_rtc_base;
308 unsigned int alrm_en;
309
310 clk_enable(rtc_clk);
311 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
312 alrm->enabled,
313 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
314 tm->tm_hour, tm->tm_min, tm->tm_sec);
315
316 alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
317 writeb(0x00, base + S3C2410_RTCALM);
318
319 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
320 alrm_en |= S3C2410_RTCALM_SECEN;
321 writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
322 }
323
324 if (tm->tm_min < 60 && tm->tm_min >= 0) {
325 alrm_en |= S3C2410_RTCALM_MINEN;
326 writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
327 }
328
329 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
330 alrm_en |= S3C2410_RTCALM_HOUREN;
331 writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
332 }
333
334 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
335
336 writeb(alrm_en, base + S3C2410_RTCALM);
337
338 s3c_rtc_setaie(dev, alrm->enabled);
339
340 clk_disable(rtc_clk);
341 return 0;
342}
343
344static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
345{
346 unsigned int ticnt;
347
348 clk_enable(rtc_clk);
349 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
350 ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
351 ticnt &= S3C64XX_RTCCON_TICEN;
352 } else {
353 ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
354 ticnt &= S3C2410_TICNT_ENABLE;
355 }
356
357 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
358 clk_disable(rtc_clk);
359 return 0;
360}
361
362static const struct rtc_class_ops s3c_rtcops = {
363 .read_time = s3c_rtc_gettime,
364 .set_time = s3c_rtc_settime,
365 .read_alarm = s3c_rtc_getalarm,
366 .set_alarm = s3c_rtc_setalarm,
367 .proc = s3c_rtc_proc,
368 .alarm_irq_enable = s3c_rtc_setaie,
369};
370
371static void s3c_rtc_enable(struct platform_device *pdev, int en)
372{
373 void __iomem *base = s3c_rtc_base;
374 unsigned int tmp;
375
376 if (s3c_rtc_base == NULL)
377 return;
378
379 clk_enable(rtc_clk);
380 if (!en) {
381 tmp = readw(base + S3C2410_RTCCON);
382 if (s3c_rtc_cpu_type == TYPE_S3C64XX)
383 tmp &= ~S3C64XX_RTCCON_TICEN;
384 tmp &= ~S3C2410_RTCCON_RTCEN;
385 writew(tmp, base + S3C2410_RTCCON);
386
387 if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
388 tmp = readb(base + S3C2410_TICNT);
389 tmp &= ~S3C2410_TICNT_ENABLE;
390 writeb(tmp, base + S3C2410_TICNT);
391 }
392 } else {
393 /* re-enable the device, and check it is ok */
394
395 if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
396 dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
397
398 tmp = readw(base + S3C2410_RTCCON);
399 writew(tmp | S3C2410_RTCCON_RTCEN,
400 base + S3C2410_RTCCON);
401 }
402
403 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
404 dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
405
406 tmp = readw(base + S3C2410_RTCCON);
407 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
408 base + S3C2410_RTCCON);
409 }
410
411 if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
412 dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
413
414 tmp = readw(base + S3C2410_RTCCON);
415 writew(tmp & ~S3C2410_RTCCON_CLKRST,
416 base + S3C2410_RTCCON);
417 }
418 }
419 clk_disable(rtc_clk);
420}
421
422static int s3c_rtc_remove(struct platform_device *dev)
423{
424 s3c_rtc_setaie(&dev->dev, 0);
425
426 clk_unprepare(rtc_clk);
427 rtc_clk = NULL;
428
429 return 0;
430}
431
432static const struct of_device_id s3c_rtc_dt_match[];
433
434static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
435{
436#ifdef CONFIG_OF
437 struct s3c_rtc_drv_data *data;
438 if (pdev->dev.of_node) {
439 const struct of_device_id *match;
440 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
441 data = (struct s3c_rtc_drv_data *) match->data;
442 return data->cpu_type;
443 }
444#endif
445 return platform_get_device_id(pdev)->driver_data;
446}
447
448static int s3c_rtc_probe(struct platform_device *pdev)
449{
450 struct rtc_device *rtc;
451 struct rtc_time rtc_tm;
452 struct resource *res;
453 int ret;
454 int tmp;
455
456 dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev);
457
458 /* find the IRQs */
459
460 s3c_rtc_tickno = platform_get_irq(pdev, 1);
461 if (s3c_rtc_tickno < 0) {
462 dev_err(&pdev->dev, "no irq for rtc tick\n");
463 return s3c_rtc_tickno;
464 }
465
466 s3c_rtc_alarmno = platform_get_irq(pdev, 0);
467 if (s3c_rtc_alarmno < 0) {
468 dev_err(&pdev->dev, "no irq for alarm\n");
469 return s3c_rtc_alarmno;
470 }
471
472 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
473 s3c_rtc_tickno, s3c_rtc_alarmno);
474
475 /* get the memory region */
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res);
479 if (IS_ERR(s3c_rtc_base))
480 return PTR_ERR(s3c_rtc_base);
481
482 rtc_clk = devm_clk_get(&pdev->dev, "rtc");
483 if (IS_ERR(rtc_clk)) {
484 dev_err(&pdev->dev, "failed to find rtc clock source\n");
485 ret = PTR_ERR(rtc_clk);
486 rtc_clk = NULL;
487 return ret;
488 }
489
490 clk_prepare_enable(rtc_clk);
491
492 /* check to see if everything is setup correctly */
493
494 s3c_rtc_enable(pdev, 1);
495
496 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
497 readw(s3c_rtc_base + S3C2410_RTCCON));
498
499 device_init_wakeup(&pdev->dev, 1);
500
501 /* register RTC and exit */
502
503 rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
504 THIS_MODULE);
505
506 if (IS_ERR(rtc)) {
507 dev_err(&pdev->dev, "cannot attach rtc\n");
508 ret = PTR_ERR(rtc);
509 goto err_nortc;
510 }
511
512 s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
513
514 /* Check RTC Time */
515
516 s3c_rtc_gettime(NULL, &rtc_tm);
517
518 if (rtc_valid_tm(&rtc_tm)) {
519 rtc_tm.tm_year = 100;
520 rtc_tm.tm_mon = 0;
521 rtc_tm.tm_mday = 1;
522 rtc_tm.tm_hour = 0;
523 rtc_tm.tm_min = 0;
524 rtc_tm.tm_sec = 0;
525
526 s3c_rtc_settime(NULL, &rtc_tm);
527
528 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
529 }
530
531 if (s3c_rtc_cpu_type != TYPE_S3C2410)
532 rtc->max_user_freq = 32768;
533 else
534 rtc->max_user_freq = 128;
535
536 if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
537 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
538 tmp |= S3C2443_RTCCON_TICSEL;
539 writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
540 }
541
542 platform_set_drvdata(pdev, rtc);
543
544 s3c_rtc_setfreq(&pdev->dev, 1);
545
546 ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
547 0, "s3c2410-rtc alarm", rtc);
548 if (ret) {
549 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
550 goto err_nortc;
551 }
552
553 ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
554 0, "s3c2410-rtc tick", rtc);
555 if (ret) {
556 dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
557 goto err_nortc;
558 }
559
560 clk_disable(rtc_clk);
561
562 return 0;
563
564 err_nortc:
565 s3c_rtc_enable(pdev, 0);
566 clk_disable_unprepare(rtc_clk);
567
568 return ret;
569}
570
571#ifdef CONFIG_PM_SLEEP
572/* RTC Power management control */
573
574static int ticnt_save, ticnt_en_save;
575static bool wake_en;
576
577static int s3c_rtc_suspend(struct device *dev)
578{
579 struct platform_device *pdev = to_platform_device(dev);
580
581 clk_enable(rtc_clk);
582 /* save TICNT for anyone using periodic interrupts */
583 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
584 ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
585 ticnt_en_save &= S3C64XX_RTCCON_TICEN;
586 ticnt_save = readl(s3c_rtc_base + S3C2410_TICNT);
587 } else {
588 ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
589 }
590 s3c_rtc_enable(pdev, 0);
591
592 if (device_may_wakeup(dev) && !wake_en) {
593 if (enable_irq_wake(s3c_rtc_alarmno) == 0)
594 wake_en = true;
595 else
596 dev_err(dev, "enable_irq_wake failed\n");
597 }
598 clk_disable(rtc_clk);
599
600 return 0;
601}
602
603static int s3c_rtc_resume(struct device *dev)
604{
605 struct platform_device *pdev = to_platform_device(dev);
606 unsigned int tmp;
607
608 clk_enable(rtc_clk);
609 s3c_rtc_enable(pdev, 1);
610 if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
611 writel(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
612 if (ticnt_en_save) {
613 tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
614 writew(tmp | ticnt_en_save,
615 s3c_rtc_base + S3C2410_RTCCON);
616 }
617 } else {
618 writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
619 }
620
621 if (device_may_wakeup(dev) && wake_en) {
622 disable_irq_wake(s3c_rtc_alarmno);
623 wake_en = false;
624 }
625 clk_disable(rtc_clk);
626
627 return 0;
628}
629#endif
630
631static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
632
633#ifdef CONFIG_OF
634static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
635 [TYPE_S3C2410] = { TYPE_S3C2410 },
636 [TYPE_S3C2416] = { TYPE_S3C2416 },
637 [TYPE_S3C2443] = { TYPE_S3C2443 },
638 [TYPE_S3C64XX] = { TYPE_S3C64XX },
639};
640
641static const struct of_device_id s3c_rtc_dt_match[] = {
642 {
643 .compatible = "samsung,s3c2410-rtc",
644 .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
645 }, {
646 .compatible = "samsung,s3c2416-rtc",
647 .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
648 }, {
649 .compatible = "samsung,s3c2443-rtc",
650 .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
651 }, {
652 .compatible = "samsung,s3c6410-rtc",
653 .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
654 },
655 {},
656};
657MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
658#endif
659
660static struct platform_device_id s3c_rtc_driver_ids[] = {
661 {
662 .name = "s3c2410-rtc",
663 .driver_data = TYPE_S3C2410,
664 }, {
665 .name = "s3c2416-rtc",
666 .driver_data = TYPE_S3C2416,
667 }, {
668 .name = "s3c2443-rtc",
669 .driver_data = TYPE_S3C2443,
670 }, {
671 .name = "s3c64xx-rtc",
672 .driver_data = TYPE_S3C64XX,
673 },
674 { }
675};
676
677MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
678
679static struct platform_driver s3c_rtc_driver = {
680 .probe = s3c_rtc_probe,
681 .remove = s3c_rtc_remove,
682 .id_table = s3c_rtc_driver_ids,
683 .driver = {
684 .name = "s3c-rtc",
685 .owner = THIS_MODULE,
686 .pm = &s3c_rtc_pm_ops,
687 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
688 },
689};
690
691module_platform_driver(s3c_rtc_driver);
692
693MODULE_DESCRIPTION("Samsung S3C RTC Driver");
694MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
695MODULE_LICENSE("GPL");
696MODULE_ALIAS("platform:s3c2410-rtc");