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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SGI IOC3 multifunction device driver
4 *
5 * Copyright (C) 2018, 2019 Thomas Bogendoerfer <tbogendoerfer@suse.de>
6 *
7 * Based on work by:
8 * Stanislaw Skowronek <skylark@unaligned.org>
9 * Joshua Kinard <kumba@gentoo.org>
10 * Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
11 * Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
12 */
13
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/mfd/core.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/platform_device.h>
21#include <linux/platform_data/sgi-w1.h>
22#include <linux/rtc/ds1685.h>
23
24#include <asm/pci/bridge.h>
25#include <asm/sn/ioc3.h>
26
27#define IOC3_IRQ_SERIAL_A 6
28#define IOC3_IRQ_SERIAL_B 15
29#define IOC3_IRQ_KBD 22
30
31/* Bitmask for selecting which IRQs are level triggered */
32#define IOC3_LVL_MASK (BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))
33
34#define M48T35_REG_SIZE 32768 /* size of m48t35 registers */
35
36/* 1.2 us latency timer (40 cycles at 33 MHz) */
37#define IOC3_LATENCY 40
38
39struct ioc3_priv_data {
40 struct irq_domain *domain;
41 struct ioc3 __iomem *regs;
42 struct pci_dev *pdev;
43 int domain_irq;
44};
45
46static void ioc3_irq_ack(struct irq_data *d)
47{
48 struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
49 unsigned int hwirq = irqd_to_hwirq(d);
50
51 writel(BIT(hwirq), &ipd->regs->sio_ir);
52}
53
54static void ioc3_irq_mask(struct irq_data *d)
55{
56 struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
57 unsigned int hwirq = irqd_to_hwirq(d);
58
59 writel(BIT(hwirq), &ipd->regs->sio_iec);
60}
61
62static void ioc3_irq_unmask(struct irq_data *d)
63{
64 struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
65 unsigned int hwirq = irqd_to_hwirq(d);
66
67 writel(BIT(hwirq), &ipd->regs->sio_ies);
68}
69
70static struct irq_chip ioc3_irq_chip = {
71 .name = "IOC3",
72 .irq_ack = ioc3_irq_ack,
73 .irq_mask = ioc3_irq_mask,
74 .irq_unmask = ioc3_irq_unmask,
75};
76
77static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
78 irq_hw_number_t hwirq)
79{
80 /* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
81 if (BIT(hwirq) & IOC3_LVL_MASK)
82 irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
83 else
84 irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);
85
86 irq_set_chip_data(irq, d->host_data);
87 return 0;
88}
89
90static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
91{
92 irq_set_chip_and_handler(irq, NULL, NULL);
93 irq_set_chip_data(irq, NULL);
94}
95
96static const struct irq_domain_ops ioc3_irq_domain_ops = {
97 .map = ioc3_irq_domain_map,
98 .unmap = ioc3_irq_domain_unmap,
99};
100
101static void ioc3_irq_handler(struct irq_desc *desc)
102{
103 struct irq_domain *domain = irq_desc_get_handler_data(desc);
104 struct ioc3_priv_data *ipd = domain->host_data;
105 struct ioc3 __iomem *regs = ipd->regs;
106 u32 pending, mask;
107 unsigned int irq;
108
109 pending = readl(®s->sio_ir);
110 mask = readl(®s->sio_ies);
111 pending &= mask; /* Mask off not enabled interrupts */
112
113 if (pending) {
114 irq = irq_find_mapping(domain, __ffs(pending));
115 if (irq)
116 generic_handle_irq(irq);
117 } else {
118 spurious_interrupt();
119 }
120}
121
122/*
123 * System boards/BaseIOs use more interrupt pins of the bridge ASIC
124 * to which the IOC3 is connected. Since the IOC3 MFD driver
125 * knows wiring of these extra pins, we use the map_irq function
126 * to get interrupts activated
127 */
128static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
129{
130 struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);
131
132 return hbrg->map_irq(pdev, slot, pin);
133}
134
135static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
136{
137 struct irq_domain *domain;
138 struct fwnode_handle *fn;
139
140 fn = irq_domain_alloc_named_fwnode("IOC3");
141 if (!fn)
142 goto err;
143
144 domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
145 if (!domain) {
146 irq_domain_free_fwnode(fn);
147 goto err;
148 }
149
150 ipd->domain = domain;
151
152 irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
153 ipd->domain_irq = irq;
154 return 0;
155
156err:
157 dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
158 return -ENOMEM;
159}
160
161static struct resource ioc3_uarta_resources[] = {
162 DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
163 sizeof_field(struct ioc3, sregs.uarta)),
164 DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
165};
166
167static struct resource ioc3_uartb_resources[] = {
168 DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
169 sizeof_field(struct ioc3, sregs.uartb)),
170 DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
171};
172
173static struct mfd_cell ioc3_serial_cells[] = {
174 {
175 .name = "ioc3-serial8250",
176 .resources = ioc3_uarta_resources,
177 .num_resources = ARRAY_SIZE(ioc3_uarta_resources),
178 },
179 {
180 .name = "ioc3-serial8250",
181 .resources = ioc3_uartb_resources,
182 .num_resources = ARRAY_SIZE(ioc3_uartb_resources),
183 }
184};
185
186static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
187{
188 int ret;
189
190 /* Set gpio pins for RS232/RS422 mode selection */
191 writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
192 &ipd->regs->gpcr_s);
193 /* Select RS232 mode for uart a */
194 writel(0, &ipd->regs->gppr[6]);
195 /* Select RS232 mode for uart b */
196 writel(0, &ipd->regs->gppr[7]);
197
198 /* Switch both ports to 16650 mode */
199 writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
200 &ipd->regs->port_a.sscr);
201 writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
202 &ipd->regs->port_b.sscr);
203 udelay(1000); /* Wait until mode switch is done */
204
205 ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
206 ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
207 &ipd->pdev->resource[0], 0, ipd->domain);
208 if (ret) {
209 dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
210 return ret;
211 }
212
213 return 0;
214}
215
216static struct resource ioc3_kbd_resources[] = {
217 DEFINE_RES_MEM(offsetof(struct ioc3, serio),
218 sizeof_field(struct ioc3, serio)),
219 DEFINE_RES_IRQ(IOC3_IRQ_KBD)
220};
221
222static struct mfd_cell ioc3_kbd_cells[] = {
223 {
224 .name = "ioc3-kbd",
225 .resources = ioc3_kbd_resources,
226 .num_resources = ARRAY_SIZE(ioc3_kbd_resources),
227 }
228};
229
230static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
231{
232 int ret;
233
234 ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
235 ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
236 &ipd->pdev->resource[0], 0, ipd->domain);
237 if (ret) {
238 dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
239 return ret;
240 }
241
242 return 0;
243}
244
245static struct resource ioc3_eth_resources[] = {
246 DEFINE_RES_MEM(offsetof(struct ioc3, eth),
247 sizeof_field(struct ioc3, eth)),
248 DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
249 sizeof_field(struct ioc3, ssram)),
250 DEFINE_RES_IRQ(0)
251};
252
253static struct resource ioc3_w1_resources[] = {
254 DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
255 sizeof_field(struct ioc3, mcr)),
256};
257static struct sgi_w1_platform_data ioc3_w1_platform_data;
258
259static struct mfd_cell ioc3_eth_cells[] = {
260 {
261 .name = "ioc3-eth",
262 .resources = ioc3_eth_resources,
263 .num_resources = ARRAY_SIZE(ioc3_eth_resources),
264 },
265 {
266 .name = "sgi_w1",
267 .resources = ioc3_w1_resources,
268 .num_resources = ARRAY_SIZE(ioc3_w1_resources),
269 .platform_data = &ioc3_w1_platform_data,
270 .pdata_size = sizeof(ioc3_w1_platform_data),
271 }
272};
273
274static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
275{
276 int ret;
277
278 /* Enable One-Wire bus */
279 writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
280
281 /* Generate unique identifier */
282 snprintf(ioc3_w1_platform_data.dev_id,
283 sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
284 ipd->pdev->resource->start);
285
286 ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
287 ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
288 &ipd->pdev->resource[0], ipd->pdev->irq, NULL);
289 if (ret) {
290 dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
291 return ret;
292 }
293
294 return 0;
295}
296
297static struct resource ioc3_m48t35_resources[] = {
298 DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
299};
300
301static struct mfd_cell ioc3_m48t35_cells[] = {
302 {
303 .name = "rtc-m48t35",
304 .resources = ioc3_m48t35_resources,
305 .num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
306 }
307};
308
309static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
310{
311 int ret;
312
313 ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
314 ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
315 &ipd->pdev->resource[0], 0, ipd->domain);
316 if (ret)
317 dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");
318
319 return ret;
320}
321
322static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
323 .bcd_mode = false,
324 .no_irq = false,
325 .uie_unsupported = true,
326 .access_type = ds1685_reg_indirect,
327};
328
329static struct resource ioc3_rtc_ds1685_resources[] = {
330 DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
331 DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
332 DEFINE_RES_IRQ(0)
333};
334
335static struct mfd_cell ioc3_ds1685_cells[] = {
336 {
337 .name = "rtc-ds1685",
338 .resources = ioc3_rtc_ds1685_resources,
339 .num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
340 .platform_data = &ip30_rtc_platform_data,
341 .pdata_size = sizeof(ip30_rtc_platform_data),
342 .id = PLATFORM_DEVID_NONE,
343 }
344};
345
346static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
347{
348 int ret, irq;
349
350 irq = ioc3_map_irq(ipd->pdev, 6, 0);
351
352 ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
353 ARRAY_SIZE(ioc3_ds1685_cells),
354 &ipd->pdev->resource[0], irq, NULL);
355 if (ret)
356 dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");
357
358 return ret;
359};
360
361
362static struct resource ioc3_leds_resources[] = {
363 DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
364 sizeof_field(struct ioc3, gppr[0])),
365 DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
366 sizeof_field(struct ioc3, gppr[1])),
367};
368
369static struct mfd_cell ioc3_led_cells[] = {
370 {
371 .name = "ip30-leds",
372 .resources = ioc3_leds_resources,
373 .num_resources = ARRAY_SIZE(ioc3_leds_resources),
374 .id = PLATFORM_DEVID_NONE,
375 }
376};
377
378static int ioc3_led_setup(struct ioc3_priv_data *ipd)
379{
380 int ret;
381
382 ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
383 ARRAY_SIZE(ioc3_led_cells),
384 &ipd->pdev->resource[0], 0, ipd->domain);
385 if (ret)
386 dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");
387
388 return ret;
389}
390
391static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
392{
393 int ret, io_irq;
394
395 io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
396 PCI_INTERRUPT_INTB);
397 ret = ioc3_irq_domain_setup(ipd, io_irq);
398 if (ret)
399 return ret;
400
401 ret = ioc3_eth_setup(ipd);
402 if (ret)
403 return ret;
404
405 ret = ioc3_serial_setup(ipd);
406 if (ret)
407 return ret;
408
409 return ioc3_m48t35_setup(ipd);
410}
411
412static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
413{
414 int ret, io_irq;
415
416 io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
417 PCI_INTERRUPT_INTB);
418 ret = ioc3_irq_domain_setup(ipd, io_irq);
419 if (ret)
420 return ret;
421
422 ret = ioc3_eth_setup(ipd);
423 if (ret)
424 return ret;
425
426 ret = ioc3_serial_setup(ipd);
427 if (ret)
428 return ret;
429
430 ret = ioc3_m48t35_setup(ipd);
431 if (ret)
432 return ret;
433
434 return ioc3_kbd_setup(ipd);
435}
436
437static int ip27_mio_setup(struct ioc3_priv_data *ipd)
438{
439 int ret;
440
441 ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
442 if (ret)
443 return ret;
444
445 ret = ioc3_serial_setup(ipd);
446 if (ret)
447 return ret;
448
449 return ioc3_kbd_setup(ipd);
450}
451
452static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
453{
454 int ret, io_irq;
455
456 io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
457 PCI_INTERRUPT_INTB);
458 ret = ioc3_irq_domain_setup(ipd, io_irq);
459 if (ret)
460 return ret;
461
462 ret = ioc3_eth_setup(ipd);
463 if (ret)
464 return ret;
465
466 ret = ioc3_serial_setup(ipd);
467 if (ret)
468 return ret;
469
470 ret = ioc3_kbd_setup(ipd);
471 if (ret)
472 return ret;
473
474 ret = ioc3_ds1685_setup(ipd);
475 if (ret)
476 return ret;
477
478 return ioc3_led_setup(ipd);
479}
480
481static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
482{
483 int ret, io_irq;
484
485 io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
486 PCI_INTERRUPT_INTB);
487 ret = ioc3_irq_domain_setup(ipd, io_irq);
488 if (ret)
489 return ret;
490
491 ret = ioc3_eth_setup(ipd);
492 if (ret)
493 return ret;
494
495 return ioc3_serial_setup(ipd);
496}
497
498static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
499{
500 return ioc3_eth_setup(ipd);
501}
502
503static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
504{
505 int ret, io_irq;
506
507 io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
508 PCI_INTERRUPT_INTB);
509 ret = ioc3_irq_domain_setup(ipd, io_irq);
510 if (ret)
511 return ret;
512
513 ret = ioc3_eth_setup(ipd);
514 if (ret)
515 return ret;
516
517 return ioc3_kbd_setup(ipd);
518}
519
520/* Helper macro for filling ioc3_info array */
521#define IOC3_SID(_name, _sid, _setup) \
522 { \
523 .name = _name, \
524 .sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16), \
525 .setup = _setup, \
526 }
527
528static struct {
529 const char *name;
530 u32 sid;
531 int (*setup)(struct ioc3_priv_data *ipd);
532} ioc3_infos[] = {
533 IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
534 IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
535 IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
536 IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
537 IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
538 IOC3_SID("MENET", MENET, &ioc3_menet_setup),
539 IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
540};
541#undef IOC3_SID
542
543static int ioc3_setup(struct ioc3_priv_data *ipd)
544{
545 u32 sid;
546 int i;
547
548 /* Clear IRQs */
549 writel(~0, &ipd->regs->sio_iec);
550 writel(~0, &ipd->regs->sio_ir);
551 writel(0, &ipd->regs->eth.eier);
552 writel(~0, &ipd->regs->eth.eisr);
553
554 /* Read subsystem vendor id and subsystem id */
555 pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
556
557 for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
558 if (sid == ioc3_infos[i].sid) {
559 pr_info("ioc3: %s\n", ioc3_infos[i].name);
560 return ioc3_infos[i].setup(ipd);
561 }
562
563 /* Treat everything not identified by PCI subid as CAD DUO */
564 pr_info("ioc3: CAD DUO\n");
565 return ioc3_cad_duo_setup(ipd);
566}
567
568static int ioc3_mfd_probe(struct pci_dev *pdev,
569 const struct pci_device_id *pci_id)
570{
571 struct ioc3_priv_data *ipd;
572 struct ioc3 __iomem *regs;
573 int ret;
574
575 ret = pci_enable_device(pdev);
576 if (ret)
577 return ret;
578
579 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
580 pci_set_master(pdev);
581
582 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
583 if (ret) {
584 pr_err("%s: No usable DMA configuration, aborting.\n",
585 pci_name(pdev));
586 goto out_disable_device;
587 }
588
589 /* Set up per-IOC3 data */
590 ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
591 GFP_KERNEL);
592 if (!ipd) {
593 ret = -ENOMEM;
594 goto out_disable_device;
595 }
596 ipd->pdev = pdev;
597
598 /*
599 * Map all IOC3 registers. These are shared between subdevices
600 * so the main IOC3 module manages them.
601 */
602 regs = pci_ioremap_bar(pdev, 0);
603 if (!regs) {
604 dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
605 pci_name(pdev));
606 ret = -ENOMEM;
607 goto out_disable_device;
608 }
609 ipd->regs = regs;
610
611 /* Track PCI-device specific data */
612 pci_set_drvdata(pdev, ipd);
613
614 ret = ioc3_setup(ipd);
615 if (ret) {
616 /* Remove all already added MFD devices */
617 mfd_remove_devices(&ipd->pdev->dev);
618 if (ipd->domain) {
619 struct fwnode_handle *fn = ipd->domain->fwnode;
620
621 irq_domain_remove(ipd->domain);
622 irq_domain_free_fwnode(fn);
623 free_irq(ipd->domain_irq, (void *)ipd);
624 }
625 pci_iounmap(pdev, regs);
626 goto out_disable_device;
627 }
628
629 return 0;
630
631out_disable_device:
632 pci_disable_device(pdev);
633 return ret;
634}
635
636static void ioc3_mfd_remove(struct pci_dev *pdev)
637{
638 struct ioc3_priv_data *ipd;
639
640 ipd = pci_get_drvdata(pdev);
641
642 /* Clear and disable all IRQs */
643 writel(~0, &ipd->regs->sio_iec);
644 writel(~0, &ipd->regs->sio_ir);
645
646 /* Release resources */
647 mfd_remove_devices(&ipd->pdev->dev);
648 if (ipd->domain) {
649 struct fwnode_handle *fn = ipd->domain->fwnode;
650
651 irq_domain_remove(ipd->domain);
652 irq_domain_free_fwnode(fn);
653 free_irq(ipd->domain_irq, (void *)ipd);
654 }
655 pci_iounmap(pdev, ipd->regs);
656 pci_disable_device(pdev);
657}
658
659static struct pci_device_id ioc3_mfd_id_table[] = {
660 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
661 { 0, },
662};
663MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);
664
665static struct pci_driver ioc3_mfd_driver = {
666 .name = "IOC3",
667 .id_table = ioc3_mfd_id_table,
668 .probe = ioc3_mfd_probe,
669 .remove = ioc3_mfd_remove,
670};
671
672module_pci_driver(ioc3_mfd_driver);
673
674MODULE_AUTHOR("Thomas Bogendoerfer <tbogendoerfer@suse.de>");
675MODULE_DESCRIPTION("SGI IOC3 MFD driver");
676MODULE_LICENSE("GPL v2");