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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/interrupt.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of_device.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/pinctrl/pinmux.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
18#include <linux/reset.h>
19#include <linux/workqueue.h>
20
21#include <drm/drm_dp_helper.h>
22#include <drm/drm_panel.h>
23
24#include "dp.h"
25#include "dpaux.h"
26#include "drm.h"
27#include "trace.h"
28
29static DEFINE_MUTEX(dpaux_lock);
30static LIST_HEAD(dpaux_list);
31
32struct tegra_dpaux_soc {
33 unsigned int cmh;
34 unsigned int drvz;
35 unsigned int drvi;
36};
37
38struct tegra_dpaux {
39 struct drm_dp_aux aux;
40 struct device *dev;
41
42 const struct tegra_dpaux_soc *soc;
43
44 void __iomem *regs;
45 int irq;
46
47 struct tegra_output *output;
48
49 struct reset_control *rst;
50 struct clk *clk_parent;
51 struct clk *clk;
52
53 struct regulator *vdd;
54
55 struct completion complete;
56 struct work_struct work;
57 struct list_head list;
58
59#ifdef CONFIG_GENERIC_PINCONF
60 struct pinctrl_dev *pinctrl;
61 struct pinctrl_desc desc;
62#endif
63};
64
65static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
66{
67 return container_of(aux, struct tegra_dpaux, aux);
68}
69
70static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
71{
72 return container_of(work, struct tegra_dpaux, work);
73}
74
75static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
76 unsigned int offset)
77{
78 u32 value = readl(dpaux->regs + (offset << 2));
79
80 trace_dpaux_readl(dpaux->dev, offset, value);
81
82 return value;
83}
84
85static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
86 u32 value, unsigned int offset)
87{
88 trace_dpaux_writel(dpaux->dev, offset, value);
89 writel(value, dpaux->regs + (offset << 2));
90}
91
92static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
93 size_t size)
94{
95 size_t i, j;
96
97 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
98 size_t num = min_t(size_t, size - i * 4, 4);
99 u32 value = 0;
100
101 for (j = 0; j < num; j++)
102 value |= buffer[i * 4 + j] << (j * 8);
103
104 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
105 }
106}
107
108static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
109 size_t size)
110{
111 size_t i, j;
112
113 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
114 size_t num = min_t(size_t, size - i * 4, 4);
115 u32 value;
116
117 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
118
119 for (j = 0; j < num; j++)
120 buffer[i * 4 + j] = value >> (j * 8);
121 }
122}
123
124static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
125 struct drm_dp_aux_msg *msg)
126{
127 unsigned long timeout = msecs_to_jiffies(250);
128 struct tegra_dpaux *dpaux = to_dpaux(aux);
129 unsigned long status;
130 ssize_t ret = 0;
131 u8 reply = 0;
132 u32 value;
133
134 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
135 if (msg->size > 16)
136 return -EINVAL;
137
138 /*
139 * Allow zero-sized messages only for I2C, in which case they specify
140 * address-only transactions.
141 */
142 if (msg->size < 1) {
143 switch (msg->request & ~DP_AUX_I2C_MOT) {
144 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
145 case DP_AUX_I2C_WRITE:
146 case DP_AUX_I2C_READ:
147 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
148 break;
149
150 default:
151 return -EINVAL;
152 }
153 } else {
154 /* For non-zero-sized messages, set the CMDLEN field. */
155 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
156 }
157
158 switch (msg->request & ~DP_AUX_I2C_MOT) {
159 case DP_AUX_I2C_WRITE:
160 if (msg->request & DP_AUX_I2C_MOT)
161 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
162 else
163 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
164
165 break;
166
167 case DP_AUX_I2C_READ:
168 if (msg->request & DP_AUX_I2C_MOT)
169 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
170 else
171 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
172
173 break;
174
175 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
176 if (msg->request & DP_AUX_I2C_MOT)
177 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
178 else
179 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
180
181 break;
182
183 case DP_AUX_NATIVE_WRITE:
184 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
185 break;
186
187 case DP_AUX_NATIVE_READ:
188 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
189 break;
190
191 default:
192 return -EINVAL;
193 }
194
195 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
197
198 if ((msg->request & DP_AUX_I2C_READ) == 0) {
199 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
200 ret = msg->size;
201 }
202
203 /* start transaction */
204 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
205 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
206 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
207
208 status = wait_for_completion_timeout(&dpaux->complete, timeout);
209 if (!status)
210 return -ETIMEDOUT;
211
212 /* read status and clear errors */
213 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
214 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
215
216 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
217 return -ETIMEDOUT;
218
219 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
220 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
221 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
222 return -EIO;
223
224 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
225 case 0x00:
226 reply = DP_AUX_NATIVE_REPLY_ACK;
227 break;
228
229 case 0x01:
230 reply = DP_AUX_NATIVE_REPLY_NACK;
231 break;
232
233 case 0x02:
234 reply = DP_AUX_NATIVE_REPLY_DEFER;
235 break;
236
237 case 0x04:
238 reply = DP_AUX_I2C_REPLY_NACK;
239 break;
240
241 case 0x08:
242 reply = DP_AUX_I2C_REPLY_DEFER;
243 break;
244 }
245
246 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
247 if (msg->request & DP_AUX_I2C_READ) {
248 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
249
250 /*
251 * There might be a smarter way to do this, but since
252 * the DP helpers will already retry transactions for
253 * an -EBUSY return value, simply reuse that instead.
254 */
255 if (count != msg->size) {
256 ret = -EBUSY;
257 goto out;
258 }
259
260 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
261 ret = count;
262 }
263 }
264
265 msg->reply = reply;
266
267out:
268 return ret;
269}
270
271static void tegra_dpaux_hotplug(struct work_struct *work)
272{
273 struct tegra_dpaux *dpaux = work_to_dpaux(work);
274
275 if (dpaux->output)
276 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
277}
278
279static irqreturn_t tegra_dpaux_irq(int irq, void *data)
280{
281 struct tegra_dpaux *dpaux = data;
282 irqreturn_t ret = IRQ_HANDLED;
283 u32 value;
284
285 /* clear interrupts */
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
288
289 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
290 schedule_work(&dpaux->work);
291
292 if (value & DPAUX_INTR_IRQ_EVENT) {
293 /* TODO: handle this */
294 }
295
296 if (value & DPAUX_INTR_AUX_DONE)
297 complete(&dpaux->complete);
298
299 return ret;
300}
301
302enum tegra_dpaux_functions {
303 DPAUX_PADCTL_FUNC_AUX,
304 DPAUX_PADCTL_FUNC_I2C,
305 DPAUX_PADCTL_FUNC_OFF,
306};
307
308static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
309{
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
311
312 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
313
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
315}
316
317static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
318{
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
320
321 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
322
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
324}
325
326static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
327{
328 u32 value;
329
330 switch (function) {
331 case DPAUX_PADCTL_FUNC_AUX:
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
335 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
336 DPAUX_HYBRID_PADCTL_MODE_AUX;
337 break;
338
339 case DPAUX_PADCTL_FUNC_I2C:
340 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
341 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
345 DPAUX_HYBRID_PADCTL_MODE_I2C;
346 break;
347
348 case DPAUX_PADCTL_FUNC_OFF:
349 tegra_dpaux_pad_power_down(dpaux);
350 return 0;
351
352 default:
353 return -ENOTSUPP;
354 }
355
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
357 tegra_dpaux_pad_power_up(dpaux);
358
359 return 0;
360}
361
362#ifdef CONFIG_GENERIC_PINCONF
363static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
364 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
365 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
366};
367
368static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
369
370static const char * const tegra_dpaux_groups[] = {
371 "dpaux-io",
372};
373
374static const char * const tegra_dpaux_functions[] = {
375 "aux",
376 "i2c",
377 "off",
378};
379
380static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
381{
382 return ARRAY_SIZE(tegra_dpaux_groups);
383}
384
385static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
386 unsigned int group)
387{
388 return tegra_dpaux_groups[group];
389}
390
391static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
392 unsigned group, const unsigned **pins,
393 unsigned *num_pins)
394{
395 *pins = tegra_dpaux_pin_numbers;
396 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
397
398 return 0;
399}
400
401static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
402 .get_groups_count = tegra_dpaux_get_groups_count,
403 .get_group_name = tegra_dpaux_get_group_name,
404 .get_group_pins = tegra_dpaux_get_group_pins,
405 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
406 .dt_free_map = pinconf_generic_dt_free_map,
407};
408
409static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
410{
411 return ARRAY_SIZE(tegra_dpaux_functions);
412}
413
414static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
415 unsigned int function)
416{
417 return tegra_dpaux_functions[function];
418}
419
420static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
421 unsigned int function,
422 const char * const **groups,
423 unsigned * const num_groups)
424{
425 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
426 *groups = tegra_dpaux_groups;
427
428 return 0;
429}
430
431static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
432 unsigned int function, unsigned int group)
433{
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
435
436 return tegra_dpaux_pad_config(dpaux, function);
437}
438
439static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
440 .get_functions_count = tegra_dpaux_get_functions_count,
441 .get_function_name = tegra_dpaux_get_function_name,
442 .get_function_groups = tegra_dpaux_get_function_groups,
443 .set_mux = tegra_dpaux_set_mux,
444};
445#endif
446
447static int tegra_dpaux_probe(struct platform_device *pdev)
448{
449 struct tegra_dpaux *dpaux;
450 struct resource *regs;
451 u32 value;
452 int err;
453
454 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
455 if (!dpaux)
456 return -ENOMEM;
457
458 dpaux->soc = of_device_get_match_data(&pdev->dev);
459 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
460 init_completion(&dpaux->complete);
461 INIT_LIST_HEAD(&dpaux->list);
462 dpaux->dev = &pdev->dev;
463
464 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
466 if (IS_ERR(dpaux->regs))
467 return PTR_ERR(dpaux->regs);
468
469 dpaux->irq = platform_get_irq(pdev, 0);
470 if (dpaux->irq < 0) {
471 dev_err(&pdev->dev, "failed to get IRQ\n");
472 return -ENXIO;
473 }
474
475 if (!pdev->dev.pm_domain) {
476 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
477 if (IS_ERR(dpaux->rst)) {
478 dev_err(&pdev->dev,
479 "failed to get reset control: %ld\n",
480 PTR_ERR(dpaux->rst));
481 return PTR_ERR(dpaux->rst);
482 }
483 }
484
485 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
486 if (IS_ERR(dpaux->clk)) {
487 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
488 PTR_ERR(dpaux->clk));
489 return PTR_ERR(dpaux->clk);
490 }
491
492 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
493 if (IS_ERR(dpaux->clk_parent)) {
494 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
495 PTR_ERR(dpaux->clk_parent));
496 return PTR_ERR(dpaux->clk_parent);
497 }
498
499 err = clk_set_rate(dpaux->clk_parent, 270000000);
500 if (err < 0) {
501 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
502 err);
503 return err;
504 }
505
506 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
507 if (IS_ERR(dpaux->vdd)) {
508 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
509 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
510 dev_err(&pdev->dev,
511 "failed to get VDD supply: %ld\n",
512 PTR_ERR(dpaux->vdd));
513
514 return PTR_ERR(dpaux->vdd);
515 }
516
517 dpaux->vdd = NULL;
518 }
519
520 platform_set_drvdata(pdev, dpaux);
521 pm_runtime_enable(&pdev->dev);
522 pm_runtime_get_sync(&pdev->dev);
523
524 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
525 dev_name(dpaux->dev), dpaux);
526 if (err < 0) {
527 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
528 dpaux->irq, err);
529 return err;
530 }
531
532 disable_irq(dpaux->irq);
533
534 dpaux->aux.transfer = tegra_dpaux_transfer;
535 dpaux->aux.dev = &pdev->dev;
536
537 err = drm_dp_aux_register(&dpaux->aux);
538 if (err < 0)
539 return err;
540
541 /*
542 * Assume that by default the DPAUX/I2C pads will be used for HDMI,
543 * so power them up and configure them in I2C mode.
544 *
545 * The DPAUX code paths reconfigure the pads in AUX mode, but there
546 * is no possibility to perform the I2C mode configuration in the
547 * HDMI path.
548 */
549 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
550 if (err < 0)
551 return err;
552
553#ifdef CONFIG_GENERIC_PINCONF
554 dpaux->desc.name = dev_name(&pdev->dev);
555 dpaux->desc.pins = tegra_dpaux_pins;
556 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
557 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
558 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
559 dpaux->desc.owner = THIS_MODULE;
560
561 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
562 if (IS_ERR(dpaux->pinctrl)) {
563 dev_err(&pdev->dev, "failed to register pincontrol\n");
564 return PTR_ERR(dpaux->pinctrl);
565 }
566#endif
567 /* enable and clear all interrupts */
568 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
569 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
570 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
571 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
572
573 mutex_lock(&dpaux_lock);
574 list_add_tail(&dpaux->list, &dpaux_list);
575 mutex_unlock(&dpaux_lock);
576
577 return 0;
578}
579
580static int tegra_dpaux_remove(struct platform_device *pdev)
581{
582 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
583
584 cancel_work_sync(&dpaux->work);
585
586 /* make sure pads are powered down when not in use */
587 tegra_dpaux_pad_power_down(dpaux);
588
589 pm_runtime_put_sync(&pdev->dev);
590 pm_runtime_disable(&pdev->dev);
591
592 drm_dp_aux_unregister(&dpaux->aux);
593
594 mutex_lock(&dpaux_lock);
595 list_del(&dpaux->list);
596 mutex_unlock(&dpaux_lock);
597
598 return 0;
599}
600
601#ifdef CONFIG_PM
602static int tegra_dpaux_suspend(struct device *dev)
603{
604 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
605 int err = 0;
606
607 if (dpaux->rst) {
608 err = reset_control_assert(dpaux->rst);
609 if (err < 0) {
610 dev_err(dev, "failed to assert reset: %d\n", err);
611 return err;
612 }
613 }
614
615 usleep_range(1000, 2000);
616
617 clk_disable_unprepare(dpaux->clk_parent);
618 clk_disable_unprepare(dpaux->clk);
619
620 return err;
621}
622
623static int tegra_dpaux_resume(struct device *dev)
624{
625 struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
626 int err;
627
628 err = clk_prepare_enable(dpaux->clk);
629 if (err < 0) {
630 dev_err(dev, "failed to enable clock: %d\n", err);
631 return err;
632 }
633
634 err = clk_prepare_enable(dpaux->clk_parent);
635 if (err < 0) {
636 dev_err(dev, "failed to enable parent clock: %d\n", err);
637 goto disable_clk;
638 }
639
640 usleep_range(1000, 2000);
641
642 if (dpaux->rst) {
643 err = reset_control_deassert(dpaux->rst);
644 if (err < 0) {
645 dev_err(dev, "failed to deassert reset: %d\n", err);
646 goto disable_parent;
647 }
648
649 usleep_range(1000, 2000);
650 }
651
652 return 0;
653
654disable_parent:
655 clk_disable_unprepare(dpaux->clk_parent);
656disable_clk:
657 clk_disable_unprepare(dpaux->clk);
658 return err;
659}
660#endif
661
662static const struct dev_pm_ops tegra_dpaux_pm_ops = {
663 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
664};
665
666static const struct tegra_dpaux_soc tegra124_dpaux_soc = {
667 .cmh = 0x02,
668 .drvz = 0x04,
669 .drvi = 0x18,
670};
671
672static const struct tegra_dpaux_soc tegra210_dpaux_soc = {
673 .cmh = 0x02,
674 .drvz = 0x04,
675 .drvi = 0x30,
676};
677
678static const struct tegra_dpaux_soc tegra194_dpaux_soc = {
679 .cmh = 0x02,
680 .drvz = 0x04,
681 .drvi = 0x2c,
682};
683
684static const struct of_device_id tegra_dpaux_of_match[] = {
685 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
686 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
687 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
688 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
689 { },
690};
691MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
692
693struct platform_driver tegra_dpaux_driver = {
694 .driver = {
695 .name = "tegra-dpaux",
696 .of_match_table = tegra_dpaux_of_match,
697 .pm = &tegra_dpaux_pm_ops,
698 },
699 .probe = tegra_dpaux_probe,
700 .remove = tegra_dpaux_remove,
701};
702
703struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
704{
705 struct tegra_dpaux *dpaux;
706
707 mutex_lock(&dpaux_lock);
708
709 list_for_each_entry(dpaux, &dpaux_list, list)
710 if (np == dpaux->dev->of_node) {
711 mutex_unlock(&dpaux_lock);
712 return &dpaux->aux;
713 }
714
715 mutex_unlock(&dpaux_lock);
716
717 return NULL;
718}
719
720int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
721{
722 struct tegra_dpaux *dpaux = to_dpaux(aux);
723 unsigned long timeout;
724 int err;
725
726 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
727 dpaux->output = output;
728
729 if (output->panel) {
730 enum drm_connector_status status;
731
732 if (dpaux->vdd) {
733 err = regulator_enable(dpaux->vdd);
734 if (err < 0)
735 return err;
736 }
737
738 timeout = jiffies + msecs_to_jiffies(250);
739
740 while (time_before(jiffies, timeout)) {
741 status = drm_dp_aux_detect(aux);
742
743 if (status == connector_status_connected)
744 break;
745
746 usleep_range(1000, 2000);
747 }
748
749 if (status != connector_status_connected)
750 return -ETIMEDOUT;
751 }
752
753 enable_irq(dpaux->irq);
754 return 0;
755}
756
757int drm_dp_aux_detach(struct drm_dp_aux *aux)
758{
759 struct tegra_dpaux *dpaux = to_dpaux(aux);
760 unsigned long timeout;
761 int err;
762
763 disable_irq(dpaux->irq);
764
765 if (dpaux->output->panel) {
766 enum drm_connector_status status;
767
768 if (dpaux->vdd) {
769 err = regulator_disable(dpaux->vdd);
770 if (err < 0)
771 return err;
772 }
773
774 timeout = jiffies + msecs_to_jiffies(250);
775
776 while (time_before(jiffies, timeout)) {
777 status = drm_dp_aux_detect(aux);
778
779 if (status == connector_status_disconnected)
780 break;
781
782 usleep_range(1000, 2000);
783 }
784
785 if (status != connector_status_disconnected)
786 return -ETIMEDOUT;
787
788 dpaux->output = NULL;
789 }
790
791 return 0;
792}
793
794enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
795{
796 struct tegra_dpaux *dpaux = to_dpaux(aux);
797 u32 value;
798
799 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
800
801 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
802 return connector_status_connected;
803
804 return connector_status_disconnected;
805}
806
807int drm_dp_aux_enable(struct drm_dp_aux *aux)
808{
809 struct tegra_dpaux *dpaux = to_dpaux(aux);
810
811 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
812}
813
814int drm_dp_aux_disable(struct drm_dp_aux *aux)
815{
816 struct tegra_dpaux *dpaux = to_dpaux(aux);
817
818 tegra_dpaux_pad_power_down(dpaux);
819
820 return 0;
821}
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_gpio.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/regulator/consumer.h>
18
19#include <drm/drm_dp_helper.h>
20#include <drm/drm_panel.h>
21
22#include "dpaux.h"
23#include "drm.h"
24
25static DEFINE_MUTEX(dpaux_lock);
26static LIST_HEAD(dpaux_list);
27
28struct tegra_dpaux {
29 struct drm_dp_aux aux;
30 struct device *dev;
31
32 void __iomem *regs;
33 int irq;
34
35 struct tegra_output *output;
36
37 struct reset_control *rst;
38 struct clk *clk_parent;
39 struct clk *clk;
40
41 struct regulator *vdd;
42
43 struct completion complete;
44 struct list_head list;
45};
46
47static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
48{
49 return container_of(aux, struct tegra_dpaux, aux);
50}
51
52static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
53 unsigned long offset)
54{
55 return readl(dpaux->regs + (offset << 2));
56}
57
58static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
59 unsigned long value,
60 unsigned long offset)
61{
62 writel(value, dpaux->regs + (offset << 2));
63}
64
65static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
66 size_t size)
67{
68 unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
69 size_t i, j;
70
71 for (i = 0; i < size; i += 4) {
72 size_t num = min_t(size_t, size - i, 4);
73 unsigned long value = 0;
74
75 for (j = 0; j < num; j++)
76 value |= buffer[i + j] << (j * 8);
77
78 tegra_dpaux_writel(dpaux, value, offset++);
79 }
80}
81
82static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
83 size_t size)
84{
85 unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
86 size_t i, j;
87
88 for (i = 0; i < size; i += 4) {
89 size_t num = min_t(size_t, size - i, 4);
90 unsigned long value;
91
92 value = tegra_dpaux_readl(dpaux, offset++);
93
94 for (j = 0; j < num; j++)
95 buffer[i + j] = value >> (j * 8);
96 }
97}
98
99static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
100 struct drm_dp_aux_msg *msg)
101{
102 unsigned long timeout = msecs_to_jiffies(250);
103 struct tegra_dpaux *dpaux = to_dpaux(aux);
104 unsigned long status;
105 ssize_t ret = 0;
106 u32 value;
107
108 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
109 if (msg->size > 16)
110 return -EINVAL;
111
112 /*
113 * Allow zero-sized messages only for I2C, in which case they specify
114 * address-only transactions.
115 */
116 if (msg->size < 1) {
117 switch (msg->request & ~DP_AUX_I2C_MOT) {
118 case DP_AUX_I2C_WRITE:
119 case DP_AUX_I2C_READ:
120 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
121 break;
122
123 default:
124 return -EINVAL;
125 }
126 } else {
127 /* For non-zero-sized messages, set the CMDLEN field. */
128 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
129 }
130
131 switch (msg->request & ~DP_AUX_I2C_MOT) {
132 case DP_AUX_I2C_WRITE:
133 if (msg->request & DP_AUX_I2C_MOT)
134 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
135 else
136 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
137
138 break;
139
140 case DP_AUX_I2C_READ:
141 if (msg->request & DP_AUX_I2C_MOT)
142 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
143 else
144 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
145
146 break;
147
148 case DP_AUX_I2C_STATUS:
149 if (msg->request & DP_AUX_I2C_MOT)
150 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
151 else
152 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
153
154 break;
155
156 case DP_AUX_NATIVE_WRITE:
157 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
158 break;
159
160 case DP_AUX_NATIVE_READ:
161 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
162 break;
163
164 default:
165 return -EINVAL;
166 }
167
168 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
169 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
170
171 if ((msg->request & DP_AUX_I2C_READ) == 0) {
172 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
173 ret = msg->size;
174 }
175
176 /* start transaction */
177 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
178 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
179 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
180
181 status = wait_for_completion_timeout(&dpaux->complete, timeout);
182 if (!status)
183 return -ETIMEDOUT;
184
185 /* read status and clear errors */
186 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
187 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
188
189 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
190 return -ETIMEDOUT;
191
192 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
193 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
194 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
195 return -EIO;
196
197 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
198 case 0x00:
199 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
200 break;
201
202 case 0x01:
203 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
204 break;
205
206 case 0x02:
207 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
208 break;
209
210 case 0x04:
211 msg->reply = DP_AUX_I2C_REPLY_NACK;
212 break;
213
214 case 0x08:
215 msg->reply = DP_AUX_I2C_REPLY_DEFER;
216 break;
217 }
218
219 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
220 if (msg->request & DP_AUX_I2C_READ) {
221 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
222
223 if (WARN_ON(count != msg->size))
224 count = min_t(size_t, count, msg->size);
225
226 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
227 ret = count;
228 }
229 }
230
231 return ret;
232}
233
234static irqreturn_t tegra_dpaux_irq(int irq, void *data)
235{
236 struct tegra_dpaux *dpaux = data;
237 irqreturn_t ret = IRQ_HANDLED;
238 unsigned long value;
239
240 /* clear interrupts */
241 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
242 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
243
244 if (value & DPAUX_INTR_PLUG_EVENT) {
245 if (dpaux->output) {
246 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
247 }
248 }
249
250 if (value & DPAUX_INTR_UNPLUG_EVENT) {
251 if (dpaux->output)
252 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
253 }
254
255 if (value & DPAUX_INTR_IRQ_EVENT) {
256 /* TODO: handle this */
257 }
258
259 if (value & DPAUX_INTR_AUX_DONE)
260 complete(&dpaux->complete);
261
262 return ret;
263}
264
265static int tegra_dpaux_probe(struct platform_device *pdev)
266{
267 struct tegra_dpaux *dpaux;
268 struct resource *regs;
269 unsigned long value;
270 int err;
271
272 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
273 if (!dpaux)
274 return -ENOMEM;
275
276 init_completion(&dpaux->complete);
277 INIT_LIST_HEAD(&dpaux->list);
278 dpaux->dev = &pdev->dev;
279
280 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
281 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
282 if (IS_ERR(dpaux->regs))
283 return PTR_ERR(dpaux->regs);
284
285 dpaux->irq = platform_get_irq(pdev, 0);
286 if (dpaux->irq < 0) {
287 dev_err(&pdev->dev, "failed to get IRQ\n");
288 return -ENXIO;
289 }
290
291 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
292 if (IS_ERR(dpaux->rst))
293 return PTR_ERR(dpaux->rst);
294
295 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
296 if (IS_ERR(dpaux->clk))
297 return PTR_ERR(dpaux->clk);
298
299 err = clk_prepare_enable(dpaux->clk);
300 if (err < 0)
301 return err;
302
303 reset_control_deassert(dpaux->rst);
304
305 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
306 if (IS_ERR(dpaux->clk_parent))
307 return PTR_ERR(dpaux->clk_parent);
308
309 err = clk_prepare_enable(dpaux->clk_parent);
310 if (err < 0)
311 return err;
312
313 err = clk_set_rate(dpaux->clk_parent, 270000000);
314 if (err < 0) {
315 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
316 err);
317 return err;
318 }
319
320 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
321 if (IS_ERR(dpaux->vdd))
322 return PTR_ERR(dpaux->vdd);
323
324 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
325 dev_name(dpaux->dev), dpaux);
326 if (err < 0) {
327 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
328 dpaux->irq, err);
329 return err;
330 }
331
332 dpaux->aux.transfer = tegra_dpaux_transfer;
333 dpaux->aux.dev = &pdev->dev;
334
335 err = drm_dp_aux_register_i2c_bus(&dpaux->aux);
336 if (err < 0)
337 return err;
338
339 /* enable and clear all interrupts */
340 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
341 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
342 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
343 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
344
345 mutex_lock(&dpaux_lock);
346 list_add_tail(&dpaux->list, &dpaux_list);
347 mutex_unlock(&dpaux_lock);
348
349 platform_set_drvdata(pdev, dpaux);
350
351 return 0;
352}
353
354static int tegra_dpaux_remove(struct platform_device *pdev)
355{
356 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
357
358 drm_dp_aux_unregister_i2c_bus(&dpaux->aux);
359
360 mutex_lock(&dpaux_lock);
361 list_del(&dpaux->list);
362 mutex_unlock(&dpaux_lock);
363
364 clk_disable_unprepare(dpaux->clk_parent);
365 reset_control_assert(dpaux->rst);
366 clk_disable_unprepare(dpaux->clk);
367
368 return 0;
369}
370
371static const struct of_device_id tegra_dpaux_of_match[] = {
372 { .compatible = "nvidia,tegra124-dpaux", },
373 { },
374};
375
376struct platform_driver tegra_dpaux_driver = {
377 .driver = {
378 .name = "tegra-dpaux",
379 .of_match_table = tegra_dpaux_of_match,
380 },
381 .probe = tegra_dpaux_probe,
382 .remove = tegra_dpaux_remove,
383};
384
385struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
386{
387 struct tegra_dpaux *dpaux;
388
389 mutex_lock(&dpaux_lock);
390
391 list_for_each_entry(dpaux, &dpaux_list, list)
392 if (np == dpaux->dev->of_node) {
393 mutex_unlock(&dpaux_lock);
394 return dpaux;
395 }
396
397 mutex_unlock(&dpaux_lock);
398
399 return NULL;
400}
401
402int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
403{
404 unsigned long timeout;
405 int err;
406
407 dpaux->output = output;
408
409 err = regulator_enable(dpaux->vdd);
410 if (err < 0)
411 return err;
412
413 timeout = jiffies + msecs_to_jiffies(250);
414
415 while (time_before(jiffies, timeout)) {
416 enum drm_connector_status status;
417
418 status = tegra_dpaux_detect(dpaux);
419 if (status == connector_status_connected)
420 return 0;
421
422 usleep_range(1000, 2000);
423 }
424
425 return -ETIMEDOUT;
426}
427
428int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
429{
430 unsigned long timeout;
431 int err;
432
433 err = regulator_disable(dpaux->vdd);
434 if (err < 0)
435 return err;
436
437 timeout = jiffies + msecs_to_jiffies(250);
438
439 while (time_before(jiffies, timeout)) {
440 enum drm_connector_status status;
441
442 status = tegra_dpaux_detect(dpaux);
443 if (status == connector_status_disconnected) {
444 dpaux->output = NULL;
445 return 0;
446 }
447
448 usleep_range(1000, 2000);
449 }
450
451 return -ETIMEDOUT;
452}
453
454enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
455{
456 unsigned long value;
457
458 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
459
460 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
461 return connector_status_connected;
462
463 return connector_status_disconnected;
464}
465
466int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
467{
468 unsigned long value;
469
470 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
471 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
472 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
473 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
474 DPAUX_HYBRID_PADCTL_MODE_AUX;
475 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
476
477 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
478 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
479 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
480
481 return 0;
482}
483
484int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
485{
486 unsigned long value;
487
488 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
489 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
490 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
491
492 return 0;
493}
494
495int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
496{
497 int err;
498
499 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
500 encoding);
501 if (err < 0)
502 return err;
503
504 return 0;
505}
506
507int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
508 u8 pattern)
509{
510 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
511 u8 status[DP_LINK_STATUS_SIZE], values[4];
512 unsigned int i;
513 int err;
514
515 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
516 if (err < 0)
517 return err;
518
519 if (tp == DP_TRAINING_PATTERN_DISABLE)
520 return 0;
521
522 for (i = 0; i < link->num_lanes; i++)
523 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
524 DP_TRAIN_PRE_EMPHASIS_0 |
525 DP_TRAIN_MAX_SWING_REACHED |
526 DP_TRAIN_VOLTAGE_SWING_400;
527
528 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
529 link->num_lanes);
530 if (err < 0)
531 return err;
532
533 usleep_range(500, 1000);
534
535 err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
536 if (err < 0)
537 return err;
538
539 switch (tp) {
540 case DP_TRAINING_PATTERN_1:
541 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
542 return -EAGAIN;
543
544 break;
545
546 case DP_TRAINING_PATTERN_2:
547 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
548 return -EAGAIN;
549
550 break;
551
552 default:
553 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
554 return -EINVAL;
555 }
556
557 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
558 if (err < 0)
559 return err;
560
561 return 0;
562}