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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25#include <linux/slab.h>
26
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
34#include "amd_pcie.h"
35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
62#include "gmc_v8_0.h"
63#include "gmc_v7_0.h"
64#include "gfx_v8_0.h"
65#include "sdma_v2_4.h"
66#include "sdma_v3_0.h"
67#include "dce_v10_0.h"
68#include "dce_v11_0.h"
69#include "iceland_ih.h"
70#include "tonga_ih.h"
71#include "cz_ih.h"
72#include "uvd_v5_0.h"
73#include "uvd_v6_0.h"
74#include "vce_v3_0.h"
75#if defined(CONFIG_DRM_AMD_ACP)
76#include "amdgpu_acp.h"
77#endif
78#include "dce_virtual.h"
79#include "mxgpu_vi.h"
80#include "amdgpu_dm.h"
81
82/*
83 * Indirect registers accessor
84 */
85static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
86{
87 unsigned long flags;
88 u32 r;
89
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
91 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
93 r = RREG32_NO_KIQ(mmPCIE_DATA);
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
95 return r;
96}
97
98static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
99{
100 unsigned long flags;
101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
105 WREG32_NO_KIQ(mmPCIE_DATA, v);
106 (void)RREG32_NO_KIQ(mmPCIE_DATA);
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
108}
109
110static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 unsigned long flags;
113 u32 r;
114
115 spin_lock_irqsave(&adev->smc_idx_lock, flags);
116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
119 return r;
120}
121
122static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&adev->smc_idx_lock, flags);
127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
130}
131
132/* smu_8_0_d.h */
133#define mmMP0PUB_IND_INDEX 0x180
134#define mmMP0PUB_IND_DATA 0x181
135
136static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
137{
138 unsigned long flags;
139 u32 r;
140
141 spin_lock_irqsave(&adev->smc_idx_lock, flags);
142 WREG32(mmMP0PUB_IND_INDEX, (reg));
143 r = RREG32(mmMP0PUB_IND_DATA);
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
145 return r;
146}
147
148static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&adev->smc_idx_lock, flags);
153 WREG32(mmMP0PUB_IND_INDEX, (reg));
154 WREG32(mmMP0PUB_IND_DATA, (v));
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
156}
157
158static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
164 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
165 r = RREG32(mmUVD_CTX_DATA);
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
167 return r;
168}
169
170static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
175 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
176 WREG32(mmUVD_CTX_DATA, (v));
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
178}
179
180static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
181{
182 unsigned long flags;
183 u32 r;
184
185 spin_lock_irqsave(&adev->didt_idx_lock, flags);
186 WREG32(mmDIDT_IND_INDEX, (reg));
187 r = RREG32(mmDIDT_IND_DATA);
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
189 return r;
190}
191
192static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
193{
194 unsigned long flags;
195
196 spin_lock_irqsave(&adev->didt_idx_lock, flags);
197 WREG32(mmDIDT_IND_INDEX, (reg));
198 WREG32(mmDIDT_IND_DATA, (v));
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
200}
201
202static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
203{
204 unsigned long flags;
205 u32 r;
206
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
208 WREG32(mmGC_CAC_IND_INDEX, (reg));
209 r = RREG32(mmGC_CAC_IND_DATA);
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
211 return r;
212}
213
214static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
215{
216 unsigned long flags;
217
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
219 WREG32(mmGC_CAC_IND_INDEX, (reg));
220 WREG32(mmGC_CAC_IND_DATA, (v));
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
222}
223
224
225static const u32 tonga_mgcg_cgcg_init[] =
226{
227 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
228 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
229 mmPCIE_DATA, 0x000f0000, 0x00000000,
230 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
231 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
234};
235
236static const u32 fiji_mgcg_cgcg_init[] =
237{
238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
239 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
240 mmPCIE_DATA, 0x000f0000, 0x00000000,
241 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
242 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
243 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
245};
246
247static const u32 iceland_mgcg_cgcg_init[] =
248{
249 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
250 mmPCIE_DATA, 0x000f0000, 0x00000000,
251 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
252 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
253 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
254};
255
256static const u32 cz_mgcg_cgcg_init[] =
257{
258 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
259 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
260 mmPCIE_DATA, 0x000f0000, 0x00000000,
261 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
262 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
263};
264
265static const u32 stoney_mgcg_cgcg_init[] =
266{
267 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
268 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
269 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
270};
271
272static void vi_init_golden_registers(struct amdgpu_device *adev)
273{
274 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
275 mutex_lock(&adev->grbm_idx_mutex);
276
277 if (amdgpu_sriov_vf(adev)) {
278 xgpu_vi_init_golden_registers(adev);
279 mutex_unlock(&adev->grbm_idx_mutex);
280 return;
281 }
282
283 switch (adev->asic_type) {
284 case CHIP_TOPAZ:
285 amdgpu_device_program_register_sequence(adev,
286 iceland_mgcg_cgcg_init,
287 ARRAY_SIZE(iceland_mgcg_cgcg_init));
288 break;
289 case CHIP_FIJI:
290 amdgpu_device_program_register_sequence(adev,
291 fiji_mgcg_cgcg_init,
292 ARRAY_SIZE(fiji_mgcg_cgcg_init));
293 break;
294 case CHIP_TONGA:
295 amdgpu_device_program_register_sequence(adev,
296 tonga_mgcg_cgcg_init,
297 ARRAY_SIZE(tonga_mgcg_cgcg_init));
298 break;
299 case CHIP_CARRIZO:
300 amdgpu_device_program_register_sequence(adev,
301 cz_mgcg_cgcg_init,
302 ARRAY_SIZE(cz_mgcg_cgcg_init));
303 break;
304 case CHIP_STONEY:
305 amdgpu_device_program_register_sequence(adev,
306 stoney_mgcg_cgcg_init,
307 ARRAY_SIZE(stoney_mgcg_cgcg_init));
308 break;
309 case CHIP_POLARIS10:
310 case CHIP_POLARIS11:
311 case CHIP_POLARIS12:
312 case CHIP_VEGAM:
313 default:
314 break;
315 }
316 mutex_unlock(&adev->grbm_idx_mutex);
317}
318
319/**
320 * vi_get_xclk - get the xclk
321 *
322 * @adev: amdgpu_device pointer
323 *
324 * Returns the reference clock used by the gfx engine
325 * (VI).
326 */
327static u32 vi_get_xclk(struct amdgpu_device *adev)
328{
329 u32 reference_clock = adev->clock.spll.reference_freq;
330 u32 tmp;
331
332 if (adev->flags & AMD_IS_APU)
333 return reference_clock;
334
335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
337 return 1000;
338
339 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
341 return reference_clock / 4;
342
343 return reference_clock;
344}
345
346/**
347 * vi_srbm_select - select specific register instances
348 *
349 * @adev: amdgpu_device pointer
350 * @me: selected ME (micro engine)
351 * @pipe: pipe
352 * @queue: queue
353 * @vmid: VMID
354 *
355 * Switches the currently active registers instances. Some
356 * registers are instanced per VMID, others are instanced per
357 * me/pipe/queue combination.
358 */
359void vi_srbm_select(struct amdgpu_device *adev,
360 u32 me, u32 pipe, u32 queue, u32 vmid)
361{
362 u32 srbm_gfx_cntl = 0;
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
366 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
367 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
368}
369
370static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
371{
372 /* todo */
373}
374
375static bool vi_read_disabled_bios(struct amdgpu_device *adev)
376{
377 u32 bus_cntl;
378 u32 d1vga_control = 0;
379 u32 d2vga_control = 0;
380 u32 vga_render_control = 0;
381 u32 rom_cntl;
382 bool r;
383
384 bus_cntl = RREG32(mmBUS_CNTL);
385 if (adev->mode_info.num_crtc) {
386 d1vga_control = RREG32(mmD1VGA_CONTROL);
387 d2vga_control = RREG32(mmD2VGA_CONTROL);
388 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
389 }
390 rom_cntl = RREG32_SMC(ixROM_CNTL);
391
392 /* enable the rom */
393 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
394 if (adev->mode_info.num_crtc) {
395 /* Disable VGA mode */
396 WREG32(mmD1VGA_CONTROL,
397 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
398 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
399 WREG32(mmD2VGA_CONTROL,
400 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
401 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
402 WREG32(mmVGA_RENDER_CONTROL,
403 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
404 }
405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
406
407 r = amdgpu_read_bios(adev);
408
409 /* restore regs */
410 WREG32(mmBUS_CNTL, bus_cntl);
411 if (adev->mode_info.num_crtc) {
412 WREG32(mmD1VGA_CONTROL, d1vga_control);
413 WREG32(mmD2VGA_CONTROL, d2vga_control);
414 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
415 }
416 WREG32_SMC(ixROM_CNTL, rom_cntl);
417 return r;
418}
419
420static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
421 u8 *bios, u32 length_bytes)
422{
423 u32 *dw_ptr;
424 unsigned long flags;
425 u32 i, length_dw;
426
427 if (bios == NULL)
428 return false;
429 if (length_bytes == 0)
430 return false;
431 /* APU vbios image is part of sbios image */
432 if (adev->flags & AMD_IS_APU)
433 return false;
434
435 dw_ptr = (u32 *)bios;
436 length_dw = ALIGN(length_bytes, 4) / 4;
437 /* take the smc lock since we are using the smc index */
438 spin_lock_irqsave(&adev->smc_idx_lock, flags);
439 /* set rom index to 0 */
440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
441 WREG32(mmSMC_IND_DATA_11, 0);
442 /* set index to data for continous read */
443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
444 for (i = 0; i < length_dw; i++)
445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447
448 return true;
449}
450
451static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
452 {mmGRBM_STATUS},
453 {mmGRBM_STATUS2},
454 {mmGRBM_STATUS_SE0},
455 {mmGRBM_STATUS_SE1},
456 {mmGRBM_STATUS_SE2},
457 {mmGRBM_STATUS_SE3},
458 {mmSRBM_STATUS},
459 {mmSRBM_STATUS2},
460 {mmSRBM_STATUS3},
461 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
462 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
463 {mmCP_STAT},
464 {mmCP_STALLED_STAT1},
465 {mmCP_STALLED_STAT2},
466 {mmCP_STALLED_STAT3},
467 {mmCP_CPF_BUSY_STAT},
468 {mmCP_CPF_STALLED_STAT1},
469 {mmCP_CPF_STATUS},
470 {mmCP_CPC_BUSY_STAT},
471 {mmCP_CPC_STALLED_STAT1},
472 {mmCP_CPC_STATUS},
473 {mmGB_ADDR_CONFIG},
474 {mmMC_ARB_RAMCFG},
475 {mmGB_TILE_MODE0},
476 {mmGB_TILE_MODE1},
477 {mmGB_TILE_MODE2},
478 {mmGB_TILE_MODE3},
479 {mmGB_TILE_MODE4},
480 {mmGB_TILE_MODE5},
481 {mmGB_TILE_MODE6},
482 {mmGB_TILE_MODE7},
483 {mmGB_TILE_MODE8},
484 {mmGB_TILE_MODE9},
485 {mmGB_TILE_MODE10},
486 {mmGB_TILE_MODE11},
487 {mmGB_TILE_MODE12},
488 {mmGB_TILE_MODE13},
489 {mmGB_TILE_MODE14},
490 {mmGB_TILE_MODE15},
491 {mmGB_TILE_MODE16},
492 {mmGB_TILE_MODE17},
493 {mmGB_TILE_MODE18},
494 {mmGB_TILE_MODE19},
495 {mmGB_TILE_MODE20},
496 {mmGB_TILE_MODE21},
497 {mmGB_TILE_MODE22},
498 {mmGB_TILE_MODE23},
499 {mmGB_TILE_MODE24},
500 {mmGB_TILE_MODE25},
501 {mmGB_TILE_MODE26},
502 {mmGB_TILE_MODE27},
503 {mmGB_TILE_MODE28},
504 {mmGB_TILE_MODE29},
505 {mmGB_TILE_MODE30},
506 {mmGB_TILE_MODE31},
507 {mmGB_MACROTILE_MODE0},
508 {mmGB_MACROTILE_MODE1},
509 {mmGB_MACROTILE_MODE2},
510 {mmGB_MACROTILE_MODE3},
511 {mmGB_MACROTILE_MODE4},
512 {mmGB_MACROTILE_MODE5},
513 {mmGB_MACROTILE_MODE6},
514 {mmGB_MACROTILE_MODE7},
515 {mmGB_MACROTILE_MODE8},
516 {mmGB_MACROTILE_MODE9},
517 {mmGB_MACROTILE_MODE10},
518 {mmGB_MACROTILE_MODE11},
519 {mmGB_MACROTILE_MODE12},
520 {mmGB_MACROTILE_MODE13},
521 {mmGB_MACROTILE_MODE14},
522 {mmGB_MACROTILE_MODE15},
523 {mmCC_RB_BACKEND_DISABLE, true},
524 {mmGC_USER_RB_BACKEND_DISABLE, true},
525 {mmGB_BACKEND_MAP, false},
526 {mmPA_SC_RASTER_CONFIG, true},
527 {mmPA_SC_RASTER_CONFIG_1, true},
528};
529
530static uint32_t vi_get_register_value(struct amdgpu_device *adev,
531 bool indexed, u32 se_num,
532 u32 sh_num, u32 reg_offset)
533{
534 if (indexed) {
535 uint32_t val;
536 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
537 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
538
539 switch (reg_offset) {
540 case mmCC_RB_BACKEND_DISABLE:
541 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
542 case mmGC_USER_RB_BACKEND_DISABLE:
543 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
544 case mmPA_SC_RASTER_CONFIG:
545 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
546 case mmPA_SC_RASTER_CONFIG_1:
547 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
548 }
549
550 mutex_lock(&adev->grbm_idx_mutex);
551 if (se_num != 0xffffffff || sh_num != 0xffffffff)
552 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
553
554 val = RREG32(reg_offset);
555
556 if (se_num != 0xffffffff || sh_num != 0xffffffff)
557 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
558 mutex_unlock(&adev->grbm_idx_mutex);
559 return val;
560 } else {
561 unsigned idx;
562
563 switch (reg_offset) {
564 case mmGB_ADDR_CONFIG:
565 return adev->gfx.config.gb_addr_config;
566 case mmMC_ARB_RAMCFG:
567 return adev->gfx.config.mc_arb_ramcfg;
568 case mmGB_TILE_MODE0:
569 case mmGB_TILE_MODE1:
570 case mmGB_TILE_MODE2:
571 case mmGB_TILE_MODE3:
572 case mmGB_TILE_MODE4:
573 case mmGB_TILE_MODE5:
574 case mmGB_TILE_MODE6:
575 case mmGB_TILE_MODE7:
576 case mmGB_TILE_MODE8:
577 case mmGB_TILE_MODE9:
578 case mmGB_TILE_MODE10:
579 case mmGB_TILE_MODE11:
580 case mmGB_TILE_MODE12:
581 case mmGB_TILE_MODE13:
582 case mmGB_TILE_MODE14:
583 case mmGB_TILE_MODE15:
584 case mmGB_TILE_MODE16:
585 case mmGB_TILE_MODE17:
586 case mmGB_TILE_MODE18:
587 case mmGB_TILE_MODE19:
588 case mmGB_TILE_MODE20:
589 case mmGB_TILE_MODE21:
590 case mmGB_TILE_MODE22:
591 case mmGB_TILE_MODE23:
592 case mmGB_TILE_MODE24:
593 case mmGB_TILE_MODE25:
594 case mmGB_TILE_MODE26:
595 case mmGB_TILE_MODE27:
596 case mmGB_TILE_MODE28:
597 case mmGB_TILE_MODE29:
598 case mmGB_TILE_MODE30:
599 case mmGB_TILE_MODE31:
600 idx = (reg_offset - mmGB_TILE_MODE0);
601 return adev->gfx.config.tile_mode_array[idx];
602 case mmGB_MACROTILE_MODE0:
603 case mmGB_MACROTILE_MODE1:
604 case mmGB_MACROTILE_MODE2:
605 case mmGB_MACROTILE_MODE3:
606 case mmGB_MACROTILE_MODE4:
607 case mmGB_MACROTILE_MODE5:
608 case mmGB_MACROTILE_MODE6:
609 case mmGB_MACROTILE_MODE7:
610 case mmGB_MACROTILE_MODE8:
611 case mmGB_MACROTILE_MODE9:
612 case mmGB_MACROTILE_MODE10:
613 case mmGB_MACROTILE_MODE11:
614 case mmGB_MACROTILE_MODE12:
615 case mmGB_MACROTILE_MODE13:
616 case mmGB_MACROTILE_MODE14:
617 case mmGB_MACROTILE_MODE15:
618 idx = (reg_offset - mmGB_MACROTILE_MODE0);
619 return adev->gfx.config.macrotile_mode_array[idx];
620 default:
621 return RREG32(reg_offset);
622 }
623 }
624}
625
626static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
627 u32 sh_num, u32 reg_offset, u32 *value)
628{
629 uint32_t i;
630
631 *value = 0;
632 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
633 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
634
635 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
636 continue;
637
638 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
639 reg_offset);
640 return 0;
641 }
642 return -EINVAL;
643}
644
645static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
646{
647 u32 i;
648
649 dev_info(adev->dev, "GPU pci config reset\n");
650
651 /* disable BM */
652 pci_clear_master(adev->pdev);
653 /* reset */
654 amdgpu_device_pci_config_reset(adev);
655
656 udelay(100);
657
658 /* wait for asic to come out of reset */
659 for (i = 0; i < adev->usec_timeout; i++) {
660 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
661 /* enable BM */
662 pci_set_master(adev->pdev);
663 adev->has_hw_reset = true;
664 return 0;
665 }
666 udelay(1);
667 }
668 return -EINVAL;
669}
670
671/**
672 * vi_asic_pci_config_reset - soft reset GPU
673 *
674 * @adev: amdgpu_device pointer
675 *
676 * Use PCI Config method to reset the GPU.
677 *
678 * Returns 0 for success.
679 */
680static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
681{
682 int r;
683
684 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
685
686 r = vi_gpu_pci_config_reset(adev);
687
688 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
689
690 return r;
691}
692
693static bool vi_asic_supports_baco(struct amdgpu_device *adev)
694{
695 switch (adev->asic_type) {
696 case CHIP_FIJI:
697 case CHIP_TONGA:
698 case CHIP_POLARIS10:
699 case CHIP_POLARIS11:
700 case CHIP_POLARIS12:
701 case CHIP_TOPAZ:
702 return amdgpu_dpm_is_baco_supported(adev);
703 default:
704 return false;
705 }
706}
707
708static enum amd_reset_method
709vi_asic_reset_method(struct amdgpu_device *adev)
710{
711 bool baco_reset;
712
713 if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
714 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
715 return amdgpu_reset_method;
716
717 if (amdgpu_reset_method != -1)
718 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
719 amdgpu_reset_method);
720
721 switch (adev->asic_type) {
722 case CHIP_FIJI:
723 case CHIP_TONGA:
724 case CHIP_POLARIS10:
725 case CHIP_POLARIS11:
726 case CHIP_POLARIS12:
727 case CHIP_TOPAZ:
728 baco_reset = amdgpu_dpm_is_baco_supported(adev);
729 break;
730 default:
731 baco_reset = false;
732 break;
733 }
734
735 if (baco_reset)
736 return AMD_RESET_METHOD_BACO;
737 else
738 return AMD_RESET_METHOD_LEGACY;
739}
740
741/**
742 * vi_asic_reset - soft reset GPU
743 *
744 * @adev: amdgpu_device pointer
745 *
746 * Look up which blocks are hung and attempt
747 * to reset them.
748 * Returns 0 for success.
749 */
750static int vi_asic_reset(struct amdgpu_device *adev)
751{
752 int r;
753
754 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
755 r = amdgpu_dpm_baco_reset(adev);
756 } else {
757 r = vi_asic_pci_config_reset(adev);
758 }
759
760 return r;
761}
762
763static u32 vi_get_config_memsize(struct amdgpu_device *adev)
764{
765 return RREG32(mmCONFIG_MEMSIZE);
766}
767
768static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
769 u32 cntl_reg, u32 status_reg)
770{
771 int r, i;
772 struct atom_clock_dividers dividers;
773 uint32_t tmp;
774
775 r = amdgpu_atombios_get_clock_dividers(adev,
776 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
777 clock, false, ÷rs);
778 if (r)
779 return r;
780
781 tmp = RREG32_SMC(cntl_reg);
782
783 if (adev->flags & AMD_IS_APU)
784 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
785 else
786 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
787 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
788 tmp |= dividers.post_divider;
789 WREG32_SMC(cntl_reg, tmp);
790
791 for (i = 0; i < 100; i++) {
792 tmp = RREG32_SMC(status_reg);
793 if (adev->flags & AMD_IS_APU) {
794 if (tmp & 0x10000)
795 break;
796 } else {
797 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
798 break;
799 }
800 mdelay(10);
801 }
802 if (i == 100)
803 return -ETIMEDOUT;
804 return 0;
805}
806
807#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
808#define ixGNB_CLK1_STATUS 0xD822010C
809#define ixGNB_CLK2_DFS_CNTL 0xD8220110
810#define ixGNB_CLK2_STATUS 0xD822012C
811#define ixGNB_CLK3_DFS_CNTL 0xD8220130
812#define ixGNB_CLK3_STATUS 0xD822014C
813
814static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
815{
816 int r;
817
818 if (adev->flags & AMD_IS_APU) {
819 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
820 if (r)
821 return r;
822
823 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
824 if (r)
825 return r;
826 } else {
827 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
828 if (r)
829 return r;
830
831 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
832 if (r)
833 return r;
834 }
835
836 return 0;
837}
838
839static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
840{
841 int r, i;
842 struct atom_clock_dividers dividers;
843 u32 tmp;
844 u32 reg_ctrl;
845 u32 reg_status;
846 u32 status_mask;
847 u32 reg_mask;
848
849 if (adev->flags & AMD_IS_APU) {
850 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
851 reg_status = ixGNB_CLK3_STATUS;
852 status_mask = 0x00010000;
853 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
854 } else {
855 reg_ctrl = ixCG_ECLK_CNTL;
856 reg_status = ixCG_ECLK_STATUS;
857 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
858 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
859 }
860
861 r = amdgpu_atombios_get_clock_dividers(adev,
862 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
863 ecclk, false, ÷rs);
864 if (r)
865 return r;
866
867 for (i = 0; i < 100; i++) {
868 if (RREG32_SMC(reg_status) & status_mask)
869 break;
870 mdelay(10);
871 }
872
873 if (i == 100)
874 return -ETIMEDOUT;
875
876 tmp = RREG32_SMC(reg_ctrl);
877 tmp &= ~reg_mask;
878 tmp |= dividers.post_divider;
879 WREG32_SMC(reg_ctrl, tmp);
880
881 for (i = 0; i < 100; i++) {
882 if (RREG32_SMC(reg_status) & status_mask)
883 break;
884 mdelay(10);
885 }
886
887 if (i == 100)
888 return -ETIMEDOUT;
889
890 return 0;
891}
892
893static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
894{
895 if (pci_is_root_bus(adev->pdev->bus))
896 return;
897
898 if (amdgpu_pcie_gen2 == 0)
899 return;
900
901 if (adev->flags & AMD_IS_APU)
902 return;
903
904 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
905 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
906 return;
907
908 /* todo */
909}
910
911static void vi_program_aspm(struct amdgpu_device *adev)
912{
913
914 if (amdgpu_aspm == 0)
915 return;
916
917 /* todo */
918}
919
920static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
921 bool enable)
922{
923 u32 tmp;
924
925 /* not necessary on CZ */
926 if (adev->flags & AMD_IS_APU)
927 return;
928
929 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
930 if (enable)
931 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
932 else
933 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
934
935 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
936}
937
938#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
939#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
940#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
941
942static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
943{
944 if (adev->flags & AMD_IS_APU)
945 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
946 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
947 else
948 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
949 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
950}
951
952static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
953{
954 if (!ring || !ring->funcs->emit_wreg) {
955 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
956 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
957 } else {
958 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
959 }
960}
961
962static void vi_invalidate_hdp(struct amdgpu_device *adev,
963 struct amdgpu_ring *ring)
964{
965 if (!ring || !ring->funcs->emit_wreg) {
966 WREG32(mmHDP_DEBUG0, 1);
967 RREG32(mmHDP_DEBUG0);
968 } else {
969 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
970 }
971}
972
973static bool vi_need_full_reset(struct amdgpu_device *adev)
974{
975 switch (adev->asic_type) {
976 case CHIP_CARRIZO:
977 case CHIP_STONEY:
978 /* CZ has hang issues with full reset at the moment */
979 return false;
980 case CHIP_FIJI:
981 case CHIP_TONGA:
982 /* XXX: soft reset should work on fiji and tonga */
983 return true;
984 case CHIP_POLARIS10:
985 case CHIP_POLARIS11:
986 case CHIP_POLARIS12:
987 case CHIP_TOPAZ:
988 default:
989 /* change this when we support soft reset */
990 return true;
991 }
992}
993
994static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
995 uint64_t *count1)
996{
997 uint32_t perfctr = 0;
998 uint64_t cnt0_of, cnt1_of;
999 int tmp;
1000
1001 /* This reports 0 on APUs, so return to avoid writing/reading registers
1002 * that may or may not be different from their GPU counterparts
1003 */
1004 if (adev->flags & AMD_IS_APU)
1005 return;
1006
1007 /* Set the 2 events that we wish to watch, defined above */
1008 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1009 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1010 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1011
1012 /* Write to enable desired perf counters */
1013 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1014 /* Zero out and enable the perf counters
1015 * Write 0x5:
1016 * Bit 0 = Start all counters(1)
1017 * Bit 2 = Global counter reset enable(1)
1018 */
1019 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1020
1021 msleep(1000);
1022
1023 /* Load the shadow and disable the perf counters
1024 * Write 0x2:
1025 * Bit 0 = Stop counters(0)
1026 * Bit 1 = Load the shadow counters(1)
1027 */
1028 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1029
1030 /* Read register values to get any >32bit overflow */
1031 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1032 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1033 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1034
1035 /* Get the values and add the overflow */
1036 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1037 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1038}
1039
1040static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1041{
1042 uint64_t nak_r, nak_g;
1043
1044 /* Get the number of NAKs received and generated */
1045 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1046 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1047
1048 /* Add the total number of NAKs, i.e the number of replays */
1049 return (nak_r + nak_g);
1050}
1051
1052static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1053{
1054 u32 clock_cntl, pc;
1055
1056 if (adev->flags & AMD_IS_APU)
1057 return false;
1058
1059 /* check if the SMC is already running */
1060 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1061 pc = RREG32_SMC(ixSMC_PC_C);
1062 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1063 (0x20100 <= pc))
1064 return true;
1065
1066 return false;
1067}
1068
1069static const struct amdgpu_asic_funcs vi_asic_funcs =
1070{
1071 .read_disabled_bios = &vi_read_disabled_bios,
1072 .read_bios_from_rom = &vi_read_bios_from_rom,
1073 .read_register = &vi_read_register,
1074 .reset = &vi_asic_reset,
1075 .reset_method = &vi_asic_reset_method,
1076 .set_vga_state = &vi_vga_set_state,
1077 .get_xclk = &vi_get_xclk,
1078 .set_uvd_clocks = &vi_set_uvd_clocks,
1079 .set_vce_clocks = &vi_set_vce_clocks,
1080 .get_config_memsize = &vi_get_config_memsize,
1081 .flush_hdp = &vi_flush_hdp,
1082 .invalidate_hdp = &vi_invalidate_hdp,
1083 .need_full_reset = &vi_need_full_reset,
1084 .init_doorbell_index = &legacy_doorbell_index_init,
1085 .get_pcie_usage = &vi_get_pcie_usage,
1086 .need_reset_on_init = &vi_need_reset_on_init,
1087 .get_pcie_replay_count = &vi_get_pcie_replay_count,
1088 .supports_baco = &vi_asic_supports_baco,
1089};
1090
1091#define CZ_REV_BRISTOL(rev) \
1092 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1093
1094static int vi_common_early_init(void *handle)
1095{
1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098 if (adev->flags & AMD_IS_APU) {
1099 adev->smc_rreg = &cz_smc_rreg;
1100 adev->smc_wreg = &cz_smc_wreg;
1101 } else {
1102 adev->smc_rreg = &vi_smc_rreg;
1103 adev->smc_wreg = &vi_smc_wreg;
1104 }
1105 adev->pcie_rreg = &vi_pcie_rreg;
1106 adev->pcie_wreg = &vi_pcie_wreg;
1107 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1108 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1109 adev->didt_rreg = &vi_didt_rreg;
1110 adev->didt_wreg = &vi_didt_wreg;
1111 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1112 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1113
1114 adev->asic_funcs = &vi_asic_funcs;
1115
1116 adev->rev_id = vi_get_rev_id(adev);
1117 adev->external_rev_id = 0xFF;
1118 switch (adev->asic_type) {
1119 case CHIP_TOPAZ:
1120 adev->cg_flags = 0;
1121 adev->pg_flags = 0;
1122 adev->external_rev_id = 0x1;
1123 break;
1124 case CHIP_FIJI:
1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1126 AMD_CG_SUPPORT_GFX_MGLS |
1127 AMD_CG_SUPPORT_GFX_RLC_LS |
1128 AMD_CG_SUPPORT_GFX_CP_LS |
1129 AMD_CG_SUPPORT_GFX_CGTS |
1130 AMD_CG_SUPPORT_GFX_CGTS_LS |
1131 AMD_CG_SUPPORT_GFX_CGCG |
1132 AMD_CG_SUPPORT_GFX_CGLS |
1133 AMD_CG_SUPPORT_SDMA_MGCG |
1134 AMD_CG_SUPPORT_SDMA_LS |
1135 AMD_CG_SUPPORT_BIF_LS |
1136 AMD_CG_SUPPORT_HDP_MGCG |
1137 AMD_CG_SUPPORT_HDP_LS |
1138 AMD_CG_SUPPORT_ROM_MGCG |
1139 AMD_CG_SUPPORT_MC_MGCG |
1140 AMD_CG_SUPPORT_MC_LS |
1141 AMD_CG_SUPPORT_UVD_MGCG;
1142 adev->pg_flags = 0;
1143 adev->external_rev_id = adev->rev_id + 0x3c;
1144 break;
1145 case CHIP_TONGA:
1146 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1147 AMD_CG_SUPPORT_GFX_CGCG |
1148 AMD_CG_SUPPORT_GFX_CGLS |
1149 AMD_CG_SUPPORT_SDMA_MGCG |
1150 AMD_CG_SUPPORT_SDMA_LS |
1151 AMD_CG_SUPPORT_BIF_LS |
1152 AMD_CG_SUPPORT_HDP_MGCG |
1153 AMD_CG_SUPPORT_HDP_LS |
1154 AMD_CG_SUPPORT_ROM_MGCG |
1155 AMD_CG_SUPPORT_MC_MGCG |
1156 AMD_CG_SUPPORT_MC_LS |
1157 AMD_CG_SUPPORT_DRM_LS |
1158 AMD_CG_SUPPORT_UVD_MGCG;
1159 adev->pg_flags = 0;
1160 adev->external_rev_id = adev->rev_id + 0x14;
1161 break;
1162 case CHIP_POLARIS11:
1163 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1164 AMD_CG_SUPPORT_GFX_RLC_LS |
1165 AMD_CG_SUPPORT_GFX_CP_LS |
1166 AMD_CG_SUPPORT_GFX_CGCG |
1167 AMD_CG_SUPPORT_GFX_CGLS |
1168 AMD_CG_SUPPORT_GFX_3D_CGCG |
1169 AMD_CG_SUPPORT_GFX_3D_CGLS |
1170 AMD_CG_SUPPORT_SDMA_MGCG |
1171 AMD_CG_SUPPORT_SDMA_LS |
1172 AMD_CG_SUPPORT_BIF_MGCG |
1173 AMD_CG_SUPPORT_BIF_LS |
1174 AMD_CG_SUPPORT_HDP_MGCG |
1175 AMD_CG_SUPPORT_HDP_LS |
1176 AMD_CG_SUPPORT_ROM_MGCG |
1177 AMD_CG_SUPPORT_MC_MGCG |
1178 AMD_CG_SUPPORT_MC_LS |
1179 AMD_CG_SUPPORT_DRM_LS |
1180 AMD_CG_SUPPORT_UVD_MGCG |
1181 AMD_CG_SUPPORT_VCE_MGCG;
1182 adev->pg_flags = 0;
1183 adev->external_rev_id = adev->rev_id + 0x5A;
1184 break;
1185 case CHIP_POLARIS10:
1186 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1187 AMD_CG_SUPPORT_GFX_RLC_LS |
1188 AMD_CG_SUPPORT_GFX_CP_LS |
1189 AMD_CG_SUPPORT_GFX_CGCG |
1190 AMD_CG_SUPPORT_GFX_CGLS |
1191 AMD_CG_SUPPORT_GFX_3D_CGCG |
1192 AMD_CG_SUPPORT_GFX_3D_CGLS |
1193 AMD_CG_SUPPORT_SDMA_MGCG |
1194 AMD_CG_SUPPORT_SDMA_LS |
1195 AMD_CG_SUPPORT_BIF_MGCG |
1196 AMD_CG_SUPPORT_BIF_LS |
1197 AMD_CG_SUPPORT_HDP_MGCG |
1198 AMD_CG_SUPPORT_HDP_LS |
1199 AMD_CG_SUPPORT_ROM_MGCG |
1200 AMD_CG_SUPPORT_MC_MGCG |
1201 AMD_CG_SUPPORT_MC_LS |
1202 AMD_CG_SUPPORT_DRM_LS |
1203 AMD_CG_SUPPORT_UVD_MGCG |
1204 AMD_CG_SUPPORT_VCE_MGCG;
1205 adev->pg_flags = 0;
1206 adev->external_rev_id = adev->rev_id + 0x50;
1207 break;
1208 case CHIP_POLARIS12:
1209 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1210 AMD_CG_SUPPORT_GFX_RLC_LS |
1211 AMD_CG_SUPPORT_GFX_CP_LS |
1212 AMD_CG_SUPPORT_GFX_CGCG |
1213 AMD_CG_SUPPORT_GFX_CGLS |
1214 AMD_CG_SUPPORT_GFX_3D_CGCG |
1215 AMD_CG_SUPPORT_GFX_3D_CGLS |
1216 AMD_CG_SUPPORT_SDMA_MGCG |
1217 AMD_CG_SUPPORT_SDMA_LS |
1218 AMD_CG_SUPPORT_BIF_MGCG |
1219 AMD_CG_SUPPORT_BIF_LS |
1220 AMD_CG_SUPPORT_HDP_MGCG |
1221 AMD_CG_SUPPORT_HDP_LS |
1222 AMD_CG_SUPPORT_ROM_MGCG |
1223 AMD_CG_SUPPORT_MC_MGCG |
1224 AMD_CG_SUPPORT_MC_LS |
1225 AMD_CG_SUPPORT_DRM_LS |
1226 AMD_CG_SUPPORT_UVD_MGCG |
1227 AMD_CG_SUPPORT_VCE_MGCG;
1228 adev->pg_flags = 0;
1229 adev->external_rev_id = adev->rev_id + 0x64;
1230 break;
1231 case CHIP_VEGAM:
1232 adev->cg_flags = 0;
1233 /*AMD_CG_SUPPORT_GFX_MGCG |
1234 AMD_CG_SUPPORT_GFX_RLC_LS |
1235 AMD_CG_SUPPORT_GFX_CP_LS |
1236 AMD_CG_SUPPORT_GFX_CGCG |
1237 AMD_CG_SUPPORT_GFX_CGLS |
1238 AMD_CG_SUPPORT_GFX_3D_CGCG |
1239 AMD_CG_SUPPORT_GFX_3D_CGLS |
1240 AMD_CG_SUPPORT_SDMA_MGCG |
1241 AMD_CG_SUPPORT_SDMA_LS |
1242 AMD_CG_SUPPORT_BIF_MGCG |
1243 AMD_CG_SUPPORT_BIF_LS |
1244 AMD_CG_SUPPORT_HDP_MGCG |
1245 AMD_CG_SUPPORT_HDP_LS |
1246 AMD_CG_SUPPORT_ROM_MGCG |
1247 AMD_CG_SUPPORT_MC_MGCG |
1248 AMD_CG_SUPPORT_MC_LS |
1249 AMD_CG_SUPPORT_DRM_LS |
1250 AMD_CG_SUPPORT_UVD_MGCG |
1251 AMD_CG_SUPPORT_VCE_MGCG;*/
1252 adev->pg_flags = 0;
1253 adev->external_rev_id = adev->rev_id + 0x6E;
1254 break;
1255 case CHIP_CARRIZO:
1256 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1257 AMD_CG_SUPPORT_GFX_MGCG |
1258 AMD_CG_SUPPORT_GFX_MGLS |
1259 AMD_CG_SUPPORT_GFX_RLC_LS |
1260 AMD_CG_SUPPORT_GFX_CP_LS |
1261 AMD_CG_SUPPORT_GFX_CGTS |
1262 AMD_CG_SUPPORT_GFX_CGTS_LS |
1263 AMD_CG_SUPPORT_GFX_CGCG |
1264 AMD_CG_SUPPORT_GFX_CGLS |
1265 AMD_CG_SUPPORT_BIF_LS |
1266 AMD_CG_SUPPORT_HDP_MGCG |
1267 AMD_CG_SUPPORT_HDP_LS |
1268 AMD_CG_SUPPORT_SDMA_MGCG |
1269 AMD_CG_SUPPORT_SDMA_LS |
1270 AMD_CG_SUPPORT_VCE_MGCG;
1271 /* rev0 hardware requires workarounds to support PG */
1272 adev->pg_flags = 0;
1273 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1274 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1275 AMD_PG_SUPPORT_GFX_PIPELINE |
1276 AMD_PG_SUPPORT_CP |
1277 AMD_PG_SUPPORT_UVD |
1278 AMD_PG_SUPPORT_VCE;
1279 }
1280 adev->external_rev_id = adev->rev_id + 0x1;
1281 break;
1282 case CHIP_STONEY:
1283 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1284 AMD_CG_SUPPORT_GFX_MGCG |
1285 AMD_CG_SUPPORT_GFX_MGLS |
1286 AMD_CG_SUPPORT_GFX_RLC_LS |
1287 AMD_CG_SUPPORT_GFX_CP_LS |
1288 AMD_CG_SUPPORT_GFX_CGTS |
1289 AMD_CG_SUPPORT_GFX_CGTS_LS |
1290 AMD_CG_SUPPORT_GFX_CGLS |
1291 AMD_CG_SUPPORT_BIF_LS |
1292 AMD_CG_SUPPORT_HDP_MGCG |
1293 AMD_CG_SUPPORT_HDP_LS |
1294 AMD_CG_SUPPORT_SDMA_MGCG |
1295 AMD_CG_SUPPORT_SDMA_LS |
1296 AMD_CG_SUPPORT_VCE_MGCG;
1297 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1298 AMD_PG_SUPPORT_GFX_SMG |
1299 AMD_PG_SUPPORT_GFX_PIPELINE |
1300 AMD_PG_SUPPORT_CP |
1301 AMD_PG_SUPPORT_UVD |
1302 AMD_PG_SUPPORT_VCE;
1303 adev->external_rev_id = adev->rev_id + 0x61;
1304 break;
1305 default:
1306 /* FIXME: not supported yet */
1307 return -EINVAL;
1308 }
1309
1310 if (amdgpu_sriov_vf(adev)) {
1311 amdgpu_virt_init_setting(adev);
1312 xgpu_vi_mailbox_set_irq_funcs(adev);
1313 }
1314
1315 return 0;
1316}
1317
1318static int vi_common_late_init(void *handle)
1319{
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322 if (amdgpu_sriov_vf(adev))
1323 xgpu_vi_mailbox_get_irq(adev);
1324
1325 return 0;
1326}
1327
1328static int vi_common_sw_init(void *handle)
1329{
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332 if (amdgpu_sriov_vf(adev))
1333 xgpu_vi_mailbox_add_irq_id(adev);
1334
1335 return 0;
1336}
1337
1338static int vi_common_sw_fini(void *handle)
1339{
1340 return 0;
1341}
1342
1343static int vi_common_hw_init(void *handle)
1344{
1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347 /* move the golden regs per IP block */
1348 vi_init_golden_registers(adev);
1349 /* enable pcie gen2/3 link */
1350 vi_pcie_gen3_enable(adev);
1351 /* enable aspm */
1352 vi_program_aspm(adev);
1353 /* enable the doorbell aperture */
1354 vi_enable_doorbell_aperture(adev, true);
1355
1356 return 0;
1357}
1358
1359static int vi_common_hw_fini(void *handle)
1360{
1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362
1363 /* enable the doorbell aperture */
1364 vi_enable_doorbell_aperture(adev, false);
1365
1366 if (amdgpu_sriov_vf(adev))
1367 xgpu_vi_mailbox_put_irq(adev);
1368
1369 return 0;
1370}
1371
1372static int vi_common_suspend(void *handle)
1373{
1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376 return vi_common_hw_fini(adev);
1377}
1378
1379static int vi_common_resume(void *handle)
1380{
1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1382
1383 return vi_common_hw_init(adev);
1384}
1385
1386static bool vi_common_is_idle(void *handle)
1387{
1388 return true;
1389}
1390
1391static int vi_common_wait_for_idle(void *handle)
1392{
1393 return 0;
1394}
1395
1396static int vi_common_soft_reset(void *handle)
1397{
1398 return 0;
1399}
1400
1401static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1402 bool enable)
1403{
1404 uint32_t temp, data;
1405
1406 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1407
1408 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1409 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1410 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1411 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1412 else
1413 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1414 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1415 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1416
1417 if (temp != data)
1418 WREG32_PCIE(ixPCIE_CNTL2, data);
1419}
1420
1421static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1422 bool enable)
1423{
1424 uint32_t temp, data;
1425
1426 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1427
1428 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1429 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1430 else
1431 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1432
1433 if (temp != data)
1434 WREG32(mmHDP_HOST_PATH_CNTL, data);
1435}
1436
1437static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1438 bool enable)
1439{
1440 uint32_t temp, data;
1441
1442 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1443
1444 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1445 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1446 else
1447 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1448
1449 if (temp != data)
1450 WREG32(mmHDP_MEM_POWER_LS, data);
1451}
1452
1453static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1454 bool enable)
1455{
1456 uint32_t temp, data;
1457
1458 temp = data = RREG32(0x157a);
1459
1460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1461 data |= 1;
1462 else
1463 data &= ~1;
1464
1465 if (temp != data)
1466 WREG32(0x157a, data);
1467}
1468
1469
1470static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1471 bool enable)
1472{
1473 uint32_t temp, data;
1474
1475 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1476
1477 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1478 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1479 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1480 else
1481 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1482 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1483
1484 if (temp != data)
1485 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1486}
1487
1488static int vi_common_set_clockgating_state_by_smu(void *handle,
1489 enum amd_clockgating_state state)
1490{
1491 uint32_t msg_id, pp_state = 0;
1492 uint32_t pp_support_state = 0;
1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1494
1495 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1496 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1497 pp_support_state = PP_STATE_SUPPORT_LS;
1498 pp_state = PP_STATE_LS;
1499 }
1500 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1501 pp_support_state |= PP_STATE_SUPPORT_CG;
1502 pp_state |= PP_STATE_CG;
1503 }
1504 if (state == AMD_CG_STATE_UNGATE)
1505 pp_state = 0;
1506 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1507 PP_BLOCK_SYS_MC,
1508 pp_support_state,
1509 pp_state);
1510 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1511 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1512 }
1513
1514 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1515 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1516 pp_support_state = PP_STATE_SUPPORT_LS;
1517 pp_state = PP_STATE_LS;
1518 }
1519 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1520 pp_support_state |= PP_STATE_SUPPORT_CG;
1521 pp_state |= PP_STATE_CG;
1522 }
1523 if (state == AMD_CG_STATE_UNGATE)
1524 pp_state = 0;
1525 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1526 PP_BLOCK_SYS_SDMA,
1527 pp_support_state,
1528 pp_state);
1529 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1530 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1531 }
1532
1533 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1534 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1535 pp_support_state = PP_STATE_SUPPORT_LS;
1536 pp_state = PP_STATE_LS;
1537 }
1538 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1539 pp_support_state |= PP_STATE_SUPPORT_CG;
1540 pp_state |= PP_STATE_CG;
1541 }
1542 if (state == AMD_CG_STATE_UNGATE)
1543 pp_state = 0;
1544 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1545 PP_BLOCK_SYS_HDP,
1546 pp_support_state,
1547 pp_state);
1548 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1549 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1550 }
1551
1552
1553 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1554 if (state == AMD_CG_STATE_UNGATE)
1555 pp_state = 0;
1556 else
1557 pp_state = PP_STATE_LS;
1558
1559 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1560 PP_BLOCK_SYS_BIF,
1561 PP_STATE_SUPPORT_LS,
1562 pp_state);
1563 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1564 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1565 }
1566 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1567 if (state == AMD_CG_STATE_UNGATE)
1568 pp_state = 0;
1569 else
1570 pp_state = PP_STATE_CG;
1571
1572 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1573 PP_BLOCK_SYS_BIF,
1574 PP_STATE_SUPPORT_CG,
1575 pp_state);
1576 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1577 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1578 }
1579
1580 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1581
1582 if (state == AMD_CG_STATE_UNGATE)
1583 pp_state = 0;
1584 else
1585 pp_state = PP_STATE_LS;
1586
1587 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1588 PP_BLOCK_SYS_DRM,
1589 PP_STATE_SUPPORT_LS,
1590 pp_state);
1591 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1592 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1593 }
1594
1595 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1596
1597 if (state == AMD_CG_STATE_UNGATE)
1598 pp_state = 0;
1599 else
1600 pp_state = PP_STATE_CG;
1601
1602 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1603 PP_BLOCK_SYS_ROM,
1604 PP_STATE_SUPPORT_CG,
1605 pp_state);
1606 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1607 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1608 }
1609 return 0;
1610}
1611
1612static int vi_common_set_clockgating_state(void *handle,
1613 enum amd_clockgating_state state)
1614{
1615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1616
1617 if (amdgpu_sriov_vf(adev))
1618 return 0;
1619
1620 switch (adev->asic_type) {
1621 case CHIP_FIJI:
1622 vi_update_bif_medium_grain_light_sleep(adev,
1623 state == AMD_CG_STATE_GATE);
1624 vi_update_hdp_medium_grain_clock_gating(adev,
1625 state == AMD_CG_STATE_GATE);
1626 vi_update_hdp_light_sleep(adev,
1627 state == AMD_CG_STATE_GATE);
1628 vi_update_rom_medium_grain_clock_gating(adev,
1629 state == AMD_CG_STATE_GATE);
1630 break;
1631 case CHIP_CARRIZO:
1632 case CHIP_STONEY:
1633 vi_update_bif_medium_grain_light_sleep(adev,
1634 state == AMD_CG_STATE_GATE);
1635 vi_update_hdp_medium_grain_clock_gating(adev,
1636 state == AMD_CG_STATE_GATE);
1637 vi_update_hdp_light_sleep(adev,
1638 state == AMD_CG_STATE_GATE);
1639 vi_update_drm_light_sleep(adev,
1640 state == AMD_CG_STATE_GATE);
1641 break;
1642 case CHIP_TONGA:
1643 case CHIP_POLARIS10:
1644 case CHIP_POLARIS11:
1645 case CHIP_POLARIS12:
1646 case CHIP_VEGAM:
1647 vi_common_set_clockgating_state_by_smu(adev, state);
1648 default:
1649 break;
1650 }
1651 return 0;
1652}
1653
1654static int vi_common_set_powergating_state(void *handle,
1655 enum amd_powergating_state state)
1656{
1657 return 0;
1658}
1659
1660static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1661{
1662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1663 int data;
1664
1665 if (amdgpu_sriov_vf(adev))
1666 *flags = 0;
1667
1668 /* AMD_CG_SUPPORT_BIF_LS */
1669 data = RREG32_PCIE(ixPCIE_CNTL2);
1670 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1671 *flags |= AMD_CG_SUPPORT_BIF_LS;
1672
1673 /* AMD_CG_SUPPORT_HDP_LS */
1674 data = RREG32(mmHDP_MEM_POWER_LS);
1675 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1676 *flags |= AMD_CG_SUPPORT_HDP_LS;
1677
1678 /* AMD_CG_SUPPORT_HDP_MGCG */
1679 data = RREG32(mmHDP_HOST_PATH_CNTL);
1680 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1681 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1682
1683 /* AMD_CG_SUPPORT_ROM_MGCG */
1684 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1685 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1686 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1687}
1688
1689static const struct amd_ip_funcs vi_common_ip_funcs = {
1690 .name = "vi_common",
1691 .early_init = vi_common_early_init,
1692 .late_init = vi_common_late_init,
1693 .sw_init = vi_common_sw_init,
1694 .sw_fini = vi_common_sw_fini,
1695 .hw_init = vi_common_hw_init,
1696 .hw_fini = vi_common_hw_fini,
1697 .suspend = vi_common_suspend,
1698 .resume = vi_common_resume,
1699 .is_idle = vi_common_is_idle,
1700 .wait_for_idle = vi_common_wait_for_idle,
1701 .soft_reset = vi_common_soft_reset,
1702 .set_clockgating_state = vi_common_set_clockgating_state,
1703 .set_powergating_state = vi_common_set_powergating_state,
1704 .get_clockgating_state = vi_common_get_clockgating_state,
1705};
1706
1707static const struct amdgpu_ip_block_version vi_common_ip_block =
1708{
1709 .type = AMD_IP_BLOCK_TYPE_COMMON,
1710 .major = 1,
1711 .minor = 0,
1712 .rev = 0,
1713 .funcs = &vi_common_ip_funcs,
1714};
1715
1716void vi_set_virt_ops(struct amdgpu_device *adev)
1717{
1718 adev->virt.ops = &xgpu_vi_virt_ops;
1719}
1720
1721int vi_set_ip_blocks(struct amdgpu_device *adev)
1722{
1723 switch (adev->asic_type) {
1724 case CHIP_TOPAZ:
1725 /* topaz has no DCE, UVD, VCE */
1726 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1727 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1728 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1729 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1730 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1731 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1732 if (adev->enable_virtual_display)
1733 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1734 break;
1735 case CHIP_FIJI:
1736 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1737 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1738 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1739 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1740 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1741 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1742 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1743 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1744#if defined(CONFIG_DRM_AMD_DC)
1745 else if (amdgpu_device_has_dc_support(adev))
1746 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1747#endif
1748 else
1749 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1750 if (!amdgpu_sriov_vf(adev)) {
1751 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1752 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1753 }
1754 break;
1755 case CHIP_TONGA:
1756 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1757 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1758 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1759 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1760 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1761 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1762 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1763 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1764#if defined(CONFIG_DRM_AMD_DC)
1765 else if (amdgpu_device_has_dc_support(adev))
1766 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1767#endif
1768 else
1769 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1770 if (!amdgpu_sriov_vf(adev)) {
1771 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1772 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1773 }
1774 break;
1775 case CHIP_POLARIS10:
1776 case CHIP_POLARIS11:
1777 case CHIP_POLARIS12:
1778 case CHIP_VEGAM:
1779 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1780 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1781 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1782 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1783 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1784 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1785 if (adev->enable_virtual_display)
1786 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1787#if defined(CONFIG_DRM_AMD_DC)
1788 else if (amdgpu_device_has_dc_support(adev))
1789 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1790#endif
1791 else
1792 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1793 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1794 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1795 break;
1796 case CHIP_CARRIZO:
1797 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1798 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1799 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1800 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1801 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1802 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1803 if (adev->enable_virtual_display)
1804 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1805#if defined(CONFIG_DRM_AMD_DC)
1806 else if (amdgpu_device_has_dc_support(adev))
1807 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1808#endif
1809 else
1810 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1811 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1812 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1813#if defined(CONFIG_DRM_AMD_ACP)
1814 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1815#endif
1816 break;
1817 case CHIP_STONEY:
1818 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1819 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1820 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1821 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1822 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1823 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1824 if (adev->enable_virtual_display)
1825 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1826#if defined(CONFIG_DRM_AMD_DC)
1827 else if (amdgpu_device_has_dc_support(adev))
1828 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1829#endif
1830 else
1831 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1832 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1833 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1834#if defined(CONFIG_DRM_AMD_ACP)
1835 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1836#endif
1837 break;
1838 default:
1839 /* FIXME: not supported yet */
1840 return -EINVAL;
1841 }
1842
1843 return 0;
1844}
1845
1846void legacy_doorbell_index_init(struct amdgpu_device *adev)
1847{
1848 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1849 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1850 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1851 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1852 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1853 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1854 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1855 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1856 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1857 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1858 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1859 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1860 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1861 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1862}