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1/*
2 * Cryptographic API.
3 *
4 * Support Blackfin CRC HW acceleration.
5 *
6 * Copyright 2012 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2.
9 */
10
11#include <linux/err.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/platform_device.h>
21#include <linux/scatterlist.h>
22#include <linux/dma-mapping.h>
23#include <linux/delay.h>
24#include <linux/unaligned/access_ok.h>
25#include <linux/crypto.h>
26#include <linux/cryptohash.h>
27#include <crypto/scatterwalk.h>
28#include <crypto/algapi.h>
29#include <crypto/hash.h>
30#include <crypto/internal/hash.h>
31
32#include <asm/blackfin.h>
33#include <asm/bfin_crc.h>
34#include <asm/dma.h>
35#include <asm/portmux.h>
36
37#define CRC_CCRYPTO_QUEUE_LENGTH 5
38
39#define DRIVER_NAME "bfin-hmac-crc"
40#define CHKSUM_DIGEST_SIZE 4
41#define CHKSUM_BLOCK_SIZE 1
42
43#define CRC_MAX_DMA_DESC 100
44
45#define CRC_CRYPTO_STATE_UPDATE 1
46#define CRC_CRYPTO_STATE_FINALUPDATE 2
47#define CRC_CRYPTO_STATE_FINISH 3
48
49struct bfin_crypto_crc {
50 struct list_head list;
51 struct device *dev;
52 spinlock_t lock;
53
54 int irq;
55 int dma_ch;
56 u32 poly;
57 volatile struct crc_register *regs;
58
59 struct ahash_request *req; /* current request in operation */
60 struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */
61 dma_addr_t sg_dma; /* phy addr of sg dma descriptors */
62 u8 *sg_mid_buf;
63
64 struct tasklet_struct done_task;
65 struct crypto_queue queue; /* waiting requests */
66
67 u8 busy:1; /* crc device in operation flag */
68};
69
70static struct bfin_crypto_crc_list {
71 struct list_head dev_list;
72 spinlock_t lock;
73} crc_list;
74
75struct bfin_crypto_crc_reqctx {
76 struct bfin_crypto_crc *crc;
77
78 unsigned int total; /* total request bytes */
79 size_t sg_buflen; /* bytes for this update */
80 unsigned int sg_nents;
81 struct scatterlist *sg; /* sg list head for this update*/
82 struct scatterlist bufsl[2]; /* chained sg list */
83
84 size_t bufnext_len;
85 size_t buflast_len;
86 u8 bufnext[CHKSUM_DIGEST_SIZE]; /* extra bytes for next udpate */
87 u8 buflast[CHKSUM_DIGEST_SIZE]; /* extra bytes from last udpate */
88
89 u8 flag;
90};
91
92struct bfin_crypto_crc_ctx {
93 struct bfin_crypto_crc *crc;
94 u32 key;
95};
96
97
98/*
99 * derive number of elements in scatterlist
100 */
101static int sg_count(struct scatterlist *sg_list)
102{
103 struct scatterlist *sg = sg_list;
104 int sg_nents = 1;
105
106 if (sg_list == NULL)
107 return 0;
108
109 while (!sg_is_last(sg)) {
110 sg_nents++;
111 sg = scatterwalk_sg_next(sg);
112 }
113
114 return sg_nents;
115}
116
117/*
118 * get element in scatter list by given index
119 */
120static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nents,
121 unsigned int index)
122{
123 struct scatterlist *sg = NULL;
124 int i;
125
126 for_each_sg(sg_list, sg, nents, i)
127 if (i == index)
128 break;
129
130 return sg;
131}
132
133static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key)
134{
135 crc->regs->datacntrld = 0;
136 crc->regs->control = MODE_CALC_CRC << OPMODE_OFFSET;
137 crc->regs->curresult = key;
138
139 /* setup CRC interrupts */
140 crc->regs->status = CMPERRI | DCNTEXPI;
141 crc->regs->intrenset = CMPERRI | DCNTEXPI;
142
143 return 0;
144}
145
146static int bfin_crypto_crc_init(struct ahash_request *req)
147{
148 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
149 struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
150 struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
151 struct bfin_crypto_crc *crc;
152
153 dev_dbg(ctx->crc->dev, "crc_init\n");
154 spin_lock_bh(&crc_list.lock);
155 list_for_each_entry(crc, &crc_list.dev_list, list) {
156 crc_ctx->crc = crc;
157 break;
158 }
159 spin_unlock_bh(&crc_list.lock);
160
161 if (sg_count(req->src) > CRC_MAX_DMA_DESC) {
162 dev_dbg(ctx->crc->dev, "init: requested sg list is too big > %d\n",
163 CRC_MAX_DMA_DESC);
164 return -EINVAL;
165 }
166
167 ctx->crc = crc;
168 ctx->bufnext_len = 0;
169 ctx->buflast_len = 0;
170 ctx->sg_buflen = 0;
171 ctx->total = 0;
172 ctx->flag = 0;
173
174 /* init crc results */
175 put_unaligned_le32(crc_ctx->key, req->result);
176
177 dev_dbg(ctx->crc->dev, "init: digest size: %d\n",
178 crypto_ahash_digestsize(tfm));
179
180 return bfin_crypto_crc_init_hw(crc, crc_ctx->key);
181}
182
183static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
184{
185 struct scatterlist *sg;
186 struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(crc->req);
187 int i = 0, j = 0;
188 unsigned long dma_config;
189 unsigned int dma_count;
190 unsigned int dma_addr;
191 unsigned int mid_dma_count = 0;
192 int dma_mod;
193
194 dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE);
195
196 for_each_sg(ctx->sg, sg, ctx->sg_nents, j) {
197 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32;
198 dma_addr = sg_dma_address(sg);
199 /* deduce extra bytes in last sg */
200 if (sg_is_last(sg))
201 dma_count = sg_dma_len(sg) - ctx->bufnext_len;
202 else
203 dma_count = sg_dma_len(sg);
204
205 if (mid_dma_count) {
206 /* Append last middle dma buffer to 4 bytes with first
207 bytes in current sg buffer. Move addr of current
208 sg and deduce the length of current sg.
209 */
210 memcpy(crc->sg_mid_buf +((i-1) << 2) + mid_dma_count,
211 (void *)dma_addr,
212 CHKSUM_DIGEST_SIZE - mid_dma_count);
213 dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count;
214 dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count;
215 }
216 /* chop current sg dma len to multiple of 32 bits */
217 mid_dma_count = dma_count % 4;
218 dma_count &= ~0x3;
219
220 if (dma_addr % 4 == 0) {
221 dma_config |= WDSIZE_32;
222 dma_count >>= 2;
223 dma_mod = 4;
224 } else if (dma_addr % 2 == 0) {
225 dma_config |= WDSIZE_16;
226 dma_count >>= 1;
227 dma_mod = 2;
228 } else {
229 dma_config |= WDSIZE_8;
230 dma_mod = 1;
231 }
232
233 crc->sg_cpu[i].start_addr = dma_addr;
234 crc->sg_cpu[i].cfg = dma_config;
235 crc->sg_cpu[i].x_count = dma_count;
236 crc->sg_cpu[i].x_modify = dma_mod;
237 dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
238 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
239 i, crc->sg_cpu[i].start_addr,
240 crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
241 crc->sg_cpu[i].x_modify);
242 i++;
243
244 if (mid_dma_count) {
245 /* copy extra bytes to next middle dma buffer */
246 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 |
247 DMAEN | PSIZE_32 | WDSIZE_32;
248 memcpy(crc->sg_mid_buf + (i << 2),
249 (void *)(dma_addr + (dma_count << 2)),
250 mid_dma_count);
251 /* setup new dma descriptor for next middle dma */
252 crc->sg_cpu[i].start_addr = dma_map_single(crc->dev,
253 crc->sg_mid_buf + (i << 2),
254 CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
255 crc->sg_cpu[i].cfg = dma_config;
256 crc->sg_cpu[i].x_count = 1;
257 crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
258 dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
259 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
260 i, crc->sg_cpu[i].start_addr,
261 crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
262 crc->sg_cpu[i].x_modify);
263 i++;
264 }
265 }
266
267 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32 | WDSIZE_32;
268 /* For final update req, append the buffer for next update as well*/
269 if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
270 ctx->flag == CRC_CRYPTO_STATE_FINISH)) {
271 crc->sg_cpu[i].start_addr = dma_map_single(crc->dev, ctx->bufnext,
272 CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
273 crc->sg_cpu[i].cfg = dma_config;
274 crc->sg_cpu[i].x_count = 1;
275 crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
276 dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
277 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
278 i, crc->sg_cpu[i].start_addr,
279 crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
280 crc->sg_cpu[i].x_modify);
281 i++;
282 }
283
284 if (i == 0)
285 return;
286
287 /* Set the last descriptor to stop mode */
288 crc->sg_cpu[i - 1].cfg &= ~(DMAFLOW | NDSIZE);
289 crc->sg_cpu[i - 1].cfg |= DI_EN;
290 set_dma_curr_desc_addr(crc->dma_ch, (unsigned long *)crc->sg_dma);
291 set_dma_x_count(crc->dma_ch, 0);
292 set_dma_x_modify(crc->dma_ch, 0);
293 set_dma_config(crc->dma_ch, dma_config);
294}
295
296static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc,
297 struct ahash_request *req)
298{
299 struct crypto_async_request *async_req, *backlog;
300 struct bfin_crypto_crc_reqctx *ctx;
301 struct scatterlist *sg;
302 int ret = 0;
303 int nsg, i, j;
304 unsigned int nextlen;
305 unsigned long flags;
306
307 spin_lock_irqsave(&crc->lock, flags);
308 if (req)
309 ret = ahash_enqueue_request(&crc->queue, req);
310 if (crc->busy) {
311 spin_unlock_irqrestore(&crc->lock, flags);
312 return ret;
313 }
314 backlog = crypto_get_backlog(&crc->queue);
315 async_req = crypto_dequeue_request(&crc->queue);
316 if (async_req)
317 crc->busy = 1;
318 spin_unlock_irqrestore(&crc->lock, flags);
319
320 if (!async_req)
321 return ret;
322
323 if (backlog)
324 backlog->complete(backlog, -EINPROGRESS);
325
326 req = ahash_request_cast(async_req);
327 crc->req = req;
328 ctx = ahash_request_ctx(req);
329 ctx->sg = NULL;
330 ctx->sg_buflen = 0;
331 ctx->sg_nents = 0;
332
333 dev_dbg(crc->dev, "handling new req, flag=%u, nbytes: %d\n",
334 ctx->flag, req->nbytes);
335
336 if (ctx->flag == CRC_CRYPTO_STATE_FINISH) {
337 if (ctx->bufnext_len == 0) {
338 crc->busy = 0;
339 return 0;
340 }
341
342 /* Pack last crc update buffer to 32bit */
343 memset(ctx->bufnext + ctx->bufnext_len, 0,
344 CHKSUM_DIGEST_SIZE - ctx->bufnext_len);
345 } else {
346 /* Pack small data which is less than 32bit to buffer for next update. */
347 if (ctx->bufnext_len + req->nbytes < CHKSUM_DIGEST_SIZE) {
348 memcpy(ctx->bufnext + ctx->bufnext_len,
349 sg_virt(req->src), req->nbytes);
350 ctx->bufnext_len += req->nbytes;
351 if (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE &&
352 ctx->bufnext_len) {
353 goto finish_update;
354 } else {
355 crc->busy = 0;
356 return 0;
357 }
358 }
359
360 if (ctx->bufnext_len) {
361 /* Chain in extra bytes of last update */
362 ctx->buflast_len = ctx->bufnext_len;
363 memcpy(ctx->buflast, ctx->bufnext, ctx->buflast_len);
364
365 nsg = ctx->sg_buflen ? 2 : 1;
366 sg_init_table(ctx->bufsl, nsg);
367 sg_set_buf(ctx->bufsl, ctx->buflast, ctx->buflast_len);
368 if (nsg > 1)
369 scatterwalk_sg_chain(ctx->bufsl, nsg,
370 req->src);
371 ctx->sg = ctx->bufsl;
372 } else
373 ctx->sg = req->src;
374
375 /* Chop crc buffer size to multiple of 32 bit */
376 nsg = ctx->sg_nents = sg_count(ctx->sg);
377 ctx->sg_buflen = ctx->buflast_len + req->nbytes;
378 ctx->bufnext_len = ctx->sg_buflen % 4;
379 ctx->sg_buflen &= ~0x3;
380
381 if (ctx->bufnext_len) {
382 /* copy extra bytes to buffer for next update */
383 memset(ctx->bufnext, 0, CHKSUM_DIGEST_SIZE);
384 nextlen = ctx->bufnext_len;
385 for (i = nsg - 1; i >= 0; i--) {
386 sg = sg_get(ctx->sg, nsg, i);
387 j = min(nextlen, sg_dma_len(sg));
388 memcpy(ctx->bufnext + nextlen - j,
389 sg_virt(sg) + sg_dma_len(sg) - j, j);
390 if (j == sg_dma_len(sg))
391 ctx->sg_nents--;
392 nextlen -= j;
393 if (nextlen == 0)
394 break;
395 }
396 }
397 }
398
399finish_update:
400 if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
401 ctx->flag == CRC_CRYPTO_STATE_FINISH))
402 ctx->sg_buflen += CHKSUM_DIGEST_SIZE;
403
404 /* set CRC data count before start DMA */
405 crc->regs->datacnt = ctx->sg_buflen >> 2;
406
407 /* setup and enable CRC DMA */
408 bfin_crypto_crc_config_dma(crc);
409
410 /* finally kick off CRC operation */
411 crc->regs->control |= BLKEN;
412
413 return -EINPROGRESS;
414}
415
416static int bfin_crypto_crc_update(struct ahash_request *req)
417{
418 struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
419
420 if (!req->nbytes)
421 return 0;
422
423 dev_dbg(ctx->crc->dev, "crc_update\n");
424 ctx->total += req->nbytes;
425 ctx->flag = CRC_CRYPTO_STATE_UPDATE;
426
427 return bfin_crypto_crc_handle_queue(ctx->crc, req);
428}
429
430static int bfin_crypto_crc_final(struct ahash_request *req)
431{
432 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
433 struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
434 struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
435
436 dev_dbg(ctx->crc->dev, "crc_final\n");
437 ctx->flag = CRC_CRYPTO_STATE_FINISH;
438 crc_ctx->key = 0;
439
440 return bfin_crypto_crc_handle_queue(ctx->crc, req);
441}
442
443static int bfin_crypto_crc_finup(struct ahash_request *req)
444{
445 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
446 struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
447 struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
448
449 dev_dbg(ctx->crc->dev, "crc_finishupdate\n");
450 ctx->total += req->nbytes;
451 ctx->flag = CRC_CRYPTO_STATE_FINALUPDATE;
452 crc_ctx->key = 0;
453
454 return bfin_crypto_crc_handle_queue(ctx->crc, req);
455}
456
457static int bfin_crypto_crc_digest(struct ahash_request *req)
458{
459 int ret;
460
461 ret = bfin_crypto_crc_init(req);
462 if (ret)
463 return ret;
464
465 return bfin_crypto_crc_finup(req);
466}
467
468static int bfin_crypto_crc_setkey(struct crypto_ahash *tfm, const u8 *key,
469 unsigned int keylen)
470{
471 struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
472
473 dev_dbg(crc_ctx->crc->dev, "crc_setkey\n");
474 if (keylen != CHKSUM_DIGEST_SIZE) {
475 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
476 return -EINVAL;
477 }
478
479 crc_ctx->key = get_unaligned_le32(key);
480
481 return 0;
482}
483
484static int bfin_crypto_crc_cra_init(struct crypto_tfm *tfm)
485{
486 struct bfin_crypto_crc_ctx *crc_ctx = crypto_tfm_ctx(tfm);
487
488 crc_ctx->key = 0;
489 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
490 sizeof(struct bfin_crypto_crc_reqctx));
491
492 return 0;
493}
494
495static void bfin_crypto_crc_cra_exit(struct crypto_tfm *tfm)
496{
497}
498
499static struct ahash_alg algs = {
500 .init = bfin_crypto_crc_init,
501 .update = bfin_crypto_crc_update,
502 .final = bfin_crypto_crc_final,
503 .finup = bfin_crypto_crc_finup,
504 .digest = bfin_crypto_crc_digest,
505 .setkey = bfin_crypto_crc_setkey,
506 .halg.digestsize = CHKSUM_DIGEST_SIZE,
507 .halg.base = {
508 .cra_name = "hmac(crc32)",
509 .cra_driver_name = DRIVER_NAME,
510 .cra_priority = 100,
511 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
512 CRYPTO_ALG_ASYNC,
513 .cra_blocksize = CHKSUM_BLOCK_SIZE,
514 .cra_ctxsize = sizeof(struct bfin_crypto_crc_ctx),
515 .cra_alignmask = 3,
516 .cra_module = THIS_MODULE,
517 .cra_init = bfin_crypto_crc_cra_init,
518 .cra_exit = bfin_crypto_crc_cra_exit,
519 }
520};
521
522static void bfin_crypto_crc_done_task(unsigned long data)
523{
524 struct bfin_crypto_crc *crc = (struct bfin_crypto_crc *)data;
525
526 bfin_crypto_crc_handle_queue(crc, NULL);
527}
528
529static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id)
530{
531 struct bfin_crypto_crc *crc = dev_id;
532
533 if (crc->regs->status & DCNTEXP) {
534 crc->regs->status = DCNTEXP;
535
536 /* prepare results */
537 put_unaligned_le32(crc->regs->result, crc->req->result);
538
539 crc->regs->control &= ~BLKEN;
540 crc->busy = 0;
541
542 if (crc->req->base.complete)
543 crc->req->base.complete(&crc->req->base, 0);
544
545 tasklet_schedule(&crc->done_task);
546
547 return IRQ_HANDLED;
548 } else
549 return IRQ_NONE;
550}
551
552#ifdef CONFIG_PM
553/**
554 * bfin_crypto_crc_suspend - suspend crc device
555 * @pdev: device being suspended
556 * @state: requested suspend state
557 */
558static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t state)
559{
560 struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
561 int i = 100000;
562
563 while ((crc->regs->control & BLKEN) && --i)
564 cpu_relax();
565
566 if (i == 0)
567 return -EBUSY;
568
569 return 0;
570}
571#else
572# define bfin_crypto_crc_suspend NULL
573#endif
574
575#define bfin_crypto_crc_resume NULL
576
577/**
578 * bfin_crypto_crc_probe - Initialize module
579 *
580 */
581static int bfin_crypto_crc_probe(struct platform_device *pdev)
582{
583 struct device *dev = &pdev->dev;
584 struct resource *res;
585 struct bfin_crypto_crc *crc;
586 unsigned int timeout = 100000;
587 int ret;
588
589 crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
590 if (!crc) {
591 dev_err(&pdev->dev, "fail to malloc bfin_crypto_crc\n");
592 return -ENOMEM;
593 }
594
595 crc->dev = dev;
596
597 INIT_LIST_HEAD(&crc->list);
598 spin_lock_init(&crc->lock);
599 tasklet_init(&crc->done_task, bfin_crypto_crc_done_task, (unsigned long)crc);
600 crypto_init_queue(&crc->queue, CRC_CCRYPTO_QUEUE_LENGTH);
601
602 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
603 if (res == NULL) {
604 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
605 return -ENOENT;
606 }
607
608 crc->regs = devm_ioremap_resource(dev, res);
609 if (IS_ERR((void *)crc->regs)) {
610 dev_err(&pdev->dev, "Cannot map CRC IO\n");
611 return PTR_ERR((void *)crc->regs);
612 }
613
614 crc->irq = platform_get_irq(pdev, 0);
615 if (crc->irq < 0) {
616 dev_err(&pdev->dev, "No CRC DCNTEXP IRQ specified\n");
617 return -ENOENT;
618 }
619
620 ret = devm_request_irq(dev, crc->irq, bfin_crypto_crc_handler,
621 IRQF_SHARED, dev_name(dev), crc);
622 if (ret) {
623 dev_err(&pdev->dev, "Unable to request blackfin crc irq\n");
624 return ret;
625 }
626
627 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
628 if (res == NULL) {
629 dev_err(&pdev->dev, "No CRC DMA channel specified\n");
630 return -ENOENT;
631 }
632 crc->dma_ch = res->start;
633
634 ret = request_dma(crc->dma_ch, dev_name(dev));
635 if (ret) {
636 dev_err(&pdev->dev, "Unable to attach Blackfin CRC DMA channel\n");
637 return ret;
638 }
639
640 crc->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &crc->sg_dma, GFP_KERNEL);
641 if (crc->sg_cpu == NULL) {
642 ret = -ENOMEM;
643 goto out_error_dma;
644 }
645 /*
646 * need at most CRC_MAX_DMA_DESC sg + CRC_MAX_DMA_DESC middle +
647 * 1 last + 1 next dma descriptors
648 */
649 crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1));
650
651 crc->regs->control = 0;
652 crc->regs->poly = crc->poly = (u32)pdev->dev.platform_data;
653
654 while (!(crc->regs->status & LUTDONE) && (--timeout) > 0)
655 cpu_relax();
656
657 if (timeout == 0)
658 dev_info(&pdev->dev, "init crc poly timeout\n");
659
660 spin_lock(&crc_list.lock);
661 list_add(&crc->list, &crc_list.dev_list);
662 spin_unlock(&crc_list.lock);
663
664 platform_set_drvdata(pdev, crc);
665
666 ret = crypto_register_ahash(&algs);
667 if (ret) {
668 spin_lock(&crc_list.lock);
669 list_del(&crc->list);
670 spin_unlock(&crc_list.lock);
671 dev_err(&pdev->dev, "Cann't register crypto ahash device\n");
672 goto out_error_dma;
673 }
674
675 dev_info(&pdev->dev, "initialized\n");
676
677 return 0;
678
679out_error_dma:
680 if (crc->sg_cpu)
681 dma_free_coherent(&pdev->dev, PAGE_SIZE, crc->sg_cpu, crc->sg_dma);
682 free_dma(crc->dma_ch);
683
684 return ret;
685}
686
687/**
688 * bfin_crypto_crc_remove - Initialize module
689 *
690 */
691static int bfin_crypto_crc_remove(struct platform_device *pdev)
692{
693 struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
694
695 if (!crc)
696 return -ENODEV;
697
698 spin_lock(&crc_list.lock);
699 list_del(&crc->list);
700 spin_unlock(&crc_list.lock);
701
702 crypto_unregister_ahash(&algs);
703 tasklet_kill(&crc->done_task);
704 free_dma(crc->dma_ch);
705
706 return 0;
707}
708
709static struct platform_driver bfin_crypto_crc_driver = {
710 .probe = bfin_crypto_crc_probe,
711 .remove = bfin_crypto_crc_remove,
712 .suspend = bfin_crypto_crc_suspend,
713 .resume = bfin_crypto_crc_resume,
714 .driver = {
715 .name = DRIVER_NAME,
716 .owner = THIS_MODULE,
717 },
718};
719
720/**
721 * bfin_crypto_crc_mod_init - Initialize module
722 *
723 * Checks the module params and registers the platform driver.
724 * Real work is in the platform probe function.
725 */
726static int __init bfin_crypto_crc_mod_init(void)
727{
728 int ret;
729
730 pr_info("Blackfin hardware CRC crypto driver\n");
731
732 INIT_LIST_HEAD(&crc_list.dev_list);
733 spin_lock_init(&crc_list.lock);
734
735 ret = platform_driver_register(&bfin_crypto_crc_driver);
736 if (ret) {
737 pr_info(KERN_ERR "unable to register driver\n");
738 return ret;
739 }
740
741 return 0;
742}
743
744/**
745 * bfin_crypto_crc_mod_exit - Deinitialize module
746 */
747static void __exit bfin_crypto_crc_mod_exit(void)
748{
749 platform_driver_unregister(&bfin_crypto_crc_driver);
750}
751
752module_init(bfin_crypto_crc_mod_init);
753module_exit(bfin_crypto_crc_mod_exit);
754
755MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
756MODULE_DESCRIPTION("Blackfin CRC hardware crypto driver");
757MODULE_LICENSE("GPL");