1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * 64-bit Periodic Interval Timer driver
  4 *
  5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
  6 *
  7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/clockchips.h>
 12#include <linux/interrupt.h>
 13#include <linux/of_address.h>
 14#include <linux/of_irq.h>
 15#include <linux/sched_clock.h>
 16#include <linux/slab.h>
 17
 18#define MCHP_PIT64B_CR			0x00	/* Control Register */
 19#define MCHP_PIT64B_CR_START		BIT(0)
 20#define MCHP_PIT64B_CR_SWRST		BIT(8)
 21
 22#define MCHP_PIT64B_MR			0x04	/* Mode Register */
 23#define MCHP_PIT64B_MR_CONT		BIT(0)
 24#define MCHP_PIT64B_MR_ONE_SHOT		(0)
 25#define MCHP_PIT64B_MR_SGCLK		BIT(3)
 26#define MCHP_PIT64B_MR_PRES		GENMASK(11, 8)
 27
 28#define MCHP_PIT64B_LSB_PR		0x08	/* LSB Period Register */
 29
 30#define MCHP_PIT64B_MSB_PR		0x0C	/* MSB Period Register */
 31
 32#define MCHP_PIT64B_IER			0x10	/* Interrupt Enable Register */
 33#define MCHP_PIT64B_IER_PERIOD		BIT(0)
 34
 35#define MCHP_PIT64B_ISR			0x1C	/* Interrupt Status Register */
 36
 37#define MCHP_PIT64B_TLSBR		0x20	/* Timer LSB Register */
 38
 39#define MCHP_PIT64B_TMSBR		0x24	/* Timer MSB Register */
 40
 41#define MCHP_PIT64B_PRES_MAX		0x10
 42#define MCHP_PIT64B_LSBMASK		GENMASK_ULL(31, 0)
 43#define MCHP_PIT64B_PRES_TO_MODE(p)	(MCHP_PIT64B_MR_PRES & ((p) << 8))
 44#define MCHP_PIT64B_MODE_TO_PRES(m)	((MCHP_PIT64B_MR_PRES & (m)) >> 8)
 45#define MCHP_PIT64B_DEF_CS_FREQ		5000000UL	/* 5 MHz */
 46#define MCHP_PIT64B_DEF_CE_FREQ		32768		/* 32 KHz */
 47
 48#define MCHP_PIT64B_NAME		"pit64b"
 49
 50/**
 51 * struct mchp_pit64b_timer - PIT64B timer data structure
 52 * @base: base address of PIT64B hardware block
 53 * @pclk: PIT64B's peripheral clock
 54 * @gclk: PIT64B's generic clock
 55 * @mode: precomputed value for mode register
 56 */
 57struct mchp_pit64b_timer {
 58	void __iomem	*base;
 59	struct clk	*pclk;
 60	struct clk	*gclk;
 61	u32		mode;
 62};
 63
 64/**
 65 * mchp_pit64b_clkevt - PIT64B clockevent data structure
 66 * @timer: PIT64B timer
 67 * @clkevt: clockevent
 68 */
 69struct mchp_pit64b_clkevt {
 70	struct mchp_pit64b_timer	timer;
 71	struct clock_event_device	clkevt;
 72};
 73
 74#define to_mchp_pit64b_timer(x) \
 75	((struct mchp_pit64b_timer *)container_of(x,\
 76		struct mchp_pit64b_clkevt, clkevt))
 77
 78/* Base address for clocksource timer. */
 79static void __iomem *mchp_pit64b_cs_base;
 80/* Default cycles for clockevent timer. */
 81static u64 mchp_pit64b_ce_cycles;
 82
 83static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
 84{
 85	unsigned long	flags;
 86	u32		low, high;
 87
 88	raw_local_irq_save(flags);
 89
 90	/*
 91	 * When using a 64 bit period TLSB must be read first, followed by the
 92	 * read of TMSB. This sequence generates an atomic read of the 64 bit
 93	 * timer value whatever the lapse of time between the accesses.
 94	 */
 95	low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
 96	high = readl_relaxed(base + MCHP_PIT64B_TMSBR);
 97
 98	raw_local_irq_restore(flags);
 99
100	return (((u64)high << 32) | low);
101}
102
103static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
104				     u64 cycles, u32 mode, u32 irqs)
105{
106	u32 low, high;
107
108	low = cycles & MCHP_PIT64B_LSBMASK;
109	high = cycles >> 32;
110
111	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
112	writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
113	writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
114	writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
115	writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
116	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
117}
118
119static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
120{
121	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
122}
123
124static u64 mchp_pit64b_sched_read_clk(void)
125{
126	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
127}
128
129static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
130{
131	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
132
133	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
134
135	return 0;
136}
137
138static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
139{
140	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
141
142	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
143			  MCHP_PIT64B_IER_PERIOD);
144
145	return 0;
146}
147
148static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
149					     struct clock_event_device *cedev)
150{
151	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
152
153	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
154			  MCHP_PIT64B_IER_PERIOD);
155
156	return 0;
157}
158
159static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
160{
161	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
162
163	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
164	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
165		clk_disable_unprepare(timer->gclk);
166	clk_disable_unprepare(timer->pclk);
167}
168
169static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
170{
171	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
172
173	clk_prepare_enable(timer->pclk);
174	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
175		clk_prepare_enable(timer->gclk);
176}
177
178static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
179{
180	struct mchp_pit64b_clkevt *irq_data = dev_id;
181
182	/* Need to clear the interrupt. */
183	readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
184
185	irq_data->clkevt.event_handler(&irq_data->clkevt);
186
187	return IRQ_HANDLED;
188}
189
190static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
191					    u32 max_rate)
192{
193	u32 tmp;
194
195	for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
196		tmp = clk_rate / (*pres + 1);
197		if (tmp <= max_rate)
198			break;
199	}
200
201	/* Use the bigest prescaler if we didn't match one. */
202	if (*pres == MCHP_PIT64B_PRES_MAX)
203		*pres = MCHP_PIT64B_PRES_MAX - 1;
204}
205
206/**
207 * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
208 *			   runtime; this includes prescaler and SGCLK bit
209 *
210 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
211 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
212 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
213 * divided by the internal PIT64B's divider.
214 *
215 * This function, first tries to use GCLK by requesting the desired rate from
216 * PMC and then using the internal PIT64B prescaler, if any, to reach the
217 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
218 * then the function falls back on using PCLK as clock source for PIT64B timer
219 * choosing the highest prescaler in case it doesn't locate one to match the
220 * requested frequency.
221 *
222 * Below is presented the PIT64B block in relation with PMC:
223 *
224 *                                PIT64B
225 *  PMC             +------------------------------------+
226 * +----+           |   +-----+                          |
227 * |    |-->gclk -->|-->|     |    +---------+  +-----+  |
228 * |    |           |   | MUX |--->| Divider |->|timer|  |
229 * |    |-->pclk -->|-->|     |    +---------+  +-----+  |
230 * +----+           |   +-----+                          |
231 *                  |      ^                             |
232 *                  |     sel                            |
233 *                  +------------------------------------+
234 *
235 * Where:
236 *	- gclk rate <= pclk rate/3
237 *	- gclk rate could be requested from PMC
238 *	- pclk rate is fixed (cannot be requested from PMC)
239 */
240static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
241					unsigned long max_rate)
242{
243	unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
244	long gclk_round = 0;
245	u32 pres, best_pres = 0;
246
247	pclk_rate = clk_get_rate(timer->pclk);
248	if (!pclk_rate)
249		return -EINVAL;
250
251	timer->mode = 0;
252
253	/* Try using GCLK. */
254	gclk_round = clk_round_rate(timer->gclk, max_rate);
255	if (gclk_round < 0)
256		goto pclk;
257
258	if (pclk_rate / gclk_round < 3)
259		goto pclk;
260
261	mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
262	best_diff = abs(gclk_round / (pres + 1) - max_rate);
263	best_pres = pres;
264
265	if (!best_diff) {
266		timer->mode |= MCHP_PIT64B_MR_SGCLK;
267		clk_set_rate(timer->gclk, gclk_round);
268		goto done;
269	}
270
271pclk:
272	/* Check if requested rate could be obtained using PCLK. */
273	mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
274	diff = abs(pclk_rate / (pres + 1) - max_rate);
275
276	if (best_diff > diff) {
277		/* Use PCLK. */
278		best_pres = pres;
279	} else {
280		/* Use GCLK. */
281		timer->mode |= MCHP_PIT64B_MR_SGCLK;
282		clk_set_rate(timer->gclk, gclk_round);
283	}
284
285done:
286	timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);
287
288	pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
289		timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
290		timer->mode & MCHP_PIT64B_MR_SGCLK ?
291		gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));
292
293	return 0;
294}
295
296static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
297					  u32 clk_rate)
298{
299	int ret;
300
301	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
302
303	mchp_pit64b_cs_base = timer->base;
304
305	ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
306				    210, 64, mchp_pit64b_clksrc_read);
307	if (ret) {
308		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
309
310		/* Stop timer. */
311		writel_relaxed(MCHP_PIT64B_CR_SWRST,
312			       timer->base + MCHP_PIT64B_CR);
313
314		return ret;
315	}
316
317	sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
318
319	return 0;
320}
321
322static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
323					  u32 clk_rate, u32 irq)
324{
325	struct mchp_pit64b_clkevt *ce;
326	int ret;
327
328	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
329	if (!ce)
330		return -ENOMEM;
331
332	mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
333
334	ce->timer.base = timer->base;
335	ce->timer.pclk = timer->pclk;
336	ce->timer.gclk = timer->gclk;
337	ce->timer.mode = timer->mode;
338	ce->clkevt.name = MCHP_PIT64B_NAME;
339	ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
340	ce->clkevt.rating = 150;
341	ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
342	ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
343	ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
344	ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
345	ce->clkevt.resume = mchp_pit64b_clkevt_resume;
346	ce->clkevt.cpumask = cpumask_of(0);
347	ce->clkevt.irq = irq;
348
349	ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
350			  "pit64b_tick", ce);
351	if (ret) {
352		pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
353		kfree(ce);
354		return ret;
355	}
356
357	clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
358
359	return 0;
360}
361
362static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
363					    bool clkevt)
364{
365	u32 freq = clkevt ? MCHP_PIT64B_DEF_CE_FREQ : MCHP_PIT64B_DEF_CS_FREQ;
366	struct mchp_pit64b_timer timer;
367	unsigned long clk_rate;
368	u32 irq = 0;
369	int ret;
370
371	/* Parse DT node. */
372	timer.pclk = of_clk_get_by_name(node, "pclk");
373	if (IS_ERR(timer.pclk))
374		return PTR_ERR(timer.pclk);
375
376	timer.gclk = of_clk_get_by_name(node, "gclk");
377	if (IS_ERR(timer.gclk))
378		return PTR_ERR(timer.gclk);
379
380	timer.base = of_iomap(node, 0);
381	if (!timer.base)
382		return -ENXIO;
383
384	if (clkevt) {
385		irq = irq_of_parse_and_map(node, 0);
386		if (!irq) {
387			ret = -ENODEV;
388			goto io_unmap;
389		}
390	}
391
392	/* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
393	ret = mchp_pit64b_init_mode(&timer, freq);
394	if (ret)
395		goto irq_unmap;
396
397	ret = clk_prepare_enable(timer.pclk);
398	if (ret)
399		goto irq_unmap;
400
401	if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
402		ret = clk_prepare_enable(timer.gclk);
403		if (ret)
404			goto pclk_unprepare;
405
406		clk_rate = clk_get_rate(timer.gclk);
407	} else {
408		clk_rate = clk_get_rate(timer.pclk);
409	}
410	clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
411
412	if (clkevt)
413		ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
414	else
415		ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
416
417	if (ret)
418		goto gclk_unprepare;
419
420	return 0;
421
422gclk_unprepare:
423	if (timer.mode & MCHP_PIT64B_MR_SGCLK)
424		clk_disable_unprepare(timer.gclk);
425pclk_unprepare:
426	clk_disable_unprepare(timer.pclk);
427irq_unmap:
428	irq_dispose_mapping(irq);
429io_unmap:
430	iounmap(timer.base);
431
432	return ret;
433}
434
435static int __init mchp_pit64b_dt_init(struct device_node *node)
436{
437	static int inits;
438
439	switch (inits++) {
440	case 0:
441		/* 1st request, register clockevent. */
442		return mchp_pit64b_dt_init_timer(node, true);
443	case 1:
444		/* 2nd request, register clocksource. */
445		return mchp_pit64b_dt_init_timer(node, false);
446	}
447
448	/* The rest, don't care. */
449	return -EINVAL;
450}
451
452TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);