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1/*
2 * MicroWire interface driver for OMAP
3 *
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
5 *
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
8 *
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
10 *
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
13 *
14 * Many updates by Imre Deak <imre.deak@nokia.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32#include <linux/kernel.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/platform_device.h>
36#include <linux/interrupt.h>
37#include <linux/err.h>
38#include <linux/clk.h>
39#include <linux/slab.h>
40#include <linux/device.h>
41
42#include <linux/spi/spi.h>
43#include <linux/spi/spi_bitbang.h>
44#include <linux/module.h>
45#include <linux/io.h>
46
47#include <mach/hardware.h>
48#include <asm/mach-types.h>
49
50#include <mach/mux.h>
51
52#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
53
54
55/* FIXME address is now a platform device resource,
56 * and irqs should show there too...
57 */
58#define UWIRE_BASE_PHYS 0xFFFB3000
59
60/* uWire Registers: */
61#define UWIRE_IO_SIZE 0x20
62#define UWIRE_TDR 0x00
63#define UWIRE_RDR 0x00
64#define UWIRE_CSR 0x01
65#define UWIRE_SR1 0x02
66#define UWIRE_SR2 0x03
67#define UWIRE_SR3 0x04
68#define UWIRE_SR4 0x05
69#define UWIRE_SR5 0x06
70
71/* CSR bits */
72#define RDRB (1 << 15)
73#define CSRB (1 << 14)
74#define START (1 << 13)
75#define CS_CMD (1 << 12)
76
77/* SR1 or SR2 bits */
78#define UWIRE_READ_FALLING_EDGE 0x0001
79#define UWIRE_READ_RISING_EDGE 0x0000
80#define UWIRE_WRITE_FALLING_EDGE 0x0000
81#define UWIRE_WRITE_RISING_EDGE 0x0002
82#define UWIRE_CS_ACTIVE_LOW 0x0000
83#define UWIRE_CS_ACTIVE_HIGH 0x0004
84#define UWIRE_FREQ_DIV_2 0x0000
85#define UWIRE_FREQ_DIV_4 0x0008
86#define UWIRE_FREQ_DIV_8 0x0010
87#define UWIRE_CHK_READY 0x0020
88#define UWIRE_CLK_INVERTED 0x0040
89
90
91struct uwire_spi {
92 struct spi_bitbang bitbang;
93 struct clk *ck;
94};
95
96struct uwire_state {
97 unsigned div1_idx;
98};
99
100/* REVISIT compile time constant for idx_shift? */
101/*
102 * Or, put it in a structure which is used throughout the driver;
103 * that avoids having to issue two loads for each bit of static data.
104 */
105static unsigned int uwire_idx_shift;
106static void __iomem *uwire_base;
107
108static inline void uwire_write_reg(int idx, u16 val)
109{
110 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
111}
112
113static inline u16 uwire_read_reg(int idx)
114{
115 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
116}
117
118static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
119{
120 u16 w, val = 0;
121 int shift, reg;
122
123 if (flags & UWIRE_CLK_INVERTED)
124 val ^= 0x03;
125 val = flags & 0x3f;
126 if (cs & 1)
127 shift = 6;
128 else
129 shift = 0;
130 if (cs <= 1)
131 reg = UWIRE_SR1;
132 else
133 reg = UWIRE_SR2;
134
135 w = uwire_read_reg(reg);
136 w &= ~(0x3f << shift);
137 w |= val << shift;
138 uwire_write_reg(reg, w);
139}
140
141static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
142{
143 u16 w;
144 int c = 0;
145 unsigned long max_jiffies = jiffies + HZ;
146
147 for (;;) {
148 w = uwire_read_reg(UWIRE_CSR);
149 if ((w & mask) == val)
150 break;
151 if (time_after(jiffies, max_jiffies)) {
152 printk(KERN_ERR "%s: timeout. reg=%#06x "
153 "mask=%#06x val=%#06x\n",
154 __func__, w, mask, val);
155 return -1;
156 }
157 c++;
158 if (might_not_catch && c > 64)
159 break;
160 }
161 return 0;
162}
163
164static void uwire_set_clk1_div(int div1_idx)
165{
166 u16 w;
167
168 w = uwire_read_reg(UWIRE_SR3);
169 w &= ~(0x03 << 1);
170 w |= div1_idx << 1;
171 uwire_write_reg(UWIRE_SR3, w);
172}
173
174static void uwire_chipselect(struct spi_device *spi, int value)
175{
176 struct uwire_state *ust = spi->controller_state;
177 u16 w;
178 int old_cs;
179
180
181 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
182
183 w = uwire_read_reg(UWIRE_CSR);
184 old_cs = (w >> 10) & 0x03;
185 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
186 /* Deselect this CS, or the previous CS */
187 w &= ~CS_CMD;
188 uwire_write_reg(UWIRE_CSR, w);
189 }
190 /* activate specfied chipselect */
191 if (value == BITBANG_CS_ACTIVE) {
192 uwire_set_clk1_div(ust->div1_idx);
193 /* invert clock? */
194 if (spi->mode & SPI_CPOL)
195 uwire_write_reg(UWIRE_SR4, 1);
196 else
197 uwire_write_reg(UWIRE_SR4, 0);
198
199 w = spi->chip_select << 10;
200 w |= CS_CMD;
201 uwire_write_reg(UWIRE_CSR, w);
202 }
203}
204
205static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
206{
207 unsigned len = t->len;
208 unsigned bits = t->bits_per_word;
209 unsigned bytes;
210 u16 val, w;
211 int status = 0;
212
213 if (!t->tx_buf && !t->rx_buf)
214 return 0;
215
216 w = spi->chip_select << 10;
217 w |= CS_CMD;
218
219 if (t->tx_buf) {
220 const u8 *buf = t->tx_buf;
221
222 /* NOTE: DMA could be used for TX transfers */
223
224 /* write one or two bytes at a time */
225 while (len >= 1) {
226 /* tx bit 15 is first sent; we byteswap multibyte words
227 * (msb-first) on the way out from memory.
228 */
229 val = *buf++;
230 if (bits > 8) {
231 bytes = 2;
232 val |= *buf++ << 8;
233 } else
234 bytes = 1;
235 val <<= 16 - bits;
236
237#ifdef VERBOSE
238 pr_debug("%s: write-%d =%04x\n",
239 dev_name(&spi->dev), bits, val);
240#endif
241 if (wait_uwire_csr_flag(CSRB, 0, 0))
242 goto eio;
243
244 uwire_write_reg(UWIRE_TDR, val);
245
246 /* start write */
247 val = START | w | (bits << 5);
248
249 uwire_write_reg(UWIRE_CSR, val);
250 len -= bytes;
251
252 /* Wait till write actually starts.
253 * This is needed with MPU clock 60+ MHz.
254 * REVISIT: we may not have time to catch it...
255 */
256 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
257 goto eio;
258
259 status += bytes;
260 }
261
262 /* REVISIT: save this for later to get more i/o overlap */
263 if (wait_uwire_csr_flag(CSRB, 0, 0))
264 goto eio;
265
266 } else if (t->rx_buf) {
267 u8 *buf = t->rx_buf;
268
269 /* read one or two bytes at a time */
270 while (len) {
271 if (bits > 8) {
272 bytes = 2;
273 } else
274 bytes = 1;
275
276 /* start read */
277 val = START | w | (bits << 0);
278 uwire_write_reg(UWIRE_CSR, val);
279 len -= bytes;
280
281 /* Wait till read actually starts */
282 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
283
284 if (wait_uwire_csr_flag(RDRB | CSRB,
285 RDRB, 0))
286 goto eio;
287
288 /* rx bit 0 is last received; multibyte words will
289 * be properly byteswapped on the way to memory.
290 */
291 val = uwire_read_reg(UWIRE_RDR);
292 val &= (1 << bits) - 1;
293 *buf++ = (u8) val;
294 if (bytes == 2)
295 *buf++ = val >> 8;
296 status += bytes;
297#ifdef VERBOSE
298 pr_debug("%s: read-%d =%04x\n",
299 dev_name(&spi->dev), bits, val);
300#endif
301
302 }
303 }
304 return status;
305eio:
306 return -EIO;
307}
308
309static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
310{
311 struct uwire_state *ust = spi->controller_state;
312 struct uwire_spi *uwire;
313 unsigned flags = 0;
314 unsigned hz;
315 unsigned long rate;
316 int div1_idx;
317 int div1;
318 int div2;
319 int status;
320
321 uwire = spi_master_get_devdata(spi->master);
322
323 /* mode 0..3, clock inverted separately;
324 * standard nCS signaling;
325 * don't treat DI=high as "not ready"
326 */
327 if (spi->mode & SPI_CS_HIGH)
328 flags |= UWIRE_CS_ACTIVE_HIGH;
329
330 if (spi->mode & SPI_CPOL)
331 flags |= UWIRE_CLK_INVERTED;
332
333 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
334 case SPI_MODE_0:
335 case SPI_MODE_3:
336 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
337 break;
338 case SPI_MODE_1:
339 case SPI_MODE_2:
340 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
341 break;
342 }
343
344 /* assume it's already enabled */
345 rate = clk_get_rate(uwire->ck);
346
347 if (t != NULL)
348 hz = t->speed_hz;
349 else
350 hz = spi->max_speed_hz;
351
352 if (!hz) {
353 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
354 status = -EINVAL;
355 goto done;
356 }
357
358 /* F_INT = mpu_xor_clk / DIV1 */
359 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
360 switch (div1_idx) {
361 case 0:
362 div1 = 2;
363 break;
364 case 1:
365 div1 = 4;
366 break;
367 case 2:
368 div1 = 7;
369 break;
370 default:
371 case 3:
372 div1 = 10;
373 break;
374 }
375 div2 = (rate / div1 + hz - 1) / hz;
376 if (div2 <= 8)
377 break;
378 }
379 if (div1_idx == 4) {
380 pr_debug("%s: lowest clock %ld, need %d\n",
381 dev_name(&spi->dev), rate / 10 / 8, hz);
382 status = -EDOM;
383 goto done;
384 }
385
386 /* we have to cache this and reset in uwire_chipselect as this is a
387 * global parameter and another uwire device can change it under
388 * us */
389 ust->div1_idx = div1_idx;
390 uwire_set_clk1_div(div1_idx);
391
392 rate /= div1;
393
394 switch (div2) {
395 case 0:
396 case 1:
397 case 2:
398 flags |= UWIRE_FREQ_DIV_2;
399 rate /= 2;
400 break;
401 case 3:
402 case 4:
403 flags |= UWIRE_FREQ_DIV_4;
404 rate /= 4;
405 break;
406 case 5:
407 case 6:
408 case 7:
409 case 8:
410 flags |= UWIRE_FREQ_DIV_8;
411 rate /= 8;
412 break;
413 }
414 omap_uwire_configure_mode(spi->chip_select, flags);
415 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
416 __func__, flags,
417 clk_get_rate(uwire->ck) / 1000,
418 rate / 1000);
419 status = 0;
420done:
421 return status;
422}
423
424static int uwire_setup(struct spi_device *spi)
425{
426 struct uwire_state *ust = spi->controller_state;
427
428 if (ust == NULL) {
429 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
430 if (ust == NULL)
431 return -ENOMEM;
432 spi->controller_state = ust;
433 }
434
435 return uwire_setup_transfer(spi, NULL);
436}
437
438static void uwire_cleanup(struct spi_device *spi)
439{
440 kfree(spi->controller_state);
441}
442
443static void uwire_off(struct uwire_spi *uwire)
444{
445 uwire_write_reg(UWIRE_SR3, 0);
446 clk_disable_unprepare(uwire->ck);
447 spi_master_put(uwire->bitbang.master);
448}
449
450static int uwire_probe(struct platform_device *pdev)
451{
452 struct spi_master *master;
453 struct uwire_spi *uwire;
454 int status;
455
456 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
457 if (!master)
458 return -ENODEV;
459
460 uwire = spi_master_get_devdata(master);
461
462 uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
463 if (!uwire_base) {
464 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
465 spi_master_put(master);
466 return -ENOMEM;
467 }
468
469 platform_set_drvdata(pdev, uwire);
470
471 uwire->ck = devm_clk_get(&pdev->dev, "fck");
472 if (IS_ERR(uwire->ck)) {
473 status = PTR_ERR(uwire->ck);
474 dev_dbg(&pdev->dev, "no functional clock?\n");
475 spi_master_put(master);
476 return status;
477 }
478 clk_prepare_enable(uwire->ck);
479
480 if (cpu_is_omap7xx())
481 uwire_idx_shift = 1;
482 else
483 uwire_idx_shift = 2;
484
485 uwire_write_reg(UWIRE_SR3, 1);
486
487 /* the spi->mode bits understood by this driver: */
488 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
489 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
490 master->flags = SPI_MASTER_HALF_DUPLEX;
491
492 master->bus_num = 2; /* "official" */
493 master->num_chipselect = 4;
494 master->setup = uwire_setup;
495 master->cleanup = uwire_cleanup;
496
497 uwire->bitbang.master = master;
498 uwire->bitbang.chipselect = uwire_chipselect;
499 uwire->bitbang.setup_transfer = uwire_setup_transfer;
500 uwire->bitbang.txrx_bufs = uwire_txrx;
501
502 status = spi_bitbang_start(&uwire->bitbang);
503 if (status < 0) {
504 uwire_off(uwire);
505 }
506 return status;
507}
508
509static int uwire_remove(struct platform_device *pdev)
510{
511 struct uwire_spi *uwire = platform_get_drvdata(pdev);
512
513 // FIXME remove all child devices, somewhere ...
514
515 spi_bitbang_stop(&uwire->bitbang);
516 uwire_off(uwire);
517 return 0;
518}
519
520/* work with hotplug and coldplug */
521MODULE_ALIAS("platform:omap_uwire");
522
523static struct platform_driver uwire_driver = {
524 .driver = {
525 .name = "omap_uwire",
526 },
527 .probe = uwire_probe,
528 .remove = uwire_remove,
529 // suspend ... unuse ck
530 // resume ... use ck
531};
532
533static int __init omap_uwire_init(void)
534{
535 /* FIXME move these into the relevant board init code. also, include
536 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
537 */
538
539 if (machine_is_omap_h2()) {
540 /* defaults: W21 SDO, U18 SDI, V19 SCL */
541 omap_cfg_reg(N14_1610_UWIRE_CS0);
542 omap_cfg_reg(N15_1610_UWIRE_CS1);
543 }
544 if (machine_is_omap_perseus2()) {
545 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
546 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
547 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
548 }
549
550 return platform_driver_register(&uwire_driver);
551}
552
553static void __exit omap_uwire_exit(void)
554{
555 platform_driver_unregister(&uwire_driver);
556}
557
558subsys_initcall(omap_uwire_init);
559module_exit(omap_uwire_exit);
560
561MODULE_LICENSE("GPL");
562
1/*
2 * MicroWire interface driver for OMAP
3 *
4 * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
5 *
6 * Ported to 2.6 OMAP uwire interface.
7 * Copyright (C) 2004 Texas Instruments.
8 *
9 * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
10 *
11 * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
12 * Copyright (C) 2006 Nokia
13 *
14 * Many updates by Imre Deak <imre.deak@nokia.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/platform_device.h>
40#include <linux/workqueue.h>
41#include <linux/interrupt.h>
42#include <linux/err.h>
43#include <linux/clk.h>
44#include <linux/slab.h>
45
46#include <linux/spi/spi.h>
47#include <linux/spi/spi_bitbang.h>
48#include <linux/module.h>
49
50#include <asm/irq.h>
51#include <mach/hardware.h>
52#include <asm/io.h>
53#include <asm/mach-types.h>
54
55#include <mach/mux.h>
56
57#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
58
59
60/* FIXME address is now a platform device resource,
61 * and irqs should show there too...
62 */
63#define UWIRE_BASE_PHYS 0xFFFB3000
64
65/* uWire Registers: */
66#define UWIRE_IO_SIZE 0x20
67#define UWIRE_TDR 0x00
68#define UWIRE_RDR 0x00
69#define UWIRE_CSR 0x01
70#define UWIRE_SR1 0x02
71#define UWIRE_SR2 0x03
72#define UWIRE_SR3 0x04
73#define UWIRE_SR4 0x05
74#define UWIRE_SR5 0x06
75
76/* CSR bits */
77#define RDRB (1 << 15)
78#define CSRB (1 << 14)
79#define START (1 << 13)
80#define CS_CMD (1 << 12)
81
82/* SR1 or SR2 bits */
83#define UWIRE_READ_FALLING_EDGE 0x0001
84#define UWIRE_READ_RISING_EDGE 0x0000
85#define UWIRE_WRITE_FALLING_EDGE 0x0000
86#define UWIRE_WRITE_RISING_EDGE 0x0002
87#define UWIRE_CS_ACTIVE_LOW 0x0000
88#define UWIRE_CS_ACTIVE_HIGH 0x0004
89#define UWIRE_FREQ_DIV_2 0x0000
90#define UWIRE_FREQ_DIV_4 0x0008
91#define UWIRE_FREQ_DIV_8 0x0010
92#define UWIRE_CHK_READY 0x0020
93#define UWIRE_CLK_INVERTED 0x0040
94
95
96struct uwire_spi {
97 struct spi_bitbang bitbang;
98 struct clk *ck;
99};
100
101struct uwire_state {
102 unsigned div1_idx;
103};
104
105/* REVISIT compile time constant for idx_shift? */
106/*
107 * Or, put it in a structure which is used throughout the driver;
108 * that avoids having to issue two loads for each bit of static data.
109 */
110static unsigned int uwire_idx_shift;
111static void __iomem *uwire_base;
112
113static inline void uwire_write_reg(int idx, u16 val)
114{
115 __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
116}
117
118static inline u16 uwire_read_reg(int idx)
119{
120 return __raw_readw(uwire_base + (idx << uwire_idx_shift));
121}
122
123static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
124{
125 u16 w, val = 0;
126 int shift, reg;
127
128 if (flags & UWIRE_CLK_INVERTED)
129 val ^= 0x03;
130 val = flags & 0x3f;
131 if (cs & 1)
132 shift = 6;
133 else
134 shift = 0;
135 if (cs <= 1)
136 reg = UWIRE_SR1;
137 else
138 reg = UWIRE_SR2;
139
140 w = uwire_read_reg(reg);
141 w &= ~(0x3f << shift);
142 w |= val << shift;
143 uwire_write_reg(reg, w);
144}
145
146static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
147{
148 u16 w;
149 int c = 0;
150 unsigned long max_jiffies = jiffies + HZ;
151
152 for (;;) {
153 w = uwire_read_reg(UWIRE_CSR);
154 if ((w & mask) == val)
155 break;
156 if (time_after(jiffies, max_jiffies)) {
157 printk(KERN_ERR "%s: timeout. reg=%#06x "
158 "mask=%#06x val=%#06x\n",
159 __func__, w, mask, val);
160 return -1;
161 }
162 c++;
163 if (might_not_catch && c > 64)
164 break;
165 }
166 return 0;
167}
168
169static void uwire_set_clk1_div(int div1_idx)
170{
171 u16 w;
172
173 w = uwire_read_reg(UWIRE_SR3);
174 w &= ~(0x03 << 1);
175 w |= div1_idx << 1;
176 uwire_write_reg(UWIRE_SR3, w);
177}
178
179static void uwire_chipselect(struct spi_device *spi, int value)
180{
181 struct uwire_state *ust = spi->controller_state;
182 u16 w;
183 int old_cs;
184
185
186 BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
187
188 w = uwire_read_reg(UWIRE_CSR);
189 old_cs = (w >> 10) & 0x03;
190 if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
191 /* Deselect this CS, or the previous CS */
192 w &= ~CS_CMD;
193 uwire_write_reg(UWIRE_CSR, w);
194 }
195 /* activate specfied chipselect */
196 if (value == BITBANG_CS_ACTIVE) {
197 uwire_set_clk1_div(ust->div1_idx);
198 /* invert clock? */
199 if (spi->mode & SPI_CPOL)
200 uwire_write_reg(UWIRE_SR4, 1);
201 else
202 uwire_write_reg(UWIRE_SR4, 0);
203
204 w = spi->chip_select << 10;
205 w |= CS_CMD;
206 uwire_write_reg(UWIRE_CSR, w);
207 }
208}
209
210static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
211{
212 unsigned len = t->len;
213 unsigned bits = t->bits_per_word ? : spi->bits_per_word;
214 unsigned bytes;
215 u16 val, w;
216 int status = 0;
217
218 if (!t->tx_buf && !t->rx_buf)
219 return 0;
220
221 w = spi->chip_select << 10;
222 w |= CS_CMD;
223
224 if (t->tx_buf) {
225 const u8 *buf = t->tx_buf;
226
227 /* NOTE: DMA could be used for TX transfers */
228
229 /* write one or two bytes at a time */
230 while (len >= 1) {
231 /* tx bit 15 is first sent; we byteswap multibyte words
232 * (msb-first) on the way out from memory.
233 */
234 val = *buf++;
235 if (bits > 8) {
236 bytes = 2;
237 val |= *buf++ << 8;
238 } else
239 bytes = 1;
240 val <<= 16 - bits;
241
242#ifdef VERBOSE
243 pr_debug("%s: write-%d =%04x\n",
244 dev_name(&spi->dev), bits, val);
245#endif
246 if (wait_uwire_csr_flag(CSRB, 0, 0))
247 goto eio;
248
249 uwire_write_reg(UWIRE_TDR, val);
250
251 /* start write */
252 val = START | w | (bits << 5);
253
254 uwire_write_reg(UWIRE_CSR, val);
255 len -= bytes;
256
257 /* Wait till write actually starts.
258 * This is needed with MPU clock 60+ MHz.
259 * REVISIT: we may not have time to catch it...
260 */
261 if (wait_uwire_csr_flag(CSRB, CSRB, 1))
262 goto eio;
263
264 status += bytes;
265 }
266
267 /* REVISIT: save this for later to get more i/o overlap */
268 if (wait_uwire_csr_flag(CSRB, 0, 0))
269 goto eio;
270
271 } else if (t->rx_buf) {
272 u8 *buf = t->rx_buf;
273
274 /* read one or two bytes at a time */
275 while (len) {
276 if (bits > 8) {
277 bytes = 2;
278 } else
279 bytes = 1;
280
281 /* start read */
282 val = START | w | (bits << 0);
283 uwire_write_reg(UWIRE_CSR, val);
284 len -= bytes;
285
286 /* Wait till read actually starts */
287 (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
288
289 if (wait_uwire_csr_flag(RDRB | CSRB,
290 RDRB, 0))
291 goto eio;
292
293 /* rx bit 0 is last received; multibyte words will
294 * be properly byteswapped on the way to memory.
295 */
296 val = uwire_read_reg(UWIRE_RDR);
297 val &= (1 << bits) - 1;
298 *buf++ = (u8) val;
299 if (bytes == 2)
300 *buf++ = val >> 8;
301 status += bytes;
302#ifdef VERBOSE
303 pr_debug("%s: read-%d =%04x\n",
304 dev_name(&spi->dev), bits, val);
305#endif
306
307 }
308 }
309 return status;
310eio:
311 return -EIO;
312}
313
314static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
315{
316 struct uwire_state *ust = spi->controller_state;
317 struct uwire_spi *uwire;
318 unsigned flags = 0;
319 unsigned hz;
320 unsigned long rate;
321 int div1_idx;
322 int div1;
323 int div2;
324 int status;
325
326 uwire = spi_master_get_devdata(spi->master);
327
328 /* mode 0..3, clock inverted separately;
329 * standard nCS signaling;
330 * don't treat DI=high as "not ready"
331 */
332 if (spi->mode & SPI_CS_HIGH)
333 flags |= UWIRE_CS_ACTIVE_HIGH;
334
335 if (spi->mode & SPI_CPOL)
336 flags |= UWIRE_CLK_INVERTED;
337
338 switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
339 case SPI_MODE_0:
340 case SPI_MODE_3:
341 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
342 break;
343 case SPI_MODE_1:
344 case SPI_MODE_2:
345 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
346 break;
347 }
348
349 /* assume it's already enabled */
350 rate = clk_get_rate(uwire->ck);
351
352 hz = spi->max_speed_hz;
353 if (t != NULL && t->speed_hz)
354 hz = t->speed_hz;
355
356 if (!hz) {
357 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
358 status = -EINVAL;
359 goto done;
360 }
361
362 /* F_INT = mpu_xor_clk / DIV1 */
363 for (div1_idx = 0; div1_idx < 4; div1_idx++) {
364 switch (div1_idx) {
365 case 0:
366 div1 = 2;
367 break;
368 case 1:
369 div1 = 4;
370 break;
371 case 2:
372 div1 = 7;
373 break;
374 default:
375 case 3:
376 div1 = 10;
377 break;
378 }
379 div2 = (rate / div1 + hz - 1) / hz;
380 if (div2 <= 8)
381 break;
382 }
383 if (div1_idx == 4) {
384 pr_debug("%s: lowest clock %ld, need %d\n",
385 dev_name(&spi->dev), rate / 10 / 8, hz);
386 status = -EDOM;
387 goto done;
388 }
389
390 /* we have to cache this and reset in uwire_chipselect as this is a
391 * global parameter and another uwire device can change it under
392 * us */
393 ust->div1_idx = div1_idx;
394 uwire_set_clk1_div(div1_idx);
395
396 rate /= div1;
397
398 switch (div2) {
399 case 0:
400 case 1:
401 case 2:
402 flags |= UWIRE_FREQ_DIV_2;
403 rate /= 2;
404 break;
405 case 3:
406 case 4:
407 flags |= UWIRE_FREQ_DIV_4;
408 rate /= 4;
409 break;
410 case 5:
411 case 6:
412 case 7:
413 case 8:
414 flags |= UWIRE_FREQ_DIV_8;
415 rate /= 8;
416 break;
417 }
418 omap_uwire_configure_mode(spi->chip_select, flags);
419 pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
420 __func__, flags,
421 clk_get_rate(uwire->ck) / 1000,
422 rate / 1000);
423 status = 0;
424done:
425 return status;
426}
427
428static int uwire_setup(struct spi_device *spi)
429{
430 struct uwire_state *ust = spi->controller_state;
431
432 if (ust == NULL) {
433 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
434 if (ust == NULL)
435 return -ENOMEM;
436 spi->controller_state = ust;
437 }
438
439 return uwire_setup_transfer(spi, NULL);
440}
441
442static void uwire_cleanup(struct spi_device *spi)
443{
444 kfree(spi->controller_state);
445}
446
447static void uwire_off(struct uwire_spi *uwire)
448{
449 uwire_write_reg(UWIRE_SR3, 0);
450 clk_disable(uwire->ck);
451 clk_put(uwire->ck);
452 spi_master_put(uwire->bitbang.master);
453}
454
455static int uwire_probe(struct platform_device *pdev)
456{
457 struct spi_master *master;
458 struct uwire_spi *uwire;
459 int status;
460
461 master = spi_alloc_master(&pdev->dev, sizeof *uwire);
462 if (!master)
463 return -ENODEV;
464
465 uwire = spi_master_get_devdata(master);
466
467 uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
468 if (!uwire_base) {
469 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
470 spi_master_put(master);
471 return -ENOMEM;
472 }
473
474 platform_set_drvdata(pdev, uwire);
475
476 uwire->ck = clk_get(&pdev->dev, "fck");
477 if (IS_ERR(uwire->ck)) {
478 status = PTR_ERR(uwire->ck);
479 dev_dbg(&pdev->dev, "no functional clock?\n");
480 spi_master_put(master);
481 iounmap(uwire_base);
482 return status;
483 }
484 clk_enable(uwire->ck);
485
486 if (cpu_is_omap7xx())
487 uwire_idx_shift = 1;
488 else
489 uwire_idx_shift = 2;
490
491 uwire_write_reg(UWIRE_SR3, 1);
492
493 /* the spi->mode bits understood by this driver: */
494 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
495 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
496 master->flags = SPI_MASTER_HALF_DUPLEX;
497
498 master->bus_num = 2; /* "official" */
499 master->num_chipselect = 4;
500 master->setup = uwire_setup;
501 master->cleanup = uwire_cleanup;
502
503 uwire->bitbang.master = master;
504 uwire->bitbang.chipselect = uwire_chipselect;
505 uwire->bitbang.setup_transfer = uwire_setup_transfer;
506 uwire->bitbang.txrx_bufs = uwire_txrx;
507
508 status = spi_bitbang_start(&uwire->bitbang);
509 if (status < 0) {
510 uwire_off(uwire);
511 iounmap(uwire_base);
512 }
513 return status;
514}
515
516static int uwire_remove(struct platform_device *pdev)
517{
518 struct uwire_spi *uwire = platform_get_drvdata(pdev);
519
520 // FIXME remove all child devices, somewhere ...
521
522 spi_bitbang_stop(&uwire->bitbang);
523 uwire_off(uwire);
524 iounmap(uwire_base);
525 return 0;
526}
527
528/* work with hotplug and coldplug */
529MODULE_ALIAS("platform:omap_uwire");
530
531static struct platform_driver uwire_driver = {
532 .driver = {
533 .name = "omap_uwire",
534 .owner = THIS_MODULE,
535 },
536 .probe = uwire_probe,
537 .remove = uwire_remove,
538 // suspend ... unuse ck
539 // resume ... use ck
540};
541
542static int __init omap_uwire_init(void)
543{
544 /* FIXME move these into the relevant board init code. also, include
545 * H3 support; it uses tsc2101 like H2 (on a different chipselect).
546 */
547
548 if (machine_is_omap_h2()) {
549 /* defaults: W21 SDO, U18 SDI, V19 SCL */
550 omap_cfg_reg(N14_1610_UWIRE_CS0);
551 omap_cfg_reg(N15_1610_UWIRE_CS1);
552 }
553 if (machine_is_omap_perseus2()) {
554 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
555 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
556 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
557 }
558
559 return platform_driver_register(&uwire_driver);
560}
561
562static void __exit omap_uwire_exit(void)
563{
564 platform_driver_unregister(&uwire_driver);
565}
566
567subsys_initcall(omap_uwire_init);
568module_exit(omap_uwire_exit);
569
570MODULE_LICENSE("GPL");
571