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1/*
2 * Instruction formats for the sequencer program downloaded to
3 * Aic7xxx SCSI host adapters
4 *
5 * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#12 $
41 *
42 * $FreeBSD$
43 */
44
45#include <asm/byteorder.h>
46
47/* 8bit ALU logic operations */
48struct ins_format1 {
49#ifdef __LITTLE_ENDIAN
50 uint32_t immediate : 8,
51 source : 9,
52 destination : 9,
53 ret : 1,
54 opcode : 4,
55 parity : 1;
56#else
57 uint32_t parity : 1,
58 opcode : 4,
59 ret : 1,
60 destination : 9,
61 source : 9,
62 immediate : 8;
63#endif
64};
65
66/* 8bit ALU shift/rotate operations */
67struct ins_format2 {
68#ifdef __LITTLE_ENDIAN
69 uint32_t shift_control : 8,
70 source : 9,
71 destination : 9,
72 ret : 1,
73 opcode : 4,
74 parity : 1;
75#else
76 uint32_t parity : 1,
77 opcode : 4,
78 ret : 1,
79 destination : 9,
80 source : 9,
81 shift_control : 8;
82#endif
83};
84
85/* 8bit branch control operations */
86struct ins_format3 {
87#ifdef __LITTLE_ENDIAN
88 uint32_t immediate : 8,
89 source : 9,
90 address : 10,
91 opcode : 4,
92 parity : 1;
93#else
94 uint32_t parity : 1,
95 opcode : 4,
96 address : 10,
97 source : 9,
98 immediate : 8;
99#endif
100};
101
102/* 16bit ALU logic operations */
103struct ins_format4 {
104#ifdef __LITTLE_ENDIAN
105 uint32_t opcode_ext : 8,
106 source : 9,
107 destination : 9,
108 ret : 1,
109 opcode : 4,
110 parity : 1;
111#else
112 uint32_t parity : 1,
113 opcode : 4,
114 ret : 1,
115 destination : 9,
116 source : 9,
117 opcode_ext : 8;
118#endif
119};
120
121/* 16bit branch control operations */
122struct ins_format5 {
123#ifdef __LITTLE_ENDIAN
124 uint32_t opcode_ext : 8,
125 source : 9,
126 address : 10,
127 opcode : 4,
128 parity : 1;
129#else
130 uint32_t parity : 1,
131 opcode : 4,
132 address : 10,
133 source : 9,
134 opcode_ext : 8;
135#endif
136};
137
138/* Far branch operations */
139struct ins_format6 {
140#ifdef __LITTLE_ENDIAN
141 uint32_t page : 3,
142 opcode_ext : 5,
143 source : 9,
144 address : 10,
145 opcode : 4,
146 parity : 1;
147#else
148 uint32_t parity : 1,
149 opcode : 4,
150 address : 10,
151 source : 9,
152 opcode_ext : 5,
153 page : 3;
154#endif
155};
156
157union ins_formats {
158 struct ins_format1 format1;
159 struct ins_format2 format2;
160 struct ins_format3 format3;
161 struct ins_format4 format4;
162 struct ins_format5 format5;
163 struct ins_format6 format6;
164 uint8_t bytes[4];
165 uint32_t integer;
166};
167struct instruction {
168 union ins_formats format;
169 u_int srcline;
170 struct symbol *patch_label;
171 STAILQ_ENTRY(instruction) links;
172};
173
174#define AIC_OP_OR 0x0
175#define AIC_OP_AND 0x1
176#define AIC_OP_XOR 0x2
177#define AIC_OP_ADD 0x3
178#define AIC_OP_ADC 0x4
179#define AIC_OP_ROL 0x5
180#define AIC_OP_BMOV 0x6
181
182#define AIC_OP_MVI16 0x7
183
184#define AIC_OP_JMP 0x8
185#define AIC_OP_JC 0x9
186#define AIC_OP_JNC 0xa
187#define AIC_OP_CALL 0xb
188#define AIC_OP_JNE 0xc
189#define AIC_OP_JNZ 0xd
190#define AIC_OP_JE 0xe
191#define AIC_OP_JZ 0xf
192
193/* Pseudo Ops */
194#define AIC_OP_SHL 0x10
195#define AIC_OP_SHR 0x20
196#define AIC_OP_ROR 0x30
197
198/* 16bit Ops. Low byte main opcode. High byte extended opcode. */
199#define AIC_OP_OR16 0x8005
200#define AIC_OP_AND16 0x8105
201#define AIC_OP_XOR16 0x8205
202#define AIC_OP_ADD16 0x8305
203#define AIC_OP_ADC16 0x8405
204#define AIC_OP_JNE16 0x8805
205#define AIC_OP_JNZ16 0x8905
206#define AIC_OP_JE16 0x8C05
207#define AIC_OP_JZ16 0x8B05
208#define AIC_OP_JMP16 0x9005
209#define AIC_OP_JC16 0x9105
210#define AIC_OP_JNC16 0x9205
211#define AIC_OP_CALL16 0x9305
212
213/* Page extension is low three bits of second opcode byte. */
214#define AIC_OP_JMPF 0xA005
215#define AIC_OP_CALLF 0xB005
216#define AIC_OP_JCF 0xC005
217#define AIC_OP_JNCF 0xD005
218#define AIC_OP_CMPXCHG 0xE005
1/*
2 * Instruction formats for the sequencer program downloaded to
3 * Aic7xxx SCSI host adapters
4 *
5 * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#12 $
41 *
42 * $FreeBSD$
43 */
44
45#include <asm/byteorder.h>
46
47/* 8bit ALU logic operations */
48struct ins_format1 {
49#ifdef __LITTLE_ENDIAN
50 uint32_t immediate : 8,
51 source : 9,
52 destination : 9,
53 ret : 1,
54 opcode : 4,
55 parity : 1;
56#else
57 uint32_t parity : 1,
58 opcode : 4,
59 ret : 1,
60 destination : 9,
61 source : 9,
62 immediate : 8;
63#endif
64};
65
66/* 8bit ALU shift/rotate operations */
67struct ins_format2 {
68#ifdef __LITTLE_ENDIAN
69 uint32_t shift_control : 8,
70 source : 9,
71 destination : 9,
72 ret : 1,
73 opcode : 4,
74 parity : 1;
75#else
76 uint32_t parity : 1,
77 opcode : 4,
78 ret : 1,
79 destination : 9,
80 source : 9,
81 shift_control : 8;
82#endif
83};
84
85/* 8bit branch control operations */
86struct ins_format3 {
87#ifdef __LITTLE_ENDIAN
88 uint32_t immediate : 8,
89 source : 9,
90 address : 10,
91 opcode : 4,
92 parity : 1;
93#else
94 uint32_t parity : 1,
95 opcode : 4,
96 address : 10,
97 source : 9,
98 immediate : 8;
99#endif
100};
101
102/* 16bit ALU logic operations */
103struct ins_format4 {
104#ifdef __LITTLE_ENDIAN
105 uint32_t opcode_ext : 8,
106 source : 9,
107 destination : 9,
108 ret : 1,
109 opcode : 4,
110 parity : 1;
111#else
112 uint32_t parity : 1,
113 opcode : 4,
114 ret : 1,
115 destination : 9,
116 source : 9,
117 opcode_ext : 8;
118#endif
119};
120
121/* 16bit branch control operations */
122struct ins_format5 {
123#ifdef __LITTLE_ENDIAN
124 uint32_t opcode_ext : 8,
125 source : 9,
126 address : 10,
127 opcode : 4,
128 parity : 1;
129#else
130 uint32_t parity : 1,
131 opcode : 4,
132 address : 10,
133 source : 9,
134 opcode_ext : 8;
135#endif
136};
137
138/* Far branch operations */
139struct ins_format6 {
140#ifdef __LITTLE_ENDIAN
141 uint32_t page : 3,
142 opcode_ext : 5,
143 source : 9,
144 address : 10,
145 opcode : 4,
146 parity : 1;
147#else
148 uint32_t parity : 1,
149 opcode : 4,
150 address : 10,
151 source : 9,
152 opcode_ext : 5,
153 page : 3;
154#endif
155};
156
157union ins_formats {
158 struct ins_format1 format1;
159 struct ins_format2 format2;
160 struct ins_format3 format3;
161 struct ins_format4 format4;
162 struct ins_format5 format5;
163 struct ins_format6 format6;
164 uint8_t bytes[4];
165 uint32_t integer;
166};
167struct instruction {
168 union ins_formats format;
169 u_int srcline;
170 struct symbol *patch_label;
171 STAILQ_ENTRY(instruction) links;
172};
173
174#define AIC_OP_OR 0x0
175#define AIC_OP_AND 0x1
176#define AIC_OP_XOR 0x2
177#define AIC_OP_ADD 0x3
178#define AIC_OP_ADC 0x4
179#define AIC_OP_ROL 0x5
180#define AIC_OP_BMOV 0x6
181
182#define AIC_OP_MVI16 0x7
183
184#define AIC_OP_JMP 0x8
185#define AIC_OP_JC 0x9
186#define AIC_OP_JNC 0xa
187#define AIC_OP_CALL 0xb
188#define AIC_OP_JNE 0xc
189#define AIC_OP_JNZ 0xd
190#define AIC_OP_JE 0xe
191#define AIC_OP_JZ 0xf
192
193/* Pseudo Ops */
194#define AIC_OP_SHL 0x10
195#define AIC_OP_SHR 0x20
196#define AIC_OP_ROR 0x30
197
198/* 16bit Ops. Low byte main opcode. High byte extended opcode. */
199#define AIC_OP_OR16 0x8005
200#define AIC_OP_AND16 0x8105
201#define AIC_OP_XOR16 0x8205
202#define AIC_OP_ADD16 0x8305
203#define AIC_OP_ADC16 0x8405
204#define AIC_OP_JNE16 0x8805
205#define AIC_OP_JNZ16 0x8905
206#define AIC_OP_JE16 0x8C05
207#define AIC_OP_JZ16 0x8B05
208#define AIC_OP_JMP16 0x9005
209#define AIC_OP_JC16 0x9105
210#define AIC_OP_JNC16 0x9205
211#define AIC_OP_CALL16 0x9305
212
213/* Page extension is low three bits of second opcode byte. */
214#define AIC_OP_JMPF 0xA005
215#define AIC_OP_CALLF 0xB005
216#define AIC_OP_JCF 0xC005
217#define AIC_OP_JNCF 0xD005
218#define AIC_OP_CMPXCHG 0xE005