Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Core driver access RC5T583 power management chip.
4 *
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * Author: Laxman dewangan <ldewangan@nvidia.com>
7 *
8 * Based on code
9 * Copyright (C) 2011 RICOH COMPANY,LTD
10 */
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/slab.h>
17#include <linux/i2c.h>
18#include <linux/mfd/core.h>
19#include <linux/mfd/rc5t583.h>
20#include <linux/regmap.h>
21
22#define RICOH_ONOFFSEL_REG 0x10
23#define RICOH_SWCTL_REG 0x5E
24
25struct deepsleep_control_data {
26 u8 reg_add;
27 u8 ds_pos_bit;
28};
29
30#define DEEPSLEEP_INIT(_id, _reg, _pos) \
31 { \
32 .reg_add = RC5T583_##_reg, \
33 .ds_pos_bit = _pos, \
34 }
35
36static struct deepsleep_control_data deepsleep_data[] = {
37 DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
38 DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
39 DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
40 DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
41 DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
42 DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
43 DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
44 DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
45 DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
46 DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
47 DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
48 DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
49 DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
50 DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
51 DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
52 DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
53 DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
54 DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
55 DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
56 DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
57 DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
58 DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
59};
60
61#define EXT_PWR_REQ \
62 (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
63
64static const struct mfd_cell rc5t583_subdevs[] = {
65 {.name = "rc5t583-gpio",},
66 {.name = "rc5t583-regulator",},
67 {.name = "rc5t583-rtc", },
68 {.name = "rc5t583-key", }
69};
70
71static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
72 int id, int ext_pwr, int slots)
73{
74 int ret;
75 uint8_t sleepseq_val = 0;
76 unsigned int en_bit;
77 unsigned int slot_bit;
78
79 if (id == RC5T583_DS_DC0) {
80 dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
81 return -EINVAL;
82 }
83
84 en_bit = deepsleep_data[id].ds_pos_bit;
85 slot_bit = en_bit + 1;
86 ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
87 if (ret < 0) {
88 dev_err(dev, "Error in reading reg 0x%x\n",
89 deepsleep_data[id].reg_add);
90 return ret;
91 }
92
93 sleepseq_val &= ~(0xF << en_bit);
94 sleepseq_val |= BIT(en_bit);
95 sleepseq_val |= ((slots & 0x7) << slot_bit);
96 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
97 if (ret < 0) {
98 dev_err(dev, "Error in updating the 0x%02x register\n",
99 RICOH_ONOFFSEL_REG);
100 return ret;
101 }
102
103 ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
104 if (ret < 0) {
105 dev_err(dev, "Error in writing reg 0x%x\n",
106 deepsleep_data[id].reg_add);
107 return ret;
108 }
109
110 if (id == RC5T583_DS_LDO4) {
111 ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
112 if (ret < 0)
113 dev_err(dev, "Error in writing reg 0x%x\n",
114 RICOH_SWCTL_REG);
115 }
116 return ret;
117}
118
119static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
120 int id, int ext_pwr)
121{
122 int ret;
123
124 if (id != RC5T583_DS_DC0) {
125 dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
126 return -EINVAL;
127 }
128
129 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
130 if (ret < 0)
131 dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
132 return ret;
133}
134
135int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
136 int ext_pwr_req, int deepsleep_slot_nr)
137{
138 if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
139 return -EINVAL;
140
141 if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
142 return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
143 ext_pwr_req, deepsleep_slot_nr);
144
145 if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
146 return __rc5t583_set_ext_pwrreq2_control(dev,
147 ds_id, ext_pwr_req);
148 return 0;
149}
150EXPORT_SYMBOL(rc5t583_ext_power_req_config);
151
152static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
153 struct rc5t583_platform_data *pdata)
154{
155 int ret;
156 int i;
157 uint8_t on_off_val = 0;
158
159 /* Clear ONOFFSEL register */
160 if (pdata->enable_shutdown)
161 on_off_val = 0x1;
162
163 ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
164 if (ret < 0)
165 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
166 RICOH_ONOFFSEL_REG, ret);
167
168 ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
169 if (ret < 0)
170 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
171 RICOH_SWCTL_REG, ret);
172
173 /* Clear sleep sequence register */
174 for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
175 ret = rc5t583_write(rc5t583->dev, i, 0x0);
176 if (ret < 0)
177 dev_warn(rc5t583->dev,
178 "Error in writing reg 0x%02x error: %d\n",
179 i, ret);
180 }
181 return 0;
182}
183
184static bool volatile_reg(struct device *dev, unsigned int reg)
185{
186 /* Enable caching in interrupt registers */
187 switch (reg) {
188 case RC5T583_INT_EN_SYS1:
189 case RC5T583_INT_EN_SYS2:
190 case RC5T583_INT_EN_DCDC:
191 case RC5T583_INT_EN_RTC:
192 case RC5T583_INT_EN_ADC1:
193 case RC5T583_INT_EN_ADC2:
194 case RC5T583_INT_EN_ADC3:
195 case RC5T583_GPIO_GPEDGE1:
196 case RC5T583_GPIO_GPEDGE2:
197 case RC5T583_GPIO_EN_INT:
198 return false;
199
200 case RC5T583_GPIO_MON_IOIN:
201 /* This is gpio input register */
202 return true;
203
204 default:
205 /* Enable caching in gpio registers */
206 if ((reg >= RC5T583_GPIO_IOSEL) &&
207 (reg <= RC5T583_GPIO_GPOFUNC))
208 return false;
209
210 /* Enable caching in sleep seq registers */
211 if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
212 return false;
213
214 /* Enable caching of regulator registers */
215 if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
216 return false;
217 if ((reg >= RC5T583_REG_LDOEN1) &&
218 (reg <= RC5T583_REG_LDO9DAC_DS))
219 return false;
220
221 break;
222 }
223
224 return true;
225}
226
227static const struct regmap_config rc5t583_regmap_config = {
228 .reg_bits = 8,
229 .val_bits = 8,
230 .volatile_reg = volatile_reg,
231 .max_register = RC5T583_MAX_REG,
232 .num_reg_defaults_raw = RC5T583_NUM_REGS,
233 .cache_type = REGCACHE_RBTREE,
234};
235
236static int rc5t583_i2c_probe(struct i2c_client *i2c,
237 const struct i2c_device_id *id)
238{
239 struct rc5t583 *rc5t583;
240 struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
241 int ret;
242
243 if (!pdata) {
244 dev_err(&i2c->dev, "Err: Platform data not found\n");
245 return -EINVAL;
246 }
247
248 rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
249 if (!rc5t583)
250 return -ENOMEM;
251
252 rc5t583->dev = &i2c->dev;
253 i2c_set_clientdata(i2c, rc5t583);
254
255 rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
256 if (IS_ERR(rc5t583->regmap)) {
257 ret = PTR_ERR(rc5t583->regmap);
258 dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
259 return ret;
260 }
261
262 ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
263 if (ret < 0)
264 return ret;
265
266 if (i2c->irq) {
267 ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
268 /* Still continue with warning, if irq init fails */
269 if (ret)
270 dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
271 }
272
273 ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
274 ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
275 if (ret) {
276 dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
277 return ret;
278 }
279
280 return 0;
281}
282
283static const struct i2c_device_id rc5t583_i2c_id[] = {
284 {.name = "rc5t583", .driver_data = 0},
285 {}
286};
287
288static struct i2c_driver rc5t583_i2c_driver = {
289 .driver = {
290 .name = "rc5t583",
291 },
292 .probe = rc5t583_i2c_probe,
293 .id_table = rc5t583_i2c_id,
294};
295
296static int __init rc5t583_i2c_init(void)
297{
298 return i2c_add_driver(&rc5t583_i2c_driver);
299}
300subsys_initcall(rc5t583_i2c_init);
1/*
2 * Core driver access RC5T583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/i2c.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rc5t583.h>
33#include <linux/regmap.h>
34
35#define RICOH_ONOFFSEL_REG 0x10
36#define RICOH_SWCTL_REG 0x5E
37
38struct deepsleep_control_data {
39 u8 reg_add;
40 u8 ds_pos_bit;
41};
42
43#define DEEPSLEEP_INIT(_id, _reg, _pos) \
44 { \
45 .reg_add = RC5T583_##_reg, \
46 .ds_pos_bit = _pos, \
47 }
48
49static struct deepsleep_control_data deepsleep_data[] = {
50 DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
51 DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
52 DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
53 DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
54 DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
55 DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
56 DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
57 DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
58 DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
59 DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
60 DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
61 DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
62 DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
63 DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
64 DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
65 DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
66 DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
67 DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
68 DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
69 DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
70 DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
71 DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
72};
73
74#define EXT_PWR_REQ \
75 (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
76
77static const struct mfd_cell rc5t583_subdevs[] = {
78 {.name = "rc5t583-gpio",},
79 {.name = "rc5t583-regulator",},
80 {.name = "rc5t583-rtc", },
81 {.name = "rc5t583-key", }
82};
83
84static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
85 int id, int ext_pwr, int slots)
86{
87 int ret;
88 uint8_t sleepseq_val = 0;
89 unsigned int en_bit;
90 unsigned int slot_bit;
91
92 if (id == RC5T583_DS_DC0) {
93 dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
94 return -EINVAL;
95 }
96
97 en_bit = deepsleep_data[id].ds_pos_bit;
98 slot_bit = en_bit + 1;
99 ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
100 if (ret < 0) {
101 dev_err(dev, "Error in reading reg 0x%x\n",
102 deepsleep_data[id].reg_add);
103 return ret;
104 }
105
106 sleepseq_val &= ~(0xF << en_bit);
107 sleepseq_val |= BIT(en_bit);
108 sleepseq_val |= ((slots & 0x7) << slot_bit);
109 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
110 if (ret < 0) {
111 dev_err(dev, "Error in updating the 0x%02x register\n",
112 RICOH_ONOFFSEL_REG);
113 return ret;
114 }
115
116 ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
117 if (ret < 0) {
118 dev_err(dev, "Error in writing reg 0x%x\n",
119 deepsleep_data[id].reg_add);
120 return ret;
121 }
122
123 if (id == RC5T583_DS_LDO4) {
124 ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
125 if (ret < 0)
126 dev_err(dev, "Error in writing reg 0x%x\n",
127 RICOH_SWCTL_REG);
128 }
129 return ret;
130}
131
132static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
133 int id, int ext_pwr)
134{
135 int ret;
136
137 if (id != RC5T583_DS_DC0) {
138 dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
139 return -EINVAL;
140 }
141
142 ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
143 if (ret < 0)
144 dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
145 return ret;
146}
147
148int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
149 int ext_pwr_req, int deepsleep_slot_nr)
150{
151 if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
152 return -EINVAL;
153
154 if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
155 return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
156 ext_pwr_req, deepsleep_slot_nr);
157
158 if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
159 return __rc5t583_set_ext_pwrreq2_control(dev,
160 ds_id, ext_pwr_req);
161 return 0;
162}
163EXPORT_SYMBOL(rc5t583_ext_power_req_config);
164
165static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
166 struct rc5t583_platform_data *pdata)
167{
168 int ret;
169 int i;
170 uint8_t on_off_val = 0;
171
172 /* Clear ONOFFSEL register */
173 if (pdata->enable_shutdown)
174 on_off_val = 0x1;
175
176 ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
177 if (ret < 0)
178 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
179 RICOH_ONOFFSEL_REG, ret);
180
181 ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
182 if (ret < 0)
183 dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
184 RICOH_SWCTL_REG, ret);
185
186 /* Clear sleep sequence register */
187 for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
188 ret = rc5t583_write(rc5t583->dev, i, 0x0);
189 if (ret < 0)
190 dev_warn(rc5t583->dev,
191 "Error in writing reg 0x%02x error: %d\n",
192 i, ret);
193 }
194 return 0;
195}
196
197static bool volatile_reg(struct device *dev, unsigned int reg)
198{
199 /* Enable caching in interrupt registers */
200 switch (reg) {
201 case RC5T583_INT_EN_SYS1:
202 case RC5T583_INT_EN_SYS2:
203 case RC5T583_INT_EN_DCDC:
204 case RC5T583_INT_EN_RTC:
205 case RC5T583_INT_EN_ADC1:
206 case RC5T583_INT_EN_ADC2:
207 case RC5T583_INT_EN_ADC3:
208 case RC5T583_GPIO_GPEDGE1:
209 case RC5T583_GPIO_GPEDGE2:
210 case RC5T583_GPIO_EN_INT:
211 return false;
212
213 case RC5T583_GPIO_MON_IOIN:
214 /* This is gpio input register */
215 return true;
216
217 default:
218 /* Enable caching in gpio registers */
219 if ((reg >= RC5T583_GPIO_IOSEL) &&
220 (reg <= RC5T583_GPIO_GPOFUNC))
221 return false;
222
223 /* Enable caching in sleep seq registers */
224 if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
225 return false;
226
227 /* Enable caching of regulator registers */
228 if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
229 return false;
230 if ((reg >= RC5T583_REG_LDOEN1) &&
231 (reg <= RC5T583_REG_LDO9DAC_DS))
232 return false;
233
234 break;
235 }
236
237 return true;
238}
239
240static const struct regmap_config rc5t583_regmap_config = {
241 .reg_bits = 8,
242 .val_bits = 8,
243 .volatile_reg = volatile_reg,
244 .max_register = RC5T583_MAX_REGS,
245 .num_reg_defaults_raw = RC5T583_MAX_REGS,
246 .cache_type = REGCACHE_RBTREE,
247};
248
249static int rc5t583_i2c_probe(struct i2c_client *i2c,
250 const struct i2c_device_id *id)
251{
252 struct rc5t583 *rc5t583;
253 struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
254 int ret;
255 bool irq_init_success = false;
256
257 if (!pdata) {
258 dev_err(&i2c->dev, "Err: Platform data not found\n");
259 return -EINVAL;
260 }
261
262 rc5t583 = devm_kzalloc(&i2c->dev, sizeof(struct rc5t583), GFP_KERNEL);
263 if (!rc5t583) {
264 dev_err(&i2c->dev, "Memory allocation failed\n");
265 return -ENOMEM;
266 }
267
268 rc5t583->dev = &i2c->dev;
269 i2c_set_clientdata(i2c, rc5t583);
270
271 rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
272 if (IS_ERR(rc5t583->regmap)) {
273 ret = PTR_ERR(rc5t583->regmap);
274 dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
275 return ret;
276 }
277
278 ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
279 if (ret < 0)
280 return ret;
281
282 if (i2c->irq) {
283 ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
284 /* Still continue with warning, if irq init fails */
285 if (ret)
286 dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
287 else
288 irq_init_success = true;
289 }
290
291 ret = mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
292 ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
293 if (ret) {
294 dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
295 goto err_add_devs;
296 }
297
298 return 0;
299
300err_add_devs:
301 if (irq_init_success)
302 rc5t583_irq_exit(rc5t583);
303 return ret;
304}
305
306static int rc5t583_i2c_remove(struct i2c_client *i2c)
307{
308 struct rc5t583 *rc5t583 = i2c_get_clientdata(i2c);
309
310 mfd_remove_devices(rc5t583->dev);
311 rc5t583_irq_exit(rc5t583);
312 return 0;
313}
314
315static const struct i2c_device_id rc5t583_i2c_id[] = {
316 {.name = "rc5t583", .driver_data = 0},
317 {}
318};
319
320MODULE_DEVICE_TABLE(i2c, rc5t583_i2c_id);
321
322static struct i2c_driver rc5t583_i2c_driver = {
323 .driver = {
324 .name = "rc5t583",
325 .owner = THIS_MODULE,
326 },
327 .probe = rc5t583_i2c_probe,
328 .remove = rc5t583_i2c_remove,
329 .id_table = rc5t583_i2c_id,
330};
331
332static int __init rc5t583_i2c_init(void)
333{
334 return i2c_add_driver(&rc5t583_i2c_driver);
335}
336subsys_initcall(rc5t583_i2c_init);
337
338static void __exit rc5t583_i2c_exit(void)
339{
340 i2c_del_driver(&rc5t583_i2c_driver);
341}
342
343module_exit(rc5t583_i2c_exit);
344
345MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
346MODULE_DESCRIPTION("RICOH RC5T583 power management system device driver");
347MODULE_LICENSE("GPL v2");