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1/*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
22#include <linux/list.h>
23#include <linux/slab.h>
24#include <linux/syscore_ops.h>
25#include <linux/interrupt.h>
26#include <linux/msi.h>
27#include <linux/amd-iommu.h>
28#include <linux/export.h>
29#include <asm/pci-direct.h>
30#include <asm/iommu.h>
31#include <asm/gart.h>
32#include <asm/x86_init.h>
33#include <asm/iommu_table.h>
34#include <asm/io_apic.h>
35#include <asm/irq_remapping.h>
36
37#include "amd_iommu_proto.h"
38#include "amd_iommu_types.h"
39#include "irq_remapping.h"
40
41/*
42 * definitions for the ACPI scanning code
43 */
44#define IVRS_HEADER_LENGTH 48
45
46#define ACPI_IVHD_TYPE 0x10
47#define ACPI_IVMD_TYPE_ALL 0x20
48#define ACPI_IVMD_TYPE 0x21
49#define ACPI_IVMD_TYPE_RANGE 0x22
50
51#define IVHD_DEV_ALL 0x01
52#define IVHD_DEV_SELECT 0x02
53#define IVHD_DEV_SELECT_RANGE_START 0x03
54#define IVHD_DEV_RANGE_END 0x04
55#define IVHD_DEV_ALIAS 0x42
56#define IVHD_DEV_ALIAS_RANGE 0x43
57#define IVHD_DEV_EXT_SELECT 0x46
58#define IVHD_DEV_EXT_SELECT_RANGE 0x47
59#define IVHD_DEV_SPECIAL 0x48
60
61#define IVHD_SPECIAL_IOAPIC 1
62#define IVHD_SPECIAL_HPET 2
63
64#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
65#define IVHD_FLAG_PASSPW_EN_MASK 0x02
66#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
67#define IVHD_FLAG_ISOC_EN_MASK 0x08
68
69#define IVMD_FLAG_EXCL_RANGE 0x08
70#define IVMD_FLAG_UNITY_MAP 0x01
71
72#define ACPI_DEVFLAG_INITPASS 0x01
73#define ACPI_DEVFLAG_EXTINT 0x02
74#define ACPI_DEVFLAG_NMI 0x04
75#define ACPI_DEVFLAG_SYSMGT1 0x10
76#define ACPI_DEVFLAG_SYSMGT2 0x20
77#define ACPI_DEVFLAG_LINT0 0x40
78#define ACPI_DEVFLAG_LINT1 0x80
79#define ACPI_DEVFLAG_ATSDIS 0x10000000
80
81/*
82 * ACPI table definitions
83 *
84 * These data structures are laid over the table to parse the important values
85 * out of it.
86 */
87
88/*
89 * structure describing one IOMMU in the ACPI table. Typically followed by one
90 * or more ivhd_entrys.
91 */
92struct ivhd_header {
93 u8 type;
94 u8 flags;
95 u16 length;
96 u16 devid;
97 u16 cap_ptr;
98 u64 mmio_phys;
99 u16 pci_seg;
100 u16 info;
101 u32 efr;
102} __attribute__((packed));
103
104/*
105 * A device entry describing which devices a specific IOMMU translates and
106 * which requestor ids they use.
107 */
108struct ivhd_entry {
109 u8 type;
110 u16 devid;
111 u8 flags;
112 u32 ext;
113} __attribute__((packed));
114
115/*
116 * An AMD IOMMU memory definition structure. It defines things like exclusion
117 * ranges for devices and regions that should be unity mapped.
118 */
119struct ivmd_header {
120 u8 type;
121 u8 flags;
122 u16 length;
123 u16 devid;
124 u16 aux;
125 u64 resv;
126 u64 range_start;
127 u64 range_length;
128} __attribute__((packed));
129
130bool amd_iommu_dump;
131bool amd_iommu_irq_remap __read_mostly;
132
133static bool amd_iommu_detected;
134static bool __initdata amd_iommu_disabled;
135
136u16 amd_iommu_last_bdf; /* largest PCI device id we have
137 to handle */
138LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
139 we find in ACPI */
140u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
141
142LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
143 system */
144
145/* Array to assign indices to IOMMUs*/
146struct amd_iommu *amd_iommus[MAX_IOMMUS];
147int amd_iommus_present;
148
149/* IOMMUs have a non-present cache? */
150bool amd_iommu_np_cache __read_mostly;
151bool amd_iommu_iotlb_sup __read_mostly = true;
152
153u32 amd_iommu_max_pasid __read_mostly = ~0;
154
155bool amd_iommu_v2_present __read_mostly;
156bool amd_iommu_pc_present __read_mostly;
157
158bool amd_iommu_force_isolation __read_mostly;
159
160/*
161 * List of protection domains - used during resume
162 */
163LIST_HEAD(amd_iommu_pd_list);
164spinlock_t amd_iommu_pd_lock;
165
166/*
167 * Pointer to the device table which is shared by all AMD IOMMUs
168 * it is indexed by the PCI device id or the HT unit id and contains
169 * information about the domain the device belongs to as well as the
170 * page table root pointer.
171 */
172struct dev_table_entry *amd_iommu_dev_table;
173
174/*
175 * The alias table is a driver specific data structure which contains the
176 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
177 * More than one device can share the same requestor id.
178 */
179u16 *amd_iommu_alias_table;
180
181/*
182 * The rlookup table is used to find the IOMMU which is responsible
183 * for a specific device. It is also indexed by the PCI device id.
184 */
185struct amd_iommu **amd_iommu_rlookup_table;
186
187/*
188 * This table is used to find the irq remapping table for a given device id
189 * quickly.
190 */
191struct irq_remap_table **irq_lookup_table;
192
193/*
194 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
195 * to know which ones are already in use.
196 */
197unsigned long *amd_iommu_pd_alloc_bitmap;
198
199static u32 dev_table_size; /* size of the device table */
200static u32 alias_table_size; /* size of the alias table */
201static u32 rlookup_table_size; /* size if the rlookup table */
202
203enum iommu_init_state {
204 IOMMU_START_STATE,
205 IOMMU_IVRS_DETECTED,
206 IOMMU_ACPI_FINISHED,
207 IOMMU_ENABLED,
208 IOMMU_PCI_INIT,
209 IOMMU_INTERRUPTS_EN,
210 IOMMU_DMA_OPS,
211 IOMMU_INITIALIZED,
212 IOMMU_NOT_FOUND,
213 IOMMU_INIT_ERROR,
214};
215
216/* Early ioapic and hpet maps from kernel command line */
217#define EARLY_MAP_SIZE 4
218static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
219static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
220static int __initdata early_ioapic_map_size;
221static int __initdata early_hpet_map_size;
222static bool __initdata cmdline_maps;
223
224static enum iommu_init_state init_state = IOMMU_START_STATE;
225
226static int amd_iommu_enable_interrupts(void);
227static int __init iommu_go_to_state(enum iommu_init_state state);
228
229static inline void update_last_devid(u16 devid)
230{
231 if (devid > amd_iommu_last_bdf)
232 amd_iommu_last_bdf = devid;
233}
234
235static inline unsigned long tbl_size(int entry_size)
236{
237 unsigned shift = PAGE_SHIFT +
238 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
239
240 return 1UL << shift;
241}
242
243/* Access to l1 and l2 indexed register spaces */
244
245static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
246{
247 u32 val;
248
249 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
250 pci_read_config_dword(iommu->dev, 0xfc, &val);
251 return val;
252}
253
254static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
255{
256 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
257 pci_write_config_dword(iommu->dev, 0xfc, val);
258 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
259}
260
261static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
262{
263 u32 val;
264
265 pci_write_config_dword(iommu->dev, 0xf0, address);
266 pci_read_config_dword(iommu->dev, 0xf4, &val);
267 return val;
268}
269
270static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
271{
272 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
273 pci_write_config_dword(iommu->dev, 0xf4, val);
274}
275
276/****************************************************************************
277 *
278 * AMD IOMMU MMIO register space handling functions
279 *
280 * These functions are used to program the IOMMU device registers in
281 * MMIO space required for that driver.
282 *
283 ****************************************************************************/
284
285/*
286 * This function set the exclusion range in the IOMMU. DMA accesses to the
287 * exclusion range are passed through untranslated
288 */
289static void iommu_set_exclusion_range(struct amd_iommu *iommu)
290{
291 u64 start = iommu->exclusion_start & PAGE_MASK;
292 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
293 u64 entry;
294
295 if (!iommu->exclusion_start)
296 return;
297
298 entry = start | MMIO_EXCL_ENABLE_MASK;
299 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
300 &entry, sizeof(entry));
301
302 entry = limit;
303 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
304 &entry, sizeof(entry));
305}
306
307/* Programs the physical address of the device table into the IOMMU hardware */
308static void iommu_set_device_table(struct amd_iommu *iommu)
309{
310 u64 entry;
311
312 BUG_ON(iommu->mmio_base == NULL);
313
314 entry = virt_to_phys(amd_iommu_dev_table);
315 entry |= (dev_table_size >> 12) - 1;
316 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
317 &entry, sizeof(entry));
318}
319
320/* Generic functions to enable/disable certain features of the IOMMU. */
321static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
322{
323 u32 ctrl;
324
325 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
326 ctrl |= (1 << bit);
327 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
328}
329
330static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
331{
332 u32 ctrl;
333
334 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
335 ctrl &= ~(1 << bit);
336 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
337}
338
339static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
340{
341 u32 ctrl;
342
343 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
344 ctrl &= ~CTRL_INV_TO_MASK;
345 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
346 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
347}
348
349/* Function to enable the hardware */
350static void iommu_enable(struct amd_iommu *iommu)
351{
352 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
353}
354
355static void iommu_disable(struct amd_iommu *iommu)
356{
357 /* Disable command buffer */
358 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
359
360 /* Disable event logging and event interrupts */
361 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
362 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
363
364 /* Disable IOMMU hardware itself */
365 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
366}
367
368/*
369 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
370 * the system has one.
371 */
372static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
373{
374 if (!request_mem_region(address, end, "amd_iommu")) {
375 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
376 address, end);
377 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
378 return NULL;
379 }
380
381 return (u8 __iomem *)ioremap_nocache(address, end);
382}
383
384static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
385{
386 if (iommu->mmio_base)
387 iounmap(iommu->mmio_base);
388 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
389}
390
391/****************************************************************************
392 *
393 * The functions below belong to the first pass of AMD IOMMU ACPI table
394 * parsing. In this pass we try to find out the highest device id this
395 * code has to handle. Upon this information the size of the shared data
396 * structures is determined later.
397 *
398 ****************************************************************************/
399
400/*
401 * This function calculates the length of a given IVHD entry
402 */
403static inline int ivhd_entry_length(u8 *ivhd)
404{
405 return 0x04 << (*ivhd >> 6);
406}
407
408/*
409 * This function reads the last device id the IOMMU has to handle from the PCI
410 * capability header for this IOMMU
411 */
412static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
413{
414 u32 cap;
415
416 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
417 update_last_devid(PCI_DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
418
419 return 0;
420}
421
422/*
423 * After reading the highest device id from the IOMMU PCI capability header
424 * this function looks if there is a higher device id defined in the ACPI table
425 */
426static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
427{
428 u8 *p = (void *)h, *end = (void *)h;
429 struct ivhd_entry *dev;
430
431 p += sizeof(*h);
432 end += h->length;
433
434 find_last_devid_on_pci(PCI_BUS_NUM(h->devid),
435 PCI_SLOT(h->devid),
436 PCI_FUNC(h->devid),
437 h->cap_ptr);
438
439 while (p < end) {
440 dev = (struct ivhd_entry *)p;
441 switch (dev->type) {
442 case IVHD_DEV_SELECT:
443 case IVHD_DEV_RANGE_END:
444 case IVHD_DEV_ALIAS:
445 case IVHD_DEV_EXT_SELECT:
446 /* all the above subfield types refer to device ids */
447 update_last_devid(dev->devid);
448 break;
449 default:
450 break;
451 }
452 p += ivhd_entry_length(p);
453 }
454
455 WARN_ON(p != end);
456
457 return 0;
458}
459
460/*
461 * Iterate over all IVHD entries in the ACPI table and find the highest device
462 * id which we need to handle. This is the first of three functions which parse
463 * the ACPI table. So we check the checksum here.
464 */
465static int __init find_last_devid_acpi(struct acpi_table_header *table)
466{
467 int i;
468 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
469 struct ivhd_header *h;
470
471 /*
472 * Validate checksum here so we don't need to do it when
473 * we actually parse the table
474 */
475 for (i = 0; i < table->length; ++i)
476 checksum += p[i];
477 if (checksum != 0)
478 /* ACPI table corrupt */
479 return -ENODEV;
480
481 p += IVRS_HEADER_LENGTH;
482
483 end += table->length;
484 while (p < end) {
485 h = (struct ivhd_header *)p;
486 switch (h->type) {
487 case ACPI_IVHD_TYPE:
488 find_last_devid_from_ivhd(h);
489 break;
490 default:
491 break;
492 }
493 p += h->length;
494 }
495 WARN_ON(p != end);
496
497 return 0;
498}
499
500/****************************************************************************
501 *
502 * The following functions belong to the code path which parses the ACPI table
503 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
504 * data structures, initialize the device/alias/rlookup table and also
505 * basically initialize the hardware.
506 *
507 ****************************************************************************/
508
509/*
510 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
511 * write commands to that buffer later and the IOMMU will execute them
512 * asynchronously
513 */
514static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
515{
516 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
517 get_order(CMD_BUFFER_SIZE));
518
519 if (cmd_buf == NULL)
520 return NULL;
521
522 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
523
524 return cmd_buf;
525}
526
527/*
528 * This function resets the command buffer if the IOMMU stopped fetching
529 * commands from it.
530 */
531void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
532{
533 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
534
535 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
536 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
537
538 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
539}
540
541/*
542 * This function writes the command buffer address to the hardware and
543 * enables it.
544 */
545static void iommu_enable_command_buffer(struct amd_iommu *iommu)
546{
547 u64 entry;
548
549 BUG_ON(iommu->cmd_buf == NULL);
550
551 entry = (u64)virt_to_phys(iommu->cmd_buf);
552 entry |= MMIO_CMD_SIZE_512;
553
554 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
555 &entry, sizeof(entry));
556
557 amd_iommu_reset_cmd_buffer(iommu);
558 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
559}
560
561static void __init free_command_buffer(struct amd_iommu *iommu)
562{
563 free_pages((unsigned long)iommu->cmd_buf,
564 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
565}
566
567/* allocates the memory where the IOMMU will log its events to */
568static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
569{
570 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
571 get_order(EVT_BUFFER_SIZE));
572
573 if (iommu->evt_buf == NULL)
574 return NULL;
575
576 iommu->evt_buf_size = EVT_BUFFER_SIZE;
577
578 return iommu->evt_buf;
579}
580
581static void iommu_enable_event_buffer(struct amd_iommu *iommu)
582{
583 u64 entry;
584
585 BUG_ON(iommu->evt_buf == NULL);
586
587 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
588
589 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
590 &entry, sizeof(entry));
591
592 /* set head and tail to zero manually */
593 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
594 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
595
596 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
597}
598
599static void __init free_event_buffer(struct amd_iommu *iommu)
600{
601 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
602}
603
604/* allocates the memory where the IOMMU will log its events to */
605static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
606{
607 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
608 get_order(PPR_LOG_SIZE));
609
610 if (iommu->ppr_log == NULL)
611 return NULL;
612
613 return iommu->ppr_log;
614}
615
616static void iommu_enable_ppr_log(struct amd_iommu *iommu)
617{
618 u64 entry;
619
620 if (iommu->ppr_log == NULL)
621 return;
622
623 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
624
625 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
626 &entry, sizeof(entry));
627
628 /* set head and tail to zero manually */
629 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
630 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
631
632 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
633 iommu_feature_enable(iommu, CONTROL_PPR_EN);
634}
635
636static void __init free_ppr_log(struct amd_iommu *iommu)
637{
638 if (iommu->ppr_log == NULL)
639 return;
640
641 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
642}
643
644static void iommu_enable_gt(struct amd_iommu *iommu)
645{
646 if (!iommu_feature(iommu, FEATURE_GT))
647 return;
648
649 iommu_feature_enable(iommu, CONTROL_GT_EN);
650}
651
652/* sets a specific bit in the device table entry. */
653static void set_dev_entry_bit(u16 devid, u8 bit)
654{
655 int i = (bit >> 6) & 0x03;
656 int _bit = bit & 0x3f;
657
658 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
659}
660
661static int get_dev_entry_bit(u16 devid, u8 bit)
662{
663 int i = (bit >> 6) & 0x03;
664 int _bit = bit & 0x3f;
665
666 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
667}
668
669
670void amd_iommu_apply_erratum_63(u16 devid)
671{
672 int sysmgt;
673
674 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
675 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
676
677 if (sysmgt == 0x01)
678 set_dev_entry_bit(devid, DEV_ENTRY_IW);
679}
680
681/* Writes the specific IOMMU for a device into the rlookup table */
682static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
683{
684 amd_iommu_rlookup_table[devid] = iommu;
685}
686
687/*
688 * This function takes the device specific flags read from the ACPI
689 * table and sets up the device table entry with that information
690 */
691static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
692 u16 devid, u32 flags, u32 ext_flags)
693{
694 if (flags & ACPI_DEVFLAG_INITPASS)
695 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
696 if (flags & ACPI_DEVFLAG_EXTINT)
697 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
698 if (flags & ACPI_DEVFLAG_NMI)
699 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
700 if (flags & ACPI_DEVFLAG_SYSMGT1)
701 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
702 if (flags & ACPI_DEVFLAG_SYSMGT2)
703 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
704 if (flags & ACPI_DEVFLAG_LINT0)
705 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
706 if (flags & ACPI_DEVFLAG_LINT1)
707 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
708
709 amd_iommu_apply_erratum_63(devid);
710
711 set_iommu_for_device(iommu, devid);
712}
713
714static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line)
715{
716 struct devid_map *entry;
717 struct list_head *list;
718
719 if (type == IVHD_SPECIAL_IOAPIC)
720 list = &ioapic_map;
721 else if (type == IVHD_SPECIAL_HPET)
722 list = &hpet_map;
723 else
724 return -EINVAL;
725
726 list_for_each_entry(entry, list, list) {
727 if (!(entry->id == id && entry->cmd_line))
728 continue;
729
730 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
731 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
732
733 return 0;
734 }
735
736 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
737 if (!entry)
738 return -ENOMEM;
739
740 entry->id = id;
741 entry->devid = devid;
742 entry->cmd_line = cmd_line;
743
744 list_add_tail(&entry->list, list);
745
746 return 0;
747}
748
749static int __init add_early_maps(void)
750{
751 int i, ret;
752
753 for (i = 0; i < early_ioapic_map_size; ++i) {
754 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
755 early_ioapic_map[i].id,
756 early_ioapic_map[i].devid,
757 early_ioapic_map[i].cmd_line);
758 if (ret)
759 return ret;
760 }
761
762 for (i = 0; i < early_hpet_map_size; ++i) {
763 ret = add_special_device(IVHD_SPECIAL_HPET,
764 early_hpet_map[i].id,
765 early_hpet_map[i].devid,
766 early_hpet_map[i].cmd_line);
767 if (ret)
768 return ret;
769 }
770
771 return 0;
772}
773
774/*
775 * Reads the device exclusion range from ACPI and initializes the IOMMU with
776 * it
777 */
778static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
779{
780 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
781
782 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
783 return;
784
785 if (iommu) {
786 /*
787 * We only can configure exclusion ranges per IOMMU, not
788 * per device. But we can enable the exclusion range per
789 * device. This is done here
790 */
791 set_dev_entry_bit(devid, DEV_ENTRY_EX);
792 iommu->exclusion_start = m->range_start;
793 iommu->exclusion_length = m->range_length;
794 }
795}
796
797/*
798 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
799 * initializes the hardware and our data structures with it.
800 */
801static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
802 struct ivhd_header *h)
803{
804 u8 *p = (u8 *)h;
805 u8 *end = p, flags = 0;
806 u16 devid = 0, devid_start = 0, devid_to = 0;
807 u32 dev_i, ext_flags = 0;
808 bool alias = false;
809 struct ivhd_entry *e;
810 int ret;
811
812
813 ret = add_early_maps();
814 if (ret)
815 return ret;
816
817 /*
818 * First save the recommended feature enable bits from ACPI
819 */
820 iommu->acpi_flags = h->flags;
821
822 /*
823 * Done. Now parse the device entries
824 */
825 p += sizeof(struct ivhd_header);
826 end += h->length;
827
828
829 while (p < end) {
830 e = (struct ivhd_entry *)p;
831 switch (e->type) {
832 case IVHD_DEV_ALL:
833
834 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
835 " last device %02x:%02x.%x flags: %02x\n",
836 PCI_BUS_NUM(iommu->first_device),
837 PCI_SLOT(iommu->first_device),
838 PCI_FUNC(iommu->first_device),
839 PCI_BUS_NUM(iommu->last_device),
840 PCI_SLOT(iommu->last_device),
841 PCI_FUNC(iommu->last_device),
842 e->flags);
843
844 for (dev_i = iommu->first_device;
845 dev_i <= iommu->last_device; ++dev_i)
846 set_dev_entry_from_acpi(iommu, dev_i,
847 e->flags, 0);
848 break;
849 case IVHD_DEV_SELECT:
850
851 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
852 "flags: %02x\n",
853 PCI_BUS_NUM(e->devid),
854 PCI_SLOT(e->devid),
855 PCI_FUNC(e->devid),
856 e->flags);
857
858 devid = e->devid;
859 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
860 break;
861 case IVHD_DEV_SELECT_RANGE_START:
862
863 DUMP_printk(" DEV_SELECT_RANGE_START\t "
864 "devid: %02x:%02x.%x flags: %02x\n",
865 PCI_BUS_NUM(e->devid),
866 PCI_SLOT(e->devid),
867 PCI_FUNC(e->devid),
868 e->flags);
869
870 devid_start = e->devid;
871 flags = e->flags;
872 ext_flags = 0;
873 alias = false;
874 break;
875 case IVHD_DEV_ALIAS:
876
877 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
878 "flags: %02x devid_to: %02x:%02x.%x\n",
879 PCI_BUS_NUM(e->devid),
880 PCI_SLOT(e->devid),
881 PCI_FUNC(e->devid),
882 e->flags,
883 PCI_BUS_NUM(e->ext >> 8),
884 PCI_SLOT(e->ext >> 8),
885 PCI_FUNC(e->ext >> 8));
886
887 devid = e->devid;
888 devid_to = e->ext >> 8;
889 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
890 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
891 amd_iommu_alias_table[devid] = devid_to;
892 break;
893 case IVHD_DEV_ALIAS_RANGE:
894
895 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
896 "devid: %02x:%02x.%x flags: %02x "
897 "devid_to: %02x:%02x.%x\n",
898 PCI_BUS_NUM(e->devid),
899 PCI_SLOT(e->devid),
900 PCI_FUNC(e->devid),
901 e->flags,
902 PCI_BUS_NUM(e->ext >> 8),
903 PCI_SLOT(e->ext >> 8),
904 PCI_FUNC(e->ext >> 8));
905
906 devid_start = e->devid;
907 flags = e->flags;
908 devid_to = e->ext >> 8;
909 ext_flags = 0;
910 alias = true;
911 break;
912 case IVHD_DEV_EXT_SELECT:
913
914 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
915 "flags: %02x ext: %08x\n",
916 PCI_BUS_NUM(e->devid),
917 PCI_SLOT(e->devid),
918 PCI_FUNC(e->devid),
919 e->flags, e->ext);
920
921 devid = e->devid;
922 set_dev_entry_from_acpi(iommu, devid, e->flags,
923 e->ext);
924 break;
925 case IVHD_DEV_EXT_SELECT_RANGE:
926
927 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
928 "%02x:%02x.%x flags: %02x ext: %08x\n",
929 PCI_BUS_NUM(e->devid),
930 PCI_SLOT(e->devid),
931 PCI_FUNC(e->devid),
932 e->flags, e->ext);
933
934 devid_start = e->devid;
935 flags = e->flags;
936 ext_flags = e->ext;
937 alias = false;
938 break;
939 case IVHD_DEV_RANGE_END:
940
941 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
942 PCI_BUS_NUM(e->devid),
943 PCI_SLOT(e->devid),
944 PCI_FUNC(e->devid));
945
946 devid = e->devid;
947 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
948 if (alias) {
949 amd_iommu_alias_table[dev_i] = devid_to;
950 set_dev_entry_from_acpi(iommu,
951 devid_to, flags, ext_flags);
952 }
953 set_dev_entry_from_acpi(iommu, dev_i,
954 flags, ext_flags);
955 }
956 break;
957 case IVHD_DEV_SPECIAL: {
958 u8 handle, type;
959 const char *var;
960 u16 devid;
961 int ret;
962
963 handle = e->ext & 0xff;
964 devid = (e->ext >> 8) & 0xffff;
965 type = (e->ext >> 24) & 0xff;
966
967 if (type == IVHD_SPECIAL_IOAPIC)
968 var = "IOAPIC";
969 else if (type == IVHD_SPECIAL_HPET)
970 var = "HPET";
971 else
972 var = "UNKNOWN";
973
974 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
975 var, (int)handle,
976 PCI_BUS_NUM(devid),
977 PCI_SLOT(devid),
978 PCI_FUNC(devid));
979
980 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
981 ret = add_special_device(type, handle, devid, false);
982 if (ret)
983 return ret;
984 break;
985 }
986 default:
987 break;
988 }
989
990 p += ivhd_entry_length(p);
991 }
992
993 return 0;
994}
995
996/* Initializes the device->iommu mapping for the driver */
997static int __init init_iommu_devices(struct amd_iommu *iommu)
998{
999 u32 i;
1000
1001 for (i = iommu->first_device; i <= iommu->last_device; ++i)
1002 set_iommu_for_device(iommu, i);
1003
1004 return 0;
1005}
1006
1007static void __init free_iommu_one(struct amd_iommu *iommu)
1008{
1009 free_command_buffer(iommu);
1010 free_event_buffer(iommu);
1011 free_ppr_log(iommu);
1012 iommu_unmap_mmio_space(iommu);
1013}
1014
1015static void __init free_iommu_all(void)
1016{
1017 struct amd_iommu *iommu, *next;
1018
1019 for_each_iommu_safe(iommu, next) {
1020 list_del(&iommu->list);
1021 free_iommu_one(iommu);
1022 kfree(iommu);
1023 }
1024}
1025
1026/*
1027 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1028 * Workaround:
1029 * BIOS should disable L2B micellaneous clock gating by setting
1030 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1031 */
1032static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1033{
1034 u32 value;
1035
1036 if ((boot_cpu_data.x86 != 0x15) ||
1037 (boot_cpu_data.x86_model < 0x10) ||
1038 (boot_cpu_data.x86_model > 0x1f))
1039 return;
1040
1041 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1042 pci_read_config_dword(iommu->dev, 0xf4, &value);
1043
1044 if (value & BIT(2))
1045 return;
1046
1047 /* Select NB indirect register 0x90 and enable writing */
1048 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1049
1050 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1051 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1052 dev_name(&iommu->dev->dev));
1053
1054 /* Clear the enable writing bit */
1055 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1056}
1057
1058/*
1059 * This function clues the initialization function for one IOMMU
1060 * together and also allocates the command buffer and programs the
1061 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1062 */
1063static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1064{
1065 int ret;
1066
1067 spin_lock_init(&iommu->lock);
1068
1069 /* Add IOMMU to internal data structures */
1070 list_add_tail(&iommu->list, &amd_iommu_list);
1071 iommu->index = amd_iommus_present++;
1072
1073 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1074 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1075 return -ENOSYS;
1076 }
1077
1078 /* Index is fine - add IOMMU to the array */
1079 amd_iommus[iommu->index] = iommu;
1080
1081 /*
1082 * Copy data from ACPI table entry to the iommu struct
1083 */
1084 iommu->devid = h->devid;
1085 iommu->cap_ptr = h->cap_ptr;
1086 iommu->pci_seg = h->pci_seg;
1087 iommu->mmio_phys = h->mmio_phys;
1088
1089 /* Check if IVHD EFR contains proper max banks/counters */
1090 if ((h->efr != 0) &&
1091 ((h->efr & (0xF << 13)) != 0) &&
1092 ((h->efr & (0x3F << 17)) != 0)) {
1093 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1094 } else {
1095 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1096 }
1097
1098 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1099 iommu->mmio_phys_end);
1100 if (!iommu->mmio_base)
1101 return -ENOMEM;
1102
1103 iommu->cmd_buf = alloc_command_buffer(iommu);
1104 if (!iommu->cmd_buf)
1105 return -ENOMEM;
1106
1107 iommu->evt_buf = alloc_event_buffer(iommu);
1108 if (!iommu->evt_buf)
1109 return -ENOMEM;
1110
1111 iommu->int_enabled = false;
1112
1113 ret = init_iommu_from_acpi(iommu, h);
1114 if (ret)
1115 return ret;
1116
1117 /*
1118 * Make sure IOMMU is not considered to translate itself. The IVRS
1119 * table tells us so, but this is a lie!
1120 */
1121 amd_iommu_rlookup_table[iommu->devid] = NULL;
1122
1123 init_iommu_devices(iommu);
1124
1125 return 0;
1126}
1127
1128/*
1129 * Iterates over all IOMMU entries in the ACPI table, allocates the
1130 * IOMMU structure and initializes it with init_iommu_one()
1131 */
1132static int __init init_iommu_all(struct acpi_table_header *table)
1133{
1134 u8 *p = (u8 *)table, *end = (u8 *)table;
1135 struct ivhd_header *h;
1136 struct amd_iommu *iommu;
1137 int ret;
1138
1139 end += table->length;
1140 p += IVRS_HEADER_LENGTH;
1141
1142 while (p < end) {
1143 h = (struct ivhd_header *)p;
1144 switch (*p) {
1145 case ACPI_IVHD_TYPE:
1146
1147 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1148 "seg: %d flags: %01x info %04x\n",
1149 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1150 PCI_FUNC(h->devid), h->cap_ptr,
1151 h->pci_seg, h->flags, h->info);
1152 DUMP_printk(" mmio-addr: %016llx\n",
1153 h->mmio_phys);
1154
1155 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1156 if (iommu == NULL)
1157 return -ENOMEM;
1158
1159 ret = init_iommu_one(iommu, h);
1160 if (ret)
1161 return ret;
1162 break;
1163 default:
1164 break;
1165 }
1166 p += h->length;
1167
1168 }
1169 WARN_ON(p != end);
1170
1171 return 0;
1172}
1173
1174
1175static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1176{
1177 u64 val = 0xabcd, val2 = 0;
1178
1179 if (!iommu_feature(iommu, FEATURE_PC))
1180 return;
1181
1182 amd_iommu_pc_present = true;
1183
1184 /* Check if the performance counters can be written to */
1185 if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
1186 (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
1187 (val != val2)) {
1188 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1189 amd_iommu_pc_present = false;
1190 return;
1191 }
1192
1193 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1194
1195 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1196 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1197 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1198}
1199
1200
1201static int iommu_init_pci(struct amd_iommu *iommu)
1202{
1203 int cap_ptr = iommu->cap_ptr;
1204 u32 range, misc, low, high;
1205
1206 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1207 iommu->devid & 0xff);
1208 if (!iommu->dev)
1209 return -ENODEV;
1210
1211 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1212 &iommu->cap);
1213 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1214 &range);
1215 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1216 &misc);
1217
1218 iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range),
1219 MMIO_GET_FD(range));
1220 iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range),
1221 MMIO_GET_LD(range));
1222
1223 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1224 amd_iommu_iotlb_sup = false;
1225
1226 /* read extended feature bits */
1227 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1228 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1229
1230 iommu->features = ((u64)high << 32) | low;
1231
1232 if (iommu_feature(iommu, FEATURE_GT)) {
1233 int glxval;
1234 u32 max_pasid;
1235 u64 pasmax;
1236
1237 pasmax = iommu->features & FEATURE_PASID_MASK;
1238 pasmax >>= FEATURE_PASID_SHIFT;
1239 max_pasid = (1 << (pasmax + 1)) - 1;
1240
1241 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1242
1243 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1244
1245 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1246 glxval >>= FEATURE_GLXVAL_SHIFT;
1247
1248 if (amd_iommu_max_glx_val == -1)
1249 amd_iommu_max_glx_val = glxval;
1250 else
1251 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1252 }
1253
1254 if (iommu_feature(iommu, FEATURE_GT) &&
1255 iommu_feature(iommu, FEATURE_PPR)) {
1256 iommu->is_iommu_v2 = true;
1257 amd_iommu_v2_present = true;
1258 }
1259
1260 if (iommu_feature(iommu, FEATURE_PPR)) {
1261 iommu->ppr_log = alloc_ppr_log(iommu);
1262 if (!iommu->ppr_log)
1263 return -ENOMEM;
1264 }
1265
1266 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1267 amd_iommu_np_cache = true;
1268
1269 init_iommu_perf_ctr(iommu);
1270
1271 if (is_rd890_iommu(iommu->dev)) {
1272 int i, j;
1273
1274 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1275 PCI_DEVFN(0, 0));
1276
1277 /*
1278 * Some rd890 systems may not be fully reconfigured by the
1279 * BIOS, so it's necessary for us to store this information so
1280 * it can be reprogrammed on resume
1281 */
1282 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1283 &iommu->stored_addr_lo);
1284 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1285 &iommu->stored_addr_hi);
1286
1287 /* Low bit locks writes to configuration space */
1288 iommu->stored_addr_lo &= ~1;
1289
1290 for (i = 0; i < 6; i++)
1291 for (j = 0; j < 0x12; j++)
1292 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1293
1294 for (i = 0; i < 0x83; i++)
1295 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1296 }
1297
1298 amd_iommu_erratum_746_workaround(iommu);
1299
1300 return pci_enable_device(iommu->dev);
1301}
1302
1303static void print_iommu_info(void)
1304{
1305 static const char * const feat_str[] = {
1306 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1307 "IA", "GA", "HE", "PC"
1308 };
1309 struct amd_iommu *iommu;
1310
1311 for_each_iommu(iommu) {
1312 int i;
1313
1314 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1315 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1316
1317 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1318 pr_info("AMD-Vi: Extended features: ");
1319 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1320 if (iommu_feature(iommu, (1ULL << i)))
1321 pr_cont(" %s", feat_str[i]);
1322 }
1323 pr_cont("\n");
1324 }
1325 }
1326 if (irq_remapping_enabled)
1327 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1328}
1329
1330static int __init amd_iommu_init_pci(void)
1331{
1332 struct amd_iommu *iommu;
1333 int ret = 0;
1334
1335 for_each_iommu(iommu) {
1336 ret = iommu_init_pci(iommu);
1337 if (ret)
1338 break;
1339 }
1340
1341 ret = amd_iommu_init_devices();
1342
1343 print_iommu_info();
1344
1345 return ret;
1346}
1347
1348/****************************************************************************
1349 *
1350 * The following functions initialize the MSI interrupts for all IOMMUs
1351 * in the system. It's a bit challenging because there could be multiple
1352 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1353 * pci_dev.
1354 *
1355 ****************************************************************************/
1356
1357static int iommu_setup_msi(struct amd_iommu *iommu)
1358{
1359 int r;
1360
1361 r = pci_enable_msi(iommu->dev);
1362 if (r)
1363 return r;
1364
1365 r = request_threaded_irq(iommu->dev->irq,
1366 amd_iommu_int_handler,
1367 amd_iommu_int_thread,
1368 0, "AMD-Vi",
1369 iommu);
1370
1371 if (r) {
1372 pci_disable_msi(iommu->dev);
1373 return r;
1374 }
1375
1376 iommu->int_enabled = true;
1377
1378 return 0;
1379}
1380
1381static int iommu_init_msi(struct amd_iommu *iommu)
1382{
1383 int ret;
1384
1385 if (iommu->int_enabled)
1386 goto enable_faults;
1387
1388 if (iommu->dev->msi_cap)
1389 ret = iommu_setup_msi(iommu);
1390 else
1391 ret = -ENODEV;
1392
1393 if (ret)
1394 return ret;
1395
1396enable_faults:
1397 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1398
1399 if (iommu->ppr_log != NULL)
1400 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1401
1402 return 0;
1403}
1404
1405/****************************************************************************
1406 *
1407 * The next functions belong to the third pass of parsing the ACPI
1408 * table. In this last pass the memory mapping requirements are
1409 * gathered (like exclusion and unity mapping ranges).
1410 *
1411 ****************************************************************************/
1412
1413static void __init free_unity_maps(void)
1414{
1415 struct unity_map_entry *entry, *next;
1416
1417 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1418 list_del(&entry->list);
1419 kfree(entry);
1420 }
1421}
1422
1423/* called when we find an exclusion range definition in ACPI */
1424static int __init init_exclusion_range(struct ivmd_header *m)
1425{
1426 int i;
1427
1428 switch (m->type) {
1429 case ACPI_IVMD_TYPE:
1430 set_device_exclusion_range(m->devid, m);
1431 break;
1432 case ACPI_IVMD_TYPE_ALL:
1433 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1434 set_device_exclusion_range(i, m);
1435 break;
1436 case ACPI_IVMD_TYPE_RANGE:
1437 for (i = m->devid; i <= m->aux; ++i)
1438 set_device_exclusion_range(i, m);
1439 break;
1440 default:
1441 break;
1442 }
1443
1444 return 0;
1445}
1446
1447/* called for unity map ACPI definition */
1448static int __init init_unity_map_range(struct ivmd_header *m)
1449{
1450 struct unity_map_entry *e = NULL;
1451 char *s;
1452
1453 e = kzalloc(sizeof(*e), GFP_KERNEL);
1454 if (e == NULL)
1455 return -ENOMEM;
1456
1457 switch (m->type) {
1458 default:
1459 kfree(e);
1460 return 0;
1461 case ACPI_IVMD_TYPE:
1462 s = "IVMD_TYPEi\t\t\t";
1463 e->devid_start = e->devid_end = m->devid;
1464 break;
1465 case ACPI_IVMD_TYPE_ALL:
1466 s = "IVMD_TYPE_ALL\t\t";
1467 e->devid_start = 0;
1468 e->devid_end = amd_iommu_last_bdf;
1469 break;
1470 case ACPI_IVMD_TYPE_RANGE:
1471 s = "IVMD_TYPE_RANGE\t\t";
1472 e->devid_start = m->devid;
1473 e->devid_end = m->aux;
1474 break;
1475 }
1476 e->address_start = PAGE_ALIGN(m->range_start);
1477 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1478 e->prot = m->flags >> 1;
1479
1480 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1481 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1482 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1483 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1484 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1485 e->address_start, e->address_end, m->flags);
1486
1487 list_add_tail(&e->list, &amd_iommu_unity_map);
1488
1489 return 0;
1490}
1491
1492/* iterates over all memory definitions we find in the ACPI table */
1493static int __init init_memory_definitions(struct acpi_table_header *table)
1494{
1495 u8 *p = (u8 *)table, *end = (u8 *)table;
1496 struct ivmd_header *m;
1497
1498 end += table->length;
1499 p += IVRS_HEADER_LENGTH;
1500
1501 while (p < end) {
1502 m = (struct ivmd_header *)p;
1503 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1504 init_exclusion_range(m);
1505 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1506 init_unity_map_range(m);
1507
1508 p += m->length;
1509 }
1510
1511 return 0;
1512}
1513
1514/*
1515 * Init the device table to not allow DMA access for devices and
1516 * suppress all page faults
1517 */
1518static void init_device_table_dma(void)
1519{
1520 u32 devid;
1521
1522 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1523 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1524 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1525 }
1526}
1527
1528static void __init uninit_device_table_dma(void)
1529{
1530 u32 devid;
1531
1532 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1533 amd_iommu_dev_table[devid].data[0] = 0ULL;
1534 amd_iommu_dev_table[devid].data[1] = 0ULL;
1535 }
1536}
1537
1538static void init_device_table(void)
1539{
1540 u32 devid;
1541
1542 if (!amd_iommu_irq_remap)
1543 return;
1544
1545 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1546 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1547}
1548
1549static void iommu_init_flags(struct amd_iommu *iommu)
1550{
1551 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1552 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1553 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1554
1555 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1556 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1557 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1558
1559 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1560 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1561 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1562
1563 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1564 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1565 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1566
1567 /*
1568 * make IOMMU memory accesses cache coherent
1569 */
1570 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1571
1572 /* Set IOTLB invalidation timeout to 1s */
1573 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1574}
1575
1576static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1577{
1578 int i, j;
1579 u32 ioc_feature_control;
1580 struct pci_dev *pdev = iommu->root_pdev;
1581
1582 /* RD890 BIOSes may not have completely reconfigured the iommu */
1583 if (!is_rd890_iommu(iommu->dev) || !pdev)
1584 return;
1585
1586 /*
1587 * First, we need to ensure that the iommu is enabled. This is
1588 * controlled by a register in the northbridge
1589 */
1590
1591 /* Select Northbridge indirect register 0x75 and enable writing */
1592 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1593 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1594
1595 /* Enable the iommu */
1596 if (!(ioc_feature_control & 0x1))
1597 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1598
1599 /* Restore the iommu BAR */
1600 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1601 iommu->stored_addr_lo);
1602 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1603 iommu->stored_addr_hi);
1604
1605 /* Restore the l1 indirect regs for each of the 6 l1s */
1606 for (i = 0; i < 6; i++)
1607 for (j = 0; j < 0x12; j++)
1608 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1609
1610 /* Restore the l2 indirect regs */
1611 for (i = 0; i < 0x83; i++)
1612 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1613
1614 /* Lock PCI setup registers */
1615 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1616 iommu->stored_addr_lo | 1);
1617}
1618
1619/*
1620 * This function finally enables all IOMMUs found in the system after
1621 * they have been initialized
1622 */
1623static void early_enable_iommus(void)
1624{
1625 struct amd_iommu *iommu;
1626
1627 for_each_iommu(iommu) {
1628 iommu_disable(iommu);
1629 iommu_init_flags(iommu);
1630 iommu_set_device_table(iommu);
1631 iommu_enable_command_buffer(iommu);
1632 iommu_enable_event_buffer(iommu);
1633 iommu_set_exclusion_range(iommu);
1634 iommu_enable(iommu);
1635 iommu_flush_all_caches(iommu);
1636 }
1637}
1638
1639static void enable_iommus_v2(void)
1640{
1641 struct amd_iommu *iommu;
1642
1643 for_each_iommu(iommu) {
1644 iommu_enable_ppr_log(iommu);
1645 iommu_enable_gt(iommu);
1646 }
1647}
1648
1649static void enable_iommus(void)
1650{
1651 early_enable_iommus();
1652
1653 enable_iommus_v2();
1654}
1655
1656static void disable_iommus(void)
1657{
1658 struct amd_iommu *iommu;
1659
1660 for_each_iommu(iommu)
1661 iommu_disable(iommu);
1662}
1663
1664/*
1665 * Suspend/Resume support
1666 * disable suspend until real resume implemented
1667 */
1668
1669static void amd_iommu_resume(void)
1670{
1671 struct amd_iommu *iommu;
1672
1673 for_each_iommu(iommu)
1674 iommu_apply_resume_quirks(iommu);
1675
1676 /* re-load the hardware */
1677 enable_iommus();
1678
1679 amd_iommu_enable_interrupts();
1680}
1681
1682static int amd_iommu_suspend(void)
1683{
1684 /* disable IOMMUs to go out of the way for BIOS */
1685 disable_iommus();
1686
1687 return 0;
1688}
1689
1690static struct syscore_ops amd_iommu_syscore_ops = {
1691 .suspend = amd_iommu_suspend,
1692 .resume = amd_iommu_resume,
1693};
1694
1695static void __init free_on_init_error(void)
1696{
1697 free_pages((unsigned long)irq_lookup_table,
1698 get_order(rlookup_table_size));
1699
1700 if (amd_iommu_irq_cache) {
1701 kmem_cache_destroy(amd_iommu_irq_cache);
1702 amd_iommu_irq_cache = NULL;
1703
1704 }
1705
1706 free_pages((unsigned long)amd_iommu_rlookup_table,
1707 get_order(rlookup_table_size));
1708
1709 free_pages((unsigned long)amd_iommu_alias_table,
1710 get_order(alias_table_size));
1711
1712 free_pages((unsigned long)amd_iommu_dev_table,
1713 get_order(dev_table_size));
1714
1715 free_iommu_all();
1716
1717#ifdef CONFIG_GART_IOMMU
1718 /*
1719 * We failed to initialize the AMD IOMMU - try fallback to GART
1720 * if possible.
1721 */
1722 gart_iommu_init();
1723
1724#endif
1725}
1726
1727/* SB IOAPIC is always on this device in AMD systems */
1728#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1729
1730static bool __init check_ioapic_information(void)
1731{
1732 const char *fw_bug = FW_BUG;
1733 bool ret, has_sb_ioapic;
1734 int idx;
1735
1736 has_sb_ioapic = false;
1737 ret = false;
1738
1739 /*
1740 * If we have map overrides on the kernel command line the
1741 * messages in this function might not describe firmware bugs
1742 * anymore - so be careful
1743 */
1744 if (cmdline_maps)
1745 fw_bug = "";
1746
1747 for (idx = 0; idx < nr_ioapics; idx++) {
1748 int devid, id = mpc_ioapic_id(idx);
1749
1750 devid = get_ioapic_devid(id);
1751 if (devid < 0) {
1752 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1753 fw_bug, id);
1754 ret = false;
1755 } else if (devid == IOAPIC_SB_DEVID) {
1756 has_sb_ioapic = true;
1757 ret = true;
1758 }
1759 }
1760
1761 if (!has_sb_ioapic) {
1762 /*
1763 * We expect the SB IOAPIC to be listed in the IVRS
1764 * table. The system timer is connected to the SB IOAPIC
1765 * and if we don't have it in the list the system will
1766 * panic at boot time. This situation usually happens
1767 * when the BIOS is buggy and provides us the wrong
1768 * device id for the IOAPIC in the system.
1769 */
1770 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1771 }
1772
1773 if (!ret)
1774 pr_err("AMD-Vi: Disabling interrupt remapping\n");
1775
1776 return ret;
1777}
1778
1779static void __init free_dma_resources(void)
1780{
1781 amd_iommu_uninit_devices();
1782
1783 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1784 get_order(MAX_DOMAIN_ID/8));
1785
1786 free_unity_maps();
1787}
1788
1789/*
1790 * This is the hardware init function for AMD IOMMU in the system.
1791 * This function is called either from amd_iommu_init or from the interrupt
1792 * remapping setup code.
1793 *
1794 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1795 * three times:
1796 *
1797 * 1 pass) Find the highest PCI device id the driver has to handle.
1798 * Upon this information the size of the data structures is
1799 * determined that needs to be allocated.
1800 *
1801 * 2 pass) Initialize the data structures just allocated with the
1802 * information in the ACPI table about available AMD IOMMUs
1803 * in the system. It also maps the PCI devices in the
1804 * system to specific IOMMUs
1805 *
1806 * 3 pass) After the basic data structures are allocated and
1807 * initialized we update them with information about memory
1808 * remapping requirements parsed out of the ACPI table in
1809 * this last pass.
1810 *
1811 * After everything is set up the IOMMUs are enabled and the necessary
1812 * hotplug and suspend notifiers are registered.
1813 */
1814static int __init early_amd_iommu_init(void)
1815{
1816 struct acpi_table_header *ivrs_base;
1817 acpi_size ivrs_size;
1818 acpi_status status;
1819 int i, ret = 0;
1820
1821 if (!amd_iommu_detected)
1822 return -ENODEV;
1823
1824 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1825 if (status == AE_NOT_FOUND)
1826 return -ENODEV;
1827 else if (ACPI_FAILURE(status)) {
1828 const char *err = acpi_format_exception(status);
1829 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1830 return -EINVAL;
1831 }
1832
1833 /*
1834 * First parse ACPI tables to find the largest Bus/Dev/Func
1835 * we need to handle. Upon this information the shared data
1836 * structures for the IOMMUs in the system will be allocated
1837 */
1838 ret = find_last_devid_acpi(ivrs_base);
1839 if (ret)
1840 goto out;
1841
1842 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1843 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1844 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1845
1846 /* Device table - directly used by all IOMMUs */
1847 ret = -ENOMEM;
1848 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1849 get_order(dev_table_size));
1850 if (amd_iommu_dev_table == NULL)
1851 goto out;
1852
1853 /*
1854 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1855 * IOMMU see for that device
1856 */
1857 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1858 get_order(alias_table_size));
1859 if (amd_iommu_alias_table == NULL)
1860 goto out;
1861
1862 /* IOMMU rlookup table - find the IOMMU for a specific device */
1863 amd_iommu_rlookup_table = (void *)__get_free_pages(
1864 GFP_KERNEL | __GFP_ZERO,
1865 get_order(rlookup_table_size));
1866 if (amd_iommu_rlookup_table == NULL)
1867 goto out;
1868
1869 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1870 GFP_KERNEL | __GFP_ZERO,
1871 get_order(MAX_DOMAIN_ID/8));
1872 if (amd_iommu_pd_alloc_bitmap == NULL)
1873 goto out;
1874
1875 /*
1876 * let all alias entries point to itself
1877 */
1878 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1879 amd_iommu_alias_table[i] = i;
1880
1881 /*
1882 * never allocate domain 0 because its used as the non-allocated and
1883 * error value placeholder
1884 */
1885 amd_iommu_pd_alloc_bitmap[0] = 1;
1886
1887 spin_lock_init(&amd_iommu_pd_lock);
1888
1889 /*
1890 * now the data structures are allocated and basically initialized
1891 * start the real acpi table scan
1892 */
1893 ret = init_iommu_all(ivrs_base);
1894 if (ret)
1895 goto out;
1896
1897 if (amd_iommu_irq_remap)
1898 amd_iommu_irq_remap = check_ioapic_information();
1899
1900 if (amd_iommu_irq_remap) {
1901 /*
1902 * Interrupt remapping enabled, create kmem_cache for the
1903 * remapping tables.
1904 */
1905 ret = -ENOMEM;
1906 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1907 MAX_IRQS_PER_TABLE * sizeof(u32),
1908 IRQ_TABLE_ALIGNMENT,
1909 0, NULL);
1910 if (!amd_iommu_irq_cache)
1911 goto out;
1912
1913 irq_lookup_table = (void *)__get_free_pages(
1914 GFP_KERNEL | __GFP_ZERO,
1915 get_order(rlookup_table_size));
1916 if (!irq_lookup_table)
1917 goto out;
1918 }
1919
1920 ret = init_memory_definitions(ivrs_base);
1921 if (ret)
1922 goto out;
1923
1924 /* init the device table */
1925 init_device_table();
1926
1927out:
1928 /* Don't leak any ACPI memory */
1929 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1930 ivrs_base = NULL;
1931
1932 return ret;
1933}
1934
1935static int amd_iommu_enable_interrupts(void)
1936{
1937 struct amd_iommu *iommu;
1938 int ret = 0;
1939
1940 for_each_iommu(iommu) {
1941 ret = iommu_init_msi(iommu);
1942 if (ret)
1943 goto out;
1944 }
1945
1946out:
1947 return ret;
1948}
1949
1950static bool detect_ivrs(void)
1951{
1952 struct acpi_table_header *ivrs_base;
1953 acpi_size ivrs_size;
1954 acpi_status status;
1955
1956 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1957 if (status == AE_NOT_FOUND)
1958 return false;
1959 else if (ACPI_FAILURE(status)) {
1960 const char *err = acpi_format_exception(status);
1961 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1962 return false;
1963 }
1964
1965 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1966
1967 /* Make sure ACS will be enabled during PCI probe */
1968 pci_request_acs();
1969
1970 if (!disable_irq_remap)
1971 amd_iommu_irq_remap = true;
1972
1973 return true;
1974}
1975
1976static int amd_iommu_init_dma(void)
1977{
1978 struct amd_iommu *iommu;
1979 int ret;
1980
1981 if (iommu_pass_through)
1982 ret = amd_iommu_init_passthrough();
1983 else
1984 ret = amd_iommu_init_dma_ops();
1985
1986 if (ret)
1987 return ret;
1988
1989 init_device_table_dma();
1990
1991 for_each_iommu(iommu)
1992 iommu_flush_all_caches(iommu);
1993
1994 amd_iommu_init_api();
1995
1996 amd_iommu_init_notifier();
1997
1998 return 0;
1999}
2000
2001/****************************************************************************
2002 *
2003 * AMD IOMMU Initialization State Machine
2004 *
2005 ****************************************************************************/
2006
2007static int __init state_next(void)
2008{
2009 int ret = 0;
2010
2011 switch (init_state) {
2012 case IOMMU_START_STATE:
2013 if (!detect_ivrs()) {
2014 init_state = IOMMU_NOT_FOUND;
2015 ret = -ENODEV;
2016 } else {
2017 init_state = IOMMU_IVRS_DETECTED;
2018 }
2019 break;
2020 case IOMMU_IVRS_DETECTED:
2021 ret = early_amd_iommu_init();
2022 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2023 break;
2024 case IOMMU_ACPI_FINISHED:
2025 early_enable_iommus();
2026 register_syscore_ops(&amd_iommu_syscore_ops);
2027 x86_platform.iommu_shutdown = disable_iommus;
2028 init_state = IOMMU_ENABLED;
2029 break;
2030 case IOMMU_ENABLED:
2031 ret = amd_iommu_init_pci();
2032 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2033 enable_iommus_v2();
2034 break;
2035 case IOMMU_PCI_INIT:
2036 ret = amd_iommu_enable_interrupts();
2037 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2038 break;
2039 case IOMMU_INTERRUPTS_EN:
2040 ret = amd_iommu_init_dma();
2041 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2042 break;
2043 case IOMMU_DMA_OPS:
2044 init_state = IOMMU_INITIALIZED;
2045 break;
2046 case IOMMU_INITIALIZED:
2047 /* Nothing to do */
2048 break;
2049 case IOMMU_NOT_FOUND:
2050 case IOMMU_INIT_ERROR:
2051 /* Error states => do nothing */
2052 ret = -EINVAL;
2053 break;
2054 default:
2055 /* Unknown state */
2056 BUG();
2057 }
2058
2059 return ret;
2060}
2061
2062static int __init iommu_go_to_state(enum iommu_init_state state)
2063{
2064 int ret = 0;
2065
2066 while (init_state != state) {
2067 ret = state_next();
2068 if (init_state == IOMMU_NOT_FOUND ||
2069 init_state == IOMMU_INIT_ERROR)
2070 break;
2071 }
2072
2073 return ret;
2074}
2075
2076#ifdef CONFIG_IRQ_REMAP
2077int __init amd_iommu_prepare(void)
2078{
2079 return iommu_go_to_state(IOMMU_ACPI_FINISHED);
2080}
2081
2082int __init amd_iommu_supported(void)
2083{
2084 return amd_iommu_irq_remap ? 1 : 0;
2085}
2086
2087int __init amd_iommu_enable(void)
2088{
2089 int ret;
2090
2091 ret = iommu_go_to_state(IOMMU_ENABLED);
2092 if (ret)
2093 return ret;
2094
2095 irq_remapping_enabled = 1;
2096
2097 return 0;
2098}
2099
2100void amd_iommu_disable(void)
2101{
2102 amd_iommu_suspend();
2103}
2104
2105int amd_iommu_reenable(int mode)
2106{
2107 amd_iommu_resume();
2108
2109 return 0;
2110}
2111
2112int __init amd_iommu_enable_faulting(void)
2113{
2114 /* We enable MSI later when PCI is initialized */
2115 return 0;
2116}
2117#endif
2118
2119/*
2120 * This is the core init function for AMD IOMMU hardware in the system.
2121 * This function is called from the generic x86 DMA layer initialization
2122 * code.
2123 */
2124static int __init amd_iommu_init(void)
2125{
2126 int ret;
2127
2128 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2129 if (ret) {
2130 free_dma_resources();
2131 if (!irq_remapping_enabled) {
2132 disable_iommus();
2133 free_on_init_error();
2134 } else {
2135 struct amd_iommu *iommu;
2136
2137 uninit_device_table_dma();
2138 for_each_iommu(iommu)
2139 iommu_flush_all_caches(iommu);
2140 }
2141 }
2142
2143 return ret;
2144}
2145
2146/****************************************************************************
2147 *
2148 * Early detect code. This code runs at IOMMU detection time in the DMA
2149 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2150 * IOMMUs
2151 *
2152 ****************************************************************************/
2153int __init amd_iommu_detect(void)
2154{
2155 int ret;
2156
2157 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2158 return -ENODEV;
2159
2160 if (amd_iommu_disabled)
2161 return -ENODEV;
2162
2163 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2164 if (ret)
2165 return ret;
2166
2167 amd_iommu_detected = true;
2168 iommu_detected = 1;
2169 x86_init.iommu.iommu_init = amd_iommu_init;
2170
2171 return 0;
2172}
2173
2174/****************************************************************************
2175 *
2176 * Parsing functions for the AMD IOMMU specific kernel command line
2177 * options.
2178 *
2179 ****************************************************************************/
2180
2181static int __init parse_amd_iommu_dump(char *str)
2182{
2183 amd_iommu_dump = true;
2184
2185 return 1;
2186}
2187
2188static int __init parse_amd_iommu_options(char *str)
2189{
2190 for (; *str; ++str) {
2191 if (strncmp(str, "fullflush", 9) == 0)
2192 amd_iommu_unmap_flush = true;
2193 if (strncmp(str, "off", 3) == 0)
2194 amd_iommu_disabled = true;
2195 if (strncmp(str, "force_isolation", 15) == 0)
2196 amd_iommu_force_isolation = true;
2197 }
2198
2199 return 1;
2200}
2201
2202static int __init parse_ivrs_ioapic(char *str)
2203{
2204 unsigned int bus, dev, fn;
2205 int ret, id, i;
2206 u16 devid;
2207
2208 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2209
2210 if (ret != 4) {
2211 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2212 return 1;
2213 }
2214
2215 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2216 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2217 str);
2218 return 1;
2219 }
2220
2221 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2222
2223 cmdline_maps = true;
2224 i = early_ioapic_map_size++;
2225 early_ioapic_map[i].id = id;
2226 early_ioapic_map[i].devid = devid;
2227 early_ioapic_map[i].cmd_line = true;
2228
2229 return 1;
2230}
2231
2232static int __init parse_ivrs_hpet(char *str)
2233{
2234 unsigned int bus, dev, fn;
2235 int ret, id, i;
2236 u16 devid;
2237
2238 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2239
2240 if (ret != 4) {
2241 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2242 return 1;
2243 }
2244
2245 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2246 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2247 str);
2248 return 1;
2249 }
2250
2251 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2252
2253 cmdline_maps = true;
2254 i = early_hpet_map_size++;
2255 early_hpet_map[i].id = id;
2256 early_hpet_map[i].devid = devid;
2257 early_hpet_map[i].cmd_line = true;
2258
2259 return 1;
2260}
2261
2262__setup("amd_iommu_dump", parse_amd_iommu_dump);
2263__setup("amd_iommu=", parse_amd_iommu_options);
2264__setup("ivrs_ioapic", parse_ivrs_ioapic);
2265__setup("ivrs_hpet", parse_ivrs_hpet);
2266
2267IOMMU_INIT_FINISH(amd_iommu_detect,
2268 gart_iommu_hole_init,
2269 NULL,
2270 NULL);
2271
2272bool amd_iommu_v2_supported(void)
2273{
2274 return amd_iommu_v2_present;
2275}
2276EXPORT_SYMBOL(amd_iommu_v2_supported);
2277
2278/****************************************************************************
2279 *
2280 * IOMMU EFR Performance Counter support functionality. This code allows
2281 * access to the IOMMU PC functionality.
2282 *
2283 ****************************************************************************/
2284
2285u8 amd_iommu_pc_get_max_banks(u16 devid)
2286{
2287 struct amd_iommu *iommu;
2288 u8 ret = 0;
2289
2290 /* locate the iommu governing the devid */
2291 iommu = amd_iommu_rlookup_table[devid];
2292 if (iommu)
2293 ret = iommu->max_banks;
2294
2295 return ret;
2296}
2297EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2298
2299bool amd_iommu_pc_supported(void)
2300{
2301 return amd_iommu_pc_present;
2302}
2303EXPORT_SYMBOL(amd_iommu_pc_supported);
2304
2305u8 amd_iommu_pc_get_max_counters(u16 devid)
2306{
2307 struct amd_iommu *iommu;
2308 u8 ret = 0;
2309
2310 /* locate the iommu governing the devid */
2311 iommu = amd_iommu_rlookup_table[devid];
2312 if (iommu)
2313 ret = iommu->max_counters;
2314
2315 return ret;
2316}
2317EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2318
2319int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2320 u64 *value, bool is_write)
2321{
2322 struct amd_iommu *iommu;
2323 u32 offset;
2324 u32 max_offset_lim;
2325
2326 /* Make sure the IOMMU PC resource is available */
2327 if (!amd_iommu_pc_present)
2328 return -ENODEV;
2329
2330 /* Locate the iommu associated with the device ID */
2331 iommu = amd_iommu_rlookup_table[devid];
2332
2333 /* Check for valid iommu and pc register indexing */
2334 if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
2335 return -ENODEV;
2336
2337 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2338
2339 /* Limit the offset to the hw defined mmio region aperture */
2340 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2341 (iommu->max_counters << 8) | 0x28);
2342 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2343 (offset > max_offset_lim))
2344 return -EINVAL;
2345
2346 if (is_write) {
2347 writel((u32)*value, iommu->mmio_base + offset);
2348 writel((*value >> 32), iommu->mmio_base + offset + 4);
2349 } else {
2350 *value = readl(iommu->mmio_base + offset + 4);
2351 *value <<= 32;
2352 *value = readl(iommu->mmio_base + offset);
2353 }
2354
2355 return 0;
2356}
2357EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);