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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Emma Mobile GPIO Support - GIO
4 *
5 * Copyright (C) 2012 Magnus Damm
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/spinlock.h>
11#include <linux/interrupt.h>
12#include <linux/ioport.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/gpio/driver.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/pinctrl/consumer.h>
22
23struct em_gio_priv {
24 void __iomem *base0;
25 void __iomem *base1;
26 spinlock_t sense_lock;
27 struct platform_device *pdev;
28 struct gpio_chip gpio_chip;
29 struct irq_chip irq_chip;
30 struct irq_domain *irq_domain;
31};
32
33#define GIO_E1 0x00
34#define GIO_E0 0x04
35#define GIO_EM 0x04
36#define GIO_OL 0x08
37#define GIO_OH 0x0c
38#define GIO_I 0x10
39#define GIO_IIA 0x14
40#define GIO_IEN 0x18
41#define GIO_IDS 0x1c
42#define GIO_IIM 0x1c
43#define GIO_RAW 0x20
44#define GIO_MST 0x24
45#define GIO_IIR 0x28
46
47#define GIO_IDT0 0x40
48#define GIO_IDT1 0x44
49#define GIO_IDT2 0x48
50#define GIO_IDT3 0x4c
51#define GIO_RAWBL 0x50
52#define GIO_RAWBH 0x54
53#define GIO_IRBL 0x58
54#define GIO_IRBH 0x5c
55
56#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
57
58static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
59{
60 if (offs < GIO_IDT0)
61 return ioread32(p->base0 + offs);
62 else
63 return ioread32(p->base1 + (offs - GIO_IDT0));
64}
65
66static inline void em_gio_write(struct em_gio_priv *p, int offs,
67 unsigned long value)
68{
69 if (offs < GIO_IDT0)
70 iowrite32(value, p->base0 + offs);
71 else
72 iowrite32(value, p->base1 + (offs - GIO_IDT0));
73}
74
75static void em_gio_irq_disable(struct irq_data *d)
76{
77 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
78
79 em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
80}
81
82static void em_gio_irq_enable(struct irq_data *d)
83{
84 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
85
86 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
87}
88
89static int em_gio_irq_reqres(struct irq_data *d)
90{
91 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
92 int ret;
93
94 ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
95 if (ret) {
96 dev_err(p->gpio_chip.parent,
97 "unable to lock HW IRQ %lu for IRQ\n",
98 irqd_to_hwirq(d));
99 return ret;
100 }
101 return 0;
102}
103
104static void em_gio_irq_relres(struct irq_data *d)
105{
106 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
107
108 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
109}
110
111
112#define GIO_ASYNC(x) (x + 8)
113
114static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
115 [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
116 [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
117 [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
118 [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
119 [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
120};
121
122static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
123{
124 unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
125 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
126 unsigned int reg, offset, shift;
127 unsigned long flags;
128 unsigned long tmp;
129
130 if (!value)
131 return -EINVAL;
132
133 offset = irqd_to_hwirq(d);
134
135 pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
136
137 /* 8 x 4 bit fields in 4 IDT registers */
138 reg = GIO_IDT(offset >> 3);
139 shift = (offset & 0x07) << 4;
140
141 spin_lock_irqsave(&p->sense_lock, flags);
142
143 /* disable the interrupt in IIA */
144 tmp = em_gio_read(p, GIO_IIA);
145 tmp &= ~BIT(offset);
146 em_gio_write(p, GIO_IIA, tmp);
147
148 /* change the sense setting in IDT */
149 tmp = em_gio_read(p, reg);
150 tmp &= ~(0xf << shift);
151 tmp |= value << shift;
152 em_gio_write(p, reg, tmp);
153
154 /* clear pending interrupts */
155 em_gio_write(p, GIO_IIR, BIT(offset));
156
157 /* enable the interrupt in IIA */
158 tmp = em_gio_read(p, GIO_IIA);
159 tmp |= BIT(offset);
160 em_gio_write(p, GIO_IIA, tmp);
161
162 spin_unlock_irqrestore(&p->sense_lock, flags);
163
164 return 0;
165}
166
167static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
168{
169 struct em_gio_priv *p = dev_id;
170 unsigned long pending;
171 unsigned int offset, irqs_handled = 0;
172
173 while ((pending = em_gio_read(p, GIO_MST))) {
174 offset = __ffs(pending);
175 em_gio_write(p, GIO_IIR, BIT(offset));
176 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
177 irqs_handled++;
178 }
179
180 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
181}
182
183static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
184{
185 return gpiochip_get_data(chip);
186}
187
188static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
189{
190 em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
191 return 0;
192}
193
194static int em_gio_get(struct gpio_chip *chip, unsigned offset)
195{
196 return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
197}
198
199static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
200 unsigned shift, int value)
201{
202 /* upper 16 bits contains mask and lower 16 actual value */
203 em_gio_write(gpio_to_priv(chip), reg,
204 (BIT(shift + 16)) | (value << shift));
205}
206
207static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
208{
209 /* output is split into two registers */
210 if (offset < 16)
211 __em_gio_set(chip, GIO_OL, offset, value);
212 else
213 __em_gio_set(chip, GIO_OH, offset - 16, value);
214}
215
216static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
217 int value)
218{
219 /* write GPIO value to output before selecting output mode of pin */
220 em_gio_set(chip, offset, value);
221 em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
222 return 0;
223}
224
225static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
226{
227 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
228}
229
230static int em_gio_request(struct gpio_chip *chip, unsigned offset)
231{
232 return pinctrl_gpio_request(chip->base + offset);
233}
234
235static void em_gio_free(struct gpio_chip *chip, unsigned offset)
236{
237 pinctrl_gpio_free(chip->base + offset);
238
239 /* Set the GPIO as an input to ensure that the next GPIO request won't
240 * drive the GPIO pin as an output.
241 */
242 em_gio_direction_input(chip, offset);
243}
244
245static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
246 irq_hw_number_t hwirq)
247{
248 struct em_gio_priv *p = h->host_data;
249
250 pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
251
252 irq_set_chip_data(irq, h->host_data);
253 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
254 return 0;
255}
256
257static const struct irq_domain_ops em_gio_irq_domain_ops = {
258 .map = em_gio_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260};
261
262static void em_gio_irq_domain_remove(void *data)
263{
264 struct irq_domain *domain = data;
265
266 irq_domain_remove(domain);
267}
268
269static int em_gio_probe(struct platform_device *pdev)
270{
271 struct em_gio_priv *p;
272 struct gpio_chip *gpio_chip;
273 struct irq_chip *irq_chip;
274 struct device *dev = &pdev->dev;
275 const char *name = dev_name(dev);
276 unsigned int ngpios;
277 int irq[2], ret;
278
279 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
280 if (!p)
281 return -ENOMEM;
282
283 p->pdev = pdev;
284 platform_set_drvdata(pdev, p);
285 spin_lock_init(&p->sense_lock);
286
287 irq[0] = platform_get_irq(pdev, 0);
288 if (irq[0] < 0)
289 return irq[0];
290
291 irq[1] = platform_get_irq(pdev, 1);
292 if (irq[1] < 0)
293 return irq[1];
294
295 p->base0 = devm_platform_ioremap_resource(pdev, 0);
296 if (IS_ERR(p->base0))
297 return PTR_ERR(p->base0);
298
299 p->base1 = devm_platform_ioremap_resource(pdev, 1);
300 if (IS_ERR(p->base1))
301 return PTR_ERR(p->base1);
302
303 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
304 dev_err(dev, "Missing ngpios OF property\n");
305 return -EINVAL;
306 }
307
308 gpio_chip = &p->gpio_chip;
309 gpio_chip->of_node = dev->of_node;
310 gpio_chip->direction_input = em_gio_direction_input;
311 gpio_chip->get = em_gio_get;
312 gpio_chip->direction_output = em_gio_direction_output;
313 gpio_chip->set = em_gio_set;
314 gpio_chip->to_irq = em_gio_to_irq;
315 gpio_chip->request = em_gio_request;
316 gpio_chip->free = em_gio_free;
317 gpio_chip->label = name;
318 gpio_chip->parent = dev;
319 gpio_chip->owner = THIS_MODULE;
320 gpio_chip->base = -1;
321 gpio_chip->ngpio = ngpios;
322
323 irq_chip = &p->irq_chip;
324 irq_chip->name = "gpio-em";
325 irq_chip->irq_mask = em_gio_irq_disable;
326 irq_chip->irq_unmask = em_gio_irq_enable;
327 irq_chip->irq_set_type = em_gio_irq_set_type;
328 irq_chip->irq_request_resources = em_gio_irq_reqres;
329 irq_chip->irq_release_resources = em_gio_irq_relres;
330 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
331
332 p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
333 &em_gio_irq_domain_ops, p);
334 if (!p->irq_domain) {
335 dev_err(dev, "cannot initialize irq domain\n");
336 return -ENXIO;
337 }
338
339 ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
340 p->irq_domain);
341 if (ret)
342 return ret;
343
344 if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
345 dev_err(dev, "failed to request low IRQ\n");
346 return -ENOENT;
347 }
348
349 if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
350 dev_err(dev, "failed to request high IRQ\n");
351 return -ENOENT;
352 }
353
354 ret = devm_gpiochip_add_data(dev, gpio_chip, p);
355 if (ret) {
356 dev_err(dev, "failed to add GPIO controller\n");
357 return ret;
358 }
359
360 return 0;
361}
362
363static const struct of_device_id em_gio_dt_ids[] = {
364 { .compatible = "renesas,em-gio", },
365 {},
366};
367MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
368
369static struct platform_driver em_gio_device_driver = {
370 .probe = em_gio_probe,
371 .driver = {
372 .name = "em_gio",
373 .of_match_table = em_gio_dt_ids,
374 }
375};
376
377static int __init em_gio_init(void)
378{
379 return platform_driver_register(&em_gio_device_driver);
380}
381postcore_initcall(em_gio_init);
382
383static void __exit em_gio_exit(void)
384{
385 platform_driver_unregister(&em_gio_device_driver);
386}
387module_exit(em_gio_exit);
388
389MODULE_AUTHOR("Magnus Damm");
390MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
391MODULE_LICENSE("GPL v2");
1/*
2 * Emma Mobile GPIO Support - GIO
3 *
4 * Copyright (C) 2012 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/bitops.h>
29#include <linux/err.h>
30#include <linux/gpio.h>
31#include <linux/slab.h>
32#include <linux/module.h>
33#include <linux/pinctrl/consumer.h>
34#include <linux/platform_data/gpio-em.h>
35
36struct em_gio_priv {
37 void __iomem *base0;
38 void __iomem *base1;
39 spinlock_t sense_lock;
40 struct platform_device *pdev;
41 struct gpio_chip gpio_chip;
42 struct irq_chip irq_chip;
43 struct irq_domain *irq_domain;
44};
45
46#define GIO_E1 0x00
47#define GIO_E0 0x04
48#define GIO_EM 0x04
49#define GIO_OL 0x08
50#define GIO_OH 0x0c
51#define GIO_I 0x10
52#define GIO_IIA 0x14
53#define GIO_IEN 0x18
54#define GIO_IDS 0x1c
55#define GIO_IIM 0x1c
56#define GIO_RAW 0x20
57#define GIO_MST 0x24
58#define GIO_IIR 0x28
59
60#define GIO_IDT0 0x40
61#define GIO_IDT1 0x44
62#define GIO_IDT2 0x48
63#define GIO_IDT3 0x4c
64#define GIO_RAWBL 0x50
65#define GIO_RAWBH 0x54
66#define GIO_IRBL 0x58
67#define GIO_IRBH 0x5c
68
69#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
70
71static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
72{
73 if (offs < GIO_IDT0)
74 return ioread32(p->base0 + offs);
75 else
76 return ioread32(p->base1 + (offs - GIO_IDT0));
77}
78
79static inline void em_gio_write(struct em_gio_priv *p, int offs,
80 unsigned long value)
81{
82 if (offs < GIO_IDT0)
83 iowrite32(value, p->base0 + offs);
84 else
85 iowrite32(value, p->base1 + (offs - GIO_IDT0));
86}
87
88static void em_gio_irq_disable(struct irq_data *d)
89{
90 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
91
92 em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
93}
94
95static void em_gio_irq_enable(struct irq_data *d)
96{
97 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
98
99 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
100}
101
102static int em_gio_irq_reqres(struct irq_data *d)
103{
104 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
105
106 if (gpio_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
107 dev_err(p->gpio_chip.dev,
108 "unable to lock HW IRQ %lu for IRQ\n",
109 irqd_to_hwirq(d));
110 return -EINVAL;
111 }
112 return 0;
113}
114
115static void em_gio_irq_relres(struct irq_data *d)
116{
117 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
118
119 gpio_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
120}
121
122
123#define GIO_ASYNC(x) (x + 8)
124
125static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
126 [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
127 [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
128 [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
129 [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
130 [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
131};
132
133static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
134{
135 unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
136 struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
137 unsigned int reg, offset, shift;
138 unsigned long flags;
139 unsigned long tmp;
140
141 if (!value)
142 return -EINVAL;
143
144 offset = irqd_to_hwirq(d);
145
146 pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
147
148 /* 8 x 4 bit fields in 4 IDT registers */
149 reg = GIO_IDT(offset >> 3);
150 shift = (offset & 0x07) << 4;
151
152 spin_lock_irqsave(&p->sense_lock, flags);
153
154 /* disable the interrupt in IIA */
155 tmp = em_gio_read(p, GIO_IIA);
156 tmp &= ~BIT(offset);
157 em_gio_write(p, GIO_IIA, tmp);
158
159 /* change the sense setting in IDT */
160 tmp = em_gio_read(p, reg);
161 tmp &= ~(0xf << shift);
162 tmp |= value << shift;
163 em_gio_write(p, reg, tmp);
164
165 /* clear pending interrupts */
166 em_gio_write(p, GIO_IIR, BIT(offset));
167
168 /* enable the interrupt in IIA */
169 tmp = em_gio_read(p, GIO_IIA);
170 tmp |= BIT(offset);
171 em_gio_write(p, GIO_IIA, tmp);
172
173 spin_unlock_irqrestore(&p->sense_lock, flags);
174
175 return 0;
176}
177
178static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
179{
180 struct em_gio_priv *p = dev_id;
181 unsigned long pending;
182 unsigned int offset, irqs_handled = 0;
183
184 while ((pending = em_gio_read(p, GIO_MST))) {
185 offset = __ffs(pending);
186 em_gio_write(p, GIO_IIR, BIT(offset));
187 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
188 irqs_handled++;
189 }
190
191 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
192}
193
194static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
195{
196 return container_of(chip, struct em_gio_priv, gpio_chip);
197}
198
199static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
200{
201 em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
202 return 0;
203}
204
205static int em_gio_get(struct gpio_chip *chip, unsigned offset)
206{
207 return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
208}
209
210static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
211 unsigned shift, int value)
212{
213 /* upper 16 bits contains mask and lower 16 actual value */
214 em_gio_write(gpio_to_priv(chip), reg,
215 (1 << (shift + 16)) | (value << shift));
216}
217
218static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
219{
220 /* output is split into two registers */
221 if (offset < 16)
222 __em_gio_set(chip, GIO_OL, offset, value);
223 else
224 __em_gio_set(chip, GIO_OH, offset - 16, value);
225}
226
227static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
228 int value)
229{
230 /* write GPIO value to output before selecting output mode of pin */
231 em_gio_set(chip, offset, value);
232 em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
233 return 0;
234}
235
236static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
237{
238 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
239}
240
241static int em_gio_request(struct gpio_chip *chip, unsigned offset)
242{
243 return pinctrl_request_gpio(chip->base + offset);
244}
245
246static void em_gio_free(struct gpio_chip *chip, unsigned offset)
247{
248 pinctrl_free_gpio(chip->base + offset);
249
250 /* Set the GPIO as an input to ensure that the next GPIO request won't
251 * drive the GPIO pin as an output.
252 */
253 em_gio_direction_input(chip, offset);
254}
255
256static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
257 irq_hw_number_t hwirq)
258{
259 struct em_gio_priv *p = h->host_data;
260
261 pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
262
263 irq_set_chip_data(irq, h->host_data);
264 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
265 set_irq_flags(irq, IRQF_VALID); /* kill me now */
266 return 0;
267}
268
269static struct irq_domain_ops em_gio_irq_domain_ops = {
270 .map = em_gio_irq_domain_map,
271 .xlate = irq_domain_xlate_twocell,
272};
273
274static int em_gio_probe(struct platform_device *pdev)
275{
276 struct gpio_em_config pdata_dt;
277 struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev);
278 struct em_gio_priv *p;
279 struct resource *io[2], *irq[2];
280 struct gpio_chip *gpio_chip;
281 struct irq_chip *irq_chip;
282 const char *name = dev_name(&pdev->dev);
283 int ret;
284
285 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
286 if (!p) {
287 dev_err(&pdev->dev, "failed to allocate driver data\n");
288 ret = -ENOMEM;
289 goto err0;
290 }
291
292 p->pdev = pdev;
293 platform_set_drvdata(pdev, p);
294 spin_lock_init(&p->sense_lock);
295
296 io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
297 io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
298 irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
299 irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
300
301 if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
302 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
303 ret = -EINVAL;
304 goto err0;
305 }
306
307 p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
308 resource_size(io[0]));
309 if (!p->base0) {
310 dev_err(&pdev->dev, "failed to remap low I/O memory\n");
311 ret = -ENXIO;
312 goto err0;
313 }
314
315 p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
316 resource_size(io[1]));
317 if (!p->base1) {
318 dev_err(&pdev->dev, "failed to remap high I/O memory\n");
319 ret = -ENXIO;
320 goto err0;
321 }
322
323 if (!pdata) {
324 memset(&pdata_dt, 0, sizeof(pdata_dt));
325 pdata = &pdata_dt;
326
327 if (of_property_read_u32(pdev->dev.of_node, "ngpios",
328 &pdata->number_of_pins)) {
329 dev_err(&pdev->dev, "Missing ngpios OF property\n");
330 ret = -EINVAL;
331 goto err0;
332 }
333
334 ret = of_alias_get_id(pdev->dev.of_node, "gpio");
335 if (ret < 0) {
336 dev_err(&pdev->dev, "Couldn't get OF id\n");
337 goto err0;
338 }
339 pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */
340 }
341
342 gpio_chip = &p->gpio_chip;
343 gpio_chip->of_node = pdev->dev.of_node;
344 gpio_chip->direction_input = em_gio_direction_input;
345 gpio_chip->get = em_gio_get;
346 gpio_chip->direction_output = em_gio_direction_output;
347 gpio_chip->set = em_gio_set;
348 gpio_chip->to_irq = em_gio_to_irq;
349 gpio_chip->request = em_gio_request;
350 gpio_chip->free = em_gio_free;
351 gpio_chip->label = name;
352 gpio_chip->dev = &pdev->dev;
353 gpio_chip->owner = THIS_MODULE;
354 gpio_chip->base = pdata->gpio_base;
355 gpio_chip->ngpio = pdata->number_of_pins;
356
357 irq_chip = &p->irq_chip;
358 irq_chip->name = name;
359 irq_chip->irq_mask = em_gio_irq_disable;
360 irq_chip->irq_unmask = em_gio_irq_enable;
361 irq_chip->irq_set_type = em_gio_irq_set_type;
362 irq_chip->irq_request_resources = em_gio_irq_reqres;
363 irq_chip->irq_release_resources = em_gio_irq_relres;
364 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
365
366 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
367 pdata->number_of_pins,
368 pdata->irq_base,
369 &em_gio_irq_domain_ops, p);
370 if (!p->irq_domain) {
371 ret = -ENXIO;
372 dev_err(&pdev->dev, "cannot initialize irq domain\n");
373 goto err0;
374 }
375
376 if (devm_request_irq(&pdev->dev, irq[0]->start,
377 em_gio_irq_handler, 0, name, p)) {
378 dev_err(&pdev->dev, "failed to request low IRQ\n");
379 ret = -ENOENT;
380 goto err1;
381 }
382
383 if (devm_request_irq(&pdev->dev, irq[1]->start,
384 em_gio_irq_handler, 0, name, p)) {
385 dev_err(&pdev->dev, "failed to request high IRQ\n");
386 ret = -ENOENT;
387 goto err1;
388 }
389
390 ret = gpiochip_add(gpio_chip);
391 if (ret) {
392 dev_err(&pdev->dev, "failed to add GPIO controller\n");
393 goto err1;
394 }
395
396 if (pdata->pctl_name) {
397 ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0,
398 gpio_chip->base, gpio_chip->ngpio);
399 if (ret < 0)
400 dev_warn(&pdev->dev, "failed to add pin range\n");
401 }
402 return 0;
403
404err1:
405 irq_domain_remove(p->irq_domain);
406err0:
407 return ret;
408}
409
410static int em_gio_remove(struct platform_device *pdev)
411{
412 struct em_gio_priv *p = platform_get_drvdata(pdev);
413 int ret;
414
415 ret = gpiochip_remove(&p->gpio_chip);
416 if (ret)
417 return ret;
418
419 irq_domain_remove(p->irq_domain);
420 return 0;
421}
422
423static const struct of_device_id em_gio_dt_ids[] = {
424 { .compatible = "renesas,em-gio", },
425 {},
426};
427MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
428
429static struct platform_driver em_gio_device_driver = {
430 .probe = em_gio_probe,
431 .remove = em_gio_remove,
432 .driver = {
433 .name = "em_gio",
434 .of_match_table = em_gio_dt_ids,
435 .owner = THIS_MODULE,
436 }
437};
438
439static int __init em_gio_init(void)
440{
441 return platform_driver_register(&em_gio_device_driver);
442}
443postcore_initcall(em_gio_init);
444
445static void __exit em_gio_exit(void)
446{
447 platform_driver_unregister(&em_gio_device_driver);
448}
449module_exit(em_gio_exit);
450
451MODULE_AUTHOR("Magnus Damm");
452MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
453MODULE_LICENSE("GPL v2");