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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support for OMAP DES and Triple DES HW acceleration.
4 *
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
7 */
8
9#define pr_fmt(fmt) "%s: " fmt, __func__
10
11#ifdef DEBUG
12#define prn(num) printk(#num "=%d\n", num)
13#define prx(num) printk(#num "=%x\n", num)
14#else
15#define prn(num) do { } while (0)
16#define prx(num) do { } while (0)
17#endif
18
19#include <linux/err.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
28#include <linux/pm_runtime.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_address.h>
32#include <linux/io.h>
33#include <linux/crypto.h>
34#include <linux/interrupt.h>
35#include <crypto/scatterwalk.h>
36#include <crypto/internal/des.h>
37#include <crypto/internal/skcipher.h>
38#include <crypto/algapi.h>
39#include <crypto/engine.h>
40
41#include "omap-crypto.h"
42
43#define DST_MAXBURST 2
44
45#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
46
47#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
48
49#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
50 ((x ^ 0x01) * 0x04))
51
52#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55#define DES_REG_CTRL_CBC BIT(4)
56#define DES_REG_CTRL_TDES BIT(3)
57#define DES_REG_CTRL_DIRECTION BIT(2)
58#define DES_REG_CTRL_INPUT_READY BIT(1)
59#define DES_REG_CTRL_OUTPUT_READY BIT(0)
60
61#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
62
63#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
64
65#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66
67#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
68
69#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71#define DES_REG_IRQ_DATA_IN BIT(1)
72#define DES_REG_IRQ_DATA_OUT BIT(2)
73
74#define FLAGS_MODE_MASK 0x000f
75#define FLAGS_ENCRYPT BIT(0)
76#define FLAGS_CBC BIT(1)
77#define FLAGS_INIT BIT(4)
78#define FLAGS_BUSY BIT(6)
79
80#define DEFAULT_AUTOSUSPEND_DELAY 1000
81
82#define FLAGS_IN_DATA_ST_SHIFT 8
83#define FLAGS_OUT_DATA_ST_SHIFT 10
84
85struct omap_des_ctx {
86 struct crypto_engine_ctx enginectx;
87 struct omap_des_dev *dd;
88
89 int keylen;
90 __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
91 unsigned long flags;
92};
93
94struct omap_des_reqctx {
95 unsigned long mode;
96};
97
98#define OMAP_DES_QUEUE_LENGTH 1
99#define OMAP_DES_CACHE_SIZE 0
100
101struct omap_des_algs_info {
102 struct skcipher_alg *algs_list;
103 unsigned int size;
104 unsigned int registered;
105};
106
107struct omap_des_pdata {
108 struct omap_des_algs_info *algs_info;
109 unsigned int algs_info_size;
110
111 void (*trigger)(struct omap_des_dev *dd, int length);
112
113 u32 key_ofs;
114 u32 iv_ofs;
115 u32 ctrl_ofs;
116 u32 data_ofs;
117 u32 rev_ofs;
118 u32 mask_ofs;
119 u32 irq_enable_ofs;
120 u32 irq_status_ofs;
121
122 u32 dma_enable_in;
123 u32 dma_enable_out;
124 u32 dma_start;
125
126 u32 major_mask;
127 u32 major_shift;
128 u32 minor_mask;
129 u32 minor_shift;
130};
131
132struct omap_des_dev {
133 struct list_head list;
134 unsigned long phys_base;
135 void __iomem *io_base;
136 struct omap_des_ctx *ctx;
137 struct device *dev;
138 unsigned long flags;
139 int err;
140
141 struct tasklet_struct done_task;
142
143 struct skcipher_request *req;
144 struct crypto_engine *engine;
145 /*
146 * total is used by PIO mode for book keeping so introduce
147 * variable total_save as need it to calc page_order
148 */
149 size_t total;
150 size_t total_save;
151
152 struct scatterlist *in_sg;
153 struct scatterlist *out_sg;
154
155 /* Buffers for copying for unaligned cases */
156 struct scatterlist in_sgl;
157 struct scatterlist out_sgl;
158 struct scatterlist *orig_out;
159
160 struct scatter_walk in_walk;
161 struct scatter_walk out_walk;
162 struct dma_chan *dma_lch_in;
163 struct dma_chan *dma_lch_out;
164 int in_sg_len;
165 int out_sg_len;
166 int pio_only;
167 const struct omap_des_pdata *pdata;
168};
169
170/* keep registered devices data here */
171static LIST_HEAD(dev_list);
172static DEFINE_SPINLOCK(list_lock);
173
174#ifdef DEBUG
175#define omap_des_read(dd, offset) \
176 ({ \
177 int _read_ret; \
178 _read_ret = __raw_readl(dd->io_base + offset); \
179 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
180 offset, _read_ret); \
181 _read_ret; \
182 })
183#else
184static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
185{
186 return __raw_readl(dd->io_base + offset);
187}
188#endif
189
190#ifdef DEBUG
191#define omap_des_write(dd, offset, value) \
192 do { \
193 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
194 offset, value); \
195 __raw_writel(value, dd->io_base + offset); \
196 } while (0)
197#else
198static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
199 u32 value)
200{
201 __raw_writel(value, dd->io_base + offset);
202}
203#endif
204
205static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
206 u32 value, u32 mask)
207{
208 u32 val;
209
210 val = omap_des_read(dd, offset);
211 val &= ~mask;
212 val |= value;
213 omap_des_write(dd, offset, val);
214}
215
216static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
217 u32 *value, int count)
218{
219 for (; count--; value++, offset += 4)
220 omap_des_write(dd, offset, *value);
221}
222
223static int omap_des_hw_init(struct omap_des_dev *dd)
224{
225 int err;
226
227 /*
228 * clocks are enabled when request starts and disabled when finished.
229 * It may be long delays between requests.
230 * Device might go to off mode to save power.
231 */
232 err = pm_runtime_get_sync(dd->dev);
233 if (err < 0) {
234 pm_runtime_put_noidle(dd->dev);
235 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
236 return err;
237 }
238
239 if (!(dd->flags & FLAGS_INIT)) {
240 dd->flags |= FLAGS_INIT;
241 dd->err = 0;
242 }
243
244 return 0;
245}
246
247static int omap_des_write_ctrl(struct omap_des_dev *dd)
248{
249 unsigned int key32;
250 int i, err;
251 u32 val = 0, mask = 0;
252
253 err = omap_des_hw_init(dd);
254 if (err)
255 return err;
256
257 key32 = dd->ctx->keylen / sizeof(u32);
258
259 /* it seems a key should always be set even if it has not changed */
260 for (i = 0; i < key32; i++) {
261 omap_des_write(dd, DES_REG_KEY(dd, i),
262 __le32_to_cpu(dd->ctx->key[i]));
263 }
264
265 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
266 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
267
268 if (dd->flags & FLAGS_CBC)
269 val |= DES_REG_CTRL_CBC;
270 if (dd->flags & FLAGS_ENCRYPT)
271 val |= DES_REG_CTRL_DIRECTION;
272 if (key32 == 6)
273 val |= DES_REG_CTRL_TDES;
274
275 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
276
277 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
278
279 return 0;
280}
281
282static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
283{
284 u32 mask, val;
285
286 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
287
288 val = dd->pdata->dma_start;
289
290 if (dd->dma_lch_out != NULL)
291 val |= dd->pdata->dma_enable_out;
292 if (dd->dma_lch_in != NULL)
293 val |= dd->pdata->dma_enable_in;
294
295 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
296 dd->pdata->dma_start;
297
298 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
299}
300
301static void omap_des_dma_stop(struct omap_des_dev *dd)
302{
303 u32 mask;
304
305 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
306 dd->pdata->dma_start;
307
308 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
309}
310
311static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
312{
313 struct omap_des_dev *dd = NULL, *tmp;
314
315 spin_lock_bh(&list_lock);
316 if (!ctx->dd) {
317 list_for_each_entry(tmp, &dev_list, list) {
318 /* FIXME: take fist available des core */
319 dd = tmp;
320 break;
321 }
322 ctx->dd = dd;
323 } else {
324 /* already found before */
325 dd = ctx->dd;
326 }
327 spin_unlock_bh(&list_lock);
328
329 return dd;
330}
331
332static void omap_des_dma_out_callback(void *data)
333{
334 struct omap_des_dev *dd = data;
335
336 /* dma_lch_out - completed */
337 tasklet_schedule(&dd->done_task);
338}
339
340static int omap_des_dma_init(struct omap_des_dev *dd)
341{
342 int err;
343
344 dd->dma_lch_out = NULL;
345 dd->dma_lch_in = NULL;
346
347 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
348 if (IS_ERR(dd->dma_lch_in)) {
349 dev_err(dd->dev, "Unable to request in DMA channel\n");
350 return PTR_ERR(dd->dma_lch_in);
351 }
352
353 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
354 if (IS_ERR(dd->dma_lch_out)) {
355 dev_err(dd->dev, "Unable to request out DMA channel\n");
356 err = PTR_ERR(dd->dma_lch_out);
357 goto err_dma_out;
358 }
359
360 return 0;
361
362err_dma_out:
363 dma_release_channel(dd->dma_lch_in);
364
365 return err;
366}
367
368static void omap_des_dma_cleanup(struct omap_des_dev *dd)
369{
370 if (dd->pio_only)
371 return;
372
373 dma_release_channel(dd->dma_lch_out);
374 dma_release_channel(dd->dma_lch_in);
375}
376
377static int omap_des_crypt_dma(struct crypto_tfm *tfm,
378 struct scatterlist *in_sg, struct scatterlist *out_sg,
379 int in_sg_len, int out_sg_len)
380{
381 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
382 struct omap_des_dev *dd = ctx->dd;
383 struct dma_async_tx_descriptor *tx_in, *tx_out;
384 struct dma_slave_config cfg;
385 int ret;
386
387 if (dd->pio_only) {
388 scatterwalk_start(&dd->in_walk, dd->in_sg);
389 scatterwalk_start(&dd->out_walk, dd->out_sg);
390
391 /* Enable DATAIN interrupt and let it take
392 care of the rest */
393 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
394 return 0;
395 }
396
397 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
398
399 memset(&cfg, 0, sizeof(cfg));
400
401 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
402 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
403 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
405 cfg.src_maxburst = DST_MAXBURST;
406 cfg.dst_maxburst = DST_MAXBURST;
407
408 /* IN */
409 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
410 if (ret) {
411 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
412 ret);
413 return ret;
414 }
415
416 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
417 DMA_MEM_TO_DEV,
418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
419 if (!tx_in) {
420 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
421 return -EINVAL;
422 }
423
424 /* No callback necessary */
425 tx_in->callback_param = dd;
426
427 /* OUT */
428 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
429 if (ret) {
430 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
431 ret);
432 return ret;
433 }
434
435 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
436 DMA_DEV_TO_MEM,
437 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
438 if (!tx_out) {
439 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
440 return -EINVAL;
441 }
442
443 tx_out->callback = omap_des_dma_out_callback;
444 tx_out->callback_param = dd;
445
446 dmaengine_submit(tx_in);
447 dmaengine_submit(tx_out);
448
449 dma_async_issue_pending(dd->dma_lch_in);
450 dma_async_issue_pending(dd->dma_lch_out);
451
452 /* start DMA */
453 dd->pdata->trigger(dd, dd->total);
454
455 return 0;
456}
457
458static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
459{
460 struct crypto_tfm *tfm = crypto_skcipher_tfm(
461 crypto_skcipher_reqtfm(dd->req));
462 int err;
463
464 pr_debug("total: %zd\n", dd->total);
465
466 if (!dd->pio_only) {
467 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
468 DMA_TO_DEVICE);
469 if (!err) {
470 dev_err(dd->dev, "dma_map_sg() error\n");
471 return -EINVAL;
472 }
473
474 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
475 DMA_FROM_DEVICE);
476 if (!err) {
477 dev_err(dd->dev, "dma_map_sg() error\n");
478 return -EINVAL;
479 }
480 }
481
482 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
483 dd->out_sg_len);
484 if (err && !dd->pio_only) {
485 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
486 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
487 DMA_FROM_DEVICE);
488 }
489
490 return err;
491}
492
493static void omap_des_finish_req(struct omap_des_dev *dd, int err)
494{
495 struct skcipher_request *req = dd->req;
496
497 pr_debug("err: %d\n", err);
498
499 crypto_finalize_skcipher_request(dd->engine, req, err);
500
501 pm_runtime_mark_last_busy(dd->dev);
502 pm_runtime_put_autosuspend(dd->dev);
503}
504
505static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
506{
507 pr_debug("total: %zd\n", dd->total);
508
509 omap_des_dma_stop(dd);
510
511 dmaengine_terminate_all(dd->dma_lch_in);
512 dmaengine_terminate_all(dd->dma_lch_out);
513
514 return 0;
515}
516
517static int omap_des_handle_queue(struct omap_des_dev *dd,
518 struct skcipher_request *req)
519{
520 if (req)
521 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
522
523 return 0;
524}
525
526static int omap_des_prepare_req(struct crypto_engine *engine,
527 void *areq)
528{
529 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
530 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
531 crypto_skcipher_reqtfm(req));
532 struct omap_des_dev *dd = omap_des_find_dev(ctx);
533 struct omap_des_reqctx *rctx;
534 int ret;
535 u16 flags;
536
537 if (!dd)
538 return -ENODEV;
539
540 /* assign new request to device */
541 dd->req = req;
542 dd->total = req->cryptlen;
543 dd->total_save = req->cryptlen;
544 dd->in_sg = req->src;
545 dd->out_sg = req->dst;
546 dd->orig_out = req->dst;
547
548 flags = OMAP_CRYPTO_COPY_DATA;
549 if (req->src == req->dst)
550 flags |= OMAP_CRYPTO_FORCE_COPY;
551
552 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
553 &dd->in_sgl, flags,
554 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
555 if (ret)
556 return ret;
557
558 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
559 &dd->out_sgl, 0,
560 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
561 if (ret)
562 return ret;
563
564 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
565 if (dd->in_sg_len < 0)
566 return dd->in_sg_len;
567
568 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
569 if (dd->out_sg_len < 0)
570 return dd->out_sg_len;
571
572 rctx = skcipher_request_ctx(req);
573 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
574 rctx->mode &= FLAGS_MODE_MASK;
575 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
576
577 dd->ctx = ctx;
578 ctx->dd = dd;
579
580 return omap_des_write_ctrl(dd);
581}
582
583static int omap_des_crypt_req(struct crypto_engine *engine,
584 void *areq)
585{
586 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
587 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
588 crypto_skcipher_reqtfm(req));
589 struct omap_des_dev *dd = omap_des_find_dev(ctx);
590
591 if (!dd)
592 return -ENODEV;
593
594 return omap_des_crypt_dma_start(dd);
595}
596
597static void omap_des_done_task(unsigned long data)
598{
599 struct omap_des_dev *dd = (struct omap_des_dev *)data;
600 int i;
601
602 pr_debug("enter done_task\n");
603
604 if (!dd->pio_only) {
605 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
606 DMA_FROM_DEVICE);
607 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
608 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
609 DMA_FROM_DEVICE);
610 omap_des_crypt_dma_stop(dd);
611 }
612
613 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
614 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
615
616 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
617 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
618
619 if ((dd->flags & FLAGS_CBC) && dd->req->iv)
620 for (i = 0; i < 2; i++)
621 ((u32 *)dd->req->iv)[i] =
622 omap_des_read(dd, DES_REG_IV(dd, i));
623
624 omap_des_finish_req(dd, 0);
625
626 pr_debug("exit\n");
627}
628
629static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
630{
631 struct omap_des_ctx *ctx = crypto_skcipher_ctx(
632 crypto_skcipher_reqtfm(req));
633 struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
634 struct omap_des_dev *dd;
635
636 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
637 !!(mode & FLAGS_ENCRYPT),
638 !!(mode & FLAGS_CBC));
639
640 if (!req->cryptlen)
641 return 0;
642
643 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
644 return -EINVAL;
645
646 dd = omap_des_find_dev(ctx);
647 if (!dd)
648 return -ENODEV;
649
650 rctx->mode = mode;
651
652 return omap_des_handle_queue(dd, req);
653}
654
655/* ********************** ALG API ************************************ */
656
657static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
658 unsigned int keylen)
659{
660 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
661 int err;
662
663 pr_debug("enter, keylen: %d\n", keylen);
664
665 err = verify_skcipher_des_key(cipher, key);
666 if (err)
667 return err;
668
669 memcpy(ctx->key, key, keylen);
670 ctx->keylen = keylen;
671
672 return 0;
673}
674
675static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
676 unsigned int keylen)
677{
678 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
679 int err;
680
681 pr_debug("enter, keylen: %d\n", keylen);
682
683 err = verify_skcipher_des3_key(cipher, key);
684 if (err)
685 return err;
686
687 memcpy(ctx->key, key, keylen);
688 ctx->keylen = keylen;
689
690 return 0;
691}
692
693static int omap_des_ecb_encrypt(struct skcipher_request *req)
694{
695 return omap_des_crypt(req, FLAGS_ENCRYPT);
696}
697
698static int omap_des_ecb_decrypt(struct skcipher_request *req)
699{
700 return omap_des_crypt(req, 0);
701}
702
703static int omap_des_cbc_encrypt(struct skcipher_request *req)
704{
705 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
706}
707
708static int omap_des_cbc_decrypt(struct skcipher_request *req)
709{
710 return omap_des_crypt(req, FLAGS_CBC);
711}
712
713static int omap_des_prepare_req(struct crypto_engine *engine,
714 void *areq);
715static int omap_des_crypt_req(struct crypto_engine *engine,
716 void *areq);
717
718static int omap_des_init_tfm(struct crypto_skcipher *tfm)
719{
720 struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm);
721
722 pr_debug("enter\n");
723
724 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
725
726 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
727 ctx->enginectx.op.unprepare_request = NULL;
728 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
729
730 return 0;
731}
732
733/* ********************** ALGS ************************************ */
734
735static struct skcipher_alg algs_ecb_cbc[] = {
736{
737 .base.cra_name = "ecb(des)",
738 .base.cra_driver_name = "ecb-des-omap",
739 .base.cra_priority = 100,
740 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
741 CRYPTO_ALG_ASYNC,
742 .base.cra_blocksize = DES_BLOCK_SIZE,
743 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
744 .base.cra_module = THIS_MODULE,
745
746 .min_keysize = DES_KEY_SIZE,
747 .max_keysize = DES_KEY_SIZE,
748 .setkey = omap_des_setkey,
749 .encrypt = omap_des_ecb_encrypt,
750 .decrypt = omap_des_ecb_decrypt,
751 .init = omap_des_init_tfm,
752},
753{
754 .base.cra_name = "cbc(des)",
755 .base.cra_driver_name = "cbc-des-omap",
756 .base.cra_priority = 100,
757 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
758 CRYPTO_ALG_ASYNC,
759 .base.cra_blocksize = DES_BLOCK_SIZE,
760 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
761 .base.cra_module = THIS_MODULE,
762
763 .min_keysize = DES_KEY_SIZE,
764 .max_keysize = DES_KEY_SIZE,
765 .ivsize = DES_BLOCK_SIZE,
766 .setkey = omap_des_setkey,
767 .encrypt = omap_des_cbc_encrypt,
768 .decrypt = omap_des_cbc_decrypt,
769 .init = omap_des_init_tfm,
770},
771{
772 .base.cra_name = "ecb(des3_ede)",
773 .base.cra_driver_name = "ecb-des3-omap",
774 .base.cra_priority = 100,
775 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
776 CRYPTO_ALG_ASYNC,
777 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
778 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
779 .base.cra_module = THIS_MODULE,
780
781 .min_keysize = DES3_EDE_KEY_SIZE,
782 .max_keysize = DES3_EDE_KEY_SIZE,
783 .setkey = omap_des3_setkey,
784 .encrypt = omap_des_ecb_encrypt,
785 .decrypt = omap_des_ecb_decrypt,
786 .init = omap_des_init_tfm,
787},
788{
789 .base.cra_name = "cbc(des3_ede)",
790 .base.cra_driver_name = "cbc-des3-omap",
791 .base.cra_priority = 100,
792 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
793 CRYPTO_ALG_ASYNC,
794 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
795 .base.cra_ctxsize = sizeof(struct omap_des_ctx),
796 .base.cra_module = THIS_MODULE,
797
798 .min_keysize = DES3_EDE_KEY_SIZE,
799 .max_keysize = DES3_EDE_KEY_SIZE,
800 .ivsize = DES3_EDE_BLOCK_SIZE,
801 .setkey = omap_des3_setkey,
802 .encrypt = omap_des_cbc_encrypt,
803 .decrypt = omap_des_cbc_decrypt,
804 .init = omap_des_init_tfm,
805}
806};
807
808static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
809 {
810 .algs_list = algs_ecb_cbc,
811 .size = ARRAY_SIZE(algs_ecb_cbc),
812 },
813};
814
815#ifdef CONFIG_OF
816static const struct omap_des_pdata omap_des_pdata_omap4 = {
817 .algs_info = omap_des_algs_info_ecb_cbc,
818 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
819 .trigger = omap_des_dma_trigger_omap4,
820 .key_ofs = 0x14,
821 .iv_ofs = 0x18,
822 .ctrl_ofs = 0x20,
823 .data_ofs = 0x28,
824 .rev_ofs = 0x30,
825 .mask_ofs = 0x34,
826 .irq_status_ofs = 0x3c,
827 .irq_enable_ofs = 0x40,
828 .dma_enable_in = BIT(5),
829 .dma_enable_out = BIT(6),
830 .major_mask = 0x0700,
831 .major_shift = 8,
832 .minor_mask = 0x003f,
833 .minor_shift = 0,
834};
835
836static irqreturn_t omap_des_irq(int irq, void *dev_id)
837{
838 struct omap_des_dev *dd = dev_id;
839 u32 status, i;
840 u32 *src, *dst;
841
842 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
843 if (status & DES_REG_IRQ_DATA_IN) {
844 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
845
846 BUG_ON(!dd->in_sg);
847
848 BUG_ON(_calc_walked(in) > dd->in_sg->length);
849
850 src = sg_virt(dd->in_sg) + _calc_walked(in);
851
852 for (i = 0; i < DES_BLOCK_WORDS; i++) {
853 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
854
855 scatterwalk_advance(&dd->in_walk, 4);
856 if (dd->in_sg->length == _calc_walked(in)) {
857 dd->in_sg = sg_next(dd->in_sg);
858 if (dd->in_sg) {
859 scatterwalk_start(&dd->in_walk,
860 dd->in_sg);
861 src = sg_virt(dd->in_sg) +
862 _calc_walked(in);
863 }
864 } else {
865 src++;
866 }
867 }
868
869 /* Clear IRQ status */
870 status &= ~DES_REG_IRQ_DATA_IN;
871 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
872
873 /* Enable DATA_OUT interrupt */
874 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
875
876 } else if (status & DES_REG_IRQ_DATA_OUT) {
877 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
878
879 BUG_ON(!dd->out_sg);
880
881 BUG_ON(_calc_walked(out) > dd->out_sg->length);
882
883 dst = sg_virt(dd->out_sg) + _calc_walked(out);
884
885 for (i = 0; i < DES_BLOCK_WORDS; i++) {
886 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
887 scatterwalk_advance(&dd->out_walk, 4);
888 if (dd->out_sg->length == _calc_walked(out)) {
889 dd->out_sg = sg_next(dd->out_sg);
890 if (dd->out_sg) {
891 scatterwalk_start(&dd->out_walk,
892 dd->out_sg);
893 dst = sg_virt(dd->out_sg) +
894 _calc_walked(out);
895 }
896 } else {
897 dst++;
898 }
899 }
900
901 BUG_ON(dd->total < DES_BLOCK_SIZE);
902
903 dd->total -= DES_BLOCK_SIZE;
904
905 /* Clear IRQ status */
906 status &= ~DES_REG_IRQ_DATA_OUT;
907 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
908
909 if (!dd->total)
910 /* All bytes read! */
911 tasklet_schedule(&dd->done_task);
912 else
913 /* Enable DATA_IN interrupt for next block */
914 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
915 }
916
917 return IRQ_HANDLED;
918}
919
920static const struct of_device_id omap_des_of_match[] = {
921 {
922 .compatible = "ti,omap4-des",
923 .data = &omap_des_pdata_omap4,
924 },
925 {},
926};
927MODULE_DEVICE_TABLE(of, omap_des_of_match);
928
929static int omap_des_get_of(struct omap_des_dev *dd,
930 struct platform_device *pdev)
931{
932
933 dd->pdata = of_device_get_match_data(&pdev->dev);
934 if (!dd->pdata) {
935 dev_err(&pdev->dev, "no compatible OF match\n");
936 return -EINVAL;
937 }
938
939 return 0;
940}
941#else
942static int omap_des_get_of(struct omap_des_dev *dd,
943 struct device *dev)
944{
945 return -EINVAL;
946}
947#endif
948
949static int omap_des_get_pdev(struct omap_des_dev *dd,
950 struct platform_device *pdev)
951{
952 /* non-DT devices get pdata from pdev */
953 dd->pdata = pdev->dev.platform_data;
954
955 return 0;
956}
957
958static int omap_des_probe(struct platform_device *pdev)
959{
960 struct device *dev = &pdev->dev;
961 struct omap_des_dev *dd;
962 struct skcipher_alg *algp;
963 struct resource *res;
964 int err = -ENOMEM, i, j, irq = -1;
965 u32 reg;
966
967 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
968 if (dd == NULL) {
969 dev_err(dev, "unable to alloc data struct.\n");
970 goto err_data;
971 }
972 dd->dev = dev;
973 platform_set_drvdata(pdev, dd);
974
975 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
976 if (!res) {
977 dev_err(dev, "no MEM resource info\n");
978 goto err_res;
979 }
980
981 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
982 omap_des_get_pdev(dd, pdev);
983 if (err)
984 goto err_res;
985
986 dd->io_base = devm_ioremap_resource(dev, res);
987 if (IS_ERR(dd->io_base)) {
988 err = PTR_ERR(dd->io_base);
989 goto err_res;
990 }
991 dd->phys_base = res->start;
992
993 pm_runtime_use_autosuspend(dev);
994 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
995
996 pm_runtime_enable(dev);
997 err = pm_runtime_get_sync(dev);
998 if (err < 0) {
999 pm_runtime_put_noidle(dev);
1000 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1001 goto err_get;
1002 }
1003
1004 omap_des_dma_stop(dd);
1005
1006 reg = omap_des_read(dd, DES_REG_REV(dd));
1007
1008 pm_runtime_put_sync(dev);
1009
1010 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1011 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1012 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1013
1014 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1015
1016 err = omap_des_dma_init(dd);
1017 if (err == -EPROBE_DEFER) {
1018 goto err_irq;
1019 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1020 dd->pio_only = 1;
1021
1022 irq = platform_get_irq(pdev, 0);
1023 if (irq < 0) {
1024 err = irq;
1025 goto err_irq;
1026 }
1027
1028 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1029 dev_name(dev), dd);
1030 if (err) {
1031 dev_err(dev, "Unable to grab omap-des IRQ\n");
1032 goto err_irq;
1033 }
1034 }
1035
1036
1037 INIT_LIST_HEAD(&dd->list);
1038 spin_lock(&list_lock);
1039 list_add_tail(&dd->list, &dev_list);
1040 spin_unlock(&list_lock);
1041
1042 /* Initialize des crypto engine */
1043 dd->engine = crypto_engine_alloc_init(dev, 1);
1044 if (!dd->engine) {
1045 err = -ENOMEM;
1046 goto err_engine;
1047 }
1048
1049 err = crypto_engine_start(dd->engine);
1050 if (err)
1051 goto err_engine;
1052
1053 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1054 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1055 algp = &dd->pdata->algs_info[i].algs_list[j];
1056
1057 pr_debug("reg alg: %s\n", algp->base.cra_name);
1058
1059 err = crypto_register_skcipher(algp);
1060 if (err)
1061 goto err_algs;
1062
1063 dd->pdata->algs_info[i].registered++;
1064 }
1065 }
1066
1067 return 0;
1068
1069err_algs:
1070 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1071 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1072 crypto_unregister_skcipher(
1073 &dd->pdata->algs_info[i].algs_list[j]);
1074
1075err_engine:
1076 if (dd->engine)
1077 crypto_engine_exit(dd->engine);
1078
1079 omap_des_dma_cleanup(dd);
1080err_irq:
1081 tasklet_kill(&dd->done_task);
1082err_get:
1083 pm_runtime_disable(dev);
1084err_res:
1085 dd = NULL;
1086err_data:
1087 dev_err(dev, "initialization failed.\n");
1088 return err;
1089}
1090
1091static int omap_des_remove(struct platform_device *pdev)
1092{
1093 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1094 int i, j;
1095
1096 if (!dd)
1097 return -ENODEV;
1098
1099 spin_lock(&list_lock);
1100 list_del(&dd->list);
1101 spin_unlock(&list_lock);
1102
1103 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1104 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1105 crypto_unregister_skcipher(
1106 &dd->pdata->algs_info[i].algs_list[j]);
1107
1108 tasklet_kill(&dd->done_task);
1109 omap_des_dma_cleanup(dd);
1110 pm_runtime_disable(dd->dev);
1111 dd = NULL;
1112
1113 return 0;
1114}
1115
1116#ifdef CONFIG_PM_SLEEP
1117static int omap_des_suspend(struct device *dev)
1118{
1119 pm_runtime_put_sync(dev);
1120 return 0;
1121}
1122
1123static int omap_des_resume(struct device *dev)
1124{
1125 int err;
1126
1127 err = pm_runtime_get_sync(dev);
1128 if (err < 0) {
1129 pm_runtime_put_noidle(dev);
1130 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1131 return err;
1132 }
1133 return 0;
1134}
1135#endif
1136
1137static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1138
1139static struct platform_driver omap_des_driver = {
1140 .probe = omap_des_probe,
1141 .remove = omap_des_remove,
1142 .driver = {
1143 .name = "omap-des",
1144 .pm = &omap_des_pm_ops,
1145 .of_match_table = of_match_ptr(omap_des_of_match),
1146 },
1147};
1148
1149module_platform_driver(omap_des_driver);
1150
1151MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1152MODULE_LICENSE("GPL v2");
1153MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
1/*
2 * Support for OMAP DES and Triple DES HW acceleration.
3 *
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 *
11 */
12
13#define pr_fmt(fmt) "%s: " fmt, __func__
14
15#ifdef DEBUG
16#define prn(num) printk(#num "=%d\n", num)
17#define prx(num) printk(#num "=%x\n", num)
18#else
19#define prn(num) do { } while (0)
20#define prx(num) do { } while (0)
21#endif
22
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/errno.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
33#include <linux/pm_runtime.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_address.h>
37#include <linux/io.h>
38#include <linux/crypto.h>
39#include <linux/interrupt.h>
40#include <crypto/scatterwalk.h>
41#include <crypto/des.h>
42
43#define DST_MAXBURST 2
44
45#define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
46
47#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
48
49#define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
50 ((x ^ 0x01) * 0x04))
51
52#define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54#define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55#define DES_REG_CTRL_CBC BIT(4)
56#define DES_REG_CTRL_TDES BIT(3)
57#define DES_REG_CTRL_DIRECTION BIT(2)
58#define DES_REG_CTRL_INPUT_READY BIT(1)
59#define DES_REG_CTRL_OUTPUT_READY BIT(0)
60
61#define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
62
63#define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
64
65#define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66
67#define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
68
69#define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70#define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71#define DES_REG_IRQ_DATA_IN BIT(1)
72#define DES_REG_IRQ_DATA_OUT BIT(2)
73
74#define FLAGS_MODE_MASK 0x000f
75#define FLAGS_ENCRYPT BIT(0)
76#define FLAGS_CBC BIT(1)
77#define FLAGS_INIT BIT(4)
78#define FLAGS_BUSY BIT(6)
79
80struct omap_des_ctx {
81 struct omap_des_dev *dd;
82
83 int keylen;
84 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
85 unsigned long flags;
86};
87
88struct omap_des_reqctx {
89 unsigned long mode;
90};
91
92#define OMAP_DES_QUEUE_LENGTH 1
93#define OMAP_DES_CACHE_SIZE 0
94
95struct omap_des_algs_info {
96 struct crypto_alg *algs_list;
97 unsigned int size;
98 unsigned int registered;
99};
100
101struct omap_des_pdata {
102 struct omap_des_algs_info *algs_info;
103 unsigned int algs_info_size;
104
105 void (*trigger)(struct omap_des_dev *dd, int length);
106
107 u32 key_ofs;
108 u32 iv_ofs;
109 u32 ctrl_ofs;
110 u32 data_ofs;
111 u32 rev_ofs;
112 u32 mask_ofs;
113 u32 irq_enable_ofs;
114 u32 irq_status_ofs;
115
116 u32 dma_enable_in;
117 u32 dma_enable_out;
118 u32 dma_start;
119
120 u32 major_mask;
121 u32 major_shift;
122 u32 minor_mask;
123 u32 minor_shift;
124};
125
126struct omap_des_dev {
127 struct list_head list;
128 unsigned long phys_base;
129 void __iomem *io_base;
130 struct omap_des_ctx *ctx;
131 struct device *dev;
132 unsigned long flags;
133 int err;
134
135 /* spinlock used for queues */
136 spinlock_t lock;
137 struct crypto_queue queue;
138
139 struct tasklet_struct done_task;
140 struct tasklet_struct queue_task;
141
142 struct ablkcipher_request *req;
143 /*
144 * total is used by PIO mode for book keeping so introduce
145 * variable total_save as need it to calc page_order
146 */
147 size_t total;
148 size_t total_save;
149
150 struct scatterlist *in_sg;
151 struct scatterlist *out_sg;
152
153 /* Buffers for copying for unaligned cases */
154 struct scatterlist in_sgl;
155 struct scatterlist out_sgl;
156 struct scatterlist *orig_out;
157 int sgs_copied;
158
159 struct scatter_walk in_walk;
160 struct scatter_walk out_walk;
161 int dma_in;
162 struct dma_chan *dma_lch_in;
163 int dma_out;
164 struct dma_chan *dma_lch_out;
165 int in_sg_len;
166 int out_sg_len;
167 int pio_only;
168 const struct omap_des_pdata *pdata;
169};
170
171/* keep registered devices data here */
172static LIST_HEAD(dev_list);
173static DEFINE_SPINLOCK(list_lock);
174
175#ifdef DEBUG
176#define omap_des_read(dd, offset) \
177 ({ \
178 int _read_ret; \
179 _read_ret = __raw_readl(dd->io_base + offset); \
180 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
181 offset, _read_ret); \
182 _read_ret; \
183 })
184#else
185static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
186{
187 return __raw_readl(dd->io_base + offset);
188}
189#endif
190
191#ifdef DEBUG
192#define omap_des_write(dd, offset, value) \
193 do { \
194 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
195 offset, value); \
196 __raw_writel(value, dd->io_base + offset); \
197 } while (0)
198#else
199static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
200 u32 value)
201{
202 __raw_writel(value, dd->io_base + offset);
203}
204#endif
205
206static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
207 u32 value, u32 mask)
208{
209 u32 val;
210
211 val = omap_des_read(dd, offset);
212 val &= ~mask;
213 val |= value;
214 omap_des_write(dd, offset, val);
215}
216
217static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
218 u32 *value, int count)
219{
220 for (; count--; value++, offset += 4)
221 omap_des_write(dd, offset, *value);
222}
223
224static int omap_des_hw_init(struct omap_des_dev *dd)
225{
226 /*
227 * clocks are enabled when request starts and disabled when finished.
228 * It may be long delays between requests.
229 * Device might go to off mode to save power.
230 */
231 pm_runtime_get_sync(dd->dev);
232
233 if (!(dd->flags & FLAGS_INIT)) {
234 dd->flags |= FLAGS_INIT;
235 dd->err = 0;
236 }
237
238 return 0;
239}
240
241static int omap_des_write_ctrl(struct omap_des_dev *dd)
242{
243 unsigned int key32;
244 int i, err;
245 u32 val = 0, mask = 0;
246
247 err = omap_des_hw_init(dd);
248 if (err)
249 return err;
250
251 key32 = dd->ctx->keylen / sizeof(u32);
252
253 /* it seems a key should always be set even if it has not changed */
254 for (i = 0; i < key32; i++) {
255 omap_des_write(dd, DES_REG_KEY(dd, i),
256 __le32_to_cpu(dd->ctx->key[i]));
257 }
258
259 if ((dd->flags & FLAGS_CBC) && dd->req->info)
260 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
261
262 if (dd->flags & FLAGS_CBC)
263 val |= DES_REG_CTRL_CBC;
264 if (dd->flags & FLAGS_ENCRYPT)
265 val |= DES_REG_CTRL_DIRECTION;
266 if (key32 == 6)
267 val |= DES_REG_CTRL_TDES;
268
269 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
270
271 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
272
273 return 0;
274}
275
276static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
277{
278 u32 mask, val;
279
280 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
281
282 val = dd->pdata->dma_start;
283
284 if (dd->dma_lch_out != NULL)
285 val |= dd->pdata->dma_enable_out;
286 if (dd->dma_lch_in != NULL)
287 val |= dd->pdata->dma_enable_in;
288
289 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
290 dd->pdata->dma_start;
291
292 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
293}
294
295static void omap_des_dma_stop(struct omap_des_dev *dd)
296{
297 u32 mask;
298
299 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
300 dd->pdata->dma_start;
301
302 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
303}
304
305static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
306{
307 struct omap_des_dev *dd = NULL, *tmp;
308
309 spin_lock_bh(&list_lock);
310 if (!ctx->dd) {
311 list_for_each_entry(tmp, &dev_list, list) {
312 /* FIXME: take fist available des core */
313 dd = tmp;
314 break;
315 }
316 ctx->dd = dd;
317 } else {
318 /* already found before */
319 dd = ctx->dd;
320 }
321 spin_unlock_bh(&list_lock);
322
323 return dd;
324}
325
326static void omap_des_dma_out_callback(void *data)
327{
328 struct omap_des_dev *dd = data;
329
330 /* dma_lch_out - completed */
331 tasklet_schedule(&dd->done_task);
332}
333
334static int omap_des_dma_init(struct omap_des_dev *dd)
335{
336 int err = -ENOMEM;
337 dma_cap_mask_t mask;
338
339 dd->dma_lch_out = NULL;
340 dd->dma_lch_in = NULL;
341
342 dma_cap_zero(mask);
343 dma_cap_set(DMA_SLAVE, mask);
344
345 dd->dma_lch_in = dma_request_slave_channel_compat(mask,
346 omap_dma_filter_fn,
347 &dd->dma_in,
348 dd->dev, "rx");
349 if (!dd->dma_lch_in) {
350 dev_err(dd->dev, "Unable to request in DMA channel\n");
351 goto err_dma_in;
352 }
353
354 dd->dma_lch_out = dma_request_slave_channel_compat(mask,
355 omap_dma_filter_fn,
356 &dd->dma_out,
357 dd->dev, "tx");
358 if (!dd->dma_lch_out) {
359 dev_err(dd->dev, "Unable to request out DMA channel\n");
360 goto err_dma_out;
361 }
362
363 return 0;
364
365err_dma_out:
366 dma_release_channel(dd->dma_lch_in);
367err_dma_in:
368 if (err)
369 pr_err("error: %d\n", err);
370 return err;
371}
372
373static void omap_des_dma_cleanup(struct omap_des_dev *dd)
374{
375 dma_release_channel(dd->dma_lch_out);
376 dma_release_channel(dd->dma_lch_in);
377}
378
379static void sg_copy_buf(void *buf, struct scatterlist *sg,
380 unsigned int start, unsigned int nbytes, int out)
381{
382 struct scatter_walk walk;
383
384 if (!nbytes)
385 return;
386
387 scatterwalk_start(&walk, sg);
388 scatterwalk_advance(&walk, start);
389 scatterwalk_copychunks(buf, &walk, nbytes, out);
390 scatterwalk_done(&walk, out, 0);
391}
392
393static int omap_des_crypt_dma(struct crypto_tfm *tfm,
394 struct scatterlist *in_sg, struct scatterlist *out_sg,
395 int in_sg_len, int out_sg_len)
396{
397 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
398 struct omap_des_dev *dd = ctx->dd;
399 struct dma_async_tx_descriptor *tx_in, *tx_out;
400 struct dma_slave_config cfg;
401 int ret;
402
403 if (dd->pio_only) {
404 scatterwalk_start(&dd->in_walk, dd->in_sg);
405 scatterwalk_start(&dd->out_walk, dd->out_sg);
406
407 /* Enable DATAIN interrupt and let it take
408 care of the rest */
409 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
410 return 0;
411 }
412
413 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
414
415 memset(&cfg, 0, sizeof(cfg));
416
417 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
418 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
419 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
420 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
421 cfg.src_maxburst = DST_MAXBURST;
422 cfg.dst_maxburst = DST_MAXBURST;
423
424 /* IN */
425 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
426 if (ret) {
427 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
428 ret);
429 return ret;
430 }
431
432 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
433 DMA_MEM_TO_DEV,
434 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
435 if (!tx_in) {
436 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
437 return -EINVAL;
438 }
439
440 /* No callback necessary */
441 tx_in->callback_param = dd;
442
443 /* OUT */
444 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
445 if (ret) {
446 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
447 ret);
448 return ret;
449 }
450
451 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
452 DMA_DEV_TO_MEM,
453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
454 if (!tx_out) {
455 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
456 return -EINVAL;
457 }
458
459 tx_out->callback = omap_des_dma_out_callback;
460 tx_out->callback_param = dd;
461
462 dmaengine_submit(tx_in);
463 dmaengine_submit(tx_out);
464
465 dma_async_issue_pending(dd->dma_lch_in);
466 dma_async_issue_pending(dd->dma_lch_out);
467
468 /* start DMA */
469 dd->pdata->trigger(dd, dd->total);
470
471 return 0;
472}
473
474static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
475{
476 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
477 crypto_ablkcipher_reqtfm(dd->req));
478 int err;
479
480 pr_debug("total: %d\n", dd->total);
481
482 if (!dd->pio_only) {
483 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
484 DMA_TO_DEVICE);
485 if (!err) {
486 dev_err(dd->dev, "dma_map_sg() error\n");
487 return -EINVAL;
488 }
489
490 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
491 DMA_FROM_DEVICE);
492 if (!err) {
493 dev_err(dd->dev, "dma_map_sg() error\n");
494 return -EINVAL;
495 }
496 }
497
498 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
499 dd->out_sg_len);
500 if (err && !dd->pio_only) {
501 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
502 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
503 DMA_FROM_DEVICE);
504 }
505
506 return err;
507}
508
509static void omap_des_finish_req(struct omap_des_dev *dd, int err)
510{
511 struct ablkcipher_request *req = dd->req;
512
513 pr_debug("err: %d\n", err);
514
515 pm_runtime_put(dd->dev);
516 dd->flags &= ~FLAGS_BUSY;
517
518 req->base.complete(&req->base, err);
519}
520
521static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
522{
523 int err = 0;
524
525 pr_debug("total: %d\n", dd->total);
526
527 omap_des_dma_stop(dd);
528
529 dmaengine_terminate_all(dd->dma_lch_in);
530 dmaengine_terminate_all(dd->dma_lch_out);
531
532 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
533 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE);
534
535 return err;
536}
537
538static int omap_des_copy_needed(struct scatterlist *sg)
539{
540 while (sg) {
541 if (!IS_ALIGNED(sg->offset, 4))
542 return -1;
543 if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE))
544 return -1;
545 sg = sg_next(sg);
546 }
547 return 0;
548}
549
550static int omap_des_copy_sgs(struct omap_des_dev *dd)
551{
552 void *buf_in, *buf_out;
553 int pages;
554
555 pages = dd->total >> PAGE_SHIFT;
556
557 if (dd->total & (PAGE_SIZE-1))
558 pages++;
559
560 BUG_ON(!pages);
561
562 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
563 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
564
565 if (!buf_in || !buf_out) {
566 pr_err("Couldn't allocated pages for unaligned cases.\n");
567 return -1;
568 }
569
570 dd->orig_out = dd->out_sg;
571
572 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
573
574 sg_init_table(&dd->in_sgl, 1);
575 sg_set_buf(&dd->in_sgl, buf_in, dd->total);
576 dd->in_sg = &dd->in_sgl;
577
578 sg_init_table(&dd->out_sgl, 1);
579 sg_set_buf(&dd->out_sgl, buf_out, dd->total);
580 dd->out_sg = &dd->out_sgl;
581
582 return 0;
583}
584
585static int omap_des_handle_queue(struct omap_des_dev *dd,
586 struct ablkcipher_request *req)
587{
588 struct crypto_async_request *async_req, *backlog;
589 struct omap_des_ctx *ctx;
590 struct omap_des_reqctx *rctx;
591 unsigned long flags;
592 int err, ret = 0;
593
594 spin_lock_irqsave(&dd->lock, flags);
595 if (req)
596 ret = ablkcipher_enqueue_request(&dd->queue, req);
597 if (dd->flags & FLAGS_BUSY) {
598 spin_unlock_irqrestore(&dd->lock, flags);
599 return ret;
600 }
601 backlog = crypto_get_backlog(&dd->queue);
602 async_req = crypto_dequeue_request(&dd->queue);
603 if (async_req)
604 dd->flags |= FLAGS_BUSY;
605 spin_unlock_irqrestore(&dd->lock, flags);
606
607 if (!async_req)
608 return ret;
609
610 if (backlog)
611 backlog->complete(backlog, -EINPROGRESS);
612
613 req = ablkcipher_request_cast(async_req);
614
615 /* assign new request to device */
616 dd->req = req;
617 dd->total = req->nbytes;
618 dd->total_save = req->nbytes;
619 dd->in_sg = req->src;
620 dd->out_sg = req->dst;
621
622 if (omap_des_copy_needed(dd->in_sg) ||
623 omap_des_copy_needed(dd->out_sg)) {
624 if (omap_des_copy_sgs(dd))
625 pr_err("Failed to copy SGs for unaligned cases\n");
626 dd->sgs_copied = 1;
627 } else {
628 dd->sgs_copied = 0;
629 }
630
631 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
632 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
633 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
634
635 rctx = ablkcipher_request_ctx(req);
636 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
637 rctx->mode &= FLAGS_MODE_MASK;
638 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
639
640 dd->ctx = ctx;
641 ctx->dd = dd;
642
643 err = omap_des_write_ctrl(dd);
644 if (!err)
645 err = omap_des_crypt_dma_start(dd);
646 if (err) {
647 /* des_task will not finish it, so do it here */
648 omap_des_finish_req(dd, err);
649 tasklet_schedule(&dd->queue_task);
650 }
651
652 return ret; /* return ret, which is enqueue return value */
653}
654
655static void omap_des_done_task(unsigned long data)
656{
657 struct omap_des_dev *dd = (struct omap_des_dev *)data;
658 void *buf_in, *buf_out;
659 int pages;
660
661 pr_debug("enter done_task\n");
662
663 if (!dd->pio_only) {
664 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
665 DMA_FROM_DEVICE);
666 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
667 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
668 DMA_FROM_DEVICE);
669 omap_des_crypt_dma_stop(dd);
670 }
671
672 if (dd->sgs_copied) {
673 buf_in = sg_virt(&dd->in_sgl);
674 buf_out = sg_virt(&dd->out_sgl);
675
676 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
677
678 pages = get_order(dd->total_save);
679 free_pages((unsigned long)buf_in, pages);
680 free_pages((unsigned long)buf_out, pages);
681 }
682
683 omap_des_finish_req(dd, 0);
684 omap_des_handle_queue(dd, NULL);
685
686 pr_debug("exit\n");
687}
688
689static void omap_des_queue_task(unsigned long data)
690{
691 struct omap_des_dev *dd = (struct omap_des_dev *)data;
692
693 omap_des_handle_queue(dd, NULL);
694}
695
696static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
697{
698 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
699 crypto_ablkcipher_reqtfm(req));
700 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
701 struct omap_des_dev *dd;
702
703 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
704 !!(mode & FLAGS_ENCRYPT),
705 !!(mode & FLAGS_CBC));
706
707 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
708 pr_err("request size is not exact amount of DES blocks\n");
709 return -EINVAL;
710 }
711
712 dd = omap_des_find_dev(ctx);
713 if (!dd)
714 return -ENODEV;
715
716 rctx->mode = mode;
717
718 return omap_des_handle_queue(dd, req);
719}
720
721/* ********************** ALG API ************************************ */
722
723static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
724 unsigned int keylen)
725{
726 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm);
727
728 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
729 return -EINVAL;
730
731 pr_debug("enter, keylen: %d\n", keylen);
732
733 memcpy(ctx->key, key, keylen);
734 ctx->keylen = keylen;
735
736 return 0;
737}
738
739static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
740{
741 return omap_des_crypt(req, FLAGS_ENCRYPT);
742}
743
744static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
745{
746 return omap_des_crypt(req, 0);
747}
748
749static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
750{
751 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
752}
753
754static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
755{
756 return omap_des_crypt(req, FLAGS_CBC);
757}
758
759static int omap_des_cra_init(struct crypto_tfm *tfm)
760{
761 pr_debug("enter\n");
762
763 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
764
765 return 0;
766}
767
768static void omap_des_cra_exit(struct crypto_tfm *tfm)
769{
770 pr_debug("enter\n");
771}
772
773/* ********************** ALGS ************************************ */
774
775static struct crypto_alg algs_ecb_cbc[] = {
776{
777 .cra_name = "ecb(des)",
778 .cra_driver_name = "ecb-des-omap",
779 .cra_priority = 100,
780 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
781 CRYPTO_ALG_KERN_DRIVER_ONLY |
782 CRYPTO_ALG_ASYNC,
783 .cra_blocksize = DES_BLOCK_SIZE,
784 .cra_ctxsize = sizeof(struct omap_des_ctx),
785 .cra_alignmask = 0,
786 .cra_type = &crypto_ablkcipher_type,
787 .cra_module = THIS_MODULE,
788 .cra_init = omap_des_cra_init,
789 .cra_exit = omap_des_cra_exit,
790 .cra_u.ablkcipher = {
791 .min_keysize = DES_KEY_SIZE,
792 .max_keysize = DES_KEY_SIZE,
793 .setkey = omap_des_setkey,
794 .encrypt = omap_des_ecb_encrypt,
795 .decrypt = omap_des_ecb_decrypt,
796 }
797},
798{
799 .cra_name = "cbc(des)",
800 .cra_driver_name = "cbc-des-omap",
801 .cra_priority = 100,
802 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
803 CRYPTO_ALG_KERN_DRIVER_ONLY |
804 CRYPTO_ALG_ASYNC,
805 .cra_blocksize = DES_BLOCK_SIZE,
806 .cra_ctxsize = sizeof(struct omap_des_ctx),
807 .cra_alignmask = 0,
808 .cra_type = &crypto_ablkcipher_type,
809 .cra_module = THIS_MODULE,
810 .cra_init = omap_des_cra_init,
811 .cra_exit = omap_des_cra_exit,
812 .cra_u.ablkcipher = {
813 .min_keysize = DES_KEY_SIZE,
814 .max_keysize = DES_KEY_SIZE,
815 .ivsize = DES_BLOCK_SIZE,
816 .setkey = omap_des_setkey,
817 .encrypt = omap_des_cbc_encrypt,
818 .decrypt = omap_des_cbc_decrypt,
819 }
820},
821{
822 .cra_name = "ecb(des3_ede)",
823 .cra_driver_name = "ecb-des3-omap",
824 .cra_priority = 100,
825 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
826 CRYPTO_ALG_KERN_DRIVER_ONLY |
827 CRYPTO_ALG_ASYNC,
828 .cra_blocksize = DES_BLOCK_SIZE,
829 .cra_ctxsize = sizeof(struct omap_des_ctx),
830 .cra_alignmask = 0,
831 .cra_type = &crypto_ablkcipher_type,
832 .cra_module = THIS_MODULE,
833 .cra_init = omap_des_cra_init,
834 .cra_exit = omap_des_cra_exit,
835 .cra_u.ablkcipher = {
836 .min_keysize = 3*DES_KEY_SIZE,
837 .max_keysize = 3*DES_KEY_SIZE,
838 .setkey = omap_des_setkey,
839 .encrypt = omap_des_ecb_encrypt,
840 .decrypt = omap_des_ecb_decrypt,
841 }
842},
843{
844 .cra_name = "cbc(des3_ede)",
845 .cra_driver_name = "cbc-des3-omap",
846 .cra_priority = 100,
847 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
848 CRYPTO_ALG_KERN_DRIVER_ONLY |
849 CRYPTO_ALG_ASYNC,
850 .cra_blocksize = DES_BLOCK_SIZE,
851 .cra_ctxsize = sizeof(struct omap_des_ctx),
852 .cra_alignmask = 0,
853 .cra_type = &crypto_ablkcipher_type,
854 .cra_module = THIS_MODULE,
855 .cra_init = omap_des_cra_init,
856 .cra_exit = omap_des_cra_exit,
857 .cra_u.ablkcipher = {
858 .min_keysize = 3*DES_KEY_SIZE,
859 .max_keysize = 3*DES_KEY_SIZE,
860 .ivsize = DES_BLOCK_SIZE,
861 .setkey = omap_des_setkey,
862 .encrypt = omap_des_cbc_encrypt,
863 .decrypt = omap_des_cbc_decrypt,
864 }
865}
866};
867
868static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
869 {
870 .algs_list = algs_ecb_cbc,
871 .size = ARRAY_SIZE(algs_ecb_cbc),
872 },
873};
874
875#ifdef CONFIG_OF
876static const struct omap_des_pdata omap_des_pdata_omap4 = {
877 .algs_info = omap_des_algs_info_ecb_cbc,
878 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
879 .trigger = omap_des_dma_trigger_omap4,
880 .key_ofs = 0x14,
881 .iv_ofs = 0x18,
882 .ctrl_ofs = 0x20,
883 .data_ofs = 0x28,
884 .rev_ofs = 0x30,
885 .mask_ofs = 0x34,
886 .irq_status_ofs = 0x3c,
887 .irq_enable_ofs = 0x40,
888 .dma_enable_in = BIT(5),
889 .dma_enable_out = BIT(6),
890 .major_mask = 0x0700,
891 .major_shift = 8,
892 .minor_mask = 0x003f,
893 .minor_shift = 0,
894};
895
896static irqreturn_t omap_des_irq(int irq, void *dev_id)
897{
898 struct omap_des_dev *dd = dev_id;
899 u32 status, i;
900 u32 *src, *dst;
901
902 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
903 if (status & DES_REG_IRQ_DATA_IN) {
904 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
905
906 BUG_ON(!dd->in_sg);
907
908 BUG_ON(_calc_walked(in) > dd->in_sg->length);
909
910 src = sg_virt(dd->in_sg) + _calc_walked(in);
911
912 for (i = 0; i < DES_BLOCK_WORDS; i++) {
913 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
914
915 scatterwalk_advance(&dd->in_walk, 4);
916 if (dd->in_sg->length == _calc_walked(in)) {
917 dd->in_sg = scatterwalk_sg_next(dd->in_sg);
918 if (dd->in_sg) {
919 scatterwalk_start(&dd->in_walk,
920 dd->in_sg);
921 src = sg_virt(dd->in_sg) +
922 _calc_walked(in);
923 }
924 } else {
925 src++;
926 }
927 }
928
929 /* Clear IRQ status */
930 status &= ~DES_REG_IRQ_DATA_IN;
931 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
932
933 /* Enable DATA_OUT interrupt */
934 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
935
936 } else if (status & DES_REG_IRQ_DATA_OUT) {
937 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
938
939 BUG_ON(!dd->out_sg);
940
941 BUG_ON(_calc_walked(out) > dd->out_sg->length);
942
943 dst = sg_virt(dd->out_sg) + _calc_walked(out);
944
945 for (i = 0; i < DES_BLOCK_WORDS; i++) {
946 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
947 scatterwalk_advance(&dd->out_walk, 4);
948 if (dd->out_sg->length == _calc_walked(out)) {
949 dd->out_sg = scatterwalk_sg_next(dd->out_sg);
950 if (dd->out_sg) {
951 scatterwalk_start(&dd->out_walk,
952 dd->out_sg);
953 dst = sg_virt(dd->out_sg) +
954 _calc_walked(out);
955 }
956 } else {
957 dst++;
958 }
959 }
960
961 dd->total -= DES_BLOCK_SIZE;
962
963 BUG_ON(dd->total < 0);
964
965 /* Clear IRQ status */
966 status &= ~DES_REG_IRQ_DATA_OUT;
967 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
968
969 if (!dd->total)
970 /* All bytes read! */
971 tasklet_schedule(&dd->done_task);
972 else
973 /* Enable DATA_IN interrupt for next block */
974 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
975 }
976
977 return IRQ_HANDLED;
978}
979
980static const struct of_device_id omap_des_of_match[] = {
981 {
982 .compatible = "ti,omap4-des",
983 .data = &omap_des_pdata_omap4,
984 },
985 {},
986};
987MODULE_DEVICE_TABLE(of, omap_des_of_match);
988
989static int omap_des_get_of(struct omap_des_dev *dd,
990 struct platform_device *pdev)
991{
992 const struct of_device_id *match;
993
994 match = of_match_device(of_match_ptr(omap_des_of_match), &pdev->dev);
995 if (!match) {
996 dev_err(&pdev->dev, "no compatible OF match\n");
997 return -EINVAL;
998 }
999
1000 dd->dma_out = -1; /* Dummy value that's unused */
1001 dd->dma_in = -1; /* Dummy value that's unused */
1002 dd->pdata = match->data;
1003
1004 return 0;
1005}
1006#else
1007static int omap_des_get_of(struct omap_des_dev *dd,
1008 struct device *dev)
1009{
1010 return -EINVAL;
1011}
1012#endif
1013
1014static int omap_des_get_pdev(struct omap_des_dev *dd,
1015 struct platform_device *pdev)
1016{
1017 struct device *dev = &pdev->dev;
1018 struct resource *r;
1019 int err = 0;
1020
1021 /* Get the DMA out channel */
1022 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1023 if (!r) {
1024 dev_err(dev, "no DMA out resource info\n");
1025 err = -ENODEV;
1026 goto err;
1027 }
1028 dd->dma_out = r->start;
1029
1030 /* Get the DMA in channel */
1031 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1032 if (!r) {
1033 dev_err(dev, "no DMA in resource info\n");
1034 err = -ENODEV;
1035 goto err;
1036 }
1037 dd->dma_in = r->start;
1038
1039 /* non-DT devices get pdata from pdev */
1040 dd->pdata = pdev->dev.platform_data;
1041
1042err:
1043 return err;
1044}
1045
1046static int omap_des_probe(struct platform_device *pdev)
1047{
1048 struct device *dev = &pdev->dev;
1049 struct omap_des_dev *dd;
1050 struct crypto_alg *algp;
1051 struct resource *res;
1052 int err = -ENOMEM, i, j, irq = -1;
1053 u32 reg;
1054
1055 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
1056 if (dd == NULL) {
1057 dev_err(dev, "unable to alloc data struct.\n");
1058 goto err_data;
1059 }
1060 dd->dev = dev;
1061 platform_set_drvdata(pdev, dd);
1062
1063 spin_lock_init(&dd->lock);
1064 crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH);
1065
1066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1067 if (!res) {
1068 dev_err(dev, "no MEM resource info\n");
1069 goto err_res;
1070 }
1071
1072 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
1073 omap_des_get_pdev(dd, pdev);
1074 if (err)
1075 goto err_res;
1076
1077 dd->io_base = devm_request_and_ioremap(dev, res);
1078 if (!dd->io_base) {
1079 dev_err(dev, "can't ioremap\n");
1080 err = -ENOMEM;
1081 goto err_res;
1082 }
1083 dd->phys_base = res->start;
1084
1085 pm_runtime_enable(dev);
1086 pm_runtime_get_sync(dev);
1087
1088 omap_des_dma_stop(dd);
1089
1090 reg = omap_des_read(dd, DES_REG_REV(dd));
1091
1092 pm_runtime_put_sync(dev);
1093
1094 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1095 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1096 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1097
1098 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1099 tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd);
1100
1101 err = omap_des_dma_init(dd);
1102 if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1103 dd->pio_only = 1;
1104
1105 irq = platform_get_irq(pdev, 0);
1106 if (irq < 0) {
1107 dev_err(dev, "can't get IRQ resource\n");
1108 goto err_irq;
1109 }
1110
1111 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1112 dev_name(dev), dd);
1113 if (err) {
1114 dev_err(dev, "Unable to grab omap-des IRQ\n");
1115 goto err_irq;
1116 }
1117 }
1118
1119
1120 INIT_LIST_HEAD(&dd->list);
1121 spin_lock(&list_lock);
1122 list_add_tail(&dd->list, &dev_list);
1123 spin_unlock(&list_lock);
1124
1125 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1126 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1127 algp = &dd->pdata->algs_info[i].algs_list[j];
1128
1129 pr_debug("reg alg: %s\n", algp->cra_name);
1130 INIT_LIST_HEAD(&algp->cra_list);
1131
1132 err = crypto_register_alg(algp);
1133 if (err)
1134 goto err_algs;
1135
1136 dd->pdata->algs_info[i].registered++;
1137 }
1138 }
1139
1140 return 0;
1141err_algs:
1142 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1143 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1144 crypto_unregister_alg(
1145 &dd->pdata->algs_info[i].algs_list[j]);
1146 if (!dd->pio_only)
1147 omap_des_dma_cleanup(dd);
1148err_irq:
1149 tasklet_kill(&dd->done_task);
1150 tasklet_kill(&dd->queue_task);
1151 pm_runtime_disable(dev);
1152err_res:
1153 dd = NULL;
1154err_data:
1155 dev_err(dev, "initialization failed.\n");
1156 return err;
1157}
1158
1159static int omap_des_remove(struct platform_device *pdev)
1160{
1161 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1162 int i, j;
1163
1164 if (!dd)
1165 return -ENODEV;
1166
1167 spin_lock(&list_lock);
1168 list_del(&dd->list);
1169 spin_unlock(&list_lock);
1170
1171 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1172 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1173 crypto_unregister_alg(
1174 &dd->pdata->algs_info[i].algs_list[j]);
1175
1176 tasklet_kill(&dd->done_task);
1177 tasklet_kill(&dd->queue_task);
1178 omap_des_dma_cleanup(dd);
1179 pm_runtime_disable(dd->dev);
1180 dd = NULL;
1181
1182 return 0;
1183}
1184
1185#ifdef CONFIG_PM_SLEEP
1186static int omap_des_suspend(struct device *dev)
1187{
1188 pm_runtime_put_sync(dev);
1189 return 0;
1190}
1191
1192static int omap_des_resume(struct device *dev)
1193{
1194 pm_runtime_get_sync(dev);
1195 return 0;
1196}
1197#endif
1198
1199static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1200
1201static struct platform_driver omap_des_driver = {
1202 .probe = omap_des_probe,
1203 .remove = omap_des_remove,
1204 .driver = {
1205 .name = "omap-des",
1206 .owner = THIS_MODULE,
1207 .pm = &omap_des_pm_ops,
1208 .of_match_table = of_match_ptr(omap_des_of_match),
1209 },
1210};
1211
1212module_platform_driver(omap_des_driver);
1213
1214MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1215MODULE_LICENSE("GPL v2");
1216MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");