1// SPDX-License-Identifier: GPL-2.0-or-later
   2
   3/* drivers/atm/firestream.c - FireStream 155 (MB86697) and
   4 *                            FireStream  50 (MB86695) device driver 
   5 */
   6 
   7/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl 
   8 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA 
   9 * and ambassador.c Copyright (C) 1995-1999  Madge Networks Ltd 
  10 */
  11
  12/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  13*/
  14
  15
  16#include <linux/module.h>
  17#include <linux/sched.h>
  18#include <linux/kernel.h>
  19#include <linux/mm.h>
  20#include <linux/pci.h>
  21#include <linux/poison.h>
  22#include <linux/errno.h>
  23#include <linux/atm.h>
  24#include <linux/atmdev.h>
  25#include <linux/sonet.h>
  26#include <linux/skbuff.h>
  27#include <linux/netdevice.h>
  28#include <linux/delay.h>
  29#include <linux/ioport.h> /* for request_region */
  30#include <linux/uio.h>
  31#include <linux/init.h>
  32#include <linux/interrupt.h>
  33#include <linux/capability.h>
  34#include <linux/bitops.h>
  35#include <linux/slab.h>
  36#include <asm/byteorder.h>
  37#include <asm/string.h>
  38#include <asm/io.h>
  39#include <linux/atomic.h>
  40#include <linux/uaccess.h>
  41#include <linux/wait.h>
  42
  43#include "firestream.h"
  44
  45static int loopback = 0;
  46static int num=0x5a;
  47
  48/* According to measurements (but they look suspicious to me!) done in
  49 * '97, 37% of the packets are one cell in size. So it pays to have
  50 * buffers allocated at that size. A large jump in percentage of
  51 * packets occurs at packets around 536 bytes in length. So it also
  52 * pays to have those pre-allocated. Unfortunately, we can't fully
  53 * take advantage of this as the majority of the packets is likely to
  54 * be TCP/IP (As where obviously the measurement comes from) There the
  55 * link would be opened with say a 1500 byte MTU, and we can't handle
  56 * smaller buffers more efficiently than the larger ones. -- REW
  57 */
  58
  59/* Due to the way Linux memory management works, specifying "576" as
  60 * an allocation size here isn't going to help. They are allocated
  61 * from 1024-byte regions anyway. With the size of the sk_buffs (quite
  62 * large), it doesn't pay to allocate the smallest size (64) -- REW */
  63
  64/* This is all guesswork. Hard numbers to back this up or disprove this, 
  65 * are appreciated. -- REW */
  66
  67/* The last entry should be about 64k. However, the "buffer size" is
  68 * passed to the chip in a 16 bit field. I don't know how "65536"
  69 * would be interpreted. -- REW */
  70
  71#define NP FS_NR_FREE_POOLS
  72static int rx_buf_sizes[NP]  = {128,  256,  512, 1024, 2048, 4096, 16384, 65520};
  73/* log2:                 7     8     9    10    11    12    14     16 */
  74
  75#if 0
  76static int rx_pool_sizes[NP] = {1024, 1024, 512, 256,  128,  64,   32,    32};
  77#else
  78/* debug */
  79static int rx_pool_sizes[NP] = {128,  128,  128, 64,   64,   64,   32,    32};
  80#endif
  81/* log2:                 10    10    9    8     7     6     5      5  */
  82/* sumlog2:              17    18    18   18    18    18    19     21 */
  83/* mem allocated:        128k  256k  256k 256k  256k  256k  512k   2M */
  84/* tot mem: almost 4M */
  85
  86/* NP is shorter, so that it fits on a single line. */
  87#undef NP
  88
  89
  90/* Small hardware gotcha:
  91
  92   The FS50 CAM (VP/VC match registers) always take the lowest channel
  93   number that matches. This is not a problem.
  94
  95   However, they also ignore whether the channel is enabled or
  96   not. This means that if you allocate channel 0 to 1.2 and then
  97   channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
  98   match channel for channel 0 will "steal" the traffic from channel
  99   1, even if you correctly disable channel 0.
 100
 101   Workaround: 
 102
 103   - When disabling channels, write an invalid VP/VC value to the
 104   match register. (We use 0xffffffff, which in the worst case 
 105   matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
 106   anything as some "when not in use, program to 0" bits are now
 107   programmed to 1...)
 108
 109   - Don't initialize the match registers to 0, as 0.0 is a valid
 110   channel.
 111*/
 112
 113
 114/* Optimization hints and tips.
 115
 116   The FireStream chips are very capable of reducing the amount of
 117   "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
 118   action. You could try to minimize this a bit. 
 119
 120   Besides that, the userspace->kernel copy and the PCI bus are the
 121   performance limiting issues for this driver.
 122
 123   You could queue up a bunch of outgoing packets without telling the
 124   FireStream. I'm not sure that's going to win you much though. The
 125   Linux layer won't tell us in advance when it's not going to give us
 126   any more packets in a while. So this is tricky to implement right without
 127   introducing extra delays. 
 128  
 129   -- REW
 130 */
 131
 132
 133
 134
 135/* The strings that define what the RX queue entry is all about. */
 136/* Fujitsu: Please tell me which ones can have a pointer to a 
 137   freepool descriptor! */
 138static char *res_strings[] = {
 139	"RX OK: streaming not EOP", 
 140	"RX OK: streaming EOP", 
 141	"RX OK: Single buffer packet", 
 142	"RX OK: packet mode", 
 143	"RX OK: F4 OAM (end to end)", 
 144	"RX OK: F4 OAM (Segment)", 
 145	"RX OK: F5 OAM (end to end)", 
 146	"RX OK: F5 OAM (Segment)", 
 147	"RX OK: RM cell", 
 148	"RX OK: TRANSP cell", 
 149	"RX OK: TRANSPC cell", 
 150	"Unmatched cell", 
 151	"reserved 12", 
 152	"reserved 13", 
 153	"reserved 14", 
 154	"Unrecognized cell", 
 155	"reserved 16", 
 156	"reassembly abort: AAL5 abort", 
 157	"packet purged", 
 158	"packet ageing timeout", 
 159	"channel ageing timeout", 
 160	"calculated length error", 
 161	"programmed length limit error", 
 162	"aal5 crc32 error", 
 163	"oam transp or transpc crc10 error", 
 164	"reserved 25", 
 165	"reserved 26", 
 166	"reserved 27", 
 167	"reserved 28", 
 168	"reserved 29", 
 169	"reserved 30", /* FIXME: The strings between 30-40 might be wrong. */
 170	"reassembly abort: no buffers", 
 171	"receive buffer overflow", 
 172	"change in GFC", 
 173	"receive buffer full", 
 174	"low priority discard - no receive descriptor", 
 175	"low priority discard - missing end of packet", 
 176	"reserved 37",
 177	"reserved 38",
 178	"reserved 39",
 179	"reserved 40",
 180	"reserved 41", 
 181	"reserved 42", 
 182	"reserved 43", 
 183	"reserved 44", 
 184	"reserved 45", 
 185	"reserved 46", 
 186	"reserved 47", 
 187	"reserved 48", 
 188	"reserved 49", 
 189	"reserved 50", 
 190	"reserved 51", 
 191	"reserved 52", 
 192	"reserved 53", 
 193	"reserved 54", 
 194	"reserved 55", 
 195	"reserved 56", 
 196	"reserved 57", 
 197	"reserved 58", 
 198	"reserved 59", 
 199	"reserved 60", 
 200	"reserved 61", 
 201	"reserved 62", 
 202	"reserved 63", 
 203};  
 204
 205static char *irq_bitname[] = {
 206	"LPCO",
 207	"DPCO",
 208	"RBRQ0_W",
 209	"RBRQ1_W",
 210	"RBRQ2_W",
 211	"RBRQ3_W",
 212	"RBRQ0_NF",
 213	"RBRQ1_NF",
 214	"RBRQ2_NF",
 215	"RBRQ3_NF",
 216	"BFP_SC",
 217	"INIT",
 218	"INIT_ERR",
 219	"USCEO",
 220	"UPEC0",
 221	"VPFCO",
 222	"CRCCO",
 223	"HECO",
 224	"TBRQ_W",
 225	"TBRQ_NF",
 226	"CTPQ_E",
 227	"GFC_C0",
 228	"PCI_FTL",
 229	"CSQ_W",
 230	"CSQ_NF",
 231	"EXT_INT",
 232	"RXDMA_S"
 233};
 234
 235
 236#define PHY_EOF -1
 237#define PHY_CLEARALL -2
 238
 239struct reginit_item {
 240	int reg, val;
 241};
 242
 243
 244static struct reginit_item PHY_NTC_INIT[] = {
 245	{ PHY_CLEARALL, 0x40 }, 
 246	{ 0x12,  0x0001 },
 247	{ 0x13,  0x7605 },
 248	{ 0x1A,  0x0001 },
 249	{ 0x1B,  0x0005 },
 250	{ 0x38,  0x0003 },
 251	{ 0x39,  0x0006 },   /* changed here to make loopback */
 252	{ 0x01,  0x5262 },
 253	{ 0x15,  0x0213 },
 254	{ 0x00,  0x0003 },
 255	{ PHY_EOF, 0},    /* -1 signals end of list */
 256};
 257
 258
 259/* Safetyfeature: If the card interrupts more than this number of times
 260   in a jiffy (1/100th of a second) then we just disable the interrupt and
 261   print a message. This prevents the system from hanging. 
 262
 263   150000 packets per second is close to the limit a PC is going to have
 264   anyway. We therefore have to disable this for production. -- REW */
 265#undef IRQ_RATE_LIMIT // 100
 266
 267/* Interrupts work now. Unlike serial cards, ATM cards don't work all
 268   that great without interrupts. -- REW */
 269#undef FS_POLL_FREQ // 100
 270
 271/* 
 272   This driver can spew a whole lot of debugging output at you. If you
 273   need maximum performance, you should disable the DEBUG define. To
 274   aid in debugging in the field, I'm leaving the compile-time debug
 275   features enabled, and disable them "runtime". That allows me to
 276   instruct people with problems to enable debugging without requiring
 277   them to recompile... -- REW
 278*/
 279#define DEBUG
 280
 281#ifdef DEBUG
 282#define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
 283#else
 284#define fs_dprintk(f, str...) /* nothing */
 285#endif
 286
 287
 288static int fs_keystream = 0;
 289
 290#ifdef DEBUG
 291/* I didn't forget to set this to zero before shipping. Hit me with a stick 
 292   if you get this with the debug default not set to zero again. -- REW */
 293static int fs_debug = 0;
 294#else
 295#define fs_debug 0
 296#endif
 297
 298#ifdef MODULE
 299#ifdef DEBUG 
 300module_param(fs_debug, int, 0644);
 301#endif
 302module_param(loopback, int, 0);
 303module_param(num, int, 0);
 304module_param(fs_keystream, int, 0);
 305/* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
 306#endif
 307
 308
 309#define FS_DEBUG_FLOW    0x00000001
 310#define FS_DEBUG_OPEN    0x00000002
 311#define FS_DEBUG_QUEUE   0x00000004
 312#define FS_DEBUG_IRQ     0x00000008
 313#define FS_DEBUG_INIT    0x00000010
 314#define FS_DEBUG_SEND    0x00000020
 315#define FS_DEBUG_PHY     0x00000040
 316#define FS_DEBUG_CLEANUP 0x00000080
 317#define FS_DEBUG_QOS     0x00000100
 318#define FS_DEBUG_TXQ     0x00000200
 319#define FS_DEBUG_ALLOC   0x00000400
 320#define FS_DEBUG_TXMEM   0x00000800
 321#define FS_DEBUG_QSIZE   0x00001000
 322
 323
 324#define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__)
 325#define func_exit()  fs_dprintk(FS_DEBUG_FLOW, "fs: exit  %s\n", __func__)
 326
 327
 328static struct fs_dev *fs_boards = NULL;
 329
 330#ifdef DEBUG
 331
 332static void my_hd (void *addr, int len)
 333{
 334	int j, ch;
 335	unsigned char *ptr = addr;
 336
 337	while (len > 0) {
 338		printk ("%p ", ptr);
 339		for (j=0;j < ((len < 16)?len:16);j++) {
 340			printk ("%02x %s", ptr[j], (j==7)?" ":"");
 341		}
 342		for (  ;j < 16;j++) {
 343			printk ("   %s", (j==7)?" ":"");
 344		}
 345		for (j=0;j < ((len < 16)?len:16);j++) {
 346			ch = ptr[j];
 347			printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
 348		}
 349		printk ("\n");
 350		ptr += 16;
 351		len -= 16;
 352	}
 353}
 354#else /* DEBUG */
 355static void my_hd (void *addr, int len){}
 356#endif /* DEBUG */
 357
 358/********** free an skb (as per ATM device driver documentation) **********/
 359
 360/* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
 361 * I copied it over from the ambassador driver. -- REW */
 362
 363static inline void fs_kfree_skb (struct sk_buff * skb) 
 364{
 365	if (ATM_SKB(skb)->vcc->pop)
 366		ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
 367	else
 368		dev_kfree_skb_any (skb);
 369}
 370
 371
 372
 373
 374/* It seems the ATM forum recommends this horribly complicated 16bit
 375 * floating point format. Turns out the Ambassador uses the exact same
 376 * encoding. I just copied it over. If Mitch agrees, I'll move it over
 377 * to the atm_misc file or something like that. (and remove it from 
 378 * here and the ambassador driver) -- REW
 379 */
 380
 381/* The good thing about this format is that it is monotonic. So, 
 382   a conversion routine need not be very complicated. To be able to
 383   round "nearest" we need to take along a few extra bits. Lets
 384   put these after 16 bits, so that we can just return the top 16
 385   bits of the 32bit number as the result:
 386
 387   int mr (unsigned int rate, int r) 
 388     {
 389     int e = 16+9;
 390     static int round[4]={0, 0, 0xffff, 0x8000};
 391     if (!rate) return 0;
 392     while (rate & 0xfc000000) {
 393       rate >>= 1;
 394       e++;
 395     }
 396     while (! (rate & 0xfe000000)) {
 397       rate <<= 1;
 398       e--;
 399     }
 400
 401// Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
 402     rate &= ~0x02000000;
 403// Next add in the exponent
 404     rate |= e << (16+9);
 405// And perform the rounding:
 406     return (rate + round[r]) >> 16;
 407   }
 408
 409   14 lines-of-code. Compare that with the 120 that the Ambassador
 410   guys needed. (would be 8 lines shorter if I'd try to really reduce
 411   the number of lines:
 412
 413   int mr (unsigned int rate, int r) 
 414   {
 415     int e = 16+9;
 416     static int round[4]={0, 0, 0xffff, 0x8000};
 417     if (!rate) return 0;
 418     for (;  rate & 0xfc000000 ;rate >>= 1, e++);
 419     for (;!(rate & 0xfe000000);rate <<= 1, e--);
 420     return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
 421   }
 422
 423   Exercise for the reader: Remove one more line-of-code, without
 424   cheating. (Just joining two lines is cheating). (I know it's
 425   possible, don't think you've beat me if you found it... If you
 426   manage to lose two lines or more, keep me updated! ;-)
 427
 428   -- REW */
 429
 430
 431#define ROUND_UP      1
 432#define ROUND_DOWN    2
 433#define ROUND_NEAREST 3
 434/********** make rate (not quite as much fun as Horizon) **********/
 435
 436static int make_rate(unsigned int rate, int r,
 437		      u16 *bits, unsigned int *actual)
 438{
 439	unsigned char exp = -1; /* hush gcc */
 440	unsigned int man = -1;  /* hush gcc */
 441  
 442	fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
 443  
 444	/* rates in cells per second, ITU format (nasty 16-bit floating-point)
 445	   given 5-bit e and 9-bit m:
 446	   rate = EITHER (1+m/2^9)*2^e    OR 0
 447	   bits = EITHER 1<<14 | e<<9 | m OR 0
 448	   (bit 15 is "reserved", bit 14 "non-zero")
 449	   smallest rate is 0 (special representation)
 450	   largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
 451	   smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
 452	   simple algorithm:
 453	   find position of top bit, this gives e
 454	   remove top bit and shift (rounding if feeling clever) by 9-e
 455	*/
 456	/* Ambassador ucode bug: please don't set bit 14! so 0 rate not
 457	   representable. // This should move into the ambassador driver
 458	   when properly merged. -- REW */
 459  
 460	if (rate > 0xffc00000U) {
 461		/* larger than largest representable rate */
 462    
 463		if (r == ROUND_UP) {
 464			return -EINVAL;
 465		} else {
 466			exp = 31;
 467			man = 511;
 468		}
 469    
 470	} else if (rate) {
 471		/* representable rate */
 472    
 473		exp = 31;
 474		man = rate;
 475    
 476		/* invariant: rate = man*2^(exp-31) */
 477		while (!(man & (1<<31))) {
 478			exp = exp - 1;
 479			man = man<<1;
 480		}
 481    
 482		/* man has top bit set
 483		   rate = (2^31+(man-2^31))*2^(exp-31)
 484		   rate = (1+(man-2^31)/2^31)*2^exp 
 485		*/
 486		man = man<<1;
 487		man &= 0xffffffffU; /* a nop on 32-bit systems */
 488		/* rate = (1+man/2^32)*2^exp
 489    
 490		   exp is in the range 0 to 31, man is in the range 0 to 2^32-1
 491		   time to lose significance... we want m in the range 0 to 2^9-1
 492		   rounding presents a minor problem... we first decide which way
 493		   we are rounding (based on given rounding direction and possibly
 494		   the bits of the mantissa that are to be discarded).
 495		*/
 496
 497		switch (r) {
 498		case ROUND_DOWN: {
 499			/* just truncate */
 500			man = man>>(32-9);
 501			break;
 502		}
 503		case ROUND_UP: {
 504			/* check all bits that we are discarding */
 505			if (man & (~0U>>9)) {
 506				man = (man>>(32-9)) + 1;
 507				if (man == (1<<9)) {
 508					/* no need to check for round up outside of range */
 509					man = 0;
 510					exp += 1;
 511				}
 512			} else {
 513				man = (man>>(32-9));
 514			}
 515			break;
 516		}
 517		case ROUND_NEAREST: {
 518			/* check msb that we are discarding */
 519			if (man & (1<<(32-9-1))) {
 520				man = (man>>(32-9)) + 1;
 521				if (man == (1<<9)) {
 522					/* no need to check for round up outside of range */
 523					man = 0;
 524					exp += 1;
 525				}
 526			} else {
 527				man = (man>>(32-9));
 528			}
 529			break;
 530		}
 531		}
 532    
 533	} else {
 534		/* zero rate - not representable */
 535    
 536		if (r == ROUND_DOWN) {
 537			return -EINVAL;
 538		} else {
 539			exp = 0;
 540			man = 0;
 541		}
 542	}
 543  
 544	fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
 545  
 546	if (bits)
 547		*bits = /* (1<<14) | */ (exp<<9) | man;
 548  
 549	if (actual)
 550		*actual = (exp >= 9)
 551			? (1 << exp) + (man << (exp-9))
 552			: (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
 553  
 554	return 0;
 555}
 556
 557
 558
 559
 560/* FireStream access routines */
 561/* For DEEP-DOWN debugging these can be rigged to intercept accesses to
 562   certain registers or to just log all accesses. */
 563
 564static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
 565{
 566	writel (val, dev->base + offset);
 567}
 568
 569
 570static inline u32  read_fs (struct fs_dev *dev, int offset)
 571{
 572	return readl (dev->base + offset);
 573}
 574
 575
 576
 577static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
 578{
 579	return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
 580}
 581
 582
 583static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
 584{
 585	u32 wp;
 586	struct FS_QENTRY *cqe;
 587
 588	/* XXX Sanity check: the write pointer can be checked to be 
 589	   still the same as the value passed as qe... -- REW */
 590	/*  udelay (5); */
 591	while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
 592		fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n", 
 593			    q->offset);
 594		schedule ();
 595	}
 596
 597	wp &= ~0xf;
 598	cqe = bus_to_virt (wp);
 599	if (qe != cqe) {
 600		fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
 601	}
 602
 603	write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
 604
 605	{
 606		static int c;
 607		if (!(c++ % 100))
 608			{
 609				int rp, wp;
 610				rp =  read_fs (dev, Q_RP(q->offset));
 611				wp =  read_fs (dev, Q_WP(q->offset));
 612				fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n", 
 613					    q->offset, rp, wp, wp-rp);
 614			}
 615	}
 616}
 617
 618#ifdef DEBUG_EXTRA
 619static struct FS_QENTRY pq[60];
 620static int qp;
 621
 622static struct FS_BPENTRY dq[60];
 623static int qd;
 624static void *da[60];
 625#endif 
 626
 627static void submit_queue (struct fs_dev *dev, struct queue *q, 
 628			  u32 cmd, u32 p1, u32 p2, u32 p3)
 629{
 630	struct FS_QENTRY *qe;
 631
 632	qe = get_qentry (dev, q);
 633	qe->cmd = cmd;
 634	qe->p0 = p1;
 635	qe->p1 = p2;
 636	qe->p2 = p3;
 637	submit_qentry (dev,  q, qe);
 638
 639#ifdef DEBUG_EXTRA
 640	pq[qp].cmd = cmd;
 641	pq[qp].p0 = p1;
 642	pq[qp].p1 = p2;
 643	pq[qp].p2 = p3;
 644	qp++;
 645	if (qp >= 60) qp = 0;
 646#endif
 647}
 648
 649/* Test the "other" way one day... -- REW */
 650#if 1
 651#define submit_command submit_queue
 652#else
 653
 654static void submit_command (struct fs_dev *dev, struct queue *q, 
 655			    u32 cmd, u32 p1, u32 p2, u32 p3)
 656{
 657	write_fs (dev, CMDR0, cmd);
 658	write_fs (dev, CMDR1, p1);
 659	write_fs (dev, CMDR2, p2);
 660	write_fs (dev, CMDR3, p3);
 661}
 662#endif
 663
 664
 665
 666static void process_return_queue (struct fs_dev *dev, struct queue *q)
 667{
 668	long rq;
 669	struct FS_QENTRY *qe;
 670	void *tc;
 671  
 672	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
 673		fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq); 
 674		qe = bus_to_virt (rq);
 675    
 676		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n", 
 677			    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
 678
 679		switch (STATUS_CODE (qe)) {
 680		case 5:
 681			tc = bus_to_virt (qe->p0);
 682			fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
 683			kfree (tc);
 684			break;
 685		}
 686    
 687		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
 688	}
 689}
 690
 691
 692static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
 693{
 694	long rq;
 695	long tmp;
 696	struct FS_QENTRY *qe;
 697	struct sk_buff *skb;
 698	struct FS_BPENTRY *td;
 699
 700	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
 701		fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq); 
 702		qe = bus_to_virt (rq);
 703    
 704		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n", 
 705			    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
 706
 707		if (STATUS_CODE (qe) != 2)
 708			fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n", 
 709				    qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
 710
 711
 712		switch (STATUS_CODE (qe)) {
 713		case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
 714			fallthrough;
 715		case 0x02:
 716			/* Process a real txdone entry. */
 717			tmp = qe->p0;
 718			if (tmp & 0x0f)
 719				printk (KERN_WARNING "td not aligned: %ld\n", tmp);
 720			tmp &= ~0x0f;
 721			td = bus_to_virt (tmp);
 722
 723			fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n", 
 724				    td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
 725      
 726			skb = td->skb;
 727			if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
 728				FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
 729				wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
 730			}
 731			td->dev->ntxpckts--;
 732
 733			{
 734				static int c=0;
 735	
 736				if (!(c++ % 100)) {
 737					fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
 738				}
 739			}
 740
 741			atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
 742
 743			fs_dprintk (FS_DEBUG_TXMEM, "i");
 744			fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
 745			fs_kfree_skb (skb);
 746
 747			fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td); 
 748			memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
 749			kfree (td);
 750			break;
 751		default:
 752			/* Here we get the tx purge inhibit command ... */
 753			/* Action, I believe, is "don't do anything". -- REW */
 754			;
 755		}
 756    
 757		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
 758	}
 759}
 760
 761
 762static void process_incoming (struct fs_dev *dev, struct queue *q)
 763{
 764	long rq;
 765	struct FS_QENTRY *qe;
 766	struct FS_BPENTRY *pe;    
 767	struct sk_buff *skb;
 768	unsigned int channo;
 769	struct atm_vcc *atm_vcc;
 770
 771	while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
 772		fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq); 
 773		qe = bus_to_virt (rq);
 774    
 775		fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x.  ", 
 776			    qe->cmd, qe->p0, qe->p1, qe->p2);
 777
 778		fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n", 
 779			    STATUS_CODE (qe), 
 780			    res_strings[STATUS_CODE(qe)]);
 781
 782		pe = bus_to_virt (qe->p0);
 783		fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n", 
 784			    pe->flags, pe->next, pe->bsa, pe->aal_bufsize, 
 785			    pe->skb, pe->fp);
 786      
 787		channo = qe->cmd & 0xffff;
 788
 789		if (channo < dev->nchannels)
 790			atm_vcc = dev->atm_vccs[channo];
 791		else
 792			atm_vcc = NULL;
 793
 794		/* Single buffer packet */
 795		switch (STATUS_CODE (qe)) {
 796		case 0x1:
 797			/* Fall through for streaming mode */
 798		case 0x2:/* Packet received OK.... */
 799			if (atm_vcc) {
 800				skb = pe->skb;
 801				pe->fp->n--;
 802#if 0
 803				fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
 804				if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
 805#endif
 806				skb_put (skb, qe->p1 & 0xffff); 
 807				ATM_SKB(skb)->vcc = atm_vcc;
 808				atomic_inc(&atm_vcc->stats->rx);
 809				__net_timestamp(skb);
 810				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
 811				atm_vcc->push (atm_vcc, skb);
 812				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
 813				kfree (pe);
 814			} else {
 815				printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
 816			}
 817			break;
 818		case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
 819			     has been consumed and needs to be processed. -- REW */
 820			if (qe->p1 & 0xffff) {
 821				pe = bus_to_virt (qe->p0);
 822				pe->fp->n--;
 823				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
 824				dev_kfree_skb_any (pe->skb);
 825				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
 826				kfree (pe);
 827			}
 828			if (atm_vcc)
 829				atomic_inc(&atm_vcc->stats->rx_drop);
 830			break;
 831		case 0x1f: /*  Reassembly abort: no buffers. */
 832			/* Silently increment error counter. */
 833			if (atm_vcc)
 834				atomic_inc(&atm_vcc->stats->rx_drop);
 835			break;
 836		default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
 837			printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n", 
 838				STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
 839		}
 840		write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
 841	}
 842}
 843
 844
 845
 846#define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
 847
 848static int fs_open(struct atm_vcc *atm_vcc)
 849{
 850	struct fs_dev *dev;
 851	struct fs_vcc *vcc;
 852	struct fs_transmit_config *tc;
 853	struct atm_trafprm * txtp;
 854	struct atm_trafprm * rxtp;
 855	/*  struct fs_receive_config *rc;*/
 856	/*  struct FS_QENTRY *qe; */
 857	int error;
 858	int bfp;
 859	int to;
 860	unsigned short tmc0;
 861	short vpi = atm_vcc->vpi;
 862	int vci = atm_vcc->vci;
 863
 864	func_enter ();
 865
 866	dev = FS_DEV(atm_vcc->dev);
 867	fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n", 
 868		    dev, atm_vcc);
 869
 870	if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
 871		set_bit(ATM_VF_ADDR, &atm_vcc->flags);
 872
 873	if ((atm_vcc->qos.aal != ATM_AAL5) &&
 874	    (atm_vcc->qos.aal != ATM_AAL2))
 875	  return -EINVAL; /* XXX AAL0 */
 876
 877	fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n", 
 878		    atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);	
 879
 880	/* XXX handle qos parameters (rate limiting) ? */
 881
 882	vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
 883	fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%zd)\n", vcc, sizeof(struct fs_vcc));
 884	if (!vcc) {
 885		clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
 886		return -ENOMEM;
 887	}
 888  
 889	atm_vcc->dev_data = vcc;
 890	vcc->last_skb = NULL;
 891
 892	init_waitqueue_head (&vcc->close_wait);
 893
 894	txtp = &atm_vcc->qos.txtp;
 895	rxtp = &atm_vcc->qos.rxtp;
 896
 897	if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
 898		if (IS_FS50(dev)) {
 899			/* Increment the channel numer: take a free one next time.  */
 900			for (to=33;to;to--, dev->channo++) {
 901				/* We only have 32 channels */
 902				if (dev->channo >= 32)
 903					dev->channo = 0;
 904				/* If we need to do RX, AND the RX is inuse, try the next */
 905				if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
 906					continue;
 907				/* If we need to do TX, AND the TX is inuse, try the next */
 908				if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
 909					continue;
 910				/* Ok, both are free! (or not needed) */
 911				break;
 912			}
 913			if (!to) {
 914				printk ("No more free channels for FS50..\n");
 915				kfree(vcc);
 916				return -EBUSY;
 917			}
 918			vcc->channo = dev->channo;
 919			dev->channo &= dev->channel_mask;
 920      
 921		} else {
 922			vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
 923			if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
 924			    ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
 925				printk ("Channel is in use for FS155.\n");
 926				kfree(vcc);
 927				return -EBUSY;
 928			}
 929		}
 930		fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n", 
 931			    vcc->channo, vcc->channo);
 932	}
 933
 934	if (DO_DIRECTION (txtp)) {
 935		tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
 936		fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%zd)\n",
 937			    tc, sizeof (struct fs_transmit_config));
 938		if (!tc) {
 939			fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
 940			kfree(vcc);
 941			return -ENOMEM;
 942		}
 943
 944		/* Allocate the "open" entry from the high priority txq. This makes
 945		   it most likely that the chip will notice it. It also prevents us
 946		   from having to wait for completion. On the other hand, we may
 947		   need to wait for completion anyway, to see if it completed
 948		   successfully. */
 949
 950		switch (atm_vcc->qos.aal) {
 951		case ATM_AAL2:
 952		case ATM_AAL0:
 953		  tc->flags = 0
 954		    | TC_FLAGS_TRANSPARENT_PAYLOAD
 955		    | TC_FLAGS_PACKET
 956		    | (1 << 28)
 957		    | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
 958		    | TC_FLAGS_CAL0;
 959		  break;
 960		case ATM_AAL5:
 961		  tc->flags = 0
 962			| TC_FLAGS_AAL5
 963			| TC_FLAGS_PACKET  /* ??? */
 964			| TC_FLAGS_TYPE_CBR
 965			| TC_FLAGS_CAL0;
 966		  break;
 967		default:
 968			printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
 969			tc->flags = 0;
 970		}
 971		/* Docs are vague about this atm_hdr field. By the way, the FS
 972		 * chip makes odd errors if lower bits are set.... -- REW */
 973		tc->atm_hdr =  (vpi << 20) | (vci << 4); 
 974		tmc0 = 0;
 975		{
 976			int pcr = atm_pcr_goal (txtp);
 977
 978			fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
 979
 980			/* XXX Hmm. officially we're only allowed to do this if rounding 
 981			   is round_down -- REW */
 982			if (IS_FS50(dev)) {
 983				if (pcr > 51840000/53/8)  pcr = 51840000/53/8;
 984			} else {
 985				if (pcr > 155520000/53/8) pcr = 155520000/53/8;
 986			}
 987			if (!pcr) {
 988				/* no rate cap */
 989				tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
 990			} else {
 991				int r;
 992				if (pcr < 0) {
 993					r = ROUND_DOWN;
 994					pcr = -pcr;
 995				} else {
 996					r = ROUND_UP;
 997				}
 998				error = make_rate (pcr, r, &tmc0, NULL);
 999				if (error) {
1000					kfree(tc);
1001					kfree(vcc);
1002					return error;
1003				}
1004			}
1005			fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
1006		}
1007      
1008		tc->TMC[0] = tmc0 | 0x4000;
1009		tc->TMC[1] = 0; /* Unused */
1010		tc->TMC[2] = 0; /* Unused */
1011		tc->TMC[3] = 0; /* Unused */
1012    
1013		tc->spec = 0;    /* UTOPIA address, UDF, HEC: Unused -> 0 */
1014		tc->rtag[0] = 0; /* What should I do with routing tags??? 
1015				    -- Not used -- AS -- Thanks -- REW*/
1016		tc->rtag[1] = 0;
1017		tc->rtag[2] = 0;
1018
1019		if (fs_debug & FS_DEBUG_OPEN) {
1020			fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
1021			my_hd (tc, sizeof (*tc));
1022		}
1023
1024		/* We now use the "submit_command" function to submit commands to
1025		   the firestream. There is a define up near the definition of
1026		   that routine that switches this routine between immediate write
1027		   to the immediate command registers and queuing the commands in
1028		   the HPTXQ for execution. This last technique might be more
1029		   efficient if we know we're going to submit a whole lot of
1030		   commands in one go, but this driver is not setup to be able to
1031		   use such a construct. So it probably doen't matter much right
1032		   now. -- REW */
1033    
1034		/* The command is IMMediate and INQueue. The parameters are out-of-line.. */
1035		submit_command (dev, &dev->hp_txq, 
1036				QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
1037				virt_to_bus (tc), 0, 0);
1038
1039		submit_command (dev, &dev->hp_txq, 
1040				QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
1041				0, 0, 0);
1042		set_bit (vcc->channo, dev->tx_inuse);
1043	}
1044
1045	if (DO_DIRECTION (rxtp)) {
1046		dev->atm_vccs[vcc->channo] = atm_vcc;
1047
1048		for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
1049			if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
1050		if (bfp >= FS_NR_FREE_POOLS) {
1051			fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n", 
1052				    atm_vcc->qos.rxtp.max_sdu);
1053			/* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
1054
1055			/* XXX clear tx inuse. Close TX part? */
1056			dev->atm_vccs[vcc->channo] = NULL;
1057			kfree (vcc);
1058			return -EINVAL;
1059		}
1060
1061		switch (atm_vcc->qos.aal) {
1062		case ATM_AAL0:
1063		case ATM_AAL2:
1064			submit_command (dev, &dev->hp_txq,
1065					QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1066					RC_FLAGS_TRANSP |
1067					RC_FLAGS_BFPS_BFP * bfp |
1068					RC_FLAGS_RXBM_PSB, 0, 0);
1069			break;
1070		case ATM_AAL5:
1071			submit_command (dev, &dev->hp_txq,
1072					QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1073					RC_FLAGS_AAL5 |
1074					RC_FLAGS_BFPS_BFP * bfp |
1075					RC_FLAGS_RXBM_PSB, 0, 0);
1076			break;
1077		}
1078		if (IS_FS50 (dev)) {
1079			submit_command (dev, &dev->hp_txq, 
1080					QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1081					0x80 + vcc->channo,
1082					(vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
1083		}
1084		submit_command (dev, &dev->hp_txq, 
1085				QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
1086				0, 0, 0);
1087	}
1088    
1089	/* Indicate we're done! */
1090	set_bit(ATM_VF_READY, &atm_vcc->flags);
1091
1092	func_exit ();
1093	return 0;
1094}
1095
1096
1097static void fs_close(struct atm_vcc *atm_vcc)
1098{
1099	struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1100	struct fs_vcc *vcc = FS_VCC (atm_vcc);
1101	struct atm_trafprm * txtp;
1102	struct atm_trafprm * rxtp;
1103
1104	func_enter ();
1105
1106	clear_bit(ATM_VF_READY, &atm_vcc->flags);
1107
1108	fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
1109	if (vcc->last_skb) {
1110		fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n", 
1111			    vcc->last_skb);
1112		/* We're going to wait for the last packet to get sent on this VC. It would
1113		   be impolite not to send them don't you think? 
1114		   XXX
1115		   We don't know which packets didn't get sent. So if we get interrupted in 
1116		   this sleep_on, we'll lose any reference to these packets. Memory leak!
1117		   On the other hand, it's awfully convenient that we can abort a "close" that
1118		   is taking too long. Maybe just use non-interruptible sleep on? -- REW */
1119		wait_event_interruptible(vcc->close_wait, !vcc->last_skb);
1120	}
1121
1122	txtp = &atm_vcc->qos.txtp;
1123	rxtp = &atm_vcc->qos.rxtp;
1124  
1125
1126	/* See App note XXX (Unpublished as of now) for the reason for the 
1127	   removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
1128
1129	if (DO_DIRECTION (txtp)) {
1130		submit_command (dev,  &dev->hp_txq,
1131				QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
1132		clear_bit (vcc->channo, dev->tx_inuse);
1133	}
1134
1135	if (DO_DIRECTION (rxtp)) {
1136		submit_command (dev,  &dev->hp_txq,
1137				QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1138		dev->atm_vccs [vcc->channo] = NULL;
1139  
1140		/* This means that this is configured as a receive channel */
1141		if (IS_FS50 (dev)) {
1142			/* Disable the receive filter. Is 0/0 indeed an invalid receive
1143			   channel? -- REW.  Yes it is. -- Hang. Ok. I'll use -1
1144			   (0xfff...) -- REW */
1145			submit_command (dev, &dev->hp_txq, 
1146					QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1147					0x80 + vcc->channo, -1, 0 ); 
1148		}
1149	}
1150
1151	fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
1152	kfree (vcc);
1153
1154	func_exit ();
1155}
1156
1157
1158static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
1159{
1160	struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1161	struct fs_vcc *vcc = FS_VCC (atm_vcc);
1162	struct FS_BPENTRY *td;
1163
1164	func_enter ();
1165
1166	fs_dprintk (FS_DEBUG_TXMEM, "I");
1167	fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n", 
1168		    atm_vcc, skb, vcc, dev);
1169
1170	fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
1171
1172	ATM_SKB(skb)->vcc = atm_vcc;
1173
1174	vcc->last_skb = skb;
1175
1176	td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
1177	fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%zd)\n", td, sizeof (struct FS_BPENTRY));
1178	if (!td) {
1179		/* Oops out of mem */
1180		return -ENOMEM;
1181	}
1182
1183	fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n", 
1184		    *(int *) skb->data);
1185
1186	td->flags =  TD_EPI | TD_DATA | skb->len;
1187	td->next = 0;
1188	td->bsa  = virt_to_bus (skb->data);
1189	td->skb = skb;
1190	td->dev = dev;
1191	dev->ntxpckts++;
1192
1193#ifdef DEBUG_EXTRA
1194	da[qd] = td;
1195	dq[qd].flags = td->flags;
1196	dq[qd].next  = td->next;
1197	dq[qd].bsa   = td->bsa;
1198	dq[qd].skb   = td->skb;
1199	dq[qd].dev   = td->dev;
1200	qd++;
1201	if (qd >= 60) qd = 0;
1202#endif
1203
1204	submit_queue (dev, &dev->hp_txq, 
1205		      QE_TRANSMIT_DE | vcc->channo,
1206		      virt_to_bus (td), 0, 
1207		      virt_to_bus (td));
1208
1209	fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n", 
1210		    read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1211		    read_fs (dev, Q_SA (dev->hp_txq.offset)),
1212		    read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1213		    read_fs (dev, Q_SA (dev->tx_relq.offset)));
1214
1215	func_exit ();
1216	return 0;
1217}
1218
1219
1220/* Some function placeholders for functions we don't yet support. */
1221
1222#if 0
1223static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1224{
1225	func_enter ();
1226	func_exit ();
1227	return -ENOIOCTLCMD;
1228}
1229
1230
1231static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
1232			 void __user *optval,int optlen)
1233{
1234	func_enter ();
1235	func_exit ();
1236	return 0;
1237}
1238
1239
1240static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
1241			 void __user *optval,unsigned int optlen)
1242{
1243	func_enter ();
1244	func_exit ();
1245	return 0;
1246}
1247
1248
1249static void fs_phy_put(struct atm_dev *dev,unsigned char value,
1250		       unsigned long addr)
1251{
1252	func_enter ();
1253	func_exit ();
1254}
1255
1256
1257static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
1258{
1259	func_enter ();
1260	func_exit ();
1261	return 0;
1262}
1263
1264
1265static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1266{
1267	func_enter ();
1268	func_exit ();
1269	return 0;
1270};
1271
1272#endif
1273
1274
1275static const struct atmdev_ops ops = {
1276	.open =         fs_open,
1277	.close =        fs_close,
1278	.send =         fs_send,
1279	.owner =        THIS_MODULE,
1280	/* ioctl:          fs_ioctl, */
 
 
1281	/* change_qos:     fs_change_qos, */
1282
1283	/* For now implement these internally here... */  
1284	/* phy_put:        fs_phy_put, */
1285	/* phy_get:        fs_phy_get, */
1286};
1287
1288
1289static void undocumented_pci_fix(struct pci_dev *pdev)
1290{
1291	u32 tint;
1292
1293	/* The Windows driver says: */
1294	/* Switch off FireStream Retry Limit Threshold 
1295	 */
1296
1297	/* The register at 0x28 is documented as "reserved", no further
1298	   comments. */
1299
1300	pci_read_config_dword (pdev, 0x28, &tint);
1301	if (tint != 0x80) {
1302		tint = 0x80;
1303		pci_write_config_dword (pdev, 0x28, tint);
1304	}
1305}
1306
1307
1308
1309/**************************************************************************
1310 *                              PHY routines                              *
1311 **************************************************************************/
1312
1313static void write_phy(struct fs_dev *dev, int regnum, int val)
1314{
1315	submit_command (dev,  &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
1316			regnum, val, 0);
1317}
1318
1319static int init_phy(struct fs_dev *dev, struct reginit_item *reginit)
1320{
1321	int i;
1322
1323	func_enter ();
1324	while (reginit->reg != PHY_EOF) {
1325		if (reginit->reg == PHY_CLEARALL) {
1326			/* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
1327			for (i=0;i<reginit->val;i++) {
1328				write_phy (dev, i, 0);
1329			}
1330		} else {
1331			write_phy (dev, reginit->reg, reginit->val);
1332		}
1333		reginit++;
1334	}
1335	func_exit ();
1336	return 0;
1337}
1338
1339static void reset_chip (struct fs_dev *dev)
1340{
1341	int i;
1342
1343	write_fs (dev, SARMODE0, SARMODE0_SRTS0);
1344
1345	/* Undocumented delay */
1346	udelay (128);
1347
1348	/* The "internal registers are documented to all reset to zero, but 
1349	   comments & code in the Windows driver indicates that the pools are
1350	   NOT reset. */
1351	for (i=0;i < FS_NR_FREE_POOLS;i++) {
1352		write_fs (dev, FP_CNF (RXB_FP(i)), 0);
1353		write_fs (dev, FP_SA  (RXB_FP(i)), 0);
1354		write_fs (dev, FP_EA  (RXB_FP(i)), 0);
1355		write_fs (dev, FP_CNT (RXB_FP(i)), 0);
1356		write_fs (dev, FP_CTU (RXB_FP(i)), 0);
1357	}
1358
1359	/* The same goes for the match channel registers, although those are
1360	   NOT documented that way in the Windows driver. -- REW */
1361	/* The Windows driver DOES write 0 to these registers somewhere in
1362	   the init sequence. However, a small hardware-feature, will
1363	   prevent reception of data on VPI/VCI = 0/0 (Unless the channel
1364	   allocated happens to have no disabled channels that have a lower
1365	   number. -- REW */
1366
1367	/* Clear the match channel registers. */
1368	if (IS_FS50 (dev)) {
1369		for (i=0;i<FS50_NR_CHANNELS;i++) {
1370			write_fs (dev, 0x200 + i * 4, -1);
1371		}
1372	}
1373}
1374
1375static void *aligned_kmalloc(int size, gfp_t flags, int alignment)
1376{
1377	void  *t;
1378
1379	if (alignment <= 0x10) {
1380		t = kmalloc (size, flags);
1381		if ((unsigned long)t & (alignment-1)) {
1382			printk ("Kmalloc doesn't align things correctly! %p\n", t);
1383			kfree (t);
1384			return aligned_kmalloc (size, flags, alignment * 4);
1385		}
1386		return t;
1387	}
1388	printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
1389	return NULL;
1390}
1391
1392static int init_q(struct fs_dev *dev, struct queue *txq, int queue,
1393		  int nentries, int is_rq)
1394{
1395	int sz = nentries * sizeof (struct FS_QENTRY);
1396	struct FS_QENTRY *p;
1397
1398	func_enter ();
1399
1400	fs_dprintk (FS_DEBUG_INIT, "Initializing queue at %x: %d entries:\n",
1401		    queue, nentries);
1402
1403	p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
1404	fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
1405
1406	if (!p) return 0;
1407
1408	write_fs (dev, Q_SA(queue), virt_to_bus(p));
1409	write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
1410	write_fs (dev, Q_WP(queue), virt_to_bus(p));
1411	write_fs (dev, Q_RP(queue), virt_to_bus(p));
1412	if (is_rq) {
1413		/* Configuration for the receive queue: 0: interrupt immediately,
1414		   no pre-warning to empty queues: We do our best to keep the
1415		   queue filled anyway. */
1416		write_fs (dev, Q_CNF(queue), 0 ); 
1417	}
1418
1419	txq->sa = p;
1420	txq->ea = p;
1421	txq->offset = queue; 
1422
1423	func_exit ();
1424	return 1;
1425}
1426
1427
1428static int init_fp(struct fs_dev *dev, struct freepool *fp, int queue,
1429		   int bufsize, int nr_buffers)
1430{
1431	func_enter ();
1432
1433	fs_dprintk (FS_DEBUG_INIT, "Initializing free pool at %x:\n", queue);
1434
1435	write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
1436	write_fs (dev, FP_SA(queue),  0);
1437	write_fs (dev, FP_EA(queue),  0);
1438	write_fs (dev, FP_CTU(queue), 0);
1439	write_fs (dev, FP_CNT(queue), 0);
1440
1441	fp->offset = queue; 
1442	fp->bufsize = bufsize;
1443	fp->nr_buffers = nr_buffers;
1444
1445	func_exit ();
1446	return 1;
1447}
1448
1449
1450static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
1451{
1452#if 0
1453	/* This seems to be unreliable.... */
1454	return read_fs (dev, FP_CNT (fp->offset));
1455#else
1456	return fp->n;
1457#endif
1458}
1459
1460
1461/* Check if this gets going again if a pool ever runs out.  -- Yes, it
1462   does. I've seen "receive abort: no buffers" and things started
1463   working again after that...  -- REW */
1464
1465static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
1466			gfp_t gfp_flags)
1467{
1468	struct FS_BPENTRY *qe, *ne;
1469	struct sk_buff *skb;
1470	int n = 0;
1471	u32 qe_tmp;
1472
1473	fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n", 
1474		    fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n, 
1475		    fp->nr_buffers);
1476	while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
1477
1478		skb = alloc_skb (fp->bufsize, gfp_flags);
1479		fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
1480		if (!skb) break;
1481		ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
1482		fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%zd)\n", ne, sizeof (struct FS_BPENTRY));
1483		if (!ne) {
1484			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
1485			dev_kfree_skb_any (skb);
1486			break;
1487		}
1488
1489		fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ", 
1490			    skb, ne, skb->data, skb->head);
1491		n++;
1492		ne->flags = FP_FLAGS_EPI | fp->bufsize;
1493		ne->next  = virt_to_bus (NULL);
1494		ne->bsa   = virt_to_bus (skb->data);
1495		ne->aal_bufsize = fp->bufsize;
1496		ne->skb = skb;
1497		ne->fp = fp;
1498
1499		/*
1500		 * FIXME: following code encodes and decodes
1501		 * machine pointers (could be 64-bit) into a
1502		 * 32-bit register.
1503		 */
1504
1505		qe_tmp = read_fs (dev, FP_EA(fp->offset));
1506		fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
1507		if (qe_tmp) {
1508			qe = bus_to_virt ((long) qe_tmp);
1509			qe->next = virt_to_bus(ne);
1510			qe->flags &= ~FP_FLAGS_EPI;
1511		} else
1512			write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
1513
1514		write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
1515		fp->n++;   /* XXX Atomic_inc? */
1516		write_fs (dev, FP_CTU(fp->offset), 1);
1517	}
1518
1519	fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
1520}
1521
1522static void free_queue(struct fs_dev *dev, struct queue *txq)
1523{
1524	func_enter ();
1525
1526	write_fs (dev, Q_SA(txq->offset), 0);
1527	write_fs (dev, Q_EA(txq->offset), 0);
1528	write_fs (dev, Q_RP(txq->offset), 0);
1529	write_fs (dev, Q_WP(txq->offset), 0);
1530	/* Configuration ? */
1531
1532	fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
1533	kfree (txq->sa);
1534
1535	func_exit ();
1536}
1537
1538static void free_freepool(struct fs_dev *dev, struct freepool *fp)
1539{
1540	func_enter ();
1541
1542	write_fs (dev, FP_CNF(fp->offset), 0);
1543	write_fs (dev, FP_SA (fp->offset), 0);
1544	write_fs (dev, FP_EA (fp->offset), 0);
1545	write_fs (dev, FP_CNT(fp->offset), 0);
1546	write_fs (dev, FP_CTU(fp->offset), 0);
1547
1548	func_exit ();
1549}
1550
1551
1552
1553static irqreturn_t fs_irq (int irq, void *dev_id) 
1554{
1555	int i;
1556	u32 status;
1557	struct fs_dev *dev = dev_id;
1558
1559	status = read_fs (dev, ISR);
1560	if (!status)
1561		return IRQ_NONE;
1562
1563	func_enter ();
1564
1565#ifdef IRQ_RATE_LIMIT
1566	/* Aaargh! I'm ashamed. This costs more lines-of-code than the actual 
1567	   interrupt routine!. (Well, used to when I wrote that comment) -- REW */
1568	{
1569		static int lastjif;
1570		static int nintr=0;
1571    
1572		if (lastjif == jiffies) {
1573			if (++nintr > IRQ_RATE_LIMIT) {
1574				free_irq (dev->irq, dev_id);
1575				printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n", 
1576					dev->irq);
1577			}
1578		} else {
1579			lastjif = jiffies;
1580			nintr = 0;
1581		}
1582	}
1583#endif
1584	fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n", 
1585		    read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1586		    read_fs (dev, Q_SA (dev->hp_txq.offset)),
1587		    read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1588		    read_fs (dev, Q_SA (dev->tx_relq.offset)));
1589
1590	/* print the bits in the ISR register. */
1591	if (fs_debug & FS_DEBUG_IRQ) {
1592		/* The FS_DEBUG things are unnecessary here. But this way it is
1593		   clear for grep that these are debug prints. */
1594		fs_dprintk (FS_DEBUG_IRQ,  "IRQ status:");
1595		for (i=0;i<27;i++) 
1596			if (status & (1 << i)) 
1597				fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
1598		fs_dprintk (FS_DEBUG_IRQ, "\n");
1599	}
1600  
1601	if (status & ISR_RBRQ0_W) {
1602		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
1603		process_incoming (dev, &dev->rx_rq[0]);
1604		/* items mentioned on RBRQ0 are from FP 0 or 1. */
1605		top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
1606		top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
1607	}
1608
1609	if (status & ISR_RBRQ1_W) {
1610		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
1611		process_incoming (dev, &dev->rx_rq[1]);
1612		top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
1613		top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
1614	}
1615
1616	if (status & ISR_RBRQ2_W) {
1617		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
1618		process_incoming (dev, &dev->rx_rq[2]);
1619		top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
1620		top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
1621	}
1622
1623	if (status & ISR_RBRQ3_W) {
1624		fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
1625		process_incoming (dev, &dev->rx_rq[3]);
1626		top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
1627		top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
1628	}
1629
1630	if (status & ISR_CSQ_W) {
1631		fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
1632		process_return_queue (dev, &dev->st_q);
1633	}
1634
1635	if (status & ISR_TBRQ_W) {
1636		fs_dprintk (FS_DEBUG_IRQ, "Data transmitted!\n");
1637		process_txdone_queue (dev, &dev->tx_relq);
1638	}
1639
1640	func_exit ();
1641	return IRQ_HANDLED;
1642}
1643
1644
1645#ifdef FS_POLL_FREQ
1646static void fs_poll (struct timer_list *t)
1647{
1648	struct fs_dev *dev = from_timer(dev, t, timer);
1649  
1650	fs_irq (0, dev);
1651	dev->timer.expires = jiffies + FS_POLL_FREQ;
1652	add_timer (&dev->timer);
1653}
1654#endif
1655
1656static int fs_init(struct fs_dev *dev)
1657{
1658	struct pci_dev  *pci_dev;
1659	int isr, to;
1660	int i;
1661
1662	func_enter ();
1663	pci_dev = dev->pci_dev;
1664
1665	printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
1666		IS_FS50(dev)?50:155,
1667		(unsigned long long)pci_resource_start(pci_dev, 0),
1668		dev->pci_dev->irq);
1669
1670	if (fs_debug & FS_DEBUG_INIT)
1671		my_hd ((unsigned char *) dev, sizeof (*dev));
1672
1673	undocumented_pci_fix (pci_dev);
1674
1675	dev->hw_base = pci_resource_start(pci_dev, 0);
1676
1677	dev->base = ioremap(dev->hw_base, 0x1000);
1678
1679	reset_chip (dev);
1680  
1681	write_fs (dev, SARMODE0, 0 
1682		  | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1683		  | (1 * SARMODE0_INTMODE_READCLEAR)
1684		  | (1 * SARMODE0_CWRE)
1685		  | (IS_FS50(dev) ? SARMODE0_PRPWT_FS50_5:
1686			  SARMODE0_PRPWT_FS155_3)
1687		  | (1 * SARMODE0_CALSUP_1)
1688		  | (IS_FS50(dev) ? (0
1689				   | SARMODE0_RXVCS_32
1690				   | SARMODE0_ABRVCS_32 
1691				   | SARMODE0_TXVCS_32):
1692		                  (0
1693				   | SARMODE0_RXVCS_1k
1694				   | SARMODE0_ABRVCS_1k 
1695				   | SARMODE0_TXVCS_1k)));
1696
1697	/* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
1698	   1ms. */
1699	to = 100;
1700	while (--to) {
1701		isr = read_fs (dev, ISR);
1702
1703		/* This bit is documented as "RESERVED" */
1704		if (isr & ISR_INIT_ERR) {
1705			printk (KERN_ERR "Error initializing the FS... \n");
1706			goto unmap;
1707		}
1708		if (isr & ISR_INIT) {
1709			fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
1710			break;
1711		}
1712
1713		/* Try again after 10ms. */
1714		msleep(10);
1715	}
1716
1717	if (!to) {
1718		printk (KERN_ERR "timeout initializing the FS... \n");
1719		goto unmap;
1720	}
1721
1722	/* XXX fix for fs155 */
1723	dev->channel_mask = 0x1f; 
1724	dev->channo = 0;
1725
1726	/* AN3: 10 */
1727	write_fs (dev, SARMODE1, 0 
1728		  | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
1729		  | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
1730		  | (1 * SARMODE1_DCRM)
1731		  | (1 * SARMODE1_DCOAM)
1732		  | (0 * SARMODE1_OAMCRC)
1733		  | (0 * SARMODE1_DUMPE)
1734		  | (0 * SARMODE1_GPLEN) 
1735		  | (0 * SARMODE1_GNAM)
1736		  | (0 * SARMODE1_GVAS)
1737		  | (0 * SARMODE1_GPAS)
1738		  | (1 * SARMODE1_GPRI)
1739		  | (0 * SARMODE1_PMS)
1740		  | (0 * SARMODE1_GFCR)
1741		  | (1 * SARMODE1_HECM2)
1742		  | (1 * SARMODE1_HECM1)
1743		  | (1 * SARMODE1_HECM0)
1744		  | (1 << 12) /* That's what hang's driver does. Program to 0 */
1745		  | (0 * 0xff) /* XXX FS155 */);
1746
1747
1748	/* Cal prescale etc */
1749
1750	/* AN3: 11 */
1751	write_fs (dev, TMCONF, 0x0000000f);
1752	write_fs (dev, CALPRESCALE, 0x01010101 * num);
1753	write_fs (dev, 0x80, 0x000F00E4);
1754
1755	/* AN3: 12 */
1756	write_fs (dev, CELLOSCONF, 0
1757		  | (   0 * CELLOSCONF_CEN)
1758		  | (       CELLOSCONF_SC1)
1759		  | (0x80 * CELLOSCONF_COBS)
1760		  | (num  * CELLOSCONF_COPK)  /* Changed from 0xff to 0x5a */
1761		  | (num  * CELLOSCONF_COST));/* after a hint from Hang. 
1762					       * performance jumped 50->70... */
1763
1764	/* Magic value by Hang */
1765	write_fs (dev, CELLOSCONF_COST, 0x0B809191);
1766
1767	if (IS_FS50 (dev)) {
1768		write_fs (dev, RAS0, RAS0_DCD_XHLT);
1769		dev->atm_dev->ci_range.vpi_bits = 12;
1770		dev->atm_dev->ci_range.vci_bits = 16;
1771		dev->nchannels = FS50_NR_CHANNELS;
1772	} else {
1773		write_fs (dev, RAS0, RAS0_DCD_XHLT 
1774			  | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
1775			  | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
1776		/* We can chose the split arbitrarily. We might be able to 
1777		   support more. Whatever. This should do for now. */
1778		dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
1779		dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
1780    
1781		/* Address bits we can't use should be compared to 0. */
1782		write_fs (dev, RAC, 0);
1783
1784		/* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
1785		 * too.  I can't find ASF1 anywhere. Anyway, we AND with just the
1786		 * other bits, then compare with 0, which is exactly what we
1787		 * want. */
1788		write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
1789		dev->nchannels = FS155_NR_CHANNELS;
1790	}
1791	dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
1792				 GFP_KERNEL);
1793	fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%zd)\n",
1794		    dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
1795
1796	if (!dev->atm_vccs) {
1797		printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
1798		/* XXX Clean up..... */
1799		goto unmap;
1800	}
1801
1802	dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
1803	fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n", 
1804		    dev->atm_vccs, dev->nchannels / 8);
1805
1806	if (!dev->tx_inuse) {
1807		printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
1808		/* XXX Clean up..... */
1809		goto unmap;
1810	}
1811	/* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
1812	/* -- RAS2 : FS50 only: Default is OK. */
1813
1814	/* DMAMODE, default should be OK. -- REW */
1815	write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
1816
1817	init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
1818	init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
1819	init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
1820	init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
1821
1822	for (i=0;i < FS_NR_FREE_POOLS;i++) {
1823		init_fp (dev, &dev->rx_fp[i], RXB_FP(i), 
1824			 rx_buf_sizes[i], rx_pool_sizes[i]);
1825		top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
1826	}
1827
1828
1829	for (i=0;i < FS_NR_RX_QUEUES;i++)
1830		init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
1831
1832	dev->irq = pci_dev->irq;
1833	if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
1834		printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
1835		/* XXX undo all previous stuff... */
1836		goto unmap;
1837	}
1838	fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
1839  
1840	/* We want to be notified of most things. Just the statistics count
1841	   overflows are not interesting */
1842	write_fs (dev, IMR, 0
1843		  | ISR_RBRQ0_W 
1844		  | ISR_RBRQ1_W 
1845		  | ISR_RBRQ2_W 
1846		  | ISR_RBRQ3_W 
1847		  | ISR_TBRQ_W
1848		  | ISR_CSQ_W);
1849
1850	write_fs (dev, SARMODE0, 0 
1851		  | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1852		  | (1 * SARMODE0_GINT)
1853		  | (1 * SARMODE0_INTMODE_READCLEAR)
1854		  | (0 * SARMODE0_CWRE)
1855		  | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5: 
1856		                  SARMODE0_PRPWT_FS155_3)
1857		  | (1 * SARMODE0_CALSUP_1)
1858		  | (IS_FS50 (dev)?(0
1859				    | SARMODE0_RXVCS_32
1860				    | SARMODE0_ABRVCS_32 
1861				    | SARMODE0_TXVCS_32):
1862		                   (0
1863				    | SARMODE0_RXVCS_1k
1864				    | SARMODE0_ABRVCS_1k 
1865				    | SARMODE0_TXVCS_1k))
1866		  | (1 * SARMODE0_RUN));
1867
1868	init_phy (dev, PHY_NTC_INIT);
1869
1870	if (loopback == 2) {
1871		write_phy (dev, 0x39, 0x000e);
1872	}
1873
1874#ifdef FS_POLL_FREQ
1875	timer_setup(&dev->timer, fs_poll, 0);
 
 
1876	dev->timer.expires = jiffies + FS_POLL_FREQ;
1877	add_timer (&dev->timer);
1878#endif
1879
1880	dev->atm_dev->dev_data = dev;
1881  
1882	func_exit ();
1883	return 0;
1884unmap:
1885	iounmap(dev->base);
1886	return 1;
1887}
1888
1889static int firestream_init_one(struct pci_dev *pci_dev,
1890			       const struct pci_device_id *ent)
1891{
1892	struct atm_dev *atm_dev;
1893	struct fs_dev *fs_dev;
1894	
1895	if (pci_enable_device(pci_dev)) 
1896		goto err_out;
1897
1898	fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
1899	fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%zd)\n",
1900		    fs_dev, sizeof (struct fs_dev));
1901	if (!fs_dev)
1902		goto err_out;
1903	atm_dev = atm_dev_register("fs", &pci_dev->dev, &ops, -1, NULL);
1904	if (!atm_dev)
1905		goto err_out_free_fs_dev;
1906  
1907	fs_dev->pci_dev = pci_dev;
1908	fs_dev->atm_dev = atm_dev;
1909	fs_dev->flags = ent->driver_data;
1910
1911	if (fs_init(fs_dev))
1912		goto err_out_free_atm_dev;
1913
1914	fs_dev->next = fs_boards;
1915	fs_boards = fs_dev;
1916	return 0;
1917
1918 err_out_free_atm_dev:
1919	atm_dev_deregister(atm_dev);
1920 err_out_free_fs_dev:
1921 	kfree(fs_dev);
1922 err_out:
1923	return -ENODEV;
1924}
1925
1926static void firestream_remove_one(struct pci_dev *pdev)
1927{
1928	int i;
1929	struct fs_dev *dev, *nxtdev;
1930	struct fs_vcc *vcc;
1931	struct FS_BPENTRY *fp, *nxt;
1932  
1933	func_enter ();
1934
1935#if 0
1936	printk ("hptxq:\n");
1937	for (i=0;i<60;i++) {
1938		printk ("%d: %08x %08x %08x %08x \n", 
1939			i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
1940		qp++;
1941		if (qp >= 60) qp = 0;
1942	}
1943
1944	printk ("descriptors:\n");
1945	for (i=0;i<60;i++) {
1946		printk ("%d: %p: %08x %08x %p %p\n", 
1947			i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
1948		qd++;
1949		if (qd >= 60) qd = 0;
1950	}
1951#endif
1952
1953	for (dev = fs_boards;dev != NULL;dev=nxtdev) {
1954		fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
1955
1956		/* XXX Hit all the tx channels too! */
1957
1958		for (i=0;i < dev->nchannels;i++) {
1959			if (dev->atm_vccs[i]) {
1960				vcc = FS_VCC (dev->atm_vccs[i]);
1961				submit_command (dev,  &dev->hp_txq,
1962						QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1963				submit_command (dev,  &dev->hp_txq,
1964						QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1965
1966			}
1967		}
1968
1969		/* XXX Wait a while for the chip to release all buffers. */
1970
1971		for (i=0;i < FS_NR_FREE_POOLS;i++) {
1972			for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
1973			     !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
1974				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1975				dev_kfree_skb_any (fp->skb);
1976				nxt = bus_to_virt (fp->next);
1977				fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1978				kfree (fp);
1979			}
1980			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1981			dev_kfree_skb_any (fp->skb);
1982			fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1983			kfree (fp);
1984		}
1985
1986		/* Hang the chip in "reset", prevent it clobbering memory that is
1987		   no longer ours. */
1988		reset_chip (dev);
1989
1990		fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
1991		free_irq (dev->irq, dev);
1992		del_timer_sync (&dev->timer);
1993
1994		atm_dev_deregister(dev->atm_dev);
1995		free_queue (dev, &dev->hp_txq);
1996		free_queue (dev, &dev->lp_txq);
1997		free_queue (dev, &dev->tx_relq);
1998		free_queue (dev, &dev->st_q);
1999
2000		fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
2001		kfree (dev->atm_vccs);
2002
2003		for (i=0;i< FS_NR_FREE_POOLS;i++)
2004			free_freepool (dev, &dev->rx_fp[i]);
2005    
2006		for (i=0;i < FS_NR_RX_QUEUES;i++)
2007			free_queue (dev, &dev->rx_rq[i]);
2008
2009		iounmap(dev->base);
2010		fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
2011		nxtdev = dev->next;
2012		kfree (dev);
2013	}
2014
2015	func_exit ();
2016}
2017
2018static const struct pci_device_id firestream_pci_tbl[] = {
2019	{ PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50), FS_IS50},
2020	{ PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155), FS_IS155},
2021	{ 0, }
2022};
2023
2024MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
2025
2026static struct pci_driver firestream_driver = {
2027	.name		= "firestream",
2028	.id_table	= firestream_pci_tbl,
2029	.probe		= firestream_init_one,
2030	.remove		= firestream_remove_one,
2031};
2032
2033static int __init firestream_init_module (void)
2034{
2035	int error;
2036
2037	func_enter ();
2038	error = pci_register_driver(&firestream_driver);
2039	func_exit ();
2040	return error;
2041}
2042
2043static void __exit firestream_cleanup_module(void)
2044{
2045	pci_unregister_driver(&firestream_driver);
2046}
2047
2048module_init(firestream_init_module);
2049module_exit(firestream_cleanup_module);
2050
2051MODULE_LICENSE("GPL");
2052
2053
2054