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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PCI address cache; allows the lookup of PCI devices based on I/O address
4 *
5 * Copyright IBM Corporation 2004
6 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
7 */
8
9#include <linux/list.h>
10#include <linux/pci.h>
11#include <linux/rbtree.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/atomic.h>
15#include <asm/pci-bridge.h>
16#include <asm/debugfs.h>
17#include <asm/ppc-pci.h>
18
19
20/**
21 * DOC: Overview
22 *
23 * The pci address cache subsystem. This subsystem places
24 * PCI device address resources into a red-black tree, sorted
25 * according to the address range, so that given only an i/o
26 * address, the corresponding PCI device can be **quickly**
27 * found. It is safe to perform an address lookup in an interrupt
28 * context; this ability is an important feature.
29 *
30 * Currently, the only customer of this code is the EEH subsystem;
31 * thus, this code has been somewhat tailored to suit EEH better.
32 * In particular, the cache does *not* hold the addresses of devices
33 * for which EEH is not enabled.
34 *
35 * (Implementation Note: The RB tree seems to be better/faster
36 * than any hash algo I could think of for this problem, even
37 * with the penalty of slow pointer chases for d-cache misses).
38 */
39
40struct pci_io_addr_range {
41 struct rb_node rb_node;
42 resource_size_t addr_lo;
43 resource_size_t addr_hi;
44 struct eeh_dev *edev;
45 struct pci_dev *pcidev;
46 unsigned long flags;
47};
48
49static struct pci_io_addr_cache {
50 struct rb_root rb_root;
51 spinlock_t piar_lock;
52} pci_io_addr_cache_root;
53
54static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
55{
56 struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
57
58 while (n) {
59 struct pci_io_addr_range *piar;
60 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
61
62 if (addr < piar->addr_lo)
63 n = n->rb_left;
64 else if (addr > piar->addr_hi)
65 n = n->rb_right;
66 else
67 return piar->edev;
68 }
69
70 return NULL;
71}
72
73/**
74 * eeh_addr_cache_get_dev - Get device, given only address
75 * @addr: mmio (PIO) phys address or i/o port number
76 *
77 * Given an mmio phys address, or a port number, find a pci device
78 * that implements this address. I/O port numbers are assumed to be offset
79 * from zero (that is, they do *not* have pci_io_addr added in).
80 * It is safe to call this function within an interrupt.
81 */
82struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
83{
84 struct eeh_dev *edev;
85 unsigned long flags;
86
87 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
88 edev = __eeh_addr_cache_get_device(addr);
89 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
90 return edev;
91}
92
93#ifdef DEBUG
94/*
95 * Handy-dandy debug print routine, does nothing more
96 * than print out the contents of our addr cache.
97 */
98static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
99{
100 struct rb_node *n;
101 int cnt = 0;
102
103 n = rb_first(&cache->rb_root);
104 while (n) {
105 struct pci_io_addr_range *piar;
106 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
107 pr_info("PCI: %s addr range %d [%pap-%pap]: %s\n",
108 (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
109 &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
110 cnt++;
111 n = rb_next(n);
112 }
113}
114#endif
115
116/* Insert address range into the rb tree. */
117static struct pci_io_addr_range *
118eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
119 resource_size_t ahi, unsigned long flags)
120{
121 struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
122 struct rb_node *parent = NULL;
123 struct pci_io_addr_range *piar;
124
125 /* Walk tree, find a place to insert into tree */
126 while (*p) {
127 parent = *p;
128 piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
129 if (ahi < piar->addr_lo) {
130 p = &parent->rb_left;
131 } else if (alo > piar->addr_hi) {
132 p = &parent->rb_right;
133 } else {
134 if (dev != piar->pcidev ||
135 alo != piar->addr_lo || ahi != piar->addr_hi) {
136 pr_warn("PIAR: overlapping address range\n");
137 }
138 return piar;
139 }
140 }
141 piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
142 if (!piar)
143 return NULL;
144
145 piar->addr_lo = alo;
146 piar->addr_hi = ahi;
147 piar->edev = pci_dev_to_eeh_dev(dev);
148 piar->pcidev = dev;
149 piar->flags = flags;
150
151 eeh_edev_dbg(piar->edev, "PIAR: insert range=[%pap:%pap]\n",
152 &alo, &ahi);
153
154 rb_link_node(&piar->rb_node, parent, p);
155 rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
156
157 return piar;
158}
159
160static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
161{
162 struct eeh_dev *edev;
163 int i;
164
165 edev = pci_dev_to_eeh_dev(dev);
166 if (!edev) {
167 pr_warn("PCI: no EEH dev found for %s\n",
168 pci_name(dev));
169 return;
170 }
171
172 /* Skip any devices for which EEH is not enabled. */
173 if (!edev->pe) {
174 dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
175 return;
176 }
177
178 /*
179 * Walk resources on this device, poke the first 7 (6 normal BAR and 1
180 * ROM BAR) into the tree.
181 */
182 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
183 resource_size_t start = pci_resource_start(dev,i);
184 resource_size_t end = pci_resource_end(dev,i);
185 unsigned long flags = pci_resource_flags(dev,i);
186
187 /* We are interested only bus addresses, not dma or other stuff */
188 if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
189 continue;
190 if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
191 continue;
192 eeh_addr_cache_insert(dev, start, end, flags);
193 }
194}
195
196/**
197 * eeh_addr_cache_insert_dev - Add a device to the address cache
198 * @dev: PCI device whose I/O addresses we are interested in.
199 *
200 * In order to support the fast lookup of devices based on addresses,
201 * we maintain a cache of devices that can be quickly searched.
202 * This routine adds a device to that cache.
203 */
204void eeh_addr_cache_insert_dev(struct pci_dev *dev)
205{
206 unsigned long flags;
207
208 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
209 __eeh_addr_cache_insert_dev(dev);
210 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
211}
212
213static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
214{
215 struct rb_node *n;
216
217restart:
218 n = rb_first(&pci_io_addr_cache_root.rb_root);
219 while (n) {
220 struct pci_io_addr_range *piar;
221 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
222
223 if (piar->pcidev == dev) {
224 eeh_edev_dbg(piar->edev, "PIAR: remove range=[%pap:%pap]\n",
225 &piar->addr_lo, &piar->addr_hi);
226 rb_erase(n, &pci_io_addr_cache_root.rb_root);
227 kfree(piar);
228 goto restart;
229 }
230 n = rb_next(n);
231 }
232}
233
234/**
235 * eeh_addr_cache_rmv_dev - remove pci device from addr cache
236 * @dev: device to remove
237 *
238 * Remove a device from the addr-cache tree.
239 * This is potentially expensive, since it will walk
240 * the tree multiple times (once per resource).
241 * But so what; device removal doesn't need to be that fast.
242 */
243void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
244{
245 unsigned long flags;
246
247 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
248 __eeh_addr_cache_rmv_dev(dev);
249 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
250}
251
252/**
253 * eeh_addr_cache_init - Initialize a cache of I/O addresses
254 *
255 * Initialize a cache of pci i/o addresses. This cache will be used to
256 * find the pci device that corresponds to a given address.
257 */
258void eeh_addr_cache_init(void)
259{
260 spin_lock_init(&pci_io_addr_cache_root.piar_lock);
261}
262
263static int eeh_addr_cache_show(struct seq_file *s, void *v)
264{
265 struct pci_io_addr_range *piar;
266 struct rb_node *n;
267
268 spin_lock(&pci_io_addr_cache_root.piar_lock);
269 for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) {
270 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
271
272 seq_printf(s, "%s addr range [%pap-%pap]: %s\n",
273 (piar->flags & IORESOURCE_IO) ? "i/o" : "mem",
274 &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
275 }
276 spin_unlock(&pci_io_addr_cache_root.piar_lock);
277
278 return 0;
279}
280DEFINE_SHOW_ATTRIBUTE(eeh_addr_cache);
281
282void eeh_cache_debugfs_init(void)
283{
284 debugfs_create_file_unsafe("eeh_address_cache", 0400,
285 powerpc_debugfs_root, NULL,
286 &eeh_addr_cache_fops);
287}
1/*
2 * PCI address cache; allows the lookup of PCI devices based on I/O address
3 *
4 * Copyright IBM Corporation 2004
5 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/list.h>
23#include <linux/pci.h>
24#include <linux/rbtree.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/atomic.h>
28#include <asm/pci-bridge.h>
29#include <asm/ppc-pci.h>
30
31
32/**
33 * The pci address cache subsystem. This subsystem places
34 * PCI device address resources into a red-black tree, sorted
35 * according to the address range, so that given only an i/o
36 * address, the corresponding PCI device can be **quickly**
37 * found. It is safe to perform an address lookup in an interrupt
38 * context; this ability is an important feature.
39 *
40 * Currently, the only customer of this code is the EEH subsystem;
41 * thus, this code has been somewhat tailored to suit EEH better.
42 * In particular, the cache does *not* hold the addresses of devices
43 * for which EEH is not enabled.
44 *
45 * (Implementation Note: The RB tree seems to be better/faster
46 * than any hash algo I could think of for this problem, even
47 * with the penalty of slow pointer chases for d-cache misses).
48 */
49struct pci_io_addr_range {
50 struct rb_node rb_node;
51 unsigned long addr_lo;
52 unsigned long addr_hi;
53 struct eeh_dev *edev;
54 struct pci_dev *pcidev;
55 unsigned int flags;
56};
57
58static struct pci_io_addr_cache {
59 struct rb_root rb_root;
60 spinlock_t piar_lock;
61} pci_io_addr_cache_root;
62
63static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
64{
65 struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
66
67 while (n) {
68 struct pci_io_addr_range *piar;
69 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
70
71 if (addr < piar->addr_lo)
72 n = n->rb_left;
73 else if (addr > piar->addr_hi)
74 n = n->rb_right;
75 else
76 return piar->edev;
77 }
78
79 return NULL;
80}
81
82/**
83 * eeh_addr_cache_get_dev - Get device, given only address
84 * @addr: mmio (PIO) phys address or i/o port number
85 *
86 * Given an mmio phys address, or a port number, find a pci device
87 * that implements this address. Be sure to pci_dev_put the device
88 * when finished. I/O port numbers are assumed to be offset
89 * from zero (that is, they do *not* have pci_io_addr added in).
90 * It is safe to call this function within an interrupt.
91 */
92struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
93{
94 struct eeh_dev *edev;
95 unsigned long flags;
96
97 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
98 edev = __eeh_addr_cache_get_device(addr);
99 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
100 return edev;
101}
102
103#ifdef DEBUG
104/*
105 * Handy-dandy debug print routine, does nothing more
106 * than print out the contents of our addr cache.
107 */
108static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
109{
110 struct rb_node *n;
111 int cnt = 0;
112
113 n = rb_first(&cache->rb_root);
114 while (n) {
115 struct pci_io_addr_range *piar;
116 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
117 pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
118 (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
119 piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
120 cnt++;
121 n = rb_next(n);
122 }
123}
124#endif
125
126/* Insert address range into the rb tree. */
127static struct pci_io_addr_range *
128eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
129 unsigned long ahi, unsigned int flags)
130{
131 struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
132 struct rb_node *parent = NULL;
133 struct pci_io_addr_range *piar;
134
135 /* Walk tree, find a place to insert into tree */
136 while (*p) {
137 parent = *p;
138 piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
139 if (ahi < piar->addr_lo) {
140 p = &parent->rb_left;
141 } else if (alo > piar->addr_hi) {
142 p = &parent->rb_right;
143 } else {
144 if (dev != piar->pcidev ||
145 alo != piar->addr_lo || ahi != piar->addr_hi) {
146 pr_warning("PIAR: overlapping address range\n");
147 }
148 return piar;
149 }
150 }
151 piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
152 if (!piar)
153 return NULL;
154
155 piar->addr_lo = alo;
156 piar->addr_hi = ahi;
157 piar->edev = pci_dev_to_eeh_dev(dev);
158 piar->pcidev = dev;
159 piar->flags = flags;
160
161#ifdef DEBUG
162 pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
163 alo, ahi, pci_name(dev));
164#endif
165
166 rb_link_node(&piar->rb_node, parent, p);
167 rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
168
169 return piar;
170}
171
172static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
173{
174 struct device_node *dn;
175 struct eeh_dev *edev;
176 int i;
177
178 dn = pci_device_to_OF_node(dev);
179 if (!dn) {
180 pr_warning("PCI: no pci dn found for dev=%s\n", pci_name(dev));
181 return;
182 }
183
184 edev = of_node_to_eeh_dev(dn);
185 if (!edev) {
186 pr_warning("PCI: no EEH dev found for dn=%s\n",
187 dn->full_name);
188 return;
189 }
190
191 /* Skip any devices for which EEH is not enabled. */
192 if (!eeh_probe_mode_dev() && !edev->pe) {
193#ifdef DEBUG
194 pr_info("PCI: skip building address cache for=%s - %s\n",
195 pci_name(dev), dn->full_name);
196#endif
197 return;
198 }
199
200 /* Walk resources on this device, poke them into the tree */
201 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
202 unsigned long start = pci_resource_start(dev,i);
203 unsigned long end = pci_resource_end(dev,i);
204 unsigned int flags = pci_resource_flags(dev,i);
205
206 /* We are interested only bus addresses, not dma or other stuff */
207 if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
208 continue;
209 if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
210 continue;
211 eeh_addr_cache_insert(dev, start, end, flags);
212 }
213}
214
215/**
216 * eeh_addr_cache_insert_dev - Add a device to the address cache
217 * @dev: PCI device whose I/O addresses we are interested in.
218 *
219 * In order to support the fast lookup of devices based on addresses,
220 * we maintain a cache of devices that can be quickly searched.
221 * This routine adds a device to that cache.
222 */
223void eeh_addr_cache_insert_dev(struct pci_dev *dev)
224{
225 unsigned long flags;
226
227 /* Ignore PCI bridges */
228 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
229 return;
230
231 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
232 __eeh_addr_cache_insert_dev(dev);
233 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
234}
235
236static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
237{
238 struct rb_node *n;
239
240restart:
241 n = rb_first(&pci_io_addr_cache_root.rb_root);
242 while (n) {
243 struct pci_io_addr_range *piar;
244 piar = rb_entry(n, struct pci_io_addr_range, rb_node);
245
246 if (piar->pcidev == dev) {
247 rb_erase(n, &pci_io_addr_cache_root.rb_root);
248 kfree(piar);
249 goto restart;
250 }
251 n = rb_next(n);
252 }
253}
254
255/**
256 * eeh_addr_cache_rmv_dev - remove pci device from addr cache
257 * @dev: device to remove
258 *
259 * Remove a device from the addr-cache tree.
260 * This is potentially expensive, since it will walk
261 * the tree multiple times (once per resource).
262 * But so what; device removal doesn't need to be that fast.
263 */
264void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
265{
266 unsigned long flags;
267
268 spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
269 __eeh_addr_cache_rmv_dev(dev);
270 spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
271}
272
273/**
274 * eeh_addr_cache_build - Build a cache of I/O addresses
275 *
276 * Build a cache of pci i/o addresses. This cache will be used to
277 * find the pci device that corresponds to a given address.
278 * This routine scans all pci busses to build the cache.
279 * Must be run late in boot process, after the pci controllers
280 * have been scanned for devices (after all device resources are known).
281 */
282void eeh_addr_cache_build(void)
283{
284 struct device_node *dn;
285 struct eeh_dev *edev;
286 struct pci_dev *dev = NULL;
287
288 spin_lock_init(&pci_io_addr_cache_root.piar_lock);
289
290 for_each_pci_dev(dev) {
291 dn = pci_device_to_OF_node(dev);
292 if (!dn)
293 continue;
294
295 edev = of_node_to_eeh_dev(dn);
296 if (!edev)
297 continue;
298
299 dev->dev.archdata.edev = edev;
300 edev->pdev = dev;
301
302 eeh_addr_cache_insert_dev(dev);
303 eeh_sysfs_add_device(dev);
304 }
305
306#ifdef DEBUG
307 /* Verify tree built up above, echo back the list of addrs. */
308 eeh_addr_cache_print(&pci_io_addr_cache_root);
309#endif
310}