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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#include <linux/dma-noncoherent.h>
7#include <asm/cache.h>
8#include <asm/cacheflush.h>
9
10/*
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
14 *
15 * For DMA coherent hardware (IOC) generic code suffices
16 */
17
18void arch_dma_prep_coherent(struct page *page, size_t size)
19{
20 /*
21 * Evict any existing L1 and/or L2 lines for the backing page
22 * in case it was used earlier as a normal "cached" page.
23 * Yeah this bit us - STAR 9000898266
24 *
25 * Although core does call flush_cache_vmap(), it gets kvaddr hence
26 * can't be used to efficiently flush L1 and/or L2 which need paddr
27 * Currently flush_cache_vmap nukes the L1 cache completely which
28 * will be optimized as a separate commit
29 */
30 dma_cache_wback_inv(page_to_phys(page), size);
31}
32
33/*
34 * Cache operations depending on function and direction argument, inspired by
35 * https://lkml.org/lkml/2018/5/18/979
36 * "dma_sync_*_for_cpu and direction=TO_DEVICE (was Re: [PATCH 02/20]
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
38 *
39 * | map == for_device | unmap == for_cpu
40 * |----------------------------------------------------------------
41 * TO_DEV | writeback writeback | none none
42 * FROM_DEV | invalidate invalidate | invalidate* invalidate*
43 * BIDIR | writeback+inv writeback+inv | invalidate invalidate
44 *
45 * [*] needed for CPU speculative prefetches
46 *
47 * NOTE: we don't check the validity of direction argument as it is done in
48 * upper layer functions (in include/linux/dma-mapping.h)
49 */
50
51void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
52 enum dma_data_direction dir)
53{
54 switch (dir) {
55 case DMA_TO_DEVICE:
56 dma_cache_wback(paddr, size);
57 break;
58
59 case DMA_FROM_DEVICE:
60 dma_cache_inv(paddr, size);
61 break;
62
63 case DMA_BIDIRECTIONAL:
64 dma_cache_wback_inv(paddr, size);
65 break;
66
67 default:
68 break;
69 }
70}
71
72void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
73 enum dma_data_direction dir)
74{
75 switch (dir) {
76 case DMA_TO_DEVICE:
77 break;
78
79 /* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
80 case DMA_FROM_DEVICE:
81 case DMA_BIDIRECTIONAL:
82 dma_cache_inv(paddr, size);
83 break;
84
85 default:
86 break;
87 }
88}
89
90/*
91 * Plug in direct dma map ops.
92 */
93void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
94 const struct iommu_ops *iommu, bool coherent)
95{
96 /*
97 * IOC hardware snoops all DMA traffic keeping the caches consistent
98 * with memory - eliding need for any explicit cache maintenance of
99 * DMA buffers.
100 */
101 if (is_isa_arcv2() && ioc_enable && coherent)
102 dev->dma_coherent = true;
103
104 dev_info(dev, "use %scoherent DMA ops\n",
105 dev->dma_coherent ? "" : "non");
106}
1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * DMA Coherent API Notes
11 *
12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
13 * implemented by accessintg it using a kernel virtual address, with
14 * Cache bit off in the TLB entry.
15 *
16 * The default DMA address == Phy address which is 0x8000_0000 based.
17 * A platform/device can make it zero based, by over-riding
18 * plat_{dma,kernel}_addr_to_{kernel,dma}
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/dma-debug.h>
23#include <linux/export.h>
24#include <asm/cacheflush.h>
25
26/*
27 * Helpers for Coherent DMA API.
28 */
29void *dma_alloc_noncoherent(struct device *dev, size_t size,
30 dma_addr_t *dma_handle, gfp_t gfp)
31{
32 void *paddr;
33
34 /* This is linear addr (0x8000_0000 based) */
35 paddr = alloc_pages_exact(size, gfp);
36 if (!paddr)
37 return NULL;
38
39 /* This is bus address, platform dependent */
40 *dma_handle = plat_kernel_addr_to_dma(dev, paddr);
41
42 return paddr;
43}
44EXPORT_SYMBOL(dma_alloc_noncoherent);
45
46void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
47 dma_addr_t dma_handle)
48{
49 free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle),
50 size);
51}
52EXPORT_SYMBOL(dma_free_noncoherent);
53
54void *dma_alloc_coherent(struct device *dev, size_t size,
55 dma_addr_t *dma_handle, gfp_t gfp)
56{
57 void *paddr, *kvaddr;
58
59 /* This is linear addr (0x8000_0000 based) */
60 paddr = alloc_pages_exact(size, gfp);
61 if (!paddr)
62 return NULL;
63
64 /* This is kernel Virtual address (0x7000_0000 based) */
65 kvaddr = ioremap_nocache((unsigned long)paddr, size);
66 if (kvaddr != NULL)
67 memset(kvaddr, 0, size);
68
69 /* This is bus address, platform dependent */
70 *dma_handle = plat_kernel_addr_to_dma(dev, paddr);
71
72 return kvaddr;
73}
74EXPORT_SYMBOL(dma_alloc_coherent);
75
76void dma_free_coherent(struct device *dev, size_t size, void *kvaddr,
77 dma_addr_t dma_handle)
78{
79 iounmap((void __force __iomem *)kvaddr);
80
81 free_pages_exact((void *)plat_dma_addr_to_kernel(dev, dma_handle),
82 size);
83}
84EXPORT_SYMBOL(dma_free_coherent);
85
86/*
87 * Helper for streaming DMA...
88 */
89void __arc_dma_cache_sync(unsigned long paddr, size_t size,
90 enum dma_data_direction dir)
91{
92 __inline_dma_cache_sync(paddr, size, dir);
93}
94EXPORT_SYMBOL(__arc_dma_cache_sync);