1/*
  2 * TI AM33XX EMIF Routines
  3 *
  4 * Copyright (C) 2016-2017 Texas Instruments Inc.
  5 *	Dave Gerlach
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License as
  9 * published by the Free Software Foundation version 2.
 10 *
 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 12 * kind, whether express or implied; without even the implied warranty
 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 */
 16#ifndef __LINUX_TI_EMIF_H
 17#define __LINUX_TI_EMIF_H
 18
 19#include <linux/kbuild.h>
 20#include <linux/types.h>
 21#ifndef __ASSEMBLY__
 22
 23struct emif_regs_amx3 {
 24	u32 emif_sdcfg_val;
 25	u32 emif_timing1_val;
 26	u32 emif_timing2_val;
 27	u32 emif_timing3_val;
 28	u32 emif_ref_ctrl_val;
 29	u32 emif_zqcfg_val;
 30	u32 emif_pmcr_val;
 31	u32 emif_pmcr_shdw_val;
 32	u32 emif_rd_wr_level_ramp_ctrl;
 33	u32 emif_rd_wr_exec_thresh;
 34	u32 emif_cos_config;
 35	u32 emif_priority_to_cos_mapping;
 36	u32 emif_connect_id_serv_1_map;
 37	u32 emif_connect_id_serv_2_map;
 38	u32 emif_ocp_config_val;
 39	u32 emif_lpddr2_nvm_tim;
 40	u32 emif_lpddr2_nvm_tim_shdw;
 41	u32 emif_dll_calib_ctrl_val;
 42	u32 emif_dll_calib_ctrl_val_shdw;
 43	u32 emif_ddr_phy_ctlr_1;
 44	u32 emif_ext_phy_ctrl_vals[120];
 45};
 46
 47struct ti_emif_pm_data {
 48	void __iomem *ti_emif_base_addr_virt;
 49	phys_addr_t ti_emif_base_addr_phys;
 50	unsigned long ti_emif_sram_config;
 51	struct emif_regs_amx3 *regs_virt;
 52	phys_addr_t regs_phys;
 53} __packed __aligned(8);
 54
 55struct ti_emif_pm_functions {
 56	u32 save_context;
 57	u32 restore_context;
 58	u32 run_hw_leveling;
 59	u32 enter_sr;
 60	u32 exit_sr;
 61	u32 abort_sr;
 62} __packed __aligned(8);
 63
 64static inline void ti_emif_asm_offsets(void)
 65{
 66	DEFINE(EMIF_SDCFG_VAL_OFFSET,
 67	       offsetof(struct emif_regs_amx3, emif_sdcfg_val));
 68	DEFINE(EMIF_TIMING1_VAL_OFFSET,
 69	       offsetof(struct emif_regs_amx3, emif_timing1_val));
 70	DEFINE(EMIF_TIMING2_VAL_OFFSET,
 71	       offsetof(struct emif_regs_amx3, emif_timing2_val));
 72	DEFINE(EMIF_TIMING3_VAL_OFFSET,
 73	       offsetof(struct emif_regs_amx3, emif_timing3_val));
 74	DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
 75	       offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
 76	DEFINE(EMIF_ZQCFG_VAL_OFFSET,
 77	       offsetof(struct emif_regs_amx3, emif_zqcfg_val));
 78	DEFINE(EMIF_PMCR_VAL_OFFSET,
 79	       offsetof(struct emif_regs_amx3, emif_pmcr_val));
 80	DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
 81	       offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
 82	DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
 83	       offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
 84	DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
 85	       offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
 86	DEFINE(EMIF_COS_CONFIG_OFFSET,
 87	       offsetof(struct emif_regs_amx3, emif_cos_config));
 88	DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
 89	       offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
 90	DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
 91	       offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
 92	DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
 93	       offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
 94	DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
 95	       offsetof(struct emif_regs_amx3, emif_ocp_config_val));
 96	DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
 97	       offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
 98	DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
 99	       offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
100	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
101	       offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
102	DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
103	       offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
104	DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
105	       offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
106	DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
107	       offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
108	DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
109
110	BLANK();
111
112	DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
113	       offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
114	DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
115	       offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
116	DEFINE(EMIF_PM_CONFIG_OFFSET,
117	       offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
118	DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
119	       offsetof(struct ti_emif_pm_data, regs_virt));
120	DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
121	       offsetof(struct ti_emif_pm_data, regs_phys));
122	DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
123
124	BLANK();
125
126	DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
127	       offsetof(struct ti_emif_pm_functions, save_context));
128	DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
129	       offsetof(struct ti_emif_pm_functions, restore_context));
130	DEFINE(EMIF_PM_RUN_HW_LEVELING,
131	       offsetof(struct ti_emif_pm_functions, run_hw_leveling));
132	DEFINE(EMIF_PM_ENTER_SR_OFFSET,
133	       offsetof(struct ti_emif_pm_functions, enter_sr));
134	DEFINE(EMIF_PM_EXIT_SR_OFFSET,
135	       offsetof(struct ti_emif_pm_functions, exit_sr));
136	DEFINE(EMIF_PM_ABORT_SR_OFFSET,
137	       offsetof(struct ti_emif_pm_functions, abort_sr));
138	DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
139}
140
141struct gen_pool;
142
143int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
144int ti_emif_get_mem_type(void);
145
146#endif
147#endif /* __LINUX_TI_EMIF_H */