1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
  3 * Copyright (C) 2015 Linaro Ltd.
  4 */
  5#ifndef __QCOM_SCM_H
  6#define __QCOM_SCM_H
  7
  8#include <linux/err.h>
  9#include <linux/types.h>
 10#include <linux/cpumask.h>
 11
 12#define QCOM_SCM_VERSION(major, minor)	(((major) << 16) | ((minor) & 0xFF))
 13#define QCOM_SCM_CPU_PWR_DOWN_L2_ON	0x0
 14#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF	0x1
 15#define QCOM_SCM_HDCP_MAX_REQ_CNT	5
 16
 17struct qcom_scm_hdcp_req {
 18	u32 addr;
 19	u32 val;
 20};
 21
 22struct qcom_scm_vmperm {
 23	int vmid;
 24	int perm;
 25};
 26
 27enum qcom_scm_ocmem_client {
 28	QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
 29	QCOM_SCM_OCMEM_GRAPHICS_ID,
 30	QCOM_SCM_OCMEM_VIDEO_ID,
 31	QCOM_SCM_OCMEM_LP_AUDIO_ID,
 32	QCOM_SCM_OCMEM_SENSORS_ID,
 33	QCOM_SCM_OCMEM_OTHER_OS_ID,
 34	QCOM_SCM_OCMEM_DEBUG_ID,
 35};
 36
 37enum qcom_scm_sec_dev_id {
 38	QCOM_SCM_MDSS_DEV_ID    = 1,
 39	QCOM_SCM_OCMEM_DEV_ID   = 5,
 40	QCOM_SCM_PCIE0_DEV_ID   = 11,
 41	QCOM_SCM_PCIE1_DEV_ID   = 12,
 42	QCOM_SCM_GFX_DEV_ID     = 18,
 43	QCOM_SCM_UFS_DEV_ID     = 19,
 44	QCOM_SCM_ICE_DEV_ID     = 20,
 45};
 46
 47enum qcom_scm_ice_cipher {
 48	QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
 49	QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
 50	QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
 51	QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
 52};
 53
 54#define QCOM_SCM_VMID_HLOS       0x3
 55#define QCOM_SCM_VMID_MSS_MSA    0xF
 56#define QCOM_SCM_VMID_WLAN       0x18
 57#define QCOM_SCM_VMID_WLAN_CE    0x19
 58#define QCOM_SCM_PERM_READ       0x4
 59#define QCOM_SCM_PERM_WRITE      0x2
 60#define QCOM_SCM_PERM_EXEC       0x1
 61#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
 62#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
 63
 64#if IS_ENABLED(CONFIG_QCOM_SCM)
 65extern bool qcom_scm_is_available(void);
 66
 67extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
 68extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
 69extern void qcom_scm_cpu_power_down(u32 flags);
 70extern int qcom_scm_set_remote_state(u32 state, u32 id);
 71
 72extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
 73				   size_t size);
 74extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
 75				  phys_addr_t size);
 76extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
 77extern int qcom_scm_pas_shutdown(u32 peripheral);
 78extern bool qcom_scm_pas_supported(u32 peripheral);
 79
 80extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
 81extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
 82
 83extern bool qcom_scm_restore_sec_cfg_available(void);
 84extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
 85extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
 86extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
 87extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
 88			       unsigned int *src,
 89			       const struct qcom_scm_vmperm *newvm,
 90			       unsigned int dest_cnt);
 91
 92extern bool qcom_scm_ocmem_lock_available(void);
 93extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
 94			       u32 size, u32 mode);
 95extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
 96				 u32 size);
 97
 98extern bool qcom_scm_ice_available(void);
 99extern int qcom_scm_ice_invalidate_key(u32 index);
100extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
101				enum qcom_scm_ice_cipher cipher,
102				u32 data_unit_size);
103
104extern bool qcom_scm_hdcp_available(void);
105extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
106			     u32 *resp);
107
108extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
109#else
110
111#include <linux/errno.h>
112
113static inline bool qcom_scm_is_available(void) { return false; }
114
115static inline int qcom_scm_set_cold_boot_addr(void *entry,
116		const cpumask_t *cpus) { return -ENODEV; }
117static inline int qcom_scm_set_warm_boot_addr(void *entry,
118		const cpumask_t *cpus) { return -ENODEV; }
119static inline void qcom_scm_cpu_power_down(u32 flags) {}
120static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
121		{ return -ENODEV; }
122
123static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
124		size_t size) { return -ENODEV; }
125static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
126		phys_addr_t size) { return -ENODEV; }
127static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
128		{ return -ENODEV; }
129static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
130static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
131
132static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
133		{ return -ENODEV; }
134static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
135		{ return -ENODEV; }
136
137static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
138static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
139		{ return -ENODEV; }
140static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
141		{ return -ENODEV; }
142static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
143		{ return -ENODEV; }
144static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
145		unsigned int *src, const struct qcom_scm_vmperm *newvm,
146		unsigned int dest_cnt) { return -ENODEV; }
147
148static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
149static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
150		u32 size, u32 mode) { return -ENODEV; }
151static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
152		u32 offset, u32 size) { return -ENODEV; }
153
154static inline bool qcom_scm_ice_available(void) { return false; }
155static inline int qcom_scm_ice_invalidate_key(u32 index) { return -ENODEV; }
156static inline int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
157				       enum qcom_scm_ice_cipher cipher,
158				       u32 data_unit_size) { return -ENODEV; }
159
160static inline bool qcom_scm_hdcp_available(void) { return false; }
161static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
162		u32 *resp) { return -ENODEV; }
163
164static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
165		{ return -ENODEV; }
166#endif
167#endif