Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18#include <linux/thermal.h>
19#include <linux/mfd/syscon.h>
20#include <linux/pinctrl/consumer.h>
21
22/*
23 * If the temperature over a period of time High,
24 * the resulting TSHUT gave CRU module,let it reset the entire chip,
25 * or via GPIO give PMIC.
26 */
27enum tshut_mode {
28 TSHUT_MODE_CRU = 0,
29 TSHUT_MODE_GPIO,
30};
31
32/*
33 * The system Temperature Sensors tshut(tshut) polarity
34 * the bit 8 is tshut polarity.
35 * 0: low active, 1: high active
36 */
37enum tshut_polarity {
38 TSHUT_LOW_ACTIVE = 0,
39 TSHUT_HIGH_ACTIVE,
40};
41
42/*
43 * The system has two Temperature Sensors.
44 * sensor0 is for CPU, and sensor1 is for GPU.
45 */
46enum sensor_id {
47 SENSOR_CPU = 0,
48 SENSOR_GPU,
49};
50
51/*
52 * The conversion table has the adc value and temperature.
53 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
54 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
55 */
56enum adc_sort_mode {
57 ADC_DECREMENT = 0,
58 ADC_INCREMENT,
59};
60
61#include "thermal_hwmon.h"
62
63/**
64 * The max sensors is two in rockchip SoCs.
65 * Two sensors: CPU and GPU sensor.
66 */
67#define SOC_MAX_SENSORS 2
68
69/**
70 * struct chip_tsadc_table - hold information about chip-specific differences
71 * @id: conversion table
72 * @length: size of conversion table
73 * @data_mask: mask to apply on data inputs
74 * @mode: sort mode of this adc variant (incrementing or decrementing)
75 */
76struct chip_tsadc_table {
77 const struct tsadc_table *id;
78 unsigned int length;
79 u32 data_mask;
80 enum adc_sort_mode mode;
81};
82
83/**
84 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
85 * @chn_id: array of sensor ids of chip corresponding to the channel
86 * @chn_num: the channel number of tsadc chip
87 * @tshut_temp: the hardware-controlled shutdown temperature value
88 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
89 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
90 * @initialize: SoC special initialize tsadc controller method
91 * @irq_ack: clear the interrupt
92 * @control: enable/disable method for the tsadc controller
93 * @get_temp: get the temperature
94 * @set_alarm_temp: set the high temperature interrupt
95 * @set_tshut_temp: set the hardware-controlled shutdown temperature
96 * @set_tshut_mode: set the hardware-controlled shutdown mode
97 * @table: the chip-specific conversion table
98 */
99struct rockchip_tsadc_chip {
100 /* The sensor id of chip correspond to the ADC channel */
101 int chn_id[SOC_MAX_SENSORS];
102 int chn_num;
103
104 /* The hardware-controlled tshut property */
105 int tshut_temp;
106 enum tshut_mode tshut_mode;
107 enum tshut_polarity tshut_polarity;
108
109 /* Chip-wide methods */
110 void (*initialize)(struct regmap *grf,
111 void __iomem *reg, enum tshut_polarity p);
112 void (*irq_ack)(void __iomem *reg);
113 void (*control)(void __iomem *reg, bool on);
114
115 /* Per-sensor methods */
116 int (*get_temp)(const struct chip_tsadc_table *table,
117 int chn, void __iomem *reg, int *temp);
118 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
119 int chn, void __iomem *reg, int temp);
120 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
121 int chn, void __iomem *reg, int temp);
122 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
123
124 /* Per-table methods */
125 struct chip_tsadc_table table;
126};
127
128/**
129 * struct rockchip_thermal_sensor - hold the information of thermal sensor
130 * @thermal: pointer to the platform/configuration data
131 * @tzd: pointer to a thermal zone
132 * @id: identifier of the thermal sensor
133 */
134struct rockchip_thermal_sensor {
135 struct rockchip_thermal_data *thermal;
136 struct thermal_zone_device *tzd;
137 int id;
138};
139
140/**
141 * struct rockchip_thermal_data - hold the private data of thermal driver
142 * @chip: pointer to the platform/configuration data
143 * @pdev: platform device of thermal
144 * @reset: the reset controller of tsadc
145 * @sensors: array of thermal sensors
146 * @clk: the controller clock is divided by the exteral 24MHz
147 * @pclk: the advanced peripherals bus clock
148 * @grf: the general register file will be used to do static set by software
149 * @regs: the base address of tsadc controller
150 * @tshut_temp: the hardware-controlled shutdown temperature value
151 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
152 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
153 */
154struct rockchip_thermal_data {
155 const struct rockchip_tsadc_chip *chip;
156 struct platform_device *pdev;
157 struct reset_control *reset;
158
159 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
160
161 struct clk *clk;
162 struct clk *pclk;
163
164 struct regmap *grf;
165 void __iomem *regs;
166
167 int tshut_temp;
168 enum tshut_mode tshut_mode;
169 enum tshut_polarity tshut_polarity;
170};
171
172/**
173 * TSADC Sensor Register description:
174 *
175 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
176 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
177 *
178 */
179#define TSADCV2_USER_CON 0x00
180#define TSADCV2_AUTO_CON 0x04
181#define TSADCV2_INT_EN 0x08
182#define TSADCV2_INT_PD 0x0c
183#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
184#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
185#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
186#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
187#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
188#define TSADCV2_AUTO_PERIOD 0x68
189#define TSADCV2_AUTO_PERIOD_HT 0x6c
190
191#define TSADCV2_AUTO_EN BIT(0)
192#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
193#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
194
195#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
196
197#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
198#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
199#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
200
201#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
202#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
203
204#define TSADCV2_DATA_MASK 0xfff
205#define TSADCV3_DATA_MASK 0x3ff
206
207#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
208#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
209#define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
210#define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
211#define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
212#define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
213
214#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
215
216#define GRF_SARADC_TESTBIT 0x0e644
217#define GRF_TSADC_TESTBIT_L 0x0e648
218#define GRF_TSADC_TESTBIT_H 0x0e64c
219
220#define PX30_GRF_SOC_CON2 0x0408
221
222#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
223#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
224#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
225#define GRF_TSADC_VCM_EN_H (0x10001 << 7)
226
227#define GRF_CON_TSADC_CH_INV (0x10001 << 1)
228
229/**
230 * struct tsadc_table - code to temperature conversion table
231 * @code: the value of adc channel
232 * @temp: the temperature
233 * Note:
234 * code to temperature mapping of the temperature sensor is a piece wise linear
235 * curve.Any temperature, code faling between to 2 give temperatures can be
236 * linearly interpolated.
237 * Code to Temperature mapping should be updated based on manufacturer results.
238 */
239struct tsadc_table {
240 u32 code;
241 int temp;
242};
243
244static const struct tsadc_table rv1108_table[] = {
245 {0, -40000},
246 {374, -40000},
247 {382, -35000},
248 {389, -30000},
249 {397, -25000},
250 {405, -20000},
251 {413, -15000},
252 {421, -10000},
253 {429, -5000},
254 {436, 0},
255 {444, 5000},
256 {452, 10000},
257 {460, 15000},
258 {468, 20000},
259 {476, 25000},
260 {483, 30000},
261 {491, 35000},
262 {499, 40000},
263 {507, 45000},
264 {515, 50000},
265 {523, 55000},
266 {531, 60000},
267 {539, 65000},
268 {547, 70000},
269 {555, 75000},
270 {562, 80000},
271 {570, 85000},
272 {578, 90000},
273 {586, 95000},
274 {594, 100000},
275 {602, 105000},
276 {610, 110000},
277 {618, 115000},
278 {626, 120000},
279 {634, 125000},
280 {TSADCV2_DATA_MASK, 125000},
281};
282
283static const struct tsadc_table rk3228_code_table[] = {
284 {0, -40000},
285 {588, -40000},
286 {593, -35000},
287 {598, -30000},
288 {603, -25000},
289 {608, -20000},
290 {613, -15000},
291 {618, -10000},
292 {623, -5000},
293 {629, 0},
294 {634, 5000},
295 {639, 10000},
296 {644, 15000},
297 {649, 20000},
298 {654, 25000},
299 {660, 30000},
300 {665, 35000},
301 {670, 40000},
302 {675, 45000},
303 {681, 50000},
304 {686, 55000},
305 {691, 60000},
306 {696, 65000},
307 {702, 70000},
308 {707, 75000},
309 {712, 80000},
310 {717, 85000},
311 {723, 90000},
312 {728, 95000},
313 {733, 100000},
314 {738, 105000},
315 {744, 110000},
316 {749, 115000},
317 {754, 120000},
318 {760, 125000},
319 {TSADCV2_DATA_MASK, 125000},
320};
321
322static const struct tsadc_table rk3288_code_table[] = {
323 {TSADCV2_DATA_MASK, -40000},
324 {3800, -40000},
325 {3792, -35000},
326 {3783, -30000},
327 {3774, -25000},
328 {3765, -20000},
329 {3756, -15000},
330 {3747, -10000},
331 {3737, -5000},
332 {3728, 0},
333 {3718, 5000},
334 {3708, 10000},
335 {3698, 15000},
336 {3688, 20000},
337 {3678, 25000},
338 {3667, 30000},
339 {3656, 35000},
340 {3645, 40000},
341 {3634, 45000},
342 {3623, 50000},
343 {3611, 55000},
344 {3600, 60000},
345 {3588, 65000},
346 {3575, 70000},
347 {3563, 75000},
348 {3550, 80000},
349 {3537, 85000},
350 {3524, 90000},
351 {3510, 95000},
352 {3496, 100000},
353 {3482, 105000},
354 {3467, 110000},
355 {3452, 115000},
356 {3437, 120000},
357 {3421, 125000},
358 {0, 125000},
359};
360
361static const struct tsadc_table rk3328_code_table[] = {
362 {0, -40000},
363 {296, -40000},
364 {304, -35000},
365 {313, -30000},
366 {331, -20000},
367 {340, -15000},
368 {349, -10000},
369 {359, -5000},
370 {368, 0},
371 {378, 5000},
372 {388, 10000},
373 {398, 15000},
374 {408, 20000},
375 {418, 25000},
376 {429, 30000},
377 {440, 35000},
378 {451, 40000},
379 {462, 45000},
380 {473, 50000},
381 {485, 55000},
382 {496, 60000},
383 {508, 65000},
384 {521, 70000},
385 {533, 75000},
386 {546, 80000},
387 {559, 85000},
388 {572, 90000},
389 {586, 95000},
390 {600, 100000},
391 {614, 105000},
392 {629, 110000},
393 {644, 115000},
394 {659, 120000},
395 {675, 125000},
396 {TSADCV2_DATA_MASK, 125000},
397};
398
399static const struct tsadc_table rk3368_code_table[] = {
400 {0, -40000},
401 {106, -40000},
402 {108, -35000},
403 {110, -30000},
404 {112, -25000},
405 {114, -20000},
406 {116, -15000},
407 {118, -10000},
408 {120, -5000},
409 {122, 0},
410 {124, 5000},
411 {126, 10000},
412 {128, 15000},
413 {130, 20000},
414 {132, 25000},
415 {134, 30000},
416 {136, 35000},
417 {138, 40000},
418 {140, 45000},
419 {142, 50000},
420 {144, 55000},
421 {146, 60000},
422 {148, 65000},
423 {150, 70000},
424 {152, 75000},
425 {154, 80000},
426 {156, 85000},
427 {158, 90000},
428 {160, 95000},
429 {162, 100000},
430 {163, 105000},
431 {165, 110000},
432 {167, 115000},
433 {169, 120000},
434 {171, 125000},
435 {TSADCV3_DATA_MASK, 125000},
436};
437
438static const struct tsadc_table rk3399_code_table[] = {
439 {0, -40000},
440 {402, -40000},
441 {410, -35000},
442 {419, -30000},
443 {427, -25000},
444 {436, -20000},
445 {444, -15000},
446 {453, -10000},
447 {461, -5000},
448 {470, 0},
449 {478, 5000},
450 {487, 10000},
451 {496, 15000},
452 {504, 20000},
453 {513, 25000},
454 {521, 30000},
455 {530, 35000},
456 {538, 40000},
457 {547, 45000},
458 {555, 50000},
459 {564, 55000},
460 {573, 60000},
461 {581, 65000},
462 {590, 70000},
463 {599, 75000},
464 {607, 80000},
465 {616, 85000},
466 {624, 90000},
467 {633, 95000},
468 {642, 100000},
469 {650, 105000},
470 {659, 110000},
471 {668, 115000},
472 {677, 120000},
473 {685, 125000},
474 {TSADCV3_DATA_MASK, 125000},
475};
476
477static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
478 int temp)
479{
480 int high, low, mid;
481 unsigned long num;
482 unsigned int denom;
483 u32 error = table->data_mask;
484
485 low = 0;
486 high = (table->length - 1) - 1; /* ignore the last check for table */
487 mid = (high + low) / 2;
488
489 /* Return mask code data when the temp is over table range */
490 if (temp < table->id[low].temp || temp > table->id[high].temp)
491 goto exit;
492
493 while (low <= high) {
494 if (temp == table->id[mid].temp)
495 return table->id[mid].code;
496 else if (temp < table->id[mid].temp)
497 high = mid - 1;
498 else
499 low = mid + 1;
500 mid = (low + high) / 2;
501 }
502
503 /*
504 * The conversion code granularity provided by the table. Let's
505 * assume that the relationship between temperature and
506 * analog value between 2 table entries is linear and interpolate
507 * to produce less granular result.
508 */
509 num = abs(table->id[mid + 1].code - table->id[mid].code);
510 num *= temp - table->id[mid].temp;
511 denom = table->id[mid + 1].temp - table->id[mid].temp;
512
513 switch (table->mode) {
514 case ADC_DECREMENT:
515 return table->id[mid].code - (num / denom);
516 case ADC_INCREMENT:
517 return table->id[mid].code + (num / denom);
518 default:
519 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
520 return error;
521 }
522
523exit:
524 pr_err("%s: invalid temperature, temp=%d error=%d\n",
525 __func__, temp, error);
526 return error;
527}
528
529static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
530 u32 code, int *temp)
531{
532 unsigned int low = 1;
533 unsigned int high = table->length - 1;
534 unsigned int mid = (low + high) / 2;
535 unsigned int num;
536 unsigned long denom;
537
538 WARN_ON(table->length < 2);
539
540 switch (table->mode) {
541 case ADC_DECREMENT:
542 code &= table->data_mask;
543 if (code <= table->id[high].code)
544 return -EAGAIN; /* Incorrect reading */
545
546 while (low <= high) {
547 if (code >= table->id[mid].code &&
548 code < table->id[mid - 1].code)
549 break;
550 else if (code < table->id[mid].code)
551 low = mid + 1;
552 else
553 high = mid - 1;
554
555 mid = (low + high) / 2;
556 }
557 break;
558 case ADC_INCREMENT:
559 code &= table->data_mask;
560 if (code < table->id[low].code)
561 return -EAGAIN; /* Incorrect reading */
562
563 while (low <= high) {
564 if (code <= table->id[mid].code &&
565 code > table->id[mid - 1].code)
566 break;
567 else if (code > table->id[mid].code)
568 low = mid + 1;
569 else
570 high = mid - 1;
571
572 mid = (low + high) / 2;
573 }
574 break;
575 default:
576 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
577 return -EINVAL;
578 }
579
580 /*
581 * The 5C granularity provided by the table is too much. Let's
582 * assume that the relationship between sensor readings and
583 * temperature between 2 table entries is linear and interpolate
584 * to produce less granular result.
585 */
586 num = table->id[mid].temp - table->id[mid - 1].temp;
587 num *= abs(table->id[mid - 1].code - code);
588 denom = abs(table->id[mid - 1].code - table->id[mid].code);
589 *temp = table->id[mid - 1].temp + (num / denom);
590
591 return 0;
592}
593
594/**
595 * rk_tsadcv2_initialize - initialize TASDC Controller.
596 * @grf: the general register file will be used to do static set by software
597 * @regs: the base address of tsadc controller
598 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
599 *
600 * (1) Set TSADC_V2_AUTO_PERIOD:
601 * Configure the interleave between every two accessing of
602 * TSADC in normal operation.
603 *
604 * (2) Set TSADCV2_AUTO_PERIOD_HT:
605 * Configure the interleave between every two accessing of
606 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
607 *
608 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
609 * If the temperature is higher than COMP_INT or COMP_SHUT for
610 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
611 */
612static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
613 enum tshut_polarity tshut_polarity)
614{
615 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
616 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
617 regs + TSADCV2_AUTO_CON);
618 else
619 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
620 regs + TSADCV2_AUTO_CON);
621
622 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
623 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
624 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
625 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
626 regs + TSADCV2_AUTO_PERIOD_HT);
627 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
628 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
629}
630
631/**
632 * rk_tsadcv3_initialize - initialize TASDC Controller.
633 * @grf: the general register file will be used to do static set by software
634 * @regs: the base address of tsadc controller
635 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
636 *
637 * (1) The tsadc control power sequence.
638 *
639 * (2) Set TSADC_V2_AUTO_PERIOD:
640 * Configure the interleave between every two accessing of
641 * TSADC in normal operation.
642 *
643 * (2) Set TSADCV2_AUTO_PERIOD_HT:
644 * Configure the interleave between every two accessing of
645 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
646 *
647 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
648 * If the temperature is higher than COMP_INT or COMP_SHUT for
649 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
650 */
651static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
652 enum tshut_polarity tshut_polarity)
653{
654 /* The tsadc control power sequence */
655 if (IS_ERR(grf)) {
656 /* Set interleave value to workround ic time sync issue */
657 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
658 TSADCV2_USER_CON);
659
660 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
661 regs + TSADCV2_AUTO_PERIOD);
662 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
663 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
664 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
665 regs + TSADCV2_AUTO_PERIOD_HT);
666 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
667 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
668
669 } else {
670 /* Enable the voltage common mode feature */
671 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
672 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
673
674 usleep_range(15, 100); /* The spec note says at least 15 us */
675 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
676 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
677 usleep_range(90, 200); /* The spec note says at least 90 us */
678
679 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
680 regs + TSADCV2_AUTO_PERIOD);
681 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
682 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
683 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
684 regs + TSADCV2_AUTO_PERIOD_HT);
685 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
686 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
687 }
688
689 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
690 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
691 regs + TSADCV2_AUTO_CON);
692 else
693 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
694 regs + TSADCV2_AUTO_CON);
695}
696
697static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
698 enum tshut_polarity tshut_polarity)
699{
700 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
701 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
702}
703
704static void rk_tsadcv2_irq_ack(void __iomem *regs)
705{
706 u32 val;
707
708 val = readl_relaxed(regs + TSADCV2_INT_PD);
709 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
710}
711
712static void rk_tsadcv3_irq_ack(void __iomem *regs)
713{
714 u32 val;
715
716 val = readl_relaxed(regs + TSADCV2_INT_PD);
717 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
718}
719
720static void rk_tsadcv2_control(void __iomem *regs, bool enable)
721{
722 u32 val;
723
724 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
725 if (enable)
726 val |= TSADCV2_AUTO_EN;
727 else
728 val &= ~TSADCV2_AUTO_EN;
729
730 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
731}
732
733/**
734 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
735 * @regs: the base address of tsadc controller
736 * @enable: boolean flag to enable the controller
737 *
738 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
739 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
740 * adc value if setting this bit to enable.
741 */
742static void rk_tsadcv3_control(void __iomem *regs, bool enable)
743{
744 u32 val;
745
746 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
747 if (enable)
748 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
749 else
750 val &= ~TSADCV2_AUTO_EN;
751
752 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
753}
754
755static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
756 int chn, void __iomem *regs, int *temp)
757{
758 u32 val;
759
760 val = readl_relaxed(regs + TSADCV2_DATA(chn));
761
762 return rk_tsadcv2_code_to_temp(table, val, temp);
763}
764
765static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
766 int chn, void __iomem *regs, int temp)
767{
768 u32 alarm_value;
769 u32 int_en, int_clr;
770
771 /*
772 * In some cases, some sensors didn't need the trip points, the
773 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
774 * in the end, ignore this case and disable the high temperature
775 * interrupt.
776 */
777 if (temp == INT_MAX) {
778 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
779 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
780 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
781 return 0;
782 }
783
784 /* Make sure the value is valid */
785 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
786 if (alarm_value == table->data_mask)
787 return -ERANGE;
788
789 writel_relaxed(alarm_value & table->data_mask,
790 regs + TSADCV2_COMP_INT(chn));
791
792 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
793 int_en |= TSADCV2_INT_SRC_EN(chn);
794 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
795
796 return 0;
797}
798
799static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
800 int chn, void __iomem *regs, int temp)
801{
802 u32 tshut_value, val;
803
804 /* Make sure the value is valid */
805 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
806 if (tshut_value == table->data_mask)
807 return -ERANGE;
808
809 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
810
811 /* TSHUT will be valid */
812 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
813 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
814
815 return 0;
816}
817
818static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
819 enum tshut_mode mode)
820{
821 u32 val;
822
823 val = readl_relaxed(regs + TSADCV2_INT_EN);
824 if (mode == TSHUT_MODE_GPIO) {
825 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
826 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
827 } else {
828 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
829 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
830 }
831
832 writel_relaxed(val, regs + TSADCV2_INT_EN);
833}
834
835static const struct rockchip_tsadc_chip px30_tsadc_data = {
836 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
837 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
838 .chn_num = 2, /* 2 channels for tsadc */
839
840 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
841 .tshut_temp = 95000,
842
843 .initialize = rk_tsadcv4_initialize,
844 .irq_ack = rk_tsadcv3_irq_ack,
845 .control = rk_tsadcv3_control,
846 .get_temp = rk_tsadcv2_get_temp,
847 .set_alarm_temp = rk_tsadcv2_alarm_temp,
848 .set_tshut_temp = rk_tsadcv2_tshut_temp,
849 .set_tshut_mode = rk_tsadcv2_tshut_mode,
850
851 .table = {
852 .id = rk3328_code_table,
853 .length = ARRAY_SIZE(rk3328_code_table),
854 .data_mask = TSADCV2_DATA_MASK,
855 .mode = ADC_INCREMENT,
856 },
857};
858
859static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
860 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
861 .chn_num = 1, /* one channel for tsadc */
862
863 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
864 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
865 .tshut_temp = 95000,
866
867 .initialize = rk_tsadcv2_initialize,
868 .irq_ack = rk_tsadcv3_irq_ack,
869 .control = rk_tsadcv3_control,
870 .get_temp = rk_tsadcv2_get_temp,
871 .set_alarm_temp = rk_tsadcv2_alarm_temp,
872 .set_tshut_temp = rk_tsadcv2_tshut_temp,
873 .set_tshut_mode = rk_tsadcv2_tshut_mode,
874
875 .table = {
876 .id = rv1108_table,
877 .length = ARRAY_SIZE(rv1108_table),
878 .data_mask = TSADCV2_DATA_MASK,
879 .mode = ADC_INCREMENT,
880 },
881};
882
883static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
884 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
885 .chn_num = 1, /* one channel for tsadc */
886
887 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
888 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
889 .tshut_temp = 95000,
890
891 .initialize = rk_tsadcv2_initialize,
892 .irq_ack = rk_tsadcv3_irq_ack,
893 .control = rk_tsadcv3_control,
894 .get_temp = rk_tsadcv2_get_temp,
895 .set_alarm_temp = rk_tsadcv2_alarm_temp,
896 .set_tshut_temp = rk_tsadcv2_tshut_temp,
897 .set_tshut_mode = rk_tsadcv2_tshut_mode,
898
899 .table = {
900 .id = rk3228_code_table,
901 .length = ARRAY_SIZE(rk3228_code_table),
902 .data_mask = TSADCV3_DATA_MASK,
903 .mode = ADC_INCREMENT,
904 },
905};
906
907static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
908 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
909 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
910 .chn_num = 2, /* two channels for tsadc */
911
912 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
913 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
914 .tshut_temp = 95000,
915
916 .initialize = rk_tsadcv2_initialize,
917 .irq_ack = rk_tsadcv2_irq_ack,
918 .control = rk_tsadcv2_control,
919 .get_temp = rk_tsadcv2_get_temp,
920 .set_alarm_temp = rk_tsadcv2_alarm_temp,
921 .set_tshut_temp = rk_tsadcv2_tshut_temp,
922 .set_tshut_mode = rk_tsadcv2_tshut_mode,
923
924 .table = {
925 .id = rk3288_code_table,
926 .length = ARRAY_SIZE(rk3288_code_table),
927 .data_mask = TSADCV2_DATA_MASK,
928 .mode = ADC_DECREMENT,
929 },
930};
931
932static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
933 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
934 .chn_num = 1, /* one channels for tsadc */
935
936 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
937 .tshut_temp = 95000,
938
939 .initialize = rk_tsadcv2_initialize,
940 .irq_ack = rk_tsadcv3_irq_ack,
941 .control = rk_tsadcv3_control,
942 .get_temp = rk_tsadcv2_get_temp,
943 .set_alarm_temp = rk_tsadcv2_alarm_temp,
944 .set_tshut_temp = rk_tsadcv2_tshut_temp,
945 .set_tshut_mode = rk_tsadcv2_tshut_mode,
946
947 .table = {
948 .id = rk3328_code_table,
949 .length = ARRAY_SIZE(rk3328_code_table),
950 .data_mask = TSADCV2_DATA_MASK,
951 .mode = ADC_INCREMENT,
952 },
953};
954
955static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
956 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
957 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
958 .chn_num = 2, /* two channels for tsadc */
959
960 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
961 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
962 .tshut_temp = 95000,
963
964 .initialize = rk_tsadcv3_initialize,
965 .irq_ack = rk_tsadcv3_irq_ack,
966 .control = rk_tsadcv3_control,
967 .get_temp = rk_tsadcv2_get_temp,
968 .set_alarm_temp = rk_tsadcv2_alarm_temp,
969 .set_tshut_temp = rk_tsadcv2_tshut_temp,
970 .set_tshut_mode = rk_tsadcv2_tshut_mode,
971
972 .table = {
973 .id = rk3228_code_table,
974 .length = ARRAY_SIZE(rk3228_code_table),
975 .data_mask = TSADCV3_DATA_MASK,
976 .mode = ADC_INCREMENT,
977 },
978};
979
980static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
981 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
982 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
983 .chn_num = 2, /* two channels for tsadc */
984
985 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
986 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
987 .tshut_temp = 95000,
988
989 .initialize = rk_tsadcv2_initialize,
990 .irq_ack = rk_tsadcv2_irq_ack,
991 .control = rk_tsadcv2_control,
992 .get_temp = rk_tsadcv2_get_temp,
993 .set_alarm_temp = rk_tsadcv2_alarm_temp,
994 .set_tshut_temp = rk_tsadcv2_tshut_temp,
995 .set_tshut_mode = rk_tsadcv2_tshut_mode,
996
997 .table = {
998 .id = rk3368_code_table,
999 .length = ARRAY_SIZE(rk3368_code_table),
1000 .data_mask = TSADCV3_DATA_MASK,
1001 .mode = ADC_INCREMENT,
1002 },
1003};
1004
1005static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1006 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1007 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1008 .chn_num = 2, /* two channels for tsadc */
1009
1010 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1011 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1012 .tshut_temp = 95000,
1013
1014 .initialize = rk_tsadcv3_initialize,
1015 .irq_ack = rk_tsadcv3_irq_ack,
1016 .control = rk_tsadcv3_control,
1017 .get_temp = rk_tsadcv2_get_temp,
1018 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1019 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1020 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1021
1022 .table = {
1023 .id = rk3399_code_table,
1024 .length = ARRAY_SIZE(rk3399_code_table),
1025 .data_mask = TSADCV3_DATA_MASK,
1026 .mode = ADC_INCREMENT,
1027 },
1028};
1029
1030static const struct of_device_id of_rockchip_thermal_match[] = {
1031 { .compatible = "rockchip,px30-tsadc",
1032 .data = (void *)&px30_tsadc_data,
1033 },
1034 {
1035 .compatible = "rockchip,rv1108-tsadc",
1036 .data = (void *)&rv1108_tsadc_data,
1037 },
1038 {
1039 .compatible = "rockchip,rk3228-tsadc",
1040 .data = (void *)&rk3228_tsadc_data,
1041 },
1042 {
1043 .compatible = "rockchip,rk3288-tsadc",
1044 .data = (void *)&rk3288_tsadc_data,
1045 },
1046 {
1047 .compatible = "rockchip,rk3328-tsadc",
1048 .data = (void *)&rk3328_tsadc_data,
1049 },
1050 {
1051 .compatible = "rockchip,rk3366-tsadc",
1052 .data = (void *)&rk3366_tsadc_data,
1053 },
1054 {
1055 .compatible = "rockchip,rk3368-tsadc",
1056 .data = (void *)&rk3368_tsadc_data,
1057 },
1058 {
1059 .compatible = "rockchip,rk3399-tsadc",
1060 .data = (void *)&rk3399_tsadc_data,
1061 },
1062 { /* end */ },
1063};
1064MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1065
1066static void
1067rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1068{
1069 struct thermal_zone_device *tzd = sensor->tzd;
1070
1071 if (on)
1072 thermal_zone_device_enable(tzd);
1073 else
1074 thermal_zone_device_disable(tzd);
1075}
1076
1077static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1078{
1079 struct rockchip_thermal_data *thermal = dev;
1080 int i;
1081
1082 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1083
1084 thermal->chip->irq_ack(thermal->regs);
1085
1086 for (i = 0; i < thermal->chip->chn_num; i++)
1087 thermal_zone_device_update(thermal->sensors[i].tzd,
1088 THERMAL_EVENT_UNSPECIFIED);
1089
1090 return IRQ_HANDLED;
1091}
1092
1093static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1094{
1095 struct rockchip_thermal_sensor *sensor = _sensor;
1096 struct rockchip_thermal_data *thermal = sensor->thermal;
1097 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1098
1099 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1100 __func__, sensor->id, low, high);
1101
1102 return tsadc->set_alarm_temp(&tsadc->table,
1103 sensor->id, thermal->regs, high);
1104}
1105
1106static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1107{
1108 struct rockchip_thermal_sensor *sensor = _sensor;
1109 struct rockchip_thermal_data *thermal = sensor->thermal;
1110 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1111 int retval;
1112
1113 retval = tsadc->get_temp(&tsadc->table,
1114 sensor->id, thermal->regs, out_temp);
1115 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1116 sensor->id, *out_temp, retval);
1117
1118 return retval;
1119}
1120
1121static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1122 .get_temp = rockchip_thermal_get_temp,
1123 .set_trips = rockchip_thermal_set_trips,
1124};
1125
1126static int rockchip_configure_from_dt(struct device *dev,
1127 struct device_node *np,
1128 struct rockchip_thermal_data *thermal)
1129{
1130 u32 shut_temp, tshut_mode, tshut_polarity;
1131
1132 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1133 dev_warn(dev,
1134 "Missing tshut temp property, using default %d\n",
1135 thermal->chip->tshut_temp);
1136 thermal->tshut_temp = thermal->chip->tshut_temp;
1137 } else {
1138 if (shut_temp > INT_MAX) {
1139 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1140 shut_temp);
1141 return -ERANGE;
1142 }
1143 thermal->tshut_temp = shut_temp;
1144 }
1145
1146 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1147 dev_warn(dev,
1148 "Missing tshut mode property, using default (%s)\n",
1149 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1150 "gpio" : "cru");
1151 thermal->tshut_mode = thermal->chip->tshut_mode;
1152 } else {
1153 thermal->tshut_mode = tshut_mode;
1154 }
1155
1156 if (thermal->tshut_mode > 1) {
1157 dev_err(dev, "Invalid tshut mode specified: %d\n",
1158 thermal->tshut_mode);
1159 return -EINVAL;
1160 }
1161
1162 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1163 &tshut_polarity)) {
1164 dev_warn(dev,
1165 "Missing tshut-polarity property, using default (%s)\n",
1166 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1167 "low" : "high");
1168 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1169 } else {
1170 thermal->tshut_polarity = tshut_polarity;
1171 }
1172
1173 if (thermal->tshut_polarity > 1) {
1174 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1175 thermal->tshut_polarity);
1176 return -EINVAL;
1177 }
1178
1179 /* The tsadc wont to handle the error in here since some SoCs didn't
1180 * need this property.
1181 */
1182 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1183 if (IS_ERR(thermal->grf))
1184 dev_warn(dev, "Missing rockchip,grf property\n");
1185
1186 return 0;
1187}
1188
1189static int
1190rockchip_thermal_register_sensor(struct platform_device *pdev,
1191 struct rockchip_thermal_data *thermal,
1192 struct rockchip_thermal_sensor *sensor,
1193 int id)
1194{
1195 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1196 int error;
1197
1198 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1199
1200 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1201 thermal->tshut_temp);
1202 if (error)
1203 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1204 __func__, thermal->tshut_temp, error);
1205
1206 sensor->thermal = thermal;
1207 sensor->id = id;
1208 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1209 sensor, &rockchip_of_thermal_ops);
1210 if (IS_ERR(sensor->tzd)) {
1211 error = PTR_ERR(sensor->tzd);
1212 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1213 id, error);
1214 return error;
1215 }
1216
1217 return 0;
1218}
1219
1220/**
1221 * Reset TSADC Controller, reset all tsadc registers.
1222 * @reset: the reset controller of tsadc
1223 */
1224static void rockchip_thermal_reset_controller(struct reset_control *reset)
1225{
1226 reset_control_assert(reset);
1227 usleep_range(10, 20);
1228 reset_control_deassert(reset);
1229}
1230
1231static int rockchip_thermal_probe(struct platform_device *pdev)
1232{
1233 struct device_node *np = pdev->dev.of_node;
1234 struct rockchip_thermal_data *thermal;
1235 const struct of_device_id *match;
1236 struct resource *res;
1237 int irq;
1238 int i;
1239 int error;
1240
1241 match = of_match_node(of_rockchip_thermal_match, np);
1242 if (!match)
1243 return -ENXIO;
1244
1245 irq = platform_get_irq(pdev, 0);
1246 if (irq < 0)
1247 return -EINVAL;
1248
1249 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1250 GFP_KERNEL);
1251 if (!thermal)
1252 return -ENOMEM;
1253
1254 thermal->pdev = pdev;
1255
1256 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1257 if (!thermal->chip)
1258 return -EINVAL;
1259
1260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1262 if (IS_ERR(thermal->regs))
1263 return PTR_ERR(thermal->regs);
1264
1265 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1266 if (IS_ERR(thermal->reset)) {
1267 error = PTR_ERR(thermal->reset);
1268 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1269 return error;
1270 }
1271
1272 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1273 if (IS_ERR(thermal->clk)) {
1274 error = PTR_ERR(thermal->clk);
1275 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1276 return error;
1277 }
1278
1279 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1280 if (IS_ERR(thermal->pclk)) {
1281 error = PTR_ERR(thermal->pclk);
1282 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1283 error);
1284 return error;
1285 }
1286
1287 error = clk_prepare_enable(thermal->clk);
1288 if (error) {
1289 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1290 error);
1291 return error;
1292 }
1293
1294 error = clk_prepare_enable(thermal->pclk);
1295 if (error) {
1296 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1297 goto err_disable_clk;
1298 }
1299
1300 rockchip_thermal_reset_controller(thermal->reset);
1301
1302 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1303 if (error) {
1304 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1305 error);
1306 goto err_disable_pclk;
1307 }
1308
1309 thermal->chip->initialize(thermal->grf, thermal->regs,
1310 thermal->tshut_polarity);
1311
1312 for (i = 0; i < thermal->chip->chn_num; i++) {
1313 error = rockchip_thermal_register_sensor(pdev, thermal,
1314 &thermal->sensors[i],
1315 thermal->chip->chn_id[i]);
1316 if (error) {
1317 dev_err(&pdev->dev,
1318 "failed to register sensor[%d] : error = %d\n",
1319 i, error);
1320 goto err_disable_pclk;
1321 }
1322 }
1323
1324 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1325 &rockchip_thermal_alarm_irq_thread,
1326 IRQF_ONESHOT,
1327 "rockchip_thermal", thermal);
1328 if (error) {
1329 dev_err(&pdev->dev,
1330 "failed to request tsadc irq: %d\n", error);
1331 goto err_disable_pclk;
1332 }
1333
1334 thermal->chip->control(thermal->regs, true);
1335
1336 for (i = 0; i < thermal->chip->chn_num; i++) {
1337 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1338 thermal->sensors[i].tzd->tzp->no_hwmon = false;
1339 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1340 if (error)
1341 dev_warn(&pdev->dev,
1342 "failed to register sensor %d with hwmon: %d\n",
1343 i, error);
1344 }
1345
1346 platform_set_drvdata(pdev, thermal);
1347
1348 return 0;
1349
1350err_disable_pclk:
1351 clk_disable_unprepare(thermal->pclk);
1352err_disable_clk:
1353 clk_disable_unprepare(thermal->clk);
1354
1355 return error;
1356}
1357
1358static int rockchip_thermal_remove(struct platform_device *pdev)
1359{
1360 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1361 int i;
1362
1363 for (i = 0; i < thermal->chip->chn_num; i++) {
1364 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1365
1366 thermal_remove_hwmon_sysfs(sensor->tzd);
1367 rockchip_thermal_toggle_sensor(sensor, false);
1368 }
1369
1370 thermal->chip->control(thermal->regs, false);
1371
1372 clk_disable_unprepare(thermal->pclk);
1373 clk_disable_unprepare(thermal->clk);
1374
1375 return 0;
1376}
1377
1378static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1379{
1380 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1381 int i;
1382
1383 for (i = 0; i < thermal->chip->chn_num; i++)
1384 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1385
1386 thermal->chip->control(thermal->regs, false);
1387
1388 clk_disable(thermal->pclk);
1389 clk_disable(thermal->clk);
1390
1391 pinctrl_pm_select_sleep_state(dev);
1392
1393 return 0;
1394}
1395
1396static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1397{
1398 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1399 int i;
1400 int error;
1401
1402 error = clk_enable(thermal->clk);
1403 if (error)
1404 return error;
1405
1406 error = clk_enable(thermal->pclk);
1407 if (error) {
1408 clk_disable(thermal->clk);
1409 return error;
1410 }
1411
1412 rockchip_thermal_reset_controller(thermal->reset);
1413
1414 thermal->chip->initialize(thermal->grf, thermal->regs,
1415 thermal->tshut_polarity);
1416
1417 for (i = 0; i < thermal->chip->chn_num; i++) {
1418 int id = thermal->sensors[i].id;
1419
1420 thermal->chip->set_tshut_mode(id, thermal->regs,
1421 thermal->tshut_mode);
1422
1423 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1424 id, thermal->regs,
1425 thermal->tshut_temp);
1426 if (error)
1427 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1428 __func__, thermal->tshut_temp, error);
1429 }
1430
1431 thermal->chip->control(thermal->regs, true);
1432
1433 for (i = 0; i < thermal->chip->chn_num; i++)
1434 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1435
1436 pinctrl_pm_select_default_state(dev);
1437
1438 return 0;
1439}
1440
1441static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1442 rockchip_thermal_suspend, rockchip_thermal_resume);
1443
1444static struct platform_driver rockchip_thermal_driver = {
1445 .driver = {
1446 .name = "rockchip-thermal",
1447 .pm = &rockchip_thermal_pm_ops,
1448 .of_match_table = of_rockchip_thermal_match,
1449 },
1450 .probe = rockchip_thermal_probe,
1451 .remove = rockchip_thermal_remove,
1452};
1453
1454module_platform_driver(rockchip_thermal_driver);
1455
1456MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1457MODULE_AUTHOR("Rockchip, Inc.");
1458MODULE_LICENSE("GPL v2");
1459MODULE_ALIAS("platform:rockchip-thermal");