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1/*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <linux/delay.h>
8#include <linux/hwspinlock.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/reboot.h>
17#include <linux/spi/spi.h>
18#include <linux/sizes.h>
19
20/* Registers definitions for ADI controller */
21#define REG_ADI_CTRL0 0x4
22#define REG_ADI_CHN_PRIL 0x8
23#define REG_ADI_CHN_PRIH 0xc
24#define REG_ADI_INT_EN 0x10
25#define REG_ADI_INT_RAW 0x14
26#define REG_ADI_INT_MASK 0x18
27#define REG_ADI_INT_CLR 0x1c
28#define REG_ADI_GSSI_CFG0 0x20
29#define REG_ADI_GSSI_CFG1 0x24
30#define REG_ADI_RD_CMD 0x28
31#define REG_ADI_RD_DATA 0x2c
32#define REG_ADI_ARM_FIFO_STS 0x30
33#define REG_ADI_STS 0x34
34#define REG_ADI_EVT_FIFO_STS 0x38
35#define REG_ADI_ARM_CMD_STS 0x3c
36#define REG_ADI_CHN_EN 0x40
37#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
38#define REG_ADI_CHN_EN1 0x20c
39
40/* Bits definitions for register REG_ADI_GSSI_CFG0 */
41#define BIT_CLK_ALL_ON BIT(30)
42
43/* Bits definitions for register REG_ADI_RD_DATA */
44#define BIT_RD_CMD_BUSY BIT(31)
45#define RD_ADDR_SHIFT 16
46#define RD_VALUE_MASK GENMASK(15, 0)
47#define RD_ADDR_MASK GENMASK(30, 16)
48
49/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
50#define BIT_FIFO_FULL BIT(11)
51#define BIT_FIFO_EMPTY BIT(10)
52
53/*
54 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
55 * The slave devices address offset is always 0x8000 and size is 4K.
56 */
57#define ADI_SLAVE_ADDR_SIZE SZ_4K
58#define ADI_SLAVE_OFFSET 0x8000
59
60/* Timeout (ms) for the trylock of hardware spinlocks */
61#define ADI_HWSPINLOCK_TIMEOUT 5000
62/*
63 * ADI controller has 50 channels including 2 software channels
64 * and 48 hardware channels.
65 */
66#define ADI_HW_CHNS 50
67
68#define ADI_FIFO_DRAIN_TIMEOUT 1000
69#define ADI_READ_TIMEOUT 2000
70#define REG_ADDR_LOW_MASK GENMASK(11, 0)
71
72/* Registers definitions for PMIC watchdog controller */
73#define REG_WDG_LOAD_LOW 0x80
74#define REG_WDG_LOAD_HIGH 0x84
75#define REG_WDG_CTRL 0x88
76#define REG_WDG_LOCK 0xa0
77
78/* Bits definitions for register REG_WDG_CTRL */
79#define BIT_WDG_RUN BIT(1)
80#define BIT_WDG_NEW BIT(2)
81#define BIT_WDG_RST BIT(3)
82
83/* Registers definitions for PMIC */
84#define PMIC_RST_STATUS 0xee8
85#define PMIC_MODULE_EN 0xc08
86#define PMIC_CLK_EN 0xc18
87#define BIT_WDG_EN BIT(2)
88
89/* Definition of PMIC reset status register */
90#define HWRST_STATUS_SECURITY 0x02
91#define HWRST_STATUS_RECOVERY 0x20
92#define HWRST_STATUS_NORMAL 0x40
93#define HWRST_STATUS_ALARM 0x50
94#define HWRST_STATUS_SLEEP 0x60
95#define HWRST_STATUS_FASTBOOT 0x30
96#define HWRST_STATUS_SPECIAL 0x70
97#define HWRST_STATUS_PANIC 0x80
98#define HWRST_STATUS_CFTREBOOT 0x90
99#define HWRST_STATUS_AUTODLOADER 0xa0
100#define HWRST_STATUS_IQMODE 0xb0
101#define HWRST_STATUS_SPRDISK 0xc0
102#define HWRST_STATUS_FACTORYTEST 0xe0
103#define HWRST_STATUS_WATCHDOG 0xf0
104
105/* Use default timeout 50 ms that converts to watchdog values */
106#define WDG_LOAD_VAL ((50 * 1000) / 32768)
107#define WDG_LOAD_MASK GENMASK(15, 0)
108#define WDG_UNLOCK_KEY 0xe551
109
110struct sprd_adi {
111 struct spi_controller *ctlr;
112 struct device *dev;
113 void __iomem *base;
114 struct hwspinlock *hwlock;
115 unsigned long slave_vbase;
116 unsigned long slave_pbase;
117 struct notifier_block restart_handler;
118};
119
120static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
121{
122 if (paddr < sadi->slave_pbase || paddr >
123 (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
124 dev_err(sadi->dev,
125 "slave physical address is incorrect, addr = 0x%x\n",
126 paddr);
127 return -EINVAL;
128 }
129
130 return 0;
131}
132
133static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
134{
135 return (paddr - sadi->slave_pbase + sadi->slave_vbase);
136}
137
138static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
139{
140 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
141 u32 sts;
142
143 do {
144 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
145 if (sts & BIT_FIFO_EMPTY)
146 break;
147
148 cpu_relax();
149 } while (--timeout);
150
151 if (timeout == 0) {
152 dev_err(sadi->dev, "drain write fifo timeout\n");
153 return -EBUSY;
154 }
155
156 return 0;
157}
158
159static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
160{
161 return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
162}
163
164static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
165{
166 int read_timeout = ADI_READ_TIMEOUT;
167 unsigned long flags;
168 u32 val, rd_addr;
169 int ret = 0;
170
171 if (sadi->hwlock) {
172 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
173 ADI_HWSPINLOCK_TIMEOUT,
174 &flags);
175 if (ret) {
176 dev_err(sadi->dev, "get the hw lock failed\n");
177 return ret;
178 }
179 }
180
181 /*
182 * Set the physical register address need to read into RD_CMD register,
183 * then ADI controller will start to transfer automatically.
184 */
185 writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
186
187 /*
188 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
189 * simultaneously when writing read command to register, and the
190 * BIT_RD_CMD_BUSY will be cleared after the read operation is
191 * completed.
192 */
193 do {
194 val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
195 if (!(val & BIT_RD_CMD_BUSY))
196 break;
197
198 cpu_relax();
199 } while (--read_timeout);
200
201 if (read_timeout == 0) {
202 dev_err(sadi->dev, "ADI read timeout\n");
203 ret = -EBUSY;
204 goto out;
205 }
206
207 /*
208 * The return value includes data and read register address, from bit 0
209 * to bit 15 are data, and from bit 16 to bit 30 are read register
210 * address. Then we can check the returned register address to validate
211 * data.
212 */
213 rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
214
215 if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
216 dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
217 reg_paddr, val);
218 ret = -EIO;
219 goto out;
220 }
221
222 *read_val = val & RD_VALUE_MASK;
223
224out:
225 if (sadi->hwlock)
226 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
227 return ret;
228}
229
230static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
231{
232 unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
233 u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
234 unsigned long flags;
235 int ret;
236
237 if (sadi->hwlock) {
238 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
239 ADI_HWSPINLOCK_TIMEOUT,
240 &flags);
241 if (ret) {
242 dev_err(sadi->dev, "get the hw lock failed\n");
243 return ret;
244 }
245 }
246
247 ret = sprd_adi_drain_fifo(sadi);
248 if (ret < 0)
249 goto out;
250
251 /*
252 * we should wait for write fifo is empty before writing data to PMIC
253 * registers.
254 */
255 do {
256 if (!sprd_adi_fifo_is_full(sadi)) {
257 writel_relaxed(val, (void __iomem *)reg);
258 break;
259 }
260
261 cpu_relax();
262 } while (--timeout);
263
264 if (timeout == 0) {
265 dev_err(sadi->dev, "write fifo is full\n");
266 ret = -EBUSY;
267 }
268
269out:
270 if (sadi->hwlock)
271 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
272 return ret;
273}
274
275static int sprd_adi_transfer_one(struct spi_controller *ctlr,
276 struct spi_device *spi_dev,
277 struct spi_transfer *t)
278{
279 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
280 u32 phy_reg, val;
281 int ret;
282
283 if (t->rx_buf) {
284 phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;
285
286 ret = sprd_adi_check_paddr(sadi, phy_reg);
287 if (ret)
288 return ret;
289
290 ret = sprd_adi_read(sadi, phy_reg, &val);
291 if (ret)
292 return ret;
293
294 *(u32 *)t->rx_buf = val;
295 } else if (t->tx_buf) {
296 u32 *p = (u32 *)t->tx_buf;
297
298 /*
299 * Get the physical register address need to write and convert
300 * the physical address to virtual address. Since we need
301 * virtual register address to write.
302 */
303 phy_reg = *p++ + sadi->slave_pbase;
304 ret = sprd_adi_check_paddr(sadi, phy_reg);
305 if (ret)
306 return ret;
307
308 val = *p;
309 ret = sprd_adi_write(sadi, phy_reg, val);
310 if (ret)
311 return ret;
312 } else {
313 dev_err(sadi->dev, "no buffer for transfer\n");
314 return -EINVAL;
315 }
316
317 return 0;
318}
319
320static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
321{
322#if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
323 u32 val;
324
325 /* Set default watchdog reboot mode */
326 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
327 val |= HWRST_STATUS_WATCHDOG;
328 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
329#endif
330}
331
332static int sprd_adi_restart_handler(struct notifier_block *this,
333 unsigned long mode, void *cmd)
334{
335 struct sprd_adi *sadi = container_of(this, struct sprd_adi,
336 restart_handler);
337 u32 val, reboot_mode = 0;
338
339 if (!cmd)
340 reboot_mode = HWRST_STATUS_NORMAL;
341 else if (!strncmp(cmd, "recovery", 8))
342 reboot_mode = HWRST_STATUS_RECOVERY;
343 else if (!strncmp(cmd, "alarm", 5))
344 reboot_mode = HWRST_STATUS_ALARM;
345 else if (!strncmp(cmd, "fastsleep", 9))
346 reboot_mode = HWRST_STATUS_SLEEP;
347 else if (!strncmp(cmd, "bootloader", 10))
348 reboot_mode = HWRST_STATUS_FASTBOOT;
349 else if (!strncmp(cmd, "panic", 5))
350 reboot_mode = HWRST_STATUS_PANIC;
351 else if (!strncmp(cmd, "special", 7))
352 reboot_mode = HWRST_STATUS_SPECIAL;
353 else if (!strncmp(cmd, "cftreboot", 9))
354 reboot_mode = HWRST_STATUS_CFTREBOOT;
355 else if (!strncmp(cmd, "autodloader", 11))
356 reboot_mode = HWRST_STATUS_AUTODLOADER;
357 else if (!strncmp(cmd, "iqmode", 6))
358 reboot_mode = HWRST_STATUS_IQMODE;
359 else if (!strncmp(cmd, "sprdisk", 7))
360 reboot_mode = HWRST_STATUS_SPRDISK;
361 else if (!strncmp(cmd, "tospanic", 8))
362 reboot_mode = HWRST_STATUS_SECURITY;
363 else if (!strncmp(cmd, "factorytest", 11))
364 reboot_mode = HWRST_STATUS_FACTORYTEST;
365 else
366 reboot_mode = HWRST_STATUS_NORMAL;
367
368 /* Record the reboot mode */
369 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
370 val &= ~HWRST_STATUS_WATCHDOG;
371 val |= reboot_mode;
372 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
373
374 /* Enable the interface clock of the watchdog */
375 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
376 val |= BIT_WDG_EN;
377 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
378
379 /* Enable the work clock of the watchdog */
380 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
381 val |= BIT_WDG_EN;
382 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
383
384 /* Unlock the watchdog */
385 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
386
387 sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
388 val |= BIT_WDG_NEW;
389 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
390
391 /* Load the watchdog timeout value, 50ms is always enough. */
392 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
393 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
394 WDG_LOAD_VAL & WDG_LOAD_MASK);
395
396 /* Start the watchdog to reset system */
397 sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
398 val |= BIT_WDG_RUN | BIT_WDG_RST;
399 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
400
401 /* Lock the watchdog */
402 sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
403
404 mdelay(1000);
405
406 dev_emerg(sadi->dev, "Unable to restart system\n");
407 return NOTIFY_DONE;
408}
409
410static void sprd_adi_hw_init(struct sprd_adi *sadi)
411{
412 struct device_node *np = sadi->dev->of_node;
413 int i, size, chn_cnt;
414 const __be32 *list;
415 u32 tmp;
416
417 /* Set all channels as default priority */
418 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
419 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
420
421 /* Set clock auto gate mode */
422 tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
423 tmp &= ~BIT_CLK_ALL_ON;
424 writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
425
426 /* Set hardware channels setting */
427 list = of_get_property(np, "sprd,hw-channels", &size);
428 if (!list || !size) {
429 dev_info(sadi->dev, "no hw channels setting in node\n");
430 return;
431 }
432
433 chn_cnt = size / 8;
434 for (i = 0; i < chn_cnt; i++) {
435 u32 value;
436 u32 chn_id = be32_to_cpu(*list++);
437 u32 chn_config = be32_to_cpu(*list++);
438
439 /* Channel 0 and 1 are software channels */
440 if (chn_id < 2)
441 continue;
442
443 writel_relaxed(chn_config, sadi->base +
444 REG_ADI_CHN_ADDR(chn_id));
445
446 if (chn_id < 32) {
447 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
448 value |= BIT(chn_id);
449 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
450 } else if (chn_id < ADI_HW_CHNS) {
451 value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
452 value |= BIT(chn_id - 32);
453 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
454 }
455 }
456}
457
458static int sprd_adi_probe(struct platform_device *pdev)
459{
460 struct device_node *np = pdev->dev.of_node;
461 struct spi_controller *ctlr;
462 struct sprd_adi *sadi;
463 struct resource *res;
464 u32 num_chipselect;
465 int ret;
466
467 if (!np) {
468 dev_err(&pdev->dev, "can not find the adi bus node\n");
469 return -ENODEV;
470 }
471
472 pdev->id = of_alias_get_id(np, "spi");
473 num_chipselect = of_get_child_count(np);
474
475 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
476 if (!ctlr)
477 return -ENOMEM;
478
479 dev_set_drvdata(&pdev->dev, ctlr);
480 sadi = spi_controller_get_devdata(ctlr);
481
482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
483 sadi->base = devm_ioremap_resource(&pdev->dev, res);
484 if (IS_ERR(sadi->base)) {
485 ret = PTR_ERR(sadi->base);
486 goto put_ctlr;
487 }
488
489 sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
490 sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
491 sadi->ctlr = ctlr;
492 sadi->dev = &pdev->dev;
493 ret = of_hwspin_lock_get_id(np, 0);
494 if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
495 sadi->hwlock =
496 devm_hwspin_lock_request_specific(&pdev->dev, ret);
497 if (!sadi->hwlock) {
498 ret = -ENXIO;
499 goto put_ctlr;
500 }
501 } else {
502 switch (ret) {
503 case -ENOENT:
504 dev_info(&pdev->dev, "no hardware spinlock supplied\n");
505 break;
506 default:
507 dev_err(&pdev->dev,
508 "failed to find hwlock id, %d\n", ret);
509 fallthrough;
510 case -EPROBE_DEFER:
511 goto put_ctlr;
512 }
513 }
514
515 sprd_adi_hw_init(sadi);
516 sprd_adi_set_wdt_rst_mode(sadi);
517
518 ctlr->dev.of_node = pdev->dev.of_node;
519 ctlr->bus_num = pdev->id;
520 ctlr->num_chipselect = num_chipselect;
521 ctlr->flags = SPI_MASTER_HALF_DUPLEX;
522 ctlr->bits_per_word_mask = 0;
523 ctlr->transfer_one = sprd_adi_transfer_one;
524
525 ret = devm_spi_register_controller(&pdev->dev, ctlr);
526 if (ret) {
527 dev_err(&pdev->dev, "failed to register SPI controller\n");
528 goto put_ctlr;
529 }
530
531 sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
532 sadi->restart_handler.priority = 128;
533 ret = register_restart_handler(&sadi->restart_handler);
534 if (ret) {
535 dev_err(&pdev->dev, "can not register restart handler\n");
536 goto put_ctlr;
537 }
538
539 return 0;
540
541put_ctlr:
542 spi_controller_put(ctlr);
543 return ret;
544}
545
546static int sprd_adi_remove(struct platform_device *pdev)
547{
548 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
549 struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
550
551 unregister_restart_handler(&sadi->restart_handler);
552 return 0;
553}
554
555static const struct of_device_id sprd_adi_of_match[] = {
556 {
557 .compatible = "sprd,sc9860-adi",
558 },
559 { },
560};
561MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
562
563static struct platform_driver sprd_adi_driver = {
564 .driver = {
565 .name = "sprd-adi",
566 .of_match_table = sprd_adi_of_match,
567 },
568 .probe = sprd_adi_probe,
569 .remove = sprd_adi_remove,
570};
571module_platform_driver(sprd_adi_driver);
572
573MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
574MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
575MODULE_LICENSE("GPL v2");