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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
3// Copyright (c) 2018, Linaro Limited
4
5#include <linux/irq.h>
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/slimbus.h>
14#include <linux/delay.h>
15#include <linux/pm_runtime.h>
16#include <linux/of.h>
17#include <linux/io.h>
18#include <linux/soc/qcom/qmi.h>
19#include <net/sock.h>
20#include "slimbus.h"
21
22/* NGD (Non-ported Generic Device) registers */
23#define NGD_CFG 0x0
24#define NGD_CFG_ENABLE BIT(0)
25#define NGD_CFG_RX_MSGQ_EN BIT(1)
26#define NGD_CFG_TX_MSGQ_EN BIT(2)
27#define NGD_STATUS 0x4
28#define NGD_LADDR BIT(1)
29#define NGD_RX_MSGQ_CFG 0x8
30#define NGD_INT_EN 0x10
31#define NGD_INT_RECFG_DONE BIT(24)
32#define NGD_INT_TX_NACKED_2 BIT(25)
33#define NGD_INT_MSG_BUF_CONTE BIT(26)
34#define NGD_INT_MSG_TX_INVAL BIT(27)
35#define NGD_INT_IE_VE_CHG BIT(28)
36#define NGD_INT_DEV_ERR BIT(29)
37#define NGD_INT_RX_MSG_RCVD BIT(30)
38#define NGD_INT_TX_MSG_SENT BIT(31)
39#define NGD_INT_STAT 0x14
40#define NGD_INT_CLR 0x18
41#define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
42 NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
43 NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
44 NGD_INT_RX_MSG_RCVD)
45
46/* Slimbus QMI service */
47#define SLIMBUS_QMI_SVC_ID 0x0301
48#define SLIMBUS_QMI_SVC_V1 1
49#define SLIMBUS_QMI_INS_ID 0
50#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
51#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
52#define SLIMBUS_QMI_POWER_REQ_V01 0x0021
53#define SLIMBUS_QMI_POWER_RESP_V01 0x0021
54#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022
55#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022
56#define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14
57#define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7
58#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14
59#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7
60#define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7
61/* QMI response timeout of 500ms */
62#define SLIMBUS_QMI_RESP_TOUT 1000
63
64/* User defined commands */
65#define SLIM_USR_MC_GENERIC_ACK 0x25
66#define SLIM_USR_MC_MASTER_CAPABILITY 0x0
67#define SLIM_USR_MC_REPORT_SATELLITE 0x1
68#define SLIM_USR_MC_ADDR_QUERY 0xD
69#define SLIM_USR_MC_ADDR_REPLY 0xE
70#define SLIM_USR_MC_DEFINE_CHAN 0x20
71#define SLIM_USR_MC_DEF_ACT_CHAN 0x21
72#define SLIM_USR_MC_CHAN_CTRL 0x23
73#define SLIM_USR_MC_RECONFIG_NOW 0x24
74#define SLIM_USR_MC_REQ_BW 0x28
75#define SLIM_USR_MC_CONNECT_SRC 0x2C
76#define SLIM_USR_MC_CONNECT_SINK 0x2D
77#define SLIM_USR_MC_DISCONNECT_PORT 0x2E
78#define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
79
80#define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC
81#define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000
82
83#define SLIM_LA_MGR 0xFF
84#define SLIM_ROOT_FREQ 24576000
85#define LADDR_RETRY 5
86
87/* Per spec.max 40 bytes per received message */
88#define SLIM_MSGQ_BUF_LEN 40
89#define QCOM_SLIM_NGD_DESC_NUM 32
90
91#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
92 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
93
94#define INIT_MX_RETRIES 10
95#define DEF_RETRY_MS 10
96#define SAT_MAGIC_LSB 0xD9
97#define SAT_MAGIC_MSB 0xC5
98#define SAT_MSG_VER 0x1
99#define SAT_MSG_PROT 0x1
100#define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev)
101
102struct ngd_reg_offset_data {
103 u32 offset, size;
104};
105
106static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
107 .offset = 0x1000,
108 .size = 0x1000,
109};
110
111enum qcom_slim_ngd_state {
112 QCOM_SLIM_NGD_CTRL_AWAKE,
113 QCOM_SLIM_NGD_CTRL_IDLE,
114 QCOM_SLIM_NGD_CTRL_ASLEEP,
115 QCOM_SLIM_NGD_CTRL_DOWN,
116};
117
118struct qcom_slim_ngd_qmi {
119 struct qmi_handle qmi;
120 struct sockaddr_qrtr svc_info;
121 struct qmi_handle svc_event_hdl;
122 struct qmi_response_type_v01 resp;
123 struct qmi_handle *handle;
124 struct completion qmi_comp;
125};
126
127struct qcom_slim_ngd_ctrl;
128struct qcom_slim_ngd;
129
130struct qcom_slim_ngd_dma_desc {
131 struct dma_async_tx_descriptor *desc;
132 struct qcom_slim_ngd_ctrl *ctrl;
133 struct completion *comp;
134 dma_cookie_t cookie;
135 dma_addr_t phys;
136 void *base;
137};
138
139struct qcom_slim_ngd {
140 struct platform_device *pdev;
141 void __iomem *base;
142 int id;
143};
144
145struct qcom_slim_ngd_ctrl {
146 struct slim_framer framer;
147 struct slim_controller ctrl;
148 struct qcom_slim_ngd_qmi qmi;
149 struct qcom_slim_ngd *ngd;
150 struct device *dev;
151 void __iomem *base;
152 struct dma_chan *dma_rx_channel;
153 struct dma_chan *dma_tx_channel;
154 struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
155 struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
156 struct completion reconf;
157 struct work_struct m_work;
158 struct workqueue_struct *mwq;
159 spinlock_t tx_buf_lock;
160 enum qcom_slim_ngd_state state;
161 dma_addr_t rx_phys_base;
162 dma_addr_t tx_phys_base;
163 void *rx_base;
164 void *tx_base;
165 int tx_tail;
166 int tx_head;
167 u32 ver;
168};
169
170enum slimbus_mode_enum_type_v01 {
171 /* To force a 32 bit signed enum. Do not change or use*/
172 SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
173 SLIMBUS_MODE_SATELLITE_V01 = 1,
174 SLIMBUS_MODE_MASTER_V01 = 2,
175 SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
176};
177
178enum slimbus_pm_enum_type_v01 {
179 /* To force a 32 bit signed enum. Do not change or use*/
180 SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
181 SLIMBUS_PM_INACTIVE_V01 = 1,
182 SLIMBUS_PM_ACTIVE_V01 = 2,
183 SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
184};
185
186enum slimbus_resp_enum_type_v01 {
187 SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
188 SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
189 SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
190};
191
192struct slimbus_select_inst_req_msg_v01 {
193 uint32_t instance;
194 uint8_t mode_valid;
195 enum slimbus_mode_enum_type_v01 mode;
196};
197
198struct slimbus_select_inst_resp_msg_v01 {
199 struct qmi_response_type_v01 resp;
200};
201
202struct slimbus_power_req_msg_v01 {
203 enum slimbus_pm_enum_type_v01 pm_req;
204 uint8_t resp_type_valid;
205 enum slimbus_resp_enum_type_v01 resp_type;
206};
207
208struct slimbus_power_resp_msg_v01 {
209 struct qmi_response_type_v01 resp;
210};
211
212static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
213 {
214 .data_type = QMI_UNSIGNED_4_BYTE,
215 .elem_len = 1,
216 .elem_size = sizeof(uint32_t),
217 .array_type = NO_ARRAY,
218 .tlv_type = 0x01,
219 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
220 instance),
221 .ei_array = NULL,
222 },
223 {
224 .data_type = QMI_OPT_FLAG,
225 .elem_len = 1,
226 .elem_size = sizeof(uint8_t),
227 .array_type = NO_ARRAY,
228 .tlv_type = 0x10,
229 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
230 mode_valid),
231 .ei_array = NULL,
232 },
233 {
234 .data_type = QMI_UNSIGNED_4_BYTE,
235 .elem_len = 1,
236 .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
237 .array_type = NO_ARRAY,
238 .tlv_type = 0x10,
239 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
240 mode),
241 .ei_array = NULL,
242 },
243 {
244 .data_type = QMI_EOTI,
245 .elem_len = 0,
246 .elem_size = 0,
247 .array_type = NO_ARRAY,
248 .tlv_type = 0x00,
249 .offset = 0,
250 .ei_array = NULL,
251 },
252};
253
254static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
255 {
256 .data_type = QMI_STRUCT,
257 .elem_len = 1,
258 .elem_size = sizeof(struct qmi_response_type_v01),
259 .array_type = NO_ARRAY,
260 .tlv_type = 0x02,
261 .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
262 resp),
263 .ei_array = qmi_response_type_v01_ei,
264 },
265 {
266 .data_type = QMI_EOTI,
267 .elem_len = 0,
268 .elem_size = 0,
269 .array_type = NO_ARRAY,
270 .tlv_type = 0x00,
271 .offset = 0,
272 .ei_array = NULL,
273 },
274};
275
276static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
277 {
278 .data_type = QMI_UNSIGNED_4_BYTE,
279 .elem_len = 1,
280 .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
281 .array_type = NO_ARRAY,
282 .tlv_type = 0x01,
283 .offset = offsetof(struct slimbus_power_req_msg_v01,
284 pm_req),
285 .ei_array = NULL,
286 },
287 {
288 .data_type = QMI_OPT_FLAG,
289 .elem_len = 1,
290 .elem_size = sizeof(uint8_t),
291 .array_type = NO_ARRAY,
292 .tlv_type = 0x10,
293 .offset = offsetof(struct slimbus_power_req_msg_v01,
294 resp_type_valid),
295 },
296 {
297 .data_type = QMI_SIGNED_4_BYTE_ENUM,
298 .elem_len = 1,
299 .elem_size = sizeof(enum slimbus_resp_enum_type_v01),
300 .array_type = NO_ARRAY,
301 .tlv_type = 0x10,
302 .offset = offsetof(struct slimbus_power_req_msg_v01,
303 resp_type),
304 },
305 {
306 .data_type = QMI_EOTI,
307 .elem_len = 0,
308 .elem_size = 0,
309 .array_type = NO_ARRAY,
310 .tlv_type = 0x00,
311 .offset = 0,
312 .ei_array = NULL,
313 },
314};
315
316static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
317 {
318 .data_type = QMI_STRUCT,
319 .elem_len = 1,
320 .elem_size = sizeof(struct qmi_response_type_v01),
321 .array_type = NO_ARRAY,
322 .tlv_type = 0x02,
323 .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
324 .ei_array = qmi_response_type_v01_ei,
325 },
326 {
327 .data_type = QMI_EOTI,
328 .elem_len = 0,
329 .elem_size = 0,
330 .array_type = NO_ARRAY,
331 .tlv_type = 0x00,
332 .offset = 0,
333 .ei_array = NULL,
334 },
335};
336
337static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
338 struct slimbus_select_inst_req_msg_v01 *req)
339{
340 struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
341 struct qmi_txn txn;
342 int rc;
343
344 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
345 slimbus_select_inst_resp_msg_v01_ei, &resp);
346 if (rc < 0) {
347 dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc);
348 return rc;
349 }
350
351 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
352 SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
353 SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
354 slimbus_select_inst_req_msg_v01_ei, req);
355 if (rc < 0) {
356 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
357 qmi_txn_cancel(&txn);
358 return rc;
359 }
360
361 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
362 if (rc < 0) {
363 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
364 return rc;
365 }
366 /* Check the response */
367 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
368 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
369 resp.resp.result);
370 return -EREMOTEIO;
371 }
372
373 return 0;
374}
375
376static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
377 struct sockaddr_qrtr *sq,
378 struct qmi_txn *txn, const void *data)
379{
380 struct slimbus_power_resp_msg_v01 *resp;
381
382 resp = (struct slimbus_power_resp_msg_v01 *)data;
383 if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
384 pr_err("QMI power request failed 0x%x\n",
385 resp->resp.result);
386
387 complete(&txn->completion);
388}
389
390static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
391 struct slimbus_power_req_msg_v01 *req)
392{
393 struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
394 struct qmi_txn txn;
395 int rc;
396
397 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
398 slimbus_power_resp_msg_v01_ei, &resp);
399
400 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
401 SLIMBUS_QMI_POWER_REQ_V01,
402 SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
403 slimbus_power_req_msg_v01_ei, req);
404 if (rc < 0) {
405 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
406 qmi_txn_cancel(&txn);
407 return rc;
408 }
409
410 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
411 if (rc < 0) {
412 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
413 return rc;
414 }
415
416 /* Check the response */
417 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
418 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
419 resp.resp.result);
420 return -EREMOTEIO;
421 }
422
423 return 0;
424}
425
426static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
427 {
428 .type = QMI_RESPONSE,
429 .msg_id = SLIMBUS_QMI_POWER_RESP_V01,
430 .ei = slimbus_power_resp_msg_v01_ei,
431 .decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
432 .fn = qcom_slim_qmi_power_resp_cb,
433 },
434 {}
435};
436
437static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
438 bool apps_is_master)
439{
440 struct slimbus_select_inst_req_msg_v01 req;
441 struct qmi_handle *handle;
442 int rc;
443
444 handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
445 if (!handle)
446 return -ENOMEM;
447
448 rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
449 NULL, qcom_slim_qmi_msg_handlers);
450 if (rc < 0) {
451 dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
452 goto qmi_handle_init_failed;
453 }
454
455 rc = kernel_connect(handle->sock,
456 (struct sockaddr *)&ctrl->qmi.svc_info,
457 sizeof(ctrl->qmi.svc_info), 0);
458 if (rc < 0) {
459 dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc);
460 goto qmi_connect_to_service_failed;
461 }
462
463 /* Instance is 0 based */
464 req.instance = (ctrl->ngd->id >> 1);
465 req.mode_valid = 1;
466
467 /* Mode indicates the role of the ADSP */
468 if (apps_is_master)
469 req.mode = SLIMBUS_MODE_SATELLITE_V01;
470 else
471 req.mode = SLIMBUS_MODE_MASTER_V01;
472
473 ctrl->qmi.handle = handle;
474
475 rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
476 if (rc) {
477 dev_err(ctrl->dev, "failed to select h/w instance\n");
478 goto qmi_select_instance_failed;
479 }
480
481 return 0;
482
483qmi_select_instance_failed:
484 ctrl->qmi.handle = NULL;
485qmi_connect_to_service_failed:
486 qmi_handle_release(handle);
487qmi_handle_init_failed:
488 devm_kfree(ctrl->dev, handle);
489 return rc;
490}
491
492static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
493{
494 if (!ctrl->qmi.handle)
495 return;
496
497 qmi_handle_release(ctrl->qmi.handle);
498 devm_kfree(ctrl->dev, ctrl->qmi.handle);
499 ctrl->qmi.handle = NULL;
500}
501
502static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
503 bool active)
504{
505 struct slimbus_power_req_msg_v01 req;
506
507 if (active)
508 req.pm_req = SLIMBUS_PM_ACTIVE_V01;
509 else
510 req.pm_req = SLIMBUS_PM_INACTIVE_V01;
511
512 req.resp_type_valid = 0;
513
514 return qcom_slim_qmi_send_power_request(ctrl, &req);
515}
516
517static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
518 struct completion *comp)
519{
520 struct qcom_slim_ngd_dma_desc *desc;
521 unsigned long flags;
522
523 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
524
525 if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) {
526 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
527 return NULL;
528 }
529 desc = &ctrl->txdesc[ctrl->tx_tail];
530 desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
531 desc->comp = comp;
532 ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
533
534 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
535
536 return desc->base;
537}
538
539static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
540{
541 struct qcom_slim_ngd_dma_desc *desc = args;
542 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
543 unsigned long flags;
544
545 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
546
547 if (desc->comp) {
548 complete(desc->comp);
549 desc->comp = NULL;
550 }
551
552 ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
553 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
554}
555
556static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
557 void *buf, int len)
558{
559 struct qcom_slim_ngd_dma_desc *desc;
560 unsigned long flags;
561 int index, offset;
562
563 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
564 offset = buf - ctrl->tx_base;
565 index = offset/SLIM_MSGQ_BUF_LEN;
566
567 desc = &ctrl->txdesc[index];
568 desc->phys = ctrl->tx_phys_base + offset;
569 desc->base = ctrl->tx_base + offset;
570 desc->ctrl = ctrl;
571 len = (len + 3) & 0xfc;
572
573 desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
574 desc->phys, len,
575 DMA_MEM_TO_DEV,
576 DMA_PREP_INTERRUPT);
577 if (!desc->desc) {
578 dev_err(ctrl->dev, "unable to prepare channel\n");
579 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
580 return -EINVAL;
581 }
582
583 desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
584 desc->desc->callback_param = desc;
585 desc->desc->cookie = dmaengine_submit(desc->desc);
586 dma_async_issue_pending(ctrl->dma_tx_channel);
587 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
588
589 return 0;
590}
591
592static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
593{
594 u8 mc, mt, len;
595
596 mt = SLIM_HEADER_GET_MT(buf[0]);
597 len = SLIM_HEADER_GET_RL(buf[0]);
598 mc = SLIM_HEADER_GET_MC(buf[1]);
599
600 if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
601 mt == SLIM_MSG_MT_SRC_REFERRED_USER)
602 queue_work(ctrl->mwq, &ctrl->m_work);
603
604 if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
605 mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
606 mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
607 (mc == SLIM_USR_MC_GENERIC_ACK &&
608 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
609 slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
610 pm_runtime_mark_last_busy(ctrl->dev);
611 }
612}
613
614static void qcom_slim_ngd_rx_msgq_cb(void *args)
615{
616 struct qcom_slim_ngd_dma_desc *desc = args;
617 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
618
619 qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
620 /* Add descriptor back to the queue */
621 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
622 desc->phys, SLIM_MSGQ_BUF_LEN,
623 DMA_DEV_TO_MEM,
624 DMA_PREP_INTERRUPT);
625 if (!desc->desc) {
626 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
627 return;
628 }
629
630 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
631 desc->desc->callback_param = desc;
632 desc->desc->cookie = dmaengine_submit(desc->desc);
633 dma_async_issue_pending(ctrl->dma_rx_channel);
634}
635
636static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
637{
638 struct qcom_slim_ngd_dma_desc *desc;
639 int i;
640
641 for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
642 desc = &ctrl->rx_desc[i];
643 desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
644 desc->ctrl = ctrl;
645 desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
646 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
647 desc->phys, SLIM_MSGQ_BUF_LEN,
648 DMA_DEV_TO_MEM,
649 DMA_PREP_INTERRUPT);
650 if (!desc->desc) {
651 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
652 return -EINVAL;
653 }
654
655 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
656 desc->desc->callback_param = desc;
657 desc->desc->cookie = dmaengine_submit(desc->desc);
658 }
659 dma_async_issue_pending(ctrl->dma_rx_channel);
660
661 return 0;
662}
663
664static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
665{
666 struct device *dev = ctrl->dev;
667 int ret, size;
668
669 ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
670 if (IS_ERR(ctrl->dma_rx_channel)) {
671 dev_err(dev, "Failed to request RX dma channel");
672 ret = PTR_ERR(ctrl->dma_rx_channel);
673 ctrl->dma_rx_channel = NULL;
674 return ret;
675 }
676
677 size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
678 ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
679 GFP_KERNEL);
680 if (!ctrl->rx_base) {
681 dev_err(dev, "dma_alloc_coherent failed\n");
682 ret = -ENOMEM;
683 goto rel_rx;
684 }
685
686 ret = qcom_slim_ngd_post_rx_msgq(ctrl);
687 if (ret) {
688 dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
689 goto rx_post_err;
690 }
691
692 return 0;
693
694rx_post_err:
695 dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
696rel_rx:
697 dma_release_channel(ctrl->dma_rx_channel);
698 return ret;
699}
700
701static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
702{
703 struct device *dev = ctrl->dev;
704 unsigned long flags;
705 int ret = 0;
706 int size;
707
708 ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
709 if (IS_ERR(ctrl->dma_tx_channel)) {
710 dev_err(dev, "Failed to request TX dma channel");
711 ret = PTR_ERR(ctrl->dma_tx_channel);
712 ctrl->dma_tx_channel = NULL;
713 return ret;
714 }
715
716 size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
717 ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
718 GFP_KERNEL);
719 if (!ctrl->tx_base) {
720 dev_err(dev, "dma_alloc_coherent failed\n");
721 ret = -EINVAL;
722 goto rel_tx;
723 }
724
725 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
726 ctrl->tx_tail = 0;
727 ctrl->tx_head = 0;
728 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
729
730 return 0;
731rel_tx:
732 dma_release_channel(ctrl->dma_tx_channel);
733 return ret;
734}
735
736static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
737{
738 int ret = 0;
739
740 ret = qcom_slim_ngd_init_rx_msgq(ctrl);
741 if (ret) {
742 dev_err(ctrl->dev, "rx dma init failed\n");
743 return ret;
744 }
745
746 ret = qcom_slim_ngd_init_tx_msgq(ctrl);
747 if (ret)
748 dev_err(ctrl->dev, "tx dma init failed\n");
749
750 return ret;
751}
752
753static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
754{
755 struct qcom_slim_ngd_ctrl *ctrl = d;
756 void __iomem *base = ctrl->ngd->base;
757 u32 stat = readl(base + NGD_INT_STAT);
758
759 if ((stat & NGD_INT_MSG_BUF_CONTE) ||
760 (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
761 (stat & NGD_INT_TX_NACKED_2)) {
762 dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat);
763 }
764
765 writel(stat, base + NGD_INT_CLR);
766
767 return IRQ_HANDLED;
768}
769
770static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
771 struct slim_msg_txn *txn)
772{
773 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
774 DECLARE_COMPLETION_ONSTACK(tx_sent);
775 DECLARE_COMPLETION_ONSTACK(done);
776 int ret, timeout, i;
777 u8 wbuf[SLIM_MSGQ_BUF_LEN];
778 u8 rbuf[SLIM_MSGQ_BUF_LEN];
779 u32 *pbuf;
780 u8 *puc;
781 u8 la = txn->la;
782 bool usr_msg = false;
783
784 if (txn->mt == SLIM_MSG_MT_CORE &&
785 (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
786 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
787 return 0;
788
789 if (txn->dt == SLIM_MSG_DEST_ENUMADDR)
790 return -EPROTONOSUPPORT;
791
792 if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
793 txn->rl > SLIM_MSGQ_BUF_LEN) {
794 dev_err(ctrl->dev, "msg exceeds HW limit\n");
795 return -EINVAL;
796 }
797
798 pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
799 if (!pbuf) {
800 dev_err(ctrl->dev, "Message buffer unavailable\n");
801 return -ENOMEM;
802 }
803
804 if (txn->mt == SLIM_MSG_MT_CORE &&
805 (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
806 txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
807 txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
808 txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
809 switch (txn->mc) {
810 case SLIM_MSG_MC_CONNECT_SOURCE:
811 txn->mc = SLIM_USR_MC_CONNECT_SRC;
812 break;
813 case SLIM_MSG_MC_CONNECT_SINK:
814 txn->mc = SLIM_USR_MC_CONNECT_SINK;
815 break;
816 case SLIM_MSG_MC_DISCONNECT_PORT:
817 txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
818 break;
819 default:
820 return -EINVAL;
821 }
822
823 usr_msg = true;
824 i = 0;
825 wbuf[i++] = txn->la;
826 la = SLIM_LA_MGR;
827 wbuf[i++] = txn->msg->wbuf[0];
828 if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
829 wbuf[i++] = txn->msg->wbuf[1];
830
831 txn->comp = &done;
832 ret = slim_alloc_txn_tid(sctrl, txn);
833 if (ret) {
834 dev_err(ctrl->dev, "Unable to allocate TID\n");
835 return ret;
836 }
837
838 wbuf[i++] = txn->tid;
839
840 txn->msg->num_bytes = i;
841 txn->msg->wbuf = wbuf;
842 txn->msg->rbuf = rbuf;
843 txn->rl = txn->msg->num_bytes + 4;
844 }
845
846 /* HW expects length field to be excluded */
847 txn->rl--;
848 puc = (u8 *)pbuf;
849 *pbuf = 0;
850 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
851 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
852 la);
853 puc += 3;
854 } else {
855 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
856 la);
857 puc += 2;
858 }
859
860 if (slim_tid_txn(txn->mt, txn->mc))
861 *(puc++) = txn->tid;
862
863 if (slim_ec_txn(txn->mt, txn->mc)) {
864 *(puc++) = (txn->ec & 0xFF);
865 *(puc++) = (txn->ec >> 8) & 0xFF;
866 }
867
868 if (txn->msg && txn->msg->wbuf)
869 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
870
871 ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
872 if (ret)
873 return ret;
874
875 timeout = wait_for_completion_timeout(&tx_sent, HZ);
876 if (!timeout) {
877 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
878 txn->mt);
879 return -ETIMEDOUT;
880 }
881
882 if (usr_msg) {
883 timeout = wait_for_completion_timeout(&done, HZ);
884 if (!timeout) {
885 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
886 txn->mc, txn->mt);
887 return -ETIMEDOUT;
888 }
889 }
890
891 return 0;
892}
893
894static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
895 struct slim_msg_txn *txn)
896{
897 DECLARE_COMPLETION_ONSTACK(done);
898 int ret, timeout;
899
900 pm_runtime_get_sync(ctrl->dev);
901
902 txn->comp = &done;
903
904 ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
905 if (ret)
906 return ret;
907
908 timeout = wait_for_completion_timeout(&done, HZ);
909 if (!timeout) {
910 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
911 txn->mt);
912 return -ETIMEDOUT;
913 }
914 return 0;
915}
916
917static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
918{
919 struct slim_device *sdev = rt->dev;
920 struct slim_controller *ctrl = sdev->ctrl;
921 struct slim_val_inf msg = {0};
922 u8 wbuf[SLIM_MSGQ_BUF_LEN];
923 u8 rbuf[SLIM_MSGQ_BUF_LEN];
924 struct slim_msg_txn txn = {0,};
925 int i, ret;
926
927 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
928 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
929 txn.la = SLIM_LA_MGR;
930 txn.ec = 0;
931 txn.msg = &msg;
932 txn.msg->num_bytes = 0;
933 txn.msg->wbuf = wbuf;
934 txn.msg->rbuf = rbuf;
935
936 for (i = 0; i < rt->num_ports; i++) {
937 struct slim_port *port = &rt->ports[i];
938
939 if (txn.msg->num_bytes == 0) {
940 int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem;
941 int exp;
942
943 wbuf[txn.msg->num_bytes++] = sdev->laddr;
944 wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
945 (port->ch.aux_fmt << 6);
946
947 /* Data channel segment interval not multiple of 3 */
948 exp = seg_interval % 3;
949 if (exp)
950 wbuf[txn.msg->num_bytes] |= BIT(5);
951
952 txn.msg->num_bytes++;
953 wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
954
955 if (rt->prot == SLIM_PROTO_ISO)
956 wbuf[txn.msg->num_bytes++] =
957 port->ch.prrate |
958 SLIM_CHANNEL_CONTENT_FL;
959 else
960 wbuf[txn.msg->num_bytes++] = port->ch.prrate;
961
962 ret = slim_alloc_txn_tid(ctrl, &txn);
963 if (ret) {
964 dev_err(&sdev->dev, "Fail to allocate TID\n");
965 return -ENXIO;
966 }
967 wbuf[txn.msg->num_bytes++] = txn.tid;
968 }
969 wbuf[txn.msg->num_bytes++] = port->ch.id;
970 }
971
972 txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
973 txn.rl = txn.msg->num_bytes + 4;
974 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
975 if (ret) {
976 slim_free_txn_tid(ctrl, &txn);
977 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
978 txn.mt);
979 return ret;
980 }
981
982 txn.mc = SLIM_USR_MC_RECONFIG_NOW;
983 txn.msg->num_bytes = 2;
984 wbuf[1] = sdev->laddr;
985 txn.rl = txn.msg->num_bytes + 4;
986
987 ret = slim_alloc_txn_tid(ctrl, &txn);
988 if (ret) {
989 dev_err(ctrl->dev, "Fail to allocate TID\n");
990 return ret;
991 }
992
993 wbuf[0] = txn.tid;
994 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
995 if (ret) {
996 slim_free_txn_tid(ctrl, &txn);
997 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
998 txn.mt);
999 }
1000
1001 return ret;
1002}
1003
1004static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
1005 struct slim_eaddr *ea, u8 *laddr)
1006{
1007 struct slim_val_inf msg = {0};
1008 u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
1009 struct slim_msg_txn txn;
1010 u8 wbuf[10] = {0};
1011 u8 rbuf[10] = {0};
1012 int ret;
1013
1014 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
1015 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1016 txn.la = SLIM_LA_MGR;
1017 txn.ec = 0;
1018
1019 txn.mc = SLIM_USR_MC_ADDR_QUERY;
1020 txn.rl = 11;
1021 txn.msg = &msg;
1022 txn.msg->num_bytes = 7;
1023 txn.msg->wbuf = wbuf;
1024 txn.msg->rbuf = rbuf;
1025
1026 ret = slim_alloc_txn_tid(ctrl, &txn);
1027 if (ret < 0)
1028 return ret;
1029
1030 wbuf[0] = (u8)txn.tid;
1031 memcpy(&wbuf[1], ea, sizeof(*ea));
1032
1033 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1034 if (ret) {
1035 slim_free_txn_tid(ctrl, &txn);
1036 return ret;
1037 }
1038
1039 if (!memcmp(rbuf, failed_ea, 6))
1040 return -ENXIO;
1041
1042 *laddr = rbuf[6];
1043
1044 return ret;
1045}
1046
1047static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
1048{
1049 if (ctrl->dma_rx_channel) {
1050 dmaengine_terminate_sync(ctrl->dma_rx_channel);
1051 dma_release_channel(ctrl->dma_rx_channel);
1052 }
1053
1054 if (ctrl->dma_tx_channel) {
1055 dmaengine_terminate_sync(ctrl->dma_tx_channel);
1056 dma_release_channel(ctrl->dma_tx_channel);
1057 }
1058
1059 ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
1060
1061 return 0;
1062}
1063
1064static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
1065{
1066 u32 cfg = readl_relaxed(ctrl->ngd->base);
1067
1068 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1069 qcom_slim_ngd_init_dma(ctrl);
1070
1071 /* By default enable message queues */
1072 cfg |= NGD_CFG_RX_MSGQ_EN;
1073 cfg |= NGD_CFG_TX_MSGQ_EN;
1074
1075 /* Enable NGD if it's not already enabled*/
1076 if (!(cfg & NGD_CFG_ENABLE))
1077 cfg |= NGD_CFG_ENABLE;
1078
1079 writel_relaxed(cfg, ctrl->ngd->base);
1080}
1081
1082static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
1083{
1084 enum qcom_slim_ngd_state cur_state = ctrl->state;
1085 struct qcom_slim_ngd *ngd = ctrl->ngd;
1086 u32 laddr, rx_msgq;
1087 int timeout, ret = 0;
1088
1089 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1090 timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
1091 if (!timeout)
1092 return -EREMOTEIO;
1093 }
1094
1095 if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
1096 ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1097 ret = qcom_slim_qmi_power_request(ctrl, true);
1098 if (ret) {
1099 dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n",
1100 ret);
1101 return ret;
1102 }
1103 }
1104
1105 ctrl->ver = readl_relaxed(ctrl->base);
1106 /* Version info in 16 MSbits */
1107 ctrl->ver >>= 16;
1108
1109 laddr = readl_relaxed(ngd->base + NGD_STATUS);
1110 if (laddr & NGD_LADDR) {
1111 /*
1112 * external MDM restart case where ADSP itself was active framer
1113 * For example, modem restarted when playback was active
1114 */
1115 if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
1116 dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n");
1117 return 0;
1118 }
1119 return 0;
1120 }
1121
1122 writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
1123 rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
1124
1125 writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
1126 ngd->base + NGD_RX_MSGQ_CFG);
1127 qcom_slim_ngd_setup(ctrl);
1128
1129 timeout = wait_for_completion_timeout(&ctrl->reconf, HZ);
1130 if (!timeout) {
1131 dev_err(ctrl->dev, "capability exchange timed-out\n");
1132 return -ETIMEDOUT;
1133 }
1134
1135 return 0;
1136}
1137
1138static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
1139{
1140 struct slim_device *sbdev;
1141 struct device_node *node;
1142
1143 for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
1144 sbdev = of_slim_get_device(&ctrl->ctrl, node);
1145 if (!sbdev)
1146 continue;
1147
1148 if (slim_get_logical_addr(sbdev))
1149 dev_err(ctrl->dev, "Failed to get logical address\n");
1150 }
1151}
1152
1153static void qcom_slim_ngd_master_worker(struct work_struct *work)
1154{
1155 struct qcom_slim_ngd_ctrl *ctrl;
1156 struct slim_msg_txn txn;
1157 struct slim_val_inf msg = {0};
1158 int retries = 0;
1159 u8 wbuf[8];
1160 int ret = 0;
1161
1162 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
1163 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1164 txn.ec = 0;
1165 txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
1166 txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
1167 txn.la = SLIM_LA_MGR;
1168 wbuf[0] = SAT_MAGIC_LSB;
1169 wbuf[1] = SAT_MAGIC_MSB;
1170 wbuf[2] = SAT_MSG_VER;
1171 wbuf[3] = SAT_MSG_PROT;
1172 txn.msg = &msg;
1173 txn.msg->wbuf = wbuf;
1174 txn.msg->num_bytes = 4;
1175 txn.rl = 8;
1176
1177 dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n");
1178
1179capability_retry:
1180 ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
1181 if (!ret) {
1182 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1183 complete(&ctrl->reconf);
1184 else
1185 dev_err(ctrl->dev, "unexpected state:%d\n",
1186 ctrl->state);
1187
1188 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1189 qcom_slim_ngd_notify_slaves(ctrl);
1190
1191 } else if (ret == -EIO) {
1192 dev_err(ctrl->dev, "capability message NACKed, retrying\n");
1193 if (retries < INIT_MX_RETRIES) {
1194 msleep(DEF_RETRY_MS);
1195 retries++;
1196 goto capability_retry;
1197 }
1198 } else {
1199 dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
1200 }
1201}
1202
1203static int qcom_slim_ngd_runtime_resume(struct device *dev)
1204{
1205 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1206 int ret = 0;
1207
1208 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1209 ret = qcom_slim_ngd_power_up(ctrl);
1210 if (ret) {
1211 /* Did SSR cause this power up failure */
1212 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
1213 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1214 else
1215 dev_err(ctrl->dev, "HW wakeup attempt during SSR\n");
1216 } else {
1217 ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
1218 }
1219
1220 return 0;
1221}
1222
1223static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
1224{
1225 if (enable) {
1226 int ret = qcom_slim_qmi_init(ctrl, false);
1227
1228 if (ret) {
1229 dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n",
1230 ret, ctrl->state);
1231 return ret;
1232 }
1233 /* controller state should be in sync with framework state */
1234 complete(&ctrl->qmi.qmi_comp);
1235 if (!pm_runtime_enabled(ctrl->dev) ||
1236 !pm_runtime_suspended(ctrl->dev))
1237 qcom_slim_ngd_runtime_resume(ctrl->dev);
1238 else
1239 pm_runtime_resume(ctrl->dev);
1240 pm_runtime_mark_last_busy(ctrl->dev);
1241 pm_runtime_put(ctrl->dev);
1242
1243 ret = slim_register_controller(&ctrl->ctrl);
1244 if (ret) {
1245 dev_err(ctrl->dev, "error adding slim controller\n");
1246 return ret;
1247 }
1248
1249 dev_info(ctrl->dev, "SLIM controller Registered\n");
1250 } else {
1251 qcom_slim_qmi_exit(ctrl);
1252 slim_unregister_controller(&ctrl->ctrl);
1253 }
1254
1255 return 0;
1256}
1257
1258static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
1259 struct qmi_service *service)
1260{
1261 struct qcom_slim_ngd_qmi *qmi =
1262 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1263 struct qcom_slim_ngd_ctrl *ctrl =
1264 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1265
1266 qmi->svc_info.sq_family = AF_QIPCRTR;
1267 qmi->svc_info.sq_node = service->node;
1268 qmi->svc_info.sq_port = service->port;
1269
1270 qcom_slim_ngd_enable(ctrl, true);
1271
1272 return 0;
1273}
1274
1275static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
1276 struct qmi_service *service)
1277{
1278 struct qcom_slim_ngd_qmi *qmi =
1279 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1280
1281 qmi->svc_info.sq_node = 0;
1282 qmi->svc_info.sq_port = 0;
1283}
1284
1285static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
1286 .new_server = qcom_slim_ngd_qmi_new_server,
1287 .del_server = qcom_slim_ngd_qmi_del_server,
1288};
1289
1290static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
1291{
1292 struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
1293 int ret;
1294
1295 ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
1296 &qcom_slim_ngd_qmi_svc_event_ops, NULL);
1297 if (ret < 0) {
1298 dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
1299 return ret;
1300 }
1301
1302 ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
1303 SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
1304 if (ret < 0) {
1305 dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
1306 qmi_handle_release(&qmi->svc_event_hdl);
1307 }
1308 return ret;
1309}
1310
1311static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
1312{
1313 qmi_handle_release(&qmi->svc_event_hdl);
1314}
1315
1316static struct platform_driver qcom_slim_ngd_driver;
1317#define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd"
1318
1319static const struct of_device_id qcom_slim_ngd_dt_match[] = {
1320 {
1321 .compatible = "qcom,slim-ngd-v1.5.0",
1322 .data = &ngd_v1_5_offset_info,
1323 },{
1324 .compatible = "qcom,slim-ngd-v2.1.0",
1325 .data = &ngd_v1_5_offset_info,
1326 },
1327 {}
1328};
1329
1330MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
1331
1332static int of_qcom_slim_ngd_register(struct device *parent,
1333 struct qcom_slim_ngd_ctrl *ctrl)
1334{
1335 const struct ngd_reg_offset_data *data;
1336 struct qcom_slim_ngd *ngd;
1337 const struct of_device_id *match;
1338 struct device_node *node;
1339 u32 id;
1340
1341 match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
1342 data = match->data;
1343 for_each_available_child_of_node(parent->of_node, node) {
1344 if (of_property_read_u32(node, "reg", &id))
1345 continue;
1346
1347 ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
1348 if (!ngd) {
1349 of_node_put(node);
1350 return -ENOMEM;
1351 }
1352
1353 ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
1354 if (!ngd->pdev) {
1355 kfree(ngd);
1356 of_node_put(node);
1357 return -ENOMEM;
1358 }
1359 ngd->id = id;
1360 ngd->pdev->dev.parent = parent;
1361 ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME;
1362 ngd->pdev->dev.of_node = node;
1363 ctrl->ngd = ngd;
1364
1365 platform_device_add(ngd->pdev);
1366 ngd->base = ctrl->base + ngd->id * data->offset +
1367 (ngd->id - 1) * data->size;
1368
1369 return 0;
1370 }
1371
1372 return -ENODEV;
1373}
1374
1375static int qcom_slim_ngd_probe(struct platform_device *pdev)
1376{
1377 struct device *dev = &pdev->dev;
1378 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
1379 int ret;
1380
1381 ctrl->ctrl.dev = dev;
1382
1383 platform_set_drvdata(pdev, ctrl);
1384 pm_runtime_use_autosuspend(dev);
1385 pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND);
1386 pm_runtime_set_suspended(dev);
1387 pm_runtime_enable(dev);
1388 pm_runtime_get_noresume(dev);
1389 ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
1390 if (ret) {
1391 dev_err(&pdev->dev, "QMI service registration failed:%d", ret);
1392 return ret;
1393 }
1394
1395 INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
1396 ctrl->mwq = create_singlethread_workqueue("ngd_master");
1397 if (!ctrl->mwq) {
1398 dev_err(&pdev->dev, "Failed to start master worker\n");
1399 ret = -ENOMEM;
1400 goto wq_err;
1401 }
1402
1403 return 0;
1404wq_err:
1405 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1406 if (ctrl->mwq)
1407 destroy_workqueue(ctrl->mwq);
1408
1409 return ret;
1410}
1411
1412static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
1413{
1414 struct device *dev = &pdev->dev;
1415 struct qcom_slim_ngd_ctrl *ctrl;
1416 struct resource *res;
1417 int ret;
1418
1419 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1420 if (!ctrl)
1421 return -ENOMEM;
1422
1423 dev_set_drvdata(dev, ctrl);
1424
1425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1426 ctrl->base = devm_ioremap_resource(dev, res);
1427 if (IS_ERR(ctrl->base))
1428 return PTR_ERR(ctrl->base);
1429
1430 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1431 if (!res) {
1432 dev_err(&pdev->dev, "no slimbus IRQ resource\n");
1433 return -ENODEV;
1434 }
1435
1436 ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt,
1437 IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
1438 if (ret) {
1439 dev_err(&pdev->dev, "request IRQ failed\n");
1440 return ret;
1441 }
1442
1443 ctrl->dev = dev;
1444 ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
1445 ctrl->framer.superfreq =
1446 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
1447
1448 ctrl->ctrl.a_framer = &ctrl->framer;
1449 ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
1450 ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
1451 ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
1452 ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
1453 ctrl->ctrl.wakeup = NULL;
1454 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1455
1456 spin_lock_init(&ctrl->tx_buf_lock);
1457 init_completion(&ctrl->reconf);
1458 init_completion(&ctrl->qmi.qmi_comp);
1459
1460 platform_driver_register(&qcom_slim_ngd_driver);
1461 return of_qcom_slim_ngd_register(dev, ctrl);
1462}
1463
1464static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
1465{
1466 platform_driver_unregister(&qcom_slim_ngd_driver);
1467
1468 return 0;
1469}
1470
1471static int qcom_slim_ngd_remove(struct platform_device *pdev)
1472{
1473 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
1474
1475 pm_runtime_disable(&pdev->dev);
1476 qcom_slim_ngd_enable(ctrl, false);
1477 qcom_slim_ngd_exit_dma(ctrl);
1478 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1479 if (ctrl->mwq)
1480 destroy_workqueue(ctrl->mwq);
1481
1482 kfree(ctrl->ngd);
1483 ctrl->ngd = NULL;
1484 return 0;
1485}
1486
1487static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
1488{
1489 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1490
1491 if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
1492 ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
1493 pm_request_autosuspend(dev);
1494 return -EAGAIN;
1495}
1496
1497static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
1498{
1499 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1500 int ret = 0;
1501
1502 ret = qcom_slim_qmi_power_request(ctrl, false);
1503 if (ret && ret != -EBUSY)
1504 dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
1505 if (!ret || ret == -ETIMEDOUT)
1506 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1507
1508 return ret;
1509}
1510
1511static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
1512 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1513 pm_runtime_force_resume)
1514 SET_RUNTIME_PM_OPS(
1515 qcom_slim_ngd_runtime_suspend,
1516 qcom_slim_ngd_runtime_resume,
1517 qcom_slim_ngd_runtime_idle
1518 )
1519};
1520
1521static struct platform_driver qcom_slim_ngd_ctrl_driver = {
1522 .probe = qcom_slim_ngd_ctrl_probe,
1523 .remove = qcom_slim_ngd_ctrl_remove,
1524 .driver = {
1525 .name = "qcom,slim-ngd-ctrl",
1526 .of_match_table = qcom_slim_ngd_dt_match,
1527 },
1528};
1529
1530static struct platform_driver qcom_slim_ngd_driver = {
1531 .probe = qcom_slim_ngd_probe,
1532 .remove = qcom_slim_ngd_remove,
1533 .driver = {
1534 .name = QCOM_SLIM_NGD_DRV_NAME,
1535 .pm = &qcom_slim_ngd_dev_pm_ops,
1536 },
1537};
1538
1539module_platform_driver(qcom_slim_ngd_ctrl_driver);
1540MODULE_LICENSE("GPL v2");
1541MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");