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1// SPDX-License-Identifier: GPL-2.0
2//
3// Linear Technology LTC3589,LTC3589-1 regulator support
4//
5// Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix
6
7#include <linux/i2c.h>
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/regmap.h>
15#include <linux/regulator/driver.h>
16#include <linux/regulator/of_regulator.h>
17
18#define DRIVER_NAME "ltc3589"
19
20#define LTC3589_IRQSTAT 0x02
21#define LTC3589_SCR1 0x07
22#define LTC3589_OVEN 0x10
23#define LTC3589_SCR2 0x12
24#define LTC3589_PGSTAT 0x13
25#define LTC3589_VCCR 0x20
26#define LTC3589_CLIRQ 0x21
27#define LTC3589_B1DTV1 0x23
28#define LTC3589_B1DTV2 0x24
29#define LTC3589_VRRCR 0x25
30#define LTC3589_B2DTV1 0x26
31#define LTC3589_B2DTV2 0x27
32#define LTC3589_B3DTV1 0x29
33#define LTC3589_B3DTV2 0x2a
34#define LTC3589_L2DTV1 0x32
35#define LTC3589_L2DTV2 0x33
36
37#define LTC3589_IRQSTAT_PGOOD_TIMEOUT BIT(3)
38#define LTC3589_IRQSTAT_UNDERVOLT_WARN BIT(4)
39#define LTC3589_IRQSTAT_UNDERVOLT_FAULT BIT(5)
40#define LTC3589_IRQSTAT_THERMAL_WARN BIT(6)
41#define LTC3589_IRQSTAT_THERMAL_FAULT BIT(7)
42
43#define LTC3589_OVEN_SW1 BIT(0)
44#define LTC3589_OVEN_SW2 BIT(1)
45#define LTC3589_OVEN_SW3 BIT(2)
46#define LTC3589_OVEN_BB_OUT BIT(3)
47#define LTC3589_OVEN_LDO2 BIT(4)
48#define LTC3589_OVEN_LDO3 BIT(5)
49#define LTC3589_OVEN_LDO4 BIT(6)
50#define LTC3589_OVEN_SW_CTRL BIT(7)
51
52#define LTC3589_VCCR_SW1_GO BIT(0)
53#define LTC3589_VCCR_SW2_GO BIT(2)
54#define LTC3589_VCCR_SW3_GO BIT(4)
55#define LTC3589_VCCR_LDO2_GO BIT(6)
56
57enum ltc3589_variant {
58 LTC3589,
59 LTC3589_1,
60 LTC3589_2,
61};
62
63enum ltc3589_reg {
64 LTC3589_SW1,
65 LTC3589_SW2,
66 LTC3589_SW3,
67 LTC3589_BB_OUT,
68 LTC3589_LDO1,
69 LTC3589_LDO2,
70 LTC3589_LDO3,
71 LTC3589_LDO4,
72 LTC3589_NUM_REGULATORS,
73};
74
75struct ltc3589 {
76 struct regmap *regmap;
77 struct device *dev;
78 enum ltc3589_variant variant;
79 struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS];
80 struct regulator_dev *regulators[LTC3589_NUM_REGULATORS];
81};
82
83static const int ltc3589_ldo4[] = {
84 2800000, 2500000, 1800000, 3300000,
85};
86
87static const int ltc3589_12_ldo4[] = {
88 1200000, 1800000, 2500000, 3200000,
89};
90
91static int ltc3589_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
92{
93 struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
94 int sel, shift;
95
96 if (unlikely(ramp_delay <= 0))
97 return -EINVAL;
98
99 /* VRRCR slew rate offsets are the same as VCCR go bit offsets */
100 shift = ffs(rdev->desc->apply_bit) - 1;
101
102 /* The slew rate can be set to 0.88, 1.75, 3.5, or 7 mV/uS */
103 for (sel = 0; sel < 4; sel++) {
104 if ((880 << sel) >= ramp_delay) {
105 return regmap_update_bits(ltc3589->regmap,
106 LTC3589_VRRCR,
107 0x3 << shift, sel << shift);
108 }
109 }
110 return -EINVAL;
111}
112
113static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV)
114{
115 struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
116 int sel;
117
118 sel = regulator_map_voltage_linear(rdev, uV, uV);
119 if (sel < 0)
120 return sel;
121
122 /* DTV2 register follows right after the corresponding DTV1 register */
123 return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1,
124 rdev->desc->vsel_mask, sel);
125}
126
127static int ltc3589_set_suspend_mode(struct regulator_dev *rdev,
128 unsigned int mode)
129{
130 struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
131 int mask, bit = 0;
132
133 /* VCCR reference selects are right next to the VCCR go bits */
134 mask = rdev->desc->apply_bit << 1;
135
136 if (mode == REGULATOR_MODE_STANDBY)
137 bit = mask; /* Select DTV2 */
138
139 mask |= rdev->desc->apply_bit;
140 bit |= rdev->desc->apply_bit;
141 return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit);
142}
143
144/* SW1, SW2, SW3, LDO2 */
145static const struct regulator_ops ltc3589_linear_regulator_ops = {
146 .enable = regulator_enable_regmap,
147 .disable = regulator_disable_regmap,
148 .is_enabled = regulator_is_enabled_regmap,
149 .list_voltage = regulator_list_voltage_linear,
150 .set_voltage_sel = regulator_set_voltage_sel_regmap,
151 .get_voltage_sel = regulator_get_voltage_sel_regmap,
152 .set_ramp_delay = ltc3589_set_ramp_delay,
153 .set_voltage_time_sel = regulator_set_voltage_time_sel,
154 .set_suspend_voltage = ltc3589_set_suspend_voltage,
155 .set_suspend_mode = ltc3589_set_suspend_mode,
156};
157
158/* BB_OUT, LDO3 */
159static const struct regulator_ops ltc3589_fixed_regulator_ops = {
160 .enable = regulator_enable_regmap,
161 .disable = regulator_disable_regmap,
162 .is_enabled = regulator_is_enabled_regmap,
163};
164
165/* LDO1 */
166static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = {
167};
168
169/* LDO4 */
170static const struct regulator_ops ltc3589_table_regulator_ops = {
171 .enable = regulator_enable_regmap,
172 .disable = regulator_disable_regmap,
173 .is_enabled = regulator_is_enabled_regmap,
174 .list_voltage = regulator_list_voltage_table,
175 .set_voltage_sel = regulator_set_voltage_sel_regmap,
176 .get_voltage_sel = regulator_get_voltage_sel_regmap,
177};
178
179static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2)
180{
181 uint64_t tmp;
182
183 if (uV == 0)
184 return 0;
185
186 tmp = (uint64_t)uV * r1;
187 do_div(tmp, r2);
188 return uV + (unsigned int)tmp;
189}
190
191static int ltc3589_of_parse_cb(struct device_node *np,
192 const struct regulator_desc *desc,
193 struct regulator_config *config)
194{
195 struct ltc3589 *ltc3589 = config->driver_data;
196 struct regulator_desc *rdesc = <c3589->regulator_descs[desc->id];
197 u32 r[2];
198 int ret;
199
200 /* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */
201 if (desc->id >= LTC3589_LDO3)
202 return 0;
203
204 ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
205 if (ret) {
206 dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n",
207 ret);
208 return ret;
209 }
210
211 if (!r[0] || !r[1])
212 return 0;
213
214 rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]);
215 rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]);
216 rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]);
217
218 return 0;
219}
220
221#define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit)\
222 [LTC3589_ ## _name] = { \
223 .name = #_name, \
224 .of_match = of_match_ptr(#_of_name), \
225 .regulators_node = of_match_ptr("regulators"), \
226 .of_parse_cb = ltc3589_of_parse_cb, \
227 .n_voltages = (dtv_mask) + 1, \
228 .min_uV = (go_bit) ? 362500 : 0, \
229 .uV_step = (go_bit) ? 12500 : 0, \
230 .ramp_delay = (go_bit) ? 1750 : 0, \
231 .fixed_uV = (dtv_mask) ? 0 : 800000, \
232 .ops = <c3589_ ## _ops ## _regulator_ops, \
233 .type = REGULATOR_VOLTAGE, \
234 .id = LTC3589_ ## _name, \
235 .owner = THIS_MODULE, \
236 .vsel_reg = (dtv1_reg), \
237 .vsel_mask = (dtv_mask), \
238 .apply_reg = (go_bit) ? LTC3589_VCCR : 0, \
239 .apply_bit = (go_bit), \
240 .enable_reg = (en_bit) ? LTC3589_OVEN : 0, \
241 .enable_mask = (en_bit), \
242 }
243
244#define LTC3589_LINEAR_REG(_name, _of_name, _dtv1) \
245 LTC3589_REG(_name, _of_name, linear, LTC3589_OVEN_ ## _name, \
246 LTC3589_ ## _dtv1, 0x1f, \
247 LTC3589_VCCR_ ## _name ## _GO)
248
249#define LTC3589_FIXED_REG(_name, _of_name) \
250 LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0, 0)
251
252static const struct regulator_desc ltc3589_regulators[] = {
253 LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
254 LTC3589_LINEAR_REG(SW2, sw2, B2DTV1),
255 LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
256 LTC3589_FIXED_REG(BB_OUT, bb-out),
257 LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
258 LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1),
259 LTC3589_FIXED_REG(LDO3, ldo3),
260 LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2,
261 0x60, 0),
262};
263
264static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg)
265{
266 switch (reg) {
267 case LTC3589_IRQSTAT:
268 case LTC3589_SCR1:
269 case LTC3589_OVEN:
270 case LTC3589_SCR2:
271 case LTC3589_VCCR:
272 case LTC3589_CLIRQ:
273 case LTC3589_B1DTV1:
274 case LTC3589_B1DTV2:
275 case LTC3589_VRRCR:
276 case LTC3589_B2DTV1:
277 case LTC3589_B2DTV2:
278 case LTC3589_B3DTV1:
279 case LTC3589_B3DTV2:
280 case LTC3589_L2DTV1:
281 case LTC3589_L2DTV2:
282 return true;
283 }
284 return false;
285}
286
287static bool ltc3589_readable_reg(struct device *dev, unsigned int reg)
288{
289 switch (reg) {
290 case LTC3589_IRQSTAT:
291 case LTC3589_SCR1:
292 case LTC3589_OVEN:
293 case LTC3589_SCR2:
294 case LTC3589_PGSTAT:
295 case LTC3589_VCCR:
296 case LTC3589_B1DTV1:
297 case LTC3589_B1DTV2:
298 case LTC3589_VRRCR:
299 case LTC3589_B2DTV1:
300 case LTC3589_B2DTV2:
301 case LTC3589_B3DTV1:
302 case LTC3589_B3DTV2:
303 case LTC3589_L2DTV1:
304 case LTC3589_L2DTV2:
305 return true;
306 }
307 return false;
308}
309
310static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
311{
312 switch (reg) {
313 case LTC3589_IRQSTAT:
314 case LTC3589_PGSTAT:
315 case LTC3589_VCCR:
316 return true;
317 }
318 return false;
319}
320
321static const struct reg_default ltc3589_reg_defaults[] = {
322 { LTC3589_SCR1, 0x00 },
323 { LTC3589_OVEN, 0x00 },
324 { LTC3589_SCR2, 0x00 },
325 { LTC3589_VCCR, 0x00 },
326 { LTC3589_B1DTV1, 0x19 },
327 { LTC3589_B1DTV2, 0x19 },
328 { LTC3589_VRRCR, 0xff },
329 { LTC3589_B2DTV1, 0x19 },
330 { LTC3589_B2DTV2, 0x19 },
331 { LTC3589_B3DTV1, 0x19 },
332 { LTC3589_B3DTV2, 0x19 },
333 { LTC3589_L2DTV1, 0x19 },
334 { LTC3589_L2DTV2, 0x19 },
335};
336
337static const struct regmap_config ltc3589_regmap_config = {
338 .reg_bits = 8,
339 .val_bits = 8,
340 .writeable_reg = ltc3589_writeable_reg,
341 .readable_reg = ltc3589_readable_reg,
342 .volatile_reg = ltc3589_volatile_reg,
343 .max_register = LTC3589_L2DTV2,
344 .reg_defaults = ltc3589_reg_defaults,
345 .num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults),
346 .use_single_read = true,
347 .use_single_write = true,
348 .cache_type = REGCACHE_RBTREE,
349};
350
351static irqreturn_t ltc3589_isr(int irq, void *dev_id)
352{
353 struct ltc3589 *ltc3589 = dev_id;
354 unsigned int i, irqstat, event;
355
356 regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);
357
358 if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
359 event = REGULATOR_EVENT_OVER_TEMP;
360 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
361 regulator_lock(ltc3589->regulators[i]);
362 regulator_notifier_call_chain(ltc3589->regulators[i],
363 event, NULL);
364 regulator_unlock(ltc3589->regulators[i]);
365 }
366 }
367
368 if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
369 event = REGULATOR_EVENT_UNDER_VOLTAGE;
370 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
371 regulator_lock(ltc3589->regulators[i]);
372 regulator_notifier_call_chain(ltc3589->regulators[i],
373 event, NULL);
374 regulator_unlock(ltc3589->regulators[i]);
375 }
376 }
377
378 /* Clear warning condition */
379 regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0);
380
381 return IRQ_HANDLED;
382}
383
384static int ltc3589_probe(struct i2c_client *client,
385 const struct i2c_device_id *id)
386{
387 struct device *dev = &client->dev;
388 struct regulator_desc *descs;
389 struct ltc3589 *ltc3589;
390 int i, ret;
391
392 ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL);
393 if (!ltc3589)
394 return -ENOMEM;
395
396 i2c_set_clientdata(client, ltc3589);
397 if (client->dev.of_node)
398 ltc3589->variant = (enum ltc3589_variant)
399 of_device_get_match_data(&client->dev);
400 else
401 ltc3589->variant = id->driver_data;
402 ltc3589->dev = dev;
403
404 descs = ltc3589->regulator_descs;
405 memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators));
406 if (ltc3589->variant == LTC3589) {
407 descs[LTC3589_LDO3].fixed_uV = 1800000;
408 descs[LTC3589_LDO4].volt_table = ltc3589_ldo4;
409 } else {
410 descs[LTC3589_LDO3].fixed_uV = 2800000;
411 descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4;
412 }
413
414 ltc3589->regmap = devm_regmap_init_i2c(client, <c3589_regmap_config);
415 if (IS_ERR(ltc3589->regmap)) {
416 ret = PTR_ERR(ltc3589->regmap);
417 dev_err(dev, "failed to initialize regmap: %d\n", ret);
418 return ret;
419 }
420
421 for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
422 struct regulator_desc *desc = <c3589->regulator_descs[i];
423 struct regulator_config config = { };
424
425 config.dev = dev;
426 config.driver_data = ltc3589;
427
428 ltc3589->regulators[i] = devm_regulator_register(dev, desc,
429 &config);
430 if (IS_ERR(ltc3589->regulators[i])) {
431 ret = PTR_ERR(ltc3589->regulators[i]);
432 dev_err(dev, "failed to register regulator %s: %d\n",
433 desc->name, ret);
434 return ret;
435 }
436 }
437
438 if (client->irq) {
439 ret = devm_request_threaded_irq(dev, client->irq, NULL,
440 ltc3589_isr,
441 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
442 client->name, ltc3589);
443 if (ret) {
444 dev_err(dev, "Failed to request IRQ: %d\n", ret);
445 return ret;
446 }
447 }
448
449 return 0;
450}
451
452static const struct i2c_device_id ltc3589_i2c_id[] = {
453 { "ltc3589", LTC3589 },
454 { "ltc3589-1", LTC3589_1 },
455 { "ltc3589-2", LTC3589_2 },
456 { }
457};
458MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);
459
460static const struct of_device_id ltc3589_of_match[] = {
461 {
462 .compatible = "lltc,ltc3589",
463 .data = (void *)LTC3589,
464 },
465 {
466 .compatible = "lltc,ltc3589-1",
467 .data = (void *)LTC3589_1,
468 },
469 {
470 .compatible = "lltc,ltc3589-2",
471 .data = (void *)LTC3589_2,
472 },
473 { },
474};
475MODULE_DEVICE_TABLE(of, ltc3589_of_match);
476
477static struct i2c_driver ltc3589_driver = {
478 .driver = {
479 .name = DRIVER_NAME,
480 .of_match_table = of_match_ptr(ltc3589_of_match),
481 },
482 .probe = ltc3589_probe,
483 .id_table = ltc3589_i2c_id,
484};
485module_i2c_driver(ltc3589_driver);
486
487MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
488MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)");
489MODULE_LICENSE("GPL v2");