1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * pinmux driver for CSR SiRFprimaII
  4 *
  5 * Authors:
  6 *	Rongjun Ying <rongjun.ying@csr.com>
  7 *	Yuping Luo <yuping.luo@csr.com>
  8 *	Barry Song <baohua.song@csr.com>
  9 *
 10 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
 11 * company.
 12 */
 13
 14#include <linux/init.h>
 15#include <linux/irq.h>
 16#include <linux/platform_device.h>
 17#include <linux/io.h>
 18#include <linux/slab.h>
 19#include <linux/err.h>
 20#include <linux/pinctrl/pinctrl.h>
 21#include <linux/pinctrl/pinmux.h>
 22#include <linux/pinctrl/consumer.h>
 23#include <linux/pinctrl/machine.h>
 24#include <linux/of.h>
 25#include <linux/of_address.h>
 26#include <linux/of_device.h>
 27#include <linux/of_platform.h>
 28#include <linux/bitops.h>
 29#include <linux/gpio/driver.h>
 30#include <linux/of_gpio.h>
 31
 32#include "pinctrl-sirf.h"
 33
 34#define DRIVER_NAME "pinmux-sirf"
 35
 36struct sirfsoc_gpio_bank {
 37	int id;
 38	int parent_irq;
 39	spinlock_t lock;
 40};
 41
 42struct sirfsoc_gpio_chip {
 43	struct of_mm_gpio_chip chip;
 44	struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
 45	spinlock_t lock;
 46};
 47
 48static struct sirfsoc_pin_group *sirfsoc_pin_groups;
 49static int sirfsoc_pingrp_cnt;
 50
 51static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 52{
 53	return sirfsoc_pingrp_cnt;
 54}
 55
 56static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
 57				       unsigned selector)
 58{
 59	return sirfsoc_pin_groups[selector].name;
 60}
 61
 62static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
 63				unsigned selector,
 64				const unsigned **pins,
 65				unsigned *num_pins)
 66{
 67	*pins = sirfsoc_pin_groups[selector].pins;
 68	*num_pins = sirfsoc_pin_groups[selector].num_pins;
 69	return 0;
 70}
 71
 72static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
 73				struct seq_file *s, unsigned offset)
 74{
 75	seq_printf(s, " " DRIVER_NAME);
 76}
 77
 78static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
 79				 struct device_node *np_config,
 80				 struct pinctrl_map **map, unsigned *num_maps)
 81{
 82	struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
 83	struct device_node *np;
 84	struct property *prop;
 85	const char *function, *group;
 86	int ret, index = 0, count = 0;
 87
 88	/* calculate number of maps required */
 89	for_each_child_of_node(np_config, np) {
 90		ret = of_property_read_string(np, "sirf,function", &function);
 91		if (ret < 0) {
 92			of_node_put(np);
 93			return ret;
 94		}
 95
 96		ret = of_property_count_strings(np, "sirf,pins");
 97		if (ret < 0) {
 98			of_node_put(np);
 99			return ret;
100		}
101
102		count += ret;
103	}
104
105	if (!count) {
106		dev_err(spmx->dev, "No child nodes passed via DT\n");
107		return -ENODEV;
108	}
109
110	*map = kcalloc(count, sizeof(**map), GFP_KERNEL);
111	if (!*map)
112		return -ENOMEM;
113
114	for_each_child_of_node(np_config, np) {
115		of_property_read_string(np, "sirf,function", &function);
116		of_property_for_each_string(np, "sirf,pins", prop, group) {
117			(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
118			(*map)[index].data.mux.group = group;
119			(*map)[index].data.mux.function = function;
120			index++;
121		}
122	}
123
124	*num_maps = count;
125
126	return 0;
127}
128
129static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
130		struct pinctrl_map *map, unsigned num_maps)
131{
132	kfree(map);
133}
134
135static const struct pinctrl_ops sirfsoc_pctrl_ops = {
136	.get_groups_count = sirfsoc_get_groups_count,
137	.get_group_name = sirfsoc_get_group_name,
138	.get_group_pins = sirfsoc_get_group_pins,
139	.pin_dbg_show = sirfsoc_pin_dbg_show,
140	.dt_node_to_map = sirfsoc_dt_node_to_map,
141	.dt_free_map = sirfsoc_dt_free_map,
142};
143
144static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
145static int sirfsoc_pmxfunc_cnt;
146
147static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
148					unsigned selector, bool enable)
149{
150	int i;
151	const struct sirfsoc_padmux *mux =
152		sirfsoc_pmx_functions[selector].padmux;
153	const struct sirfsoc_muxmask *mask = mux->muxmask;
154
155	for (i = 0; i < mux->muxmask_counts; i++) {
156		u32 muxval;
157		muxval = readl(spmx->gpio_virtbase +
158			SIRFSOC_GPIO_PAD_EN(mask[i].group));
159		if (enable)
160			muxval = muxval & ~mask[i].mask;
161		else
162			muxval = muxval | mask[i].mask;
163		writel(muxval, spmx->gpio_virtbase +
164			SIRFSOC_GPIO_PAD_EN(mask[i].group));
165	}
166
167	if (mux->funcmask && enable) {
168		u32 func_en_val;
169
170		func_en_val =
171			readl(spmx->rsc_virtbase + mux->ctrlreg);
172		func_en_val =
173			(func_en_val & ~mux->funcmask) | (mux->funcval);
174		writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
175	}
176}
177
178static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
179				unsigned selector,
180				unsigned group)
181{
182	struct sirfsoc_pmx *spmx;
183
184	spmx = pinctrl_dev_get_drvdata(pmxdev);
185	sirfsoc_pinmux_endisable(spmx, selector, true);
186
187	return 0;
188}
189
190static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
191{
192	return sirfsoc_pmxfunc_cnt;
193}
194
195static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
196					  unsigned selector)
197{
198	return sirfsoc_pmx_functions[selector].name;
199}
200
201static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
202				unsigned selector,
203				const char * const **groups,
204				unsigned * const num_groups)
205{
206	*groups = sirfsoc_pmx_functions[selector].groups;
207	*num_groups = sirfsoc_pmx_functions[selector].num_groups;
208	return 0;
209}
210
211static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
212	struct pinctrl_gpio_range *range, unsigned offset)
213{
214	struct sirfsoc_pmx *spmx;
215
216	int group = range->id;
217
218	u32 muxval;
219
220	spmx = pinctrl_dev_get_drvdata(pmxdev);
221
222	muxval = readl(spmx->gpio_virtbase +
223		SIRFSOC_GPIO_PAD_EN(group));
224	muxval = muxval | (1 << (offset - range->pin_base));
225	writel(muxval, spmx->gpio_virtbase +
226		SIRFSOC_GPIO_PAD_EN(group));
227
228	return 0;
229}
230
231static const struct pinmux_ops sirfsoc_pinmux_ops = {
232	.set_mux = sirfsoc_pinmux_set_mux,
233	.get_functions_count = sirfsoc_pinmux_get_funcs_count,
234	.get_function_name = sirfsoc_pinmux_get_func_name,
235	.get_function_groups = sirfsoc_pinmux_get_groups,
236	.gpio_request_enable = sirfsoc_pinmux_request_gpio,
237};
238
239static struct pinctrl_desc sirfsoc_pinmux_desc = {
240	.name = DRIVER_NAME,
241	.pctlops = &sirfsoc_pctrl_ops,
242	.pmxops = &sirfsoc_pinmux_ops,
243	.owner = THIS_MODULE,
244};
245
246static void __iomem *sirfsoc_rsc_of_iomap(void)
247{
248	const struct of_device_id rsc_ids[]  = {
249		{ .compatible = "sirf,prima2-rsc" },
250		{}
251	};
252	struct device_node *np;
253
254	np = of_find_matching_node(NULL, rsc_ids);
255	if (!np)
256		panic("unable to find compatible rsc node in dtb\n");
257
258	return of_iomap(np, 0);
259}
260
261static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
262	const struct of_phandle_args *gpiospec,
263	u32 *flags)
264{
265	if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
266		return -EINVAL;
267
268	if (flags)
269		*flags = gpiospec->args[1];
270
271	return gpiospec->args[0];
272}
273
274static const struct of_device_id pinmux_ids[] = {
275	{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
276	{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
277	{}
278};
279
280static int sirfsoc_pinmux_probe(struct platform_device *pdev)
281{
282	int ret;
283	struct sirfsoc_pmx *spmx;
284	struct device_node *np = pdev->dev.of_node;
285	const struct sirfsoc_pinctrl_data *pdata;
286
287	/* Create state holders etc for this driver */
288	spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
289	if (!spmx)
290		return -ENOMEM;
291
292	spmx->dev = &pdev->dev;
293
294	platform_set_drvdata(pdev, spmx);
295
296	spmx->gpio_virtbase = of_iomap(np, 0);
297	if (!spmx->gpio_virtbase) {
298		dev_err(&pdev->dev, "can't map gpio registers\n");
299		return -ENOMEM;
300	}
301
302	spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
303	if (!spmx->rsc_virtbase) {
304		ret = -ENOMEM;
305		dev_err(&pdev->dev, "can't map rsc registers\n");
306		goto out_no_rsc_remap;
307	}
308
309	pdata = of_match_node(pinmux_ids, np)->data;
310	sirfsoc_pin_groups = pdata->grps;
311	sirfsoc_pingrp_cnt = pdata->grps_cnt;
312	sirfsoc_pmx_functions = pdata->funcs;
313	sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
314	sirfsoc_pinmux_desc.pins = pdata->pads;
315	sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
316
317
318	/* Now register the pin controller and all pins it handles */
319	spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
320	if (IS_ERR(spmx->pmx)) {
321		dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
322		ret = PTR_ERR(spmx->pmx);
323		goto out_no_pmx;
324	}
325
326	dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
327
328	return 0;
329
330out_no_pmx:
331	iounmap(spmx->rsc_virtbase);
332out_no_rsc_remap:
333	iounmap(spmx->gpio_virtbase);
334	return ret;
335}
336
337#ifdef CONFIG_PM_SLEEP
338static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
339{
340	int i, j;
341	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
342
343	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
344		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
345			spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
346				SIRFSOC_GPIO_CTRL(i, j));
347		}
348		spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
349			SIRFSOC_GPIO_INT_STATUS(i));
350		spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
351			SIRFSOC_GPIO_PAD_EN(i));
352	}
353	spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
354
355	for (i = 0; i < 3; i++)
356		spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
357
358	return 0;
359}
360
361static int sirfsoc_pinmux_resume_noirq(struct device *dev)
362{
363	int i, j;
364	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
365
366	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
367		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
368			writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
369				SIRFSOC_GPIO_CTRL(i, j));
370		}
371		writel(spmx->ints_regs[i], spmx->gpio_virtbase +
372			SIRFSOC_GPIO_INT_STATUS(i));
373		writel(spmx->paden_regs[i], spmx->gpio_virtbase +
374			SIRFSOC_GPIO_PAD_EN(i));
375	}
376	writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
377
378	for (i = 0; i < 3; i++)
379		writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
380
381	return 0;
382}
383
384static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
385	.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
386	.resume_noirq = sirfsoc_pinmux_resume_noirq,
387	.freeze_noirq = sirfsoc_pinmux_suspend_noirq,
388	.restore_noirq = sirfsoc_pinmux_resume_noirq,
389};
390#endif
391
392static struct platform_driver sirfsoc_pinmux_driver = {
393	.driver = {
394		.name = DRIVER_NAME,
395		.of_match_table = pinmux_ids,
396#ifdef CONFIG_PM_SLEEP
397		.pm = &sirfsoc_pinmux_pm_ops,
398#endif
399	},
400	.probe = sirfsoc_pinmux_probe,
401};
402
403static int __init sirfsoc_pinmux_init(void)
404{
405	return platform_driver_register(&sirfsoc_pinmux_driver);
406}
407arch_initcall(sirfsoc_pinmux_init);
408
409static inline struct sirfsoc_gpio_bank *
410sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
411{
412	return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
413}
414
415static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
416{
417	return offset % SIRFSOC_GPIO_BANK_SIZE;
418}
419
420static void sirfsoc_gpio_irq_ack(struct irq_data *d)
421{
422	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
423	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
424	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
425	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
426	u32 val, offset;
427	unsigned long flags;
428
429	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
430
431	spin_lock_irqsave(&sgpio->lock, flags);
432
433	val = readl(sgpio->chip.regs + offset);
434
435	writel(val, sgpio->chip.regs + offset);
436
437	spin_unlock_irqrestore(&sgpio->lock, flags);
438}
439
440static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
441				    struct sirfsoc_gpio_bank *bank,
442				    int idx)
443{
444	u32 val, offset;
445	unsigned long flags;
446
447	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
448
449	spin_lock_irqsave(&sgpio->lock, flags);
450
451	val = readl(sgpio->chip.regs + offset);
452	val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
453	val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
454	writel(val, sgpio->chip.regs + offset);
455
456	spin_unlock_irqrestore(&sgpio->lock, flags);
457}
458
459static void sirfsoc_gpio_irq_mask(struct irq_data *d)
460{
461	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
462	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
463	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
464
465	__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
466}
467
468static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
469{
470	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
471	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
472	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
473	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
474	u32 val, offset;
475	unsigned long flags;
476
477	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
478
479	spin_lock_irqsave(&sgpio->lock, flags);
480
481	val = readl(sgpio->chip.regs + offset);
482	val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
483	val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
484	writel(val, sgpio->chip.regs + offset);
485
486	spin_unlock_irqrestore(&sgpio->lock, flags);
487}
488
489static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
490{
491	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
492	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
493	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
494	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
495	u32 val, offset;
496	unsigned long flags;
497
498	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
499
500	spin_lock_irqsave(&sgpio->lock, flags);
501
502	val = readl(sgpio->chip.regs + offset);
503	val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
504
505	switch (type) {
506	case IRQ_TYPE_NONE:
507		break;
508	case IRQ_TYPE_EDGE_RISING:
509		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
510			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
511		val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
512		break;
513	case IRQ_TYPE_EDGE_FALLING:
514		val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
515		val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
516			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
517		break;
518	case IRQ_TYPE_EDGE_BOTH:
519		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
520			SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
521			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
522		break;
523	case IRQ_TYPE_LEVEL_LOW:
524		val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
525			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
526		val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
527		break;
528	case IRQ_TYPE_LEVEL_HIGH:
529		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
530		val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
531			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
532		break;
533	}
534
535	writel(val, sgpio->chip.regs + offset);
536
537	spin_unlock_irqrestore(&sgpio->lock, flags);
538
539	return 0;
540}
541
542static struct irq_chip sirfsoc_irq_chip = {
543	.name = "sirf-gpio-irq",
544	.irq_ack = sirfsoc_gpio_irq_ack,
545	.irq_mask = sirfsoc_gpio_irq_mask,
546	.irq_unmask = sirfsoc_gpio_irq_unmask,
547	.irq_set_type = sirfsoc_gpio_irq_type,
548};
549
550static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
551{
552	unsigned int irq = irq_desc_get_irq(desc);
553	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
554	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
555	struct sirfsoc_gpio_bank *bank;
556	u32 status, ctrl;
557	int idx = 0;
558	struct irq_chip *chip = irq_desc_get_chip(desc);
559	int i;
560
561	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
562		bank = &sgpio->sgpio_bank[i];
563		if (bank->parent_irq == irq)
564			break;
565	}
566	BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
567
568	chained_irq_enter(chip, desc);
569
570	status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
571	if (!status) {
572		printk(KERN_WARNING
573			"%s: gpio id %d status %#x no interrupt is flagged\n",
574			__func__, bank->id, status);
575		handle_bad_irq(desc);
576		return;
577	}
578
579	while (status) {
580		ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
581
582		/*
583		 * Here we must check whether the corresponding GPIO's interrupt
584		 * has been enabled, otherwise just skip it
585		 */
586		if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
587			pr_debug("%s: gpio id %d idx %d happens\n",
588				__func__, bank->id, idx);
589			generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
590					bank->id * SIRFSOC_GPIO_BANK_SIZE));
591		}
592
593		idx++;
594		status = status >> 1;
595	}
596
597	chained_irq_exit(chip, desc);
598}
599
600static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
601					  unsigned ctrl_offset)
602{
603	u32 val;
604
605	val = readl(sgpio->chip.regs + ctrl_offset);
606	val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
607	writel(val, sgpio->chip.regs + ctrl_offset);
608}
609
610static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
611{
612	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
613	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
614	unsigned long flags;
615
616	if (pinctrl_gpio_request(chip->base + offset))
617		return -ENODEV;
618
619	spin_lock_irqsave(&bank->lock, flags);
620
621	/*
622	 * default status:
623	 * set direction as input and mask irq
624	 */
625	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
626	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
627
628	spin_unlock_irqrestore(&bank->lock, flags);
629
630	return 0;
631}
632
633static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
634{
635	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
636	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
637	unsigned long flags;
638
639	spin_lock_irqsave(&bank->lock, flags);
640
641	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
642	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
643
644	spin_unlock_irqrestore(&bank->lock, flags);
645
646	pinctrl_gpio_free(chip->base + offset);
647}
648
649static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
650{
651	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
652	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
653	int idx = sirfsoc_gpio_to_bankoff(gpio);
654	unsigned long flags;
655	unsigned offset;
656
657	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
658
659	spin_lock_irqsave(&bank->lock, flags);
660
661	sirfsoc_gpio_set_input(sgpio, offset);
662
663	spin_unlock_irqrestore(&bank->lock, flags);
664
665	return 0;
666}
667
668static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
669					   struct sirfsoc_gpio_bank *bank,
670					   unsigned offset,
671					   int value)
672{
673	u32 out_ctrl;
674	unsigned long flags;
675
676	spin_lock_irqsave(&bank->lock, flags);
677
678	out_ctrl = readl(sgpio->chip.regs + offset);
679	if (value)
680		out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
681	else
682		out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
683
684	out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
685	out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
686	writel(out_ctrl, sgpio->chip.regs + offset);
687
688	spin_unlock_irqrestore(&bank->lock, flags);
689}
690
691static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
692	unsigned gpio, int value)
693{
694	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
695	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
696	int idx = sirfsoc_gpio_to_bankoff(gpio);
697	u32 offset;
698	unsigned long flags;
699
700	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
701
702	spin_lock_irqsave(&sgpio->lock, flags);
703
704	sirfsoc_gpio_set_output(sgpio, bank, offset, value);
705
706	spin_unlock_irqrestore(&sgpio->lock, flags);
707
708	return 0;
709}
710
711static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
712{
713	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
714	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
715	u32 val;
716	unsigned long flags;
717
718	spin_lock_irqsave(&bank->lock, flags);
719
720	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
721
722	spin_unlock_irqrestore(&bank->lock, flags);
723
724	return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
725}
726
727static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
728	int value)
729{
730	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
731	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
732	u32 ctrl;
733	unsigned long flags;
734
735	spin_lock_irqsave(&bank->lock, flags);
736
737	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
738	if (value)
739		ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
740	else
741		ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
742	writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
743
744	spin_unlock_irqrestore(&bank->lock, flags);
745}
746
747static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
748				    const u32 *pullups)
749{
750	int i, n;
751	const unsigned long *p = (const unsigned long *)pullups;
752
753	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
754		for_each_set_bit(n, p + i, BITS_PER_LONG) {
755			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
756			u32 val = readl(sgpio->chip.regs + offset);
757			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
758			val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
759			writel(val, sgpio->chip.regs + offset);
760		}
761	}
762}
763
764static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
765				      const u32 *pulldowns)
766{
767	int i, n;
768	const unsigned long *p = (const unsigned long *)pulldowns;
769
770	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
771		for_each_set_bit(n, p + i, BITS_PER_LONG) {
772			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
773			u32 val = readl(sgpio->chip.regs + offset);
774			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
775			val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
776			writel(val, sgpio->chip.regs + offset);
777		}
778	}
779}
780
781static int sirfsoc_gpio_probe(struct device_node *np)
782{
783	int i, err = 0;
784	struct sirfsoc_gpio_chip *sgpio;
785	struct sirfsoc_gpio_bank *bank;
786	void __iomem *regs;
787	struct platform_device *pdev;
788	struct gpio_irq_chip *girq;
789
790	u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
791
792	pdev = of_find_device_by_node(np);
793	if (!pdev)
794		return -ENODEV;
795
796	sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
797	if (!sgpio) {
798		err = -ENOMEM;
799		goto out_put_device;
800	}
801	spin_lock_init(&sgpio->lock);
802
803	regs = of_iomap(np, 0);
804	if (!regs) {
805		err = -ENOMEM;
806		goto out_put_device;
807	}
808
809	sgpio->chip.gc.request = sirfsoc_gpio_request;
810	sgpio->chip.gc.free = sirfsoc_gpio_free;
811	sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
812	sgpio->chip.gc.get = sirfsoc_gpio_get_value;
813	sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
814	sgpio->chip.gc.set = sirfsoc_gpio_set_value;
815	sgpio->chip.gc.base = 0;
816	sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
817	sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
818	sgpio->chip.gc.of_node = np;
819	sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
820	sgpio->chip.gc.of_gpio_n_cells = 2;
821	sgpio->chip.gc.parent = &pdev->dev;
822	sgpio->chip.regs = regs;
823
824	girq = &sgpio->chip.gc.irq;
825	girq->chip = &sirfsoc_irq_chip;
826	girq->parent_handler = sirfsoc_gpio_handle_irq;
827	girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;
828	girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,
829				     sizeof(*girq->parents),
830				     GFP_KERNEL);
831	if (!girq->parents) {
832		err = -ENOMEM;
833		goto out_put_device;
834	}
835	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
836		bank = &sgpio->sgpio_bank[i];
837		spin_lock_init(&bank->lock);
838		bank->parent_irq = platform_get_irq(pdev, i);
839		if (bank->parent_irq < 0) {
840			err = bank->parent_irq;
841			goto out;
842		}
843		girq->parents[i] = bank->parent_irq;
844	}
845	girq->default_type = IRQ_TYPE_NONE;
846	girq->handler = handle_level_irq;
847
848	err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
849	if (err) {
850		dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
851			np, err);
852		goto out;
853	}
854
855	err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
856		0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
857	if (err) {
858		dev_err(&pdev->dev,
859			"could not add gpiochip pin range\n");
860		goto out_no_range;
861	}
862
863	if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
864		SIRFSOC_GPIO_NO_OF_BANKS))
865		sirfsoc_gpio_set_pullup(sgpio, pullups);
866
867	if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
868		SIRFSOC_GPIO_NO_OF_BANKS))
869		sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
870
871	return 0;
872
873out_no_range:
874	gpiochip_remove(&sgpio->chip.gc);
875out:
876	iounmap(regs);
877out_put_device:
878	put_device(&pdev->dev);
879	return err;
880}
881
882static int __init sirfsoc_gpio_init(void)
883{
884
885	struct device_node *np;
886
887	np = of_find_matching_node(NULL, pinmux_ids);
888
889	if (!np)
890		return -ENODEV;
891
892	return sirfsoc_gpio_probe(np);
893}
894subsys_initcall(sirfsoc_gpio_init);