1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A7790 processor support
   4 *
   5 * Copyright (C) 2013  Renesas Electronics Corporation
   6 * Copyright (C) 2013  Magnus Damm
   7 * Copyright (C) 2012  Renesas Solutions Corp.
   8 * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   9 */
  10
  11#include <linux/errno.h>
  12#include <linux/io.h>
  13#include <linux/kernel.h>
  14#include <linux/sys_soc.h>
  15
  16#include "core.h"
  17#include "sh_pfc.h"
  18
  19/*
  20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
  21 * which case they support both 3.3V and 1.8V signalling.
  22 */
  23#define CPU_ALL_GP(fn, sfx)						\
  24	PORT_GP_32(0, fn, sfx),						\
  25	PORT_GP_30(1, fn, sfx),						\
  26	PORT_GP_30(2, fn, sfx),						\
  27	PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),		\
  28	PORT_GP_32(4, fn, sfx),						\
  29	PORT_GP_32(5, fn, sfx)
  30
  31#define CPU_ALL_NOGP(fn)		\
  32	PIN_NOGP(IIC0_SDA, "AF15", fn),	\
  33	PIN_NOGP(IIC0_SCL, "AG15", fn),	\
  34	PIN_NOGP(IIC3_SDA, "AH15", fn),	\
  35	PIN_NOGP(IIC3_SCL, "AJ15", fn)
  36
  37enum {
  38	PINMUX_RESERVED = 0,
  39
  40	PINMUX_DATA_BEGIN,
  41	GP_ALL(DATA),
  42	PINMUX_DATA_END,
  43
  44	PINMUX_FUNCTION_BEGIN,
  45	GP_ALL(FN),
  46
  47	/* GPSR0 */
  48	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
  49	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
  50	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
  51	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
  52	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
  53	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
  54	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
  55	FN_IP3_14_12, FN_IP3_17_15,
  56
  57	/* GPSR1 */
  58	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
  59	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
  60	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
  61	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
  62	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
  63	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
  64	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
  65
  66	/* GPSR2 */
  67	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  68	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
  69	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
  70	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
  71	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
  72	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
  73	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
  74
  75	/* GPSR3 */
  76	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
  77	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
  78	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
  79	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
  80	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
  81	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
  82	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
  83
  84	/* GPSR4 */
  85	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
  86	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
  87	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
  88	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
  89	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
  90	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
  91	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
  92	FN_IP14_15_12, FN_IP14_18_16,
  93
  94	/* GPSR5 */
  95	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
  96	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
  97	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
  98	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
  99	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 100	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 101	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 102
 103	/* IPSR0 */
 104	FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 105	FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 106	FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 107	FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 108	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 109	FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 110	FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 111	FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 112	FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 113	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 114	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 115	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
 116	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 117	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 118
 119	/* IPSR1 */
 120	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 121	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 122	FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 123	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 124	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 125	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 126	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 127	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 128	FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 129	FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 130	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 131	FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 132	FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 133	FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 134	FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 135
 136	/* IPSR2 */
 137	FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 138	FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 139	FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 140	FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 141	FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 142	FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 143	FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
 144	FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 145	FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
 146	FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 147	FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 148
 149	/* IPSR3 */
 150	FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 151	FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 152	FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 153	FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 154	FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 155	FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 156	FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 157	FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 158	FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 159	FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 160	FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 161	FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 162	FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 163
 164	/* IPSR4 */
 165	FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 166	FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 167	FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 168	FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 169	FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 170	FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 171	FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 172	FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 173	FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 174	FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 175	FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 176	FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 177	FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 178	FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 179	FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 180
 181	/* IPSR5 */
 182	FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 183	FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 184	FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 185	FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 186	FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 187	FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 188	FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 189	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 190	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 191	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 192	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 193	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 194	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 195	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 196	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 197	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 198	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 199	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 200	FN_SSI_WS78_B,
 201
 202	/* IPSR6 */
 203	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 204	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 205	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 206	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 207	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 208	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 209	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 210	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 211	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 212	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 213	FN_I2C2_SCL_E, FN_ETH_RX_ER,
 214	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 215	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 216	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 217	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 218	FN_HRX0_E, FN_STP_ISSYNC_0_B,
 219	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 220	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 221	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 222	FN_ETH_REF_CLK, FN_HCTS0_N_E,
 223	FN_STP_IVCXO27_1_B, FN_HRX0_F,
 224
 225	/* IPSR7 */
 226	FN_ETH_MDIO, FN_HRTS0_N_E,
 227	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 228	FN_HTX0_F, FN_BPFCLK_G,
 229	FN_ETH_TX_EN, FN_SIM0_CLK_C,
 230	FN_HRTS0_N_F, FN_ETH_MAGIC,
 231	FN_SIM0_RST_C, FN_ETH_TXD0,
 232	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 233	FN_ETH_MDC, FN_STP_ISD_1_B,
 234	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 235	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 236	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 237	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 238	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 239	FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
 240	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 241	FN_ATACS00_N, FN_AVB_RXD1,
 242	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 243
 244	/* IPSR8 */
 245	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 246	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 247	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 248	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 249	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 250	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 251	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 252	FN_VI1_CLK, FN_AVB_RX_DV,
 253	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 254	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 255	FN_SCIFA1_RXD_D, FN_AVB_MDC,
 256	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 257	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 258	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 259	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 260	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 261	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 262	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 263
 264	/* IPSR9 */
 265	FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 266	FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 267	FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 268	FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 269	FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 270	FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 271	FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 272	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 273	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 274	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 275	FN_AVB_TX_EN, FN_SD1_CMD,
 276	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 277	FN_SD1_DAT0, FN_AVB_TX_CLK,
 278	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 279	FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 280	FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 281	FN_SD1_DAT3, FN_AVB_RXD0,
 282	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 283	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 284	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 285	FN_VI3_CLK_B,
 286
 287	/* IPSR10 */
 288	FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 289	FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 290	FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 291	FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 292	FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 293	FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 294	FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 295	FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 296	FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 297	FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 298	FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 299	FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 300	FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 301	FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 302	FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 303	FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 304	FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 305	FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 306	FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 307	FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 308	FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 309	FN_GLO_I0_B, FN_VI3_DATA6_B,
 310
 311	/* IPSR11 */
 312	FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 313	FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 314	FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 315	FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 316	FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 317	FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 318	FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 319	FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 320	FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 321	FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 322	FN_FMIN_E, FN_FMIN_F,
 323	FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 324	FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 325	FN_I2C2_SDA_B, FN_MLB_DAT,
 326	FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 327	FN_SSI_SCK0129, FN_CAN_CLK_B,
 328	FN_MOUT0,
 329
 330	/* IPSR12 */
 331	FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 332	FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 333	FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 334	FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 335	FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 336	FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 337	FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 338	FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 339	FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 340	FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 341	FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 342	FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 343	FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 344	FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 345	FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 346	FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 347	FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 348	FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 349	FN_CAN_DEBUGOUT4,
 350
 351	/* IPSR13 */
 352	FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 353	FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 354	FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 355	FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 356	FN_BPFCLK_F, FN_SSI_WS6,
 357	FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 358	FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 359	FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 360	FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 361	FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 362	FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 363	FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 364	FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 365	FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 366	FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 367	FN_BPFCLK_E, FN_SSI_SDATA7_B,
 368	FN_FMIN_G, FN_SSI_SDATA8,
 369	FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 370	FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 371	FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 372	FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 373	FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 374
 375	/* IPSR14 */
 376	FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 377	FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 378	FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 379	FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 380	FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 381	FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 382	FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 383	FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 384	FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 385	FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 386	FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 387	FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 388	FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 389	FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 390	FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 391	FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 392	FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 393	FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 394	FN_HRTS0_N_C,
 395
 396	/* IPSR15 */
 397	FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
 398	FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 399	FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 400	FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
 401	FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 402	FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 403	FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 404	FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 405	FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 406	FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 407	FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 408	FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 409	FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 410	FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 411	FN_DU2_DG6, FN_LCDOUT14,
 412
 413	/* IPSR16 */
 414	FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 415	FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 416	FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 417	FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 418	FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 419	FN_TCLK1_B,
 420
 421	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 422	FN_SEL_SCIF1_4,
 423	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 424	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 425	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 426	FN_SEL_SCIFB1_4,
 427	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 428	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 429	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 430	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 431	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 432	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 433	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 434	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 435	FN_SEL_VI3_0, FN_SEL_VI3_1,
 436	FN_SEL_VI2_0, FN_SEL_VI2_1,
 437	FN_SEL_VI1_0, FN_SEL_VI1_1,
 438	FN_SEL_VI0_0, FN_SEL_VI0_1,
 439	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 440	FN_SEL_LBS_0, FN_SEL_LBS_1,
 441	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 442	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 443	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 444
 445	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 446	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 447	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 448	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 449	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 450	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 451	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 452	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
 453	FN_SEL_ADI_0, FN_SEL_ADI_1,
 454	FN_SEL_SSP_0, FN_SEL_SSP_1,
 455	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 456	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 457	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 458	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 459	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 460	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 461	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 462
 463	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 464	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 465	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 466	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 467	FN_SEL_IIC2_4,
 468	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 469	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 470	FN_SEL_I2C2_4,
 471	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 472	PINMUX_FUNCTION_END,
 473
 474	PINMUX_MARK_BEGIN,
 475
 476	VI1_DATA7_VI1_B7_MARK,
 477
 478	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 479	USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 480	DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 481
 482	D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 483	D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 484	VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 485	VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 486	VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 487	SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 488	VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 489	SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 490	VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 491	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 492	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 493	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
 494	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 495	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 496
 497	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 498	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 499	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 500	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 501	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 502	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 503	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 504	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 505	D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 506	VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 507	SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 508	VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 509	D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 510	VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 511	A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 512
 513	A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 514	PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 515	TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 516	A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 517	SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 518	A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 519	VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
 520	A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 521	VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
 522	A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 523	VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 524
 525	A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 526	VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 527	A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 528	VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 529	A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 530	MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 531	VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 532	ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 533	ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 534	A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 535	AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 536	ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 537	VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 538
 539	A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 540	A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 541	VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 542	VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 543	VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 544	VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 545	VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 546	VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 547	CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 548	VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 549	VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 550	MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 551	HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 552	VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 553	VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 554
 555	EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 556	VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 557	EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 558	VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 559	INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 560	MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 561	VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 562	I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 563	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 564	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 565	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 566	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 567	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 568	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 569	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 570	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 571	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 572	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 573	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 574	SSI_WS78_B_MARK,
 575
 576	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 577	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 578	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 579	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 580	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 581	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 582	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 583	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 584	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 585	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 586	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 587	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 588	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 589	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 590	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 591	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 592	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 593	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 594	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 595	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 596	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 597
 598	ETH_MDIO_MARK, HRTS0_N_E_MARK,
 599	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 600	HTX0_F_MARK, BPFCLK_G_MARK,
 601	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 602	HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 603	SIM0_RST_C_MARK, ETH_TXD0_MARK,
 604	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 605	ETH_MDC_MARK, STP_ISD_1_B_MARK,
 606	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 607	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 608	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 609	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 610	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 611	PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
 612	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 613	ATACS00_N_MARK, AVB_RXD1_MARK,
 614	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 615
 616	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 617	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 618	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 619	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 620	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 621	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 622	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 623	VI1_CLK_MARK, AVB_RX_DV_MARK,
 624	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 625	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 626	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 627	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 628	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 629	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 630	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 631	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 632	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 633	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 634
 635	SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 636	SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 637	SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 638	SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 639	SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 640	GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 641	I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 642	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 643	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 644	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 645	AVB_TX_EN_MARK, SD1_CMD_MARK,
 646	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 647	SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 648	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 649	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 650	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 651	SD1_DAT3_MARK, AVB_RXD0_MARK,
 652	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 653	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 654	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 655	VI3_CLK_B_MARK,
 656
 657	SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 658	GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 659	SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 660	VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 661	VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 662	VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 663	TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 664	SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 665	VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 666	TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 667	SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 668	VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 669	TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 670	SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 671	VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 672	GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 673	MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 674	HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 675	VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 676	TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 677	VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 678	GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 679
 680	SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 681	GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 682	TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 683	SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 684	MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 685	SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 686	MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 687	SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 688	VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 689	MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 690	FMIN_E_MARK, FMIN_F_MARK,
 691	MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 692	MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 693	I2C2_SDA_B_MARK, MLB_DAT_MARK,
 694	SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 695	SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 696	MOUT0_MARK,
 697
 698	SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 699	SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 700	SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 701	SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 702	SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 703	MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 704	STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 705	CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 706	SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 707	SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 708	MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 709	SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 710	MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 711	SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 712	CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 713	IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 714	CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 715	IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 716	CAN_DEBUGOUT4_MARK,
 717
 718	SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 719	LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 720	SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 721	DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 722	BPFCLK_F_MARK, SSI_WS6_MARK,
 723	SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 724	LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 725	FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 726	CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 727	SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 728	CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 729	SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 730	LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 731	STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 732	TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 733	BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 734	FMIN_G_MARK, SSI_SDATA8_MARK,
 735	STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 736	CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 737	STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 738	SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 739	SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 740
 741	AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 742	DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 743	REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 744	MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 745	I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 746	DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 747	TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 748	HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 749	LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 750	SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 751	MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 752	SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 753	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 754	SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 755	LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 756	CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 757	SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 758	MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 759	HRTS0_N_C_MARK,
 760
 761	SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 762	LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 763	TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 764	SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 765	IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 766	DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 767	DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 768	LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 769	LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 770	LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 771	DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 772	SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 773	HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 774	DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 775	DU2_DG6_MARK, LCDOUT14_MARK,
 776
 777	MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 778	DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 779	MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 780	ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 781	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 782	TCLK1_B_MARK,
 783
 784	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
 785	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
 786	PINMUX_MARK_END,
 787};
 788
 789static const u16 pinmux_data[] = {
 790	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 791
 792	PINMUX_SINGLE(VI1_DATA7_VI1_B7),
 793	PINMUX_SINGLE(USB0_PWEN),
 794	PINMUX_SINGLE(USB0_OVC_VBUS),
 795	PINMUX_SINGLE(USB2_PWEN),
 796	PINMUX_SINGLE(USB2_OVC),
 797	PINMUX_SINGLE(AVS1),
 798	PINMUX_SINGLE(AVS2),
 799	PINMUX_SINGLE(DU_DOTCLKIN0),
 800	PINMUX_SINGLE(DU_DOTCLKIN2),
 801
 802	PINMUX_IPSR_GPSR(IP0_2_0, D0),
 803	PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 804	PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 805	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
 806	PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 807	PINMUX_IPSR_GPSR(IP0_5_3, D1),
 808	PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 809	PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 810	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
 811	PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 812	PINMUX_IPSR_GPSR(IP0_8_6, D2),
 813	PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 814	PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 815	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
 816	PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 817	PINMUX_IPSR_GPSR(IP0_11_9, D3),
 818	PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 819	PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 820	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
 821	PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 822	PINMUX_IPSR_GPSR(IP0_15_12, D4),
 823	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 824	PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 825	PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 826	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
 827	PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 828	PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
 829	PINMUX_IPSR_GPSR(IP0_19_16, D5),
 830	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 831	PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 832	PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 833	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
 834	PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 835	PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
 836	PINMUX_IPSR_GPSR(IP0_22_20, D6),
 837	PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 838	PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 839	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
 840	PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 841	PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 842	PINMUX_IPSR_GPSR(IP0_26_23, D7),
 843	PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
 844	PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 845	PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 846	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
 847	PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 848	PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 849	PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
 850	PINMUX_IPSR_GPSR(IP0_30_27, D8),
 851	PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 852	PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
 853	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
 854	PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 855	PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 856
 857	PINMUX_IPSR_GPSR(IP1_3_0, D9),
 858	PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 859	PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
 860	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
 861	PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 862	PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 863	PINMUX_IPSR_GPSR(IP1_7_4, D10),
 864	PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 865	PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
 866	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
 867	PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 868	PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 869	PINMUX_IPSR_GPSR(IP1_11_8, D11),
 870	PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 871	PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
 872	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
 873	PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 874	PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 875	PINMUX_IPSR_GPSR(IP1_14_12, D12),
 876	PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 877	PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
 878	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 879	PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 880	PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 881	PINMUX_IPSR_GPSR(IP1_17_15, D13),
 882	PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
 883	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 884	PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 885	PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 886	PINMUX_IPSR_GPSR(IP1_21_18, D14),
 887	PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 888	PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
 889	PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
 890	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 891	PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 892	PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 893	PINMUX_IPSR_GPSR(IP1_25_22, D15),
 894	PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 895	PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
 896	PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
 897	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 898	PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 899	PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 900	PINMUX_IPSR_GPSR(IP1_27_26, A0),
 901	PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
 902	PINMUX_IPSR_GPSR(IP1_29_28, A1),
 903	PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
 904
 905	PINMUX_IPSR_GPSR(IP2_2_0, A2),
 906	PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
 907	PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 908	PINMUX_IPSR_GPSR(IP2_5_3, A3),
 909	PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
 910	PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 911	PINMUX_IPSR_GPSR(IP2_8_6, A4),
 912	PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 913	PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
 914	PINMUX_IPSR_GPSR(IP2_11_9, A5),
 915	PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 916	PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
 917	PINMUX_IPSR_GPSR(IP2_14_12, A6),
 918	PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 919	PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
 920	PINMUX_IPSR_GPSR(IP2_17_15, A7),
 921	PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 922	PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
 923	PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
 924	PINMUX_IPSR_GPSR(IP2_21_18, A8),
 925	PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 926	PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 927	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
 928	PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 929	PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 930	PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
 931	PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 932	PINMUX_IPSR_GPSR(IP2_25_22, A9),
 933	PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 934	PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 935	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
 936	PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 937	PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 938	PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
 939	PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 940	PINMUX_IPSR_GPSR(IP2_28_26, A10),
 941	PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 942	PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
 943	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
 944	PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
 945	PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 946
 947	PINMUX_IPSR_GPSR(IP3_3_0, A11),
 948	PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
 949	PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
 950	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
 951	PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
 952	PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
 953	PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
 954	PINMUX_IPSR_GPSR(IP3_7_4, A12),
 955	PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
 956	PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
 957	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
 958	PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
 959	PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
 960	PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
 961	PINMUX_IPSR_GPSR(IP3_11_8, A13),
 962	PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
 963	PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
 964	PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
 965	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
 966	PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
 967	PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
 968	PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
 969	PINMUX_IPSR_GPSR(IP3_14_12, A14),
 970	PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
 971	PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
 972	PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
 973	PINMUX_IPSR_GPSR(IP3_17_15, A15),
 974	PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
 975	PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
 976	PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
 977	PINMUX_IPSR_GPSR(IP3_19_18, A16),
 978	PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
 979	PINMUX_IPSR_GPSR(IP3_22_20, A17),
 980	PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
 981	PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
 982	PINMUX_IPSR_GPSR(IP3_25_23, A18),
 983	PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
 984	PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
 985	PINMUX_IPSR_GPSR(IP3_28_26, A19),
 986	PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
 987	PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
 988	PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
 989	PINMUX_IPSR_GPSR(IP3_31_29, A20),
 990	PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
 991	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
 992	PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
 993	PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
 994
 995	PINMUX_IPSR_GPSR(IP4_2_0, A21),
 996	PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
 997	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
 998	PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
 999	PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1000	PINMUX_IPSR_GPSR(IP4_5_3, A22),
1001	PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1002	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1003	PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004	PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1005	PINMUX_IPSR_GPSR(IP4_8_6, A23),
1006	PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1007	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1008	PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009	PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1010	PINMUX_IPSR_GPSR(IP4_11_9, A24),
1011	PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1012	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1013	PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015	PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016	PINMUX_IPSR_GPSR(IP4_14_12, A25),
1017	PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1018	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1019	PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021	PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022	PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1023	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1024	PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025	PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1026	PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027	PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1028	PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1029	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1030	PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032	PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033	PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1034	PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1036	PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037	PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1038	PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039	PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040	PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1041	PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1042	PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044	PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045	PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1046	PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1047	PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1048	PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049	PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1050	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1051	PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052	PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1053
1054	PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1055	PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1056	PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1057	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1058	PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059	PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1060	PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1061	PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062	PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1063	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1064	PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1065	PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066	PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1067	PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1068	PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1069	PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070	PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071	PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1072	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1073	PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074	PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1075	PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1076	PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1077	PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1078	PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1079	PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1080	PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081	PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082	PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1083	PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1084	PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1085	PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086	PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087	PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1088	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1089	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1091	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092	PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
1093	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1094	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1095	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097	PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098	PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099	PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1100	PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1101	PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1103	PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104	PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1105	PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1107	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1108	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1109	PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
1110	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113	PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114	PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1115	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116	PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117	PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1118	PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119	PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1120
1121	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1122	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1123	PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
1124	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127	PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128	PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1129	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130	PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1134	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1135	PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
1136	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1139	PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140	PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1143	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1144	PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
1145	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148	PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1149	PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150	PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151	PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152	PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153	PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154	PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1155	PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156	PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157	PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158	PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159	PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160	PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1161	PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162	PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163	PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164	PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165	PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166	PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1167	PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168	PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169	PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170	PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171	PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172	PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173	PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1174	PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175	PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176	PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177	PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178	PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1179	PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180	PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181	PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1182
1183	PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1184	PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185	PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186	PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187	PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1188	PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189	PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190	PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1191	PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192	PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193	PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1194	PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195	PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1196	PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197	PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198	PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199	PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1200	PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201	PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202	PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203	PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1204	PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205	PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206	PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207	PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208	PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1209	PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210	PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211	PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212	PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213	PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1214	PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1215	PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1216	PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217	PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1218	PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1219	PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1220	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1221	PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1222	PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223	PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1224	PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1225	PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226	PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1227	PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1228
1229	PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230	PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1231	PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1232	PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233	PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1234	PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1235	PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236	PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1237	PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1238	PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239	PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1240	PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1241	PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242	PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1243	PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1244	PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245	PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1246	PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247	PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1248	PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249	PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1250	PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251	PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252	PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1253	PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254	PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255	PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1256	PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257	PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258	PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1259	PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260	PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261	PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1262	PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263	PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264	PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1265	PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266	PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1267	PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268	PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1269	PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1270	PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271	PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1272	PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273	PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1274
1275	PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1276	PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277	PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278	PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1279	PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280	PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281	PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1282	PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283	PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284	PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1285	PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286	PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287	PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1288	PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1289	PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290	PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1291	PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292	PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293	PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294	PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295	PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296	PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1297	PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1298	PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299	PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1300	PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301	PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302	PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303	PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304	PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305	PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1306	PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1307	PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1308	PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1309	PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310	PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1311	PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1312	PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313	PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1314	PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1315	PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316	PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1317	PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1318	PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319	PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1320	PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1321	PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322	PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1323	PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1324	PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325	PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1326	PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1327	PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328	PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329	PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330	PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331	PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1332
1333	PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1334	PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1335	PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336	PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1337	PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338	PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339	PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340	PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341	PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342	PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1343	PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1344	PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345	PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346	PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347	PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348	PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349	PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1350	PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1351	PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1352	PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353	PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354	PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355	PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356	PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357	PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358	PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1359	PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1360	PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1361	PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362	PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363	PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364	PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365	PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366	PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367	PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1368	PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1369	PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1370	PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371	PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372	PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373	PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374	PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375	PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376	PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1377	PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1378	PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379	PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380	PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381	PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382	PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383	PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384	PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1385	PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1386	PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387	PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388	PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389	PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390	PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391	PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392	PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1393	PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1394	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395	PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1396	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1397	PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398	PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399	PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400	PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401	PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1402
1403	PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1404	PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1405	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406	PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1407	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1408	PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409	PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410	PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411	PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412	PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413	PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1414	PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1415	PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1416	PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1417	PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1418	PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1419	PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1420	PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1421	PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1422	PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1423	PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1424	PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1425	PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1426	PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1427	PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1428	PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1429	PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1430	PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1431	PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1432	PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433	PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1434	PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435	PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436	PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1437	PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1438	PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439	PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1441	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1442	PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1443	PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1444	PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445	PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446	PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1447	PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448	PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449	PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450	PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451	PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1452	PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453	PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454	PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455	PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1456	PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457	PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1458
1459	PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1460	PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461	PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1462	PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1463	PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464	PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1465	PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1466	PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467	PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1468	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1469	PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470	PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1471	PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1472	PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1473	PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1474	PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475	PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476	PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477	PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1478	PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479	PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480	PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1481	PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1482	PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1483	PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484	PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485	PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486	PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1487	PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1488	PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489	PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490	PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491	PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492	PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1493	PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1494	PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495	PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496	PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497	PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498	PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1499	PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1500	PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501	PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502	PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1503	PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504	PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505	PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1506	PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507	PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1508	PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1509	PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510	PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511	PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1512	PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513	PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1514	PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1515
1516	PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517	PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518	PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1519	PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1520	PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1521	PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1522	PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523	PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525	PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1526	PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1527	PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1528	PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529	PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530	PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531	PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532	PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1533	PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1534	PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1535	PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536	PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1537	PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1538	PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1539	PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1540	PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541	PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542	PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1543	PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544	PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1545	PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1546	PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1547	PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548	PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549	PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550	PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1551	PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1552	PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1553	PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1554	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555	PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556	PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557	PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1558	PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1559	PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1560	PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1561	PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562	PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563	PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1564	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565	PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566	PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567	PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568	PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1569	PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570	PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1571	PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572	PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573	PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1574	PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575	PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1576	PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1577	PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578	PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1579
1580	PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1581	PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583	PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1584	PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585	PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1586	PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1587	PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588	PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589	PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1590	PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1591	PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1592	PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1593	PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594	PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595	PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596	PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597	PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1598	PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1599	PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1600	PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601	PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602	PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1603	PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1604	PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1605	PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606	PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607	PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1608	PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609	PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1610	PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1611	PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1612	PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613	PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614	PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615	PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616	PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1617	PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1618	PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1619	PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1620	PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1621	PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622	PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1623	PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1624	PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625	PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1626	PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627	PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1628	PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1629	PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1630	PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1631	PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632	PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1633	PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1634	PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635	PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1636	PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1637	PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638	PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639	PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1640	PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641	PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1642	PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1643	PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1644
1645	PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646	PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1647	PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1648	PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649	PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1650	PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1651	PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652	PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653	PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1654	PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1655	PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1656	PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1657	PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658	PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659	PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660	PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1661	PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1662	PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1663	PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1664	PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665	PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666	PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1667	PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668	PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1669	PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1670	PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671	PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672	PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1673	PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1674	PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675	PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1676	PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1677	PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678	PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1679	PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1680	PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1681	PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682	PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1683	PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1684	PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1685	PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686	PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687	PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1688	PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1689	PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1690	PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1691	PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692	PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1693	PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1694	PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1695	PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1696	PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697	PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698	PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1699	PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1700	PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1701	PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702	PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1703	PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1704	PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1705
1706	PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707	PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1708	PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1709	PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1710	PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1711	PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712	PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713	PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714	PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715	PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1716	PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1717	PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1718	PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1719	PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720	PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1721	PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1722	PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1723	PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1724
1725	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1726	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1727	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1728	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1729
1730	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1731	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1732	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1733	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1734};
1735
1736/*
1737 * Pins not associated with a GPIO port.
1738 */
1739enum {
1740	GP_ASSIGN_LAST(),
1741	NOGP_ALL(),
1742};
1743
1744static const struct sh_pfc_pin pinmux_pins[] = {
1745	PINMUX_GPIO_GP_ALL(),
1746	PINMUX_NOGP_ALL(),
1747};
1748
1749/* - AUDIO CLOCK ------------------------------------------------------------ */
1750static const unsigned int audio_clk_a_pins[] = {
1751	/* CLK A */
1752	RCAR_GP_PIN(4, 25),
1753};
1754static const unsigned int audio_clk_a_mux[] = {
1755	AUDIO_CLKA_MARK,
1756};
1757static const unsigned int audio_clk_b_pins[] = {
1758	/* CLK B */
1759	RCAR_GP_PIN(4, 26),
1760};
1761static const unsigned int audio_clk_b_mux[] = {
1762	AUDIO_CLKB_MARK,
1763};
1764static const unsigned int audio_clk_c_pins[] = {
1765	/* CLK C */
1766	RCAR_GP_PIN(5, 27),
1767};
1768static const unsigned int audio_clk_c_mux[] = {
1769	AUDIO_CLKC_MARK,
1770};
1771static const unsigned int audio_clkout_pins[] = {
1772	/* CLK OUT */
1773	RCAR_GP_PIN(5, 16),
1774};
1775static const unsigned int audio_clkout_mux[] = {
1776	AUDIO_CLKOUT_MARK,
1777};
1778static const unsigned int audio_clkout_b_pins[] = {
1779	/* CLK OUT B */
1780	RCAR_GP_PIN(0, 23),
1781};
1782static const unsigned int audio_clkout_b_mux[] = {
1783	AUDIO_CLKOUT_B_MARK,
1784};
1785static const unsigned int audio_clkout_c_pins[] = {
1786	/* CLK OUT C */
1787	RCAR_GP_PIN(5, 27),
1788};
1789static const unsigned int audio_clkout_c_mux[] = {
1790	AUDIO_CLKOUT_C_MARK,
1791};
1792static const unsigned int audio_clkout_d_pins[] = {
1793	/* CLK OUT D */
1794	RCAR_GP_PIN(5, 20),
1795};
1796static const unsigned int audio_clkout_d_mux[] = {
1797	AUDIO_CLKOUT_D_MARK,
1798};
1799/* - AVB -------------------------------------------------------------------- */
1800static const unsigned int avb_link_pins[] = {
1801	RCAR_GP_PIN(3, 11),
1802};
1803static const unsigned int avb_link_mux[] = {
1804	AVB_LINK_MARK,
1805};
1806static const unsigned int avb_magic_pins[] = {
1807	RCAR_GP_PIN(2, 14),
1808};
1809static const unsigned int avb_magic_mux[] = {
1810	AVB_MAGIC_MARK,
1811};
1812static const unsigned int avb_phy_int_pins[] = {
1813	RCAR_GP_PIN(2, 15),
1814};
1815static const unsigned int avb_phy_int_mux[] = {
1816	AVB_PHY_INT_MARK,
1817};
1818static const unsigned int avb_mdio_pins[] = {
1819	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1820};
1821static const unsigned int avb_mdio_mux[] = {
1822	AVB_MDC_MARK, AVB_MDIO_MARK,
1823};
1824static const unsigned int avb_mii_pins[] = {
1825	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1826	RCAR_GP_PIN(0, 11),
1827
1828	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1829	RCAR_GP_PIN(2, 2),
1830
1831	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1832	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1833	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1834};
1835static const unsigned int avb_mii_mux[] = {
1836	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1837	AVB_TXD3_MARK,
1838
1839	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1840	AVB_RXD3_MARK,
1841
1842	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1843	AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1844	AVB_TX_CLK_MARK, AVB_COL_MARK,
1845};
1846static const unsigned int avb_gmii_pins[] = {
1847	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1849	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1850
1851	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1852	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1853	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1854
1855	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1856	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1857	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1858	RCAR_GP_PIN(3, 12),
1859};
1860static const unsigned int avb_gmii_mux[] = {
1861	AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1862	AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1863	AVB_TXD6_MARK, AVB_TXD7_MARK,
1864
1865	AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1866	AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1867	AVB_RXD6_MARK, AVB_RXD7_MARK,
1868
1869	AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1870	AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1871	AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1872	AVB_COL_MARK,
1873};
1874/* - DU RGB ----------------------------------------------------------------- */
1875static const unsigned int du_rgb666_pins[] = {
1876	/* R[7:2], G[7:2], B[7:2] */
1877	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1878	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1879	RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1880	RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1881	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1882	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1883};
1884static const unsigned int du_rgb666_mux[] = {
1885	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1886	DU2_DR3_MARK, DU2_DR2_MARK,
1887	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1888	DU2_DG3_MARK, DU2_DG2_MARK,
1889	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1890	DU2_DB3_MARK, DU2_DB2_MARK,
1891};
1892static const unsigned int du_rgb888_pins[] = {
1893	/* R[7:0], G[7:0], B[7:0] */
1894	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1895	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1896	RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1897	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1898	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1899	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1900	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1901	RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1902};
1903static const unsigned int du_rgb888_mux[] = {
1904	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1905	DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1906	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1907	DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1908	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1909	DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1910};
1911static const unsigned int du_clk_out_0_pins[] = {
1912	/* CLKOUT */
1913	RCAR_GP_PIN(5, 2),
1914};
1915static const unsigned int du_clk_out_0_mux[] = {
1916	DU0_DOTCLKOUT_MARK
1917};
1918static const unsigned int du_clk_out_1_pins[] = {
1919	/* CLKOUT */
1920	RCAR_GP_PIN(5, 3),
1921};
1922static const unsigned int du_clk_out_1_mux[] = {
1923	DU1_DOTCLKOUT_MARK
1924};
1925static const unsigned int du_sync_0_pins[] = {
1926	/* VSYNC, HSYNC, DISP */
1927	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1928};
1929static const unsigned int du_sync_0_mux[] = {
1930	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1931	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1932};
1933static const unsigned int du_sync_1_pins[] = {
1934	/* VSYNC, HSYNC, DISP */
1935	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1936};
1937static const unsigned int du_sync_1_mux[] = {
1938	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1939	DU2_DISP_MARK
1940};
1941static const unsigned int du_cde_pins[] = {
1942	/* CDE */
1943	RCAR_GP_PIN(5, 17),
1944};
1945static const unsigned int du_cde_mux[] = {
1946	DU2_CDE_MARK,
1947};
1948/* - DU0 -------------------------------------------------------------------- */
1949static const unsigned int du0_clk_in_pins[] = {
1950	/* CLKIN */
1951	RCAR_GP_PIN(5, 26),
1952};
1953static const unsigned int du0_clk_in_mux[] = {
1954	DU_DOTCLKIN0_MARK
1955};
1956/* - DU1 -------------------------------------------------------------------- */
1957static const unsigned int du1_clk_in_pins[] = {
1958	/* CLKIN */
1959	RCAR_GP_PIN(5, 27),
1960};
1961static const unsigned int du1_clk_in_mux[] = {
1962	DU_DOTCLKIN1_MARK,
1963};
1964/* - DU2 -------------------------------------------------------------------- */
1965static const unsigned int du2_clk_in_pins[] = {
1966	/* CLKIN */
1967	RCAR_GP_PIN(5, 28),
1968};
1969static const unsigned int du2_clk_in_mux[] = {
1970	DU_DOTCLKIN2_MARK,
1971};
1972/* - ETH -------------------------------------------------------------------- */
1973static const unsigned int eth_link_pins[] = {
1974	/* LINK */
1975	RCAR_GP_PIN(2, 22),
1976};
1977static const unsigned int eth_link_mux[] = {
1978	ETH_LINK_MARK,
1979};
1980static const unsigned int eth_magic_pins[] = {
1981	/* MAGIC */
1982	RCAR_GP_PIN(2, 27),
1983};
1984static const unsigned int eth_magic_mux[] = {
1985	ETH_MAGIC_MARK,
1986};
1987static const unsigned int eth_mdio_pins[] = {
1988	/* MDC, MDIO */
1989	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1990};
1991static const unsigned int eth_mdio_mux[] = {
1992	ETH_MDC_MARK, ETH_MDIO_MARK,
1993};
1994static const unsigned int eth_rmii_pins[] = {
1995	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1996	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1997	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1998	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1999};
2000static const unsigned int eth_rmii_mux[] = {
2001	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2002	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2003};
2004/* - HSCIF0 ----------------------------------------------------------------- */
2005static const unsigned int hscif0_data_pins[] = {
2006	/* RX, TX */
2007	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2008};
2009static const unsigned int hscif0_data_mux[] = {
2010	HRX0_MARK, HTX0_MARK,
2011};
2012static const unsigned int hscif0_clk_pins[] = {
2013	/* SCK */
2014	RCAR_GP_PIN(5, 7),
2015};
2016static const unsigned int hscif0_clk_mux[] = {
2017	HSCK0_MARK,
2018};
2019static const unsigned int hscif0_ctrl_pins[] = {
2020	/* RTS, CTS */
2021	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2022};
2023static const unsigned int hscif0_ctrl_mux[] = {
2024	HRTS0_N_MARK, HCTS0_N_MARK,
2025};
2026static const unsigned int hscif0_data_b_pins[] = {
2027	/* RX, TX */
2028	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2029};
2030static const unsigned int hscif0_data_b_mux[] = {
2031	HRX0_B_MARK, HTX0_B_MARK,
2032};
2033static const unsigned int hscif0_ctrl_b_pins[] = {
2034	/* RTS, CTS */
2035	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2036};
2037static const unsigned int hscif0_ctrl_b_mux[] = {
2038	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2039};
2040static const unsigned int hscif0_data_c_pins[] = {
2041	/* RX, TX */
2042	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2043};
2044static const unsigned int hscif0_data_c_mux[] = {
2045	HRX0_C_MARK, HTX0_C_MARK,
2046};
2047static const unsigned int hscif0_ctrl_c_pins[] = {
2048	/* RTS, CTS */
2049	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2050};
2051static const unsigned int hscif0_ctrl_c_mux[] = {
2052	HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2053};
2054static const unsigned int hscif0_data_d_pins[] = {
2055	/* RX, TX */
2056	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2057};
2058static const unsigned int hscif0_data_d_mux[] = {
2059	HRX0_D_MARK, HTX0_D_MARK,
2060};
2061static const unsigned int hscif0_ctrl_d_pins[] = {
2062	/* RTS, CTS */
2063	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2064};
2065static const unsigned int hscif0_ctrl_d_mux[] = {
2066	HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2067};
2068static const unsigned int hscif0_data_e_pins[] = {
2069	/* RX, TX */
2070	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2071};
2072static const unsigned int hscif0_data_e_mux[] = {
2073	HRX0_E_MARK, HTX0_E_MARK,
2074};
2075static const unsigned int hscif0_ctrl_e_pins[] = {
2076	/* RTS, CTS */
2077	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2078};
2079static const unsigned int hscif0_ctrl_e_mux[] = {
2080	HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2081};
2082static const unsigned int hscif0_data_f_pins[] = {
2083	/* RX, TX */
2084	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2085};
2086static const unsigned int hscif0_data_f_mux[] = {
2087	HRX0_F_MARK, HTX0_F_MARK,
2088};
2089static const unsigned int hscif0_ctrl_f_pins[] = {
2090	/* RTS, CTS */
2091	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2092};
2093static const unsigned int hscif0_ctrl_f_mux[] = {
2094	HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2095};
2096/* - HSCIF1 ----------------------------------------------------------------- */
2097static const unsigned int hscif1_data_pins[] = {
2098	/* RX, TX */
2099	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2100};
2101static const unsigned int hscif1_data_mux[] = {
2102	HRX1_MARK, HTX1_MARK,
2103};
2104static const unsigned int hscif1_clk_pins[] = {
2105	/* SCK */
2106	RCAR_GP_PIN(4, 27),
2107};
2108static const unsigned int hscif1_clk_mux[] = {
2109	HSCK1_MARK,
2110};
2111static const unsigned int hscif1_ctrl_pins[] = {
2112	/* RTS, CTS */
2113	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2114};
2115static const unsigned int hscif1_ctrl_mux[] = {
2116	HRTS1_N_MARK, HCTS1_N_MARK,
2117};
2118static const unsigned int hscif1_data_b_pins[] = {
2119	/* RX, TX */
2120	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2121};
2122static const unsigned int hscif1_data_b_mux[] = {
2123	HRX1_B_MARK, HTX1_B_MARK,
2124};
2125static const unsigned int hscif1_clk_b_pins[] = {
2126	/* SCK */
2127	RCAR_GP_PIN(1, 28),
2128};
2129static const unsigned int hscif1_clk_b_mux[] = {
2130	HSCK1_B_MARK,
2131};
2132static const unsigned int hscif1_ctrl_b_pins[] = {
2133	/* RTS, CTS */
2134	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2135};
2136static const unsigned int hscif1_ctrl_b_mux[] = {
2137	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2138};
2139/* - I2C0 ------------------------------------------------------------------- */
2140static const unsigned int i2c0_pins[] = {
2141	/* SCL, SDA */
2142	PIN_IIC0_SCL, PIN_IIC0_SDA,
2143};
2144static const unsigned int i2c0_mux[] = {
2145	I2C0_SCL_MARK, I2C0_SDA_MARK,
2146};
2147/* - I2C1 ------------------------------------------------------------------- */
2148static const unsigned int i2c1_pins[] = {
2149	/* SCL, SDA */
2150	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2151};
2152static const unsigned int i2c1_mux[] = {
2153	I2C1_SCL_MARK, I2C1_SDA_MARK,
2154};
2155static const unsigned int i2c1_b_pins[] = {
2156	/* SCL, SDA */
2157	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2158};
2159static const unsigned int i2c1_b_mux[] = {
2160	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2161};
2162static const unsigned int i2c1_c_pins[] = {
2163	/* SCL, SDA */
2164	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2165};
2166static const unsigned int i2c1_c_mux[] = {
2167	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2168};
2169/* - I2C2 ------------------------------------------------------------------- */
2170static const unsigned int i2c2_pins[] = {
2171	/* SCL, SDA */
2172	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2173};
2174static const unsigned int i2c2_mux[] = {
2175	I2C2_SCL_MARK, I2C2_SDA_MARK,
2176};
2177static const unsigned int i2c2_b_pins[] = {
2178	/* SCL, SDA */
2179	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2180};
2181static const unsigned int i2c2_b_mux[] = {
2182	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2183};
2184static const unsigned int i2c2_c_pins[] = {
2185	/* SCL, SDA */
2186	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2187};
2188static const unsigned int i2c2_c_mux[] = {
2189	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2190};
2191static const unsigned int i2c2_d_pins[] = {
2192	/* SCL, SDA */
2193	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2194};
2195static const unsigned int i2c2_d_mux[] = {
2196	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2197};
2198static const unsigned int i2c2_e_pins[] = {
2199	/* SCL, SDA */
2200	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2201};
2202static const unsigned int i2c2_e_mux[] = {
2203	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2204};
2205/* - I2C3 ------------------------------------------------------------------- */
2206static const unsigned int i2c3_pins[] = {
2207	/* SCL, SDA */
2208	PIN_IIC3_SCL, PIN_IIC3_SDA,
2209};
2210static const unsigned int i2c3_mux[] = {
2211	I2C3_SCL_MARK, I2C3_SDA_MARK,
2212};
2213/* - IIC0 (I2C4) ------------------------------------------------------------ */
2214static const unsigned int iic0_pins[] = {
2215	/* SCL, SDA */
2216	PIN_IIC0_SCL, PIN_IIC0_SDA,
2217};
2218static const unsigned int iic0_mux[] = {
2219	IIC0_SCL_MARK, IIC0_SDA_MARK,
2220};
2221/* - IIC1 (I2C5) ------------------------------------------------------------ */
2222static const unsigned int iic1_pins[] = {
2223	/* SCL, SDA */
2224	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2225};
2226static const unsigned int iic1_mux[] = {
2227	IIC1_SCL_MARK, IIC1_SDA_MARK,
2228};
2229static const unsigned int iic1_b_pins[] = {
2230	/* SCL, SDA */
2231	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2232};
2233static const unsigned int iic1_b_mux[] = {
2234	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2235};
2236static const unsigned int iic1_c_pins[] = {
2237	/* SCL, SDA */
2238	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2239};
2240static const unsigned int iic1_c_mux[] = {
2241	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2242};
2243/* - IIC2 (I2C6) ------------------------------------------------------------ */
2244static const unsigned int iic2_pins[] = {
2245	/* SCL, SDA */
2246	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2247};
2248static const unsigned int iic2_mux[] = {
2249	IIC2_SCL_MARK, IIC2_SDA_MARK,
2250};
2251static const unsigned int iic2_b_pins[] = {
2252	/* SCL, SDA */
2253	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2254};
2255static const unsigned int iic2_b_mux[] = {
2256	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2257};
2258static const unsigned int iic2_c_pins[] = {
2259	/* SCL, SDA */
2260	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2261};
2262static const unsigned int iic2_c_mux[] = {
2263	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2264};
2265static const unsigned int iic2_d_pins[] = {
2266	/* SCL, SDA */
2267	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2268};
2269static const unsigned int iic2_d_mux[] = {
2270	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2271};
2272static const unsigned int iic2_e_pins[] = {
2273	/* SCL, SDA */
2274	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2275};
2276static const unsigned int iic2_e_mux[] = {
2277	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2278};
2279/* - IIC3 (I2C7) ------------------------------------------------------------ */
2280static const unsigned int iic3_pins[] = {
2281	/* SCL, SDA */
2282	PIN_IIC3_SCL, PIN_IIC3_SDA,
2283};
2284static const unsigned int iic3_mux[] = {
2285	IIC3_SCL_MARK, IIC3_SDA_MARK,
2286};
2287/* - INTC ------------------------------------------------------------------- */
2288static const unsigned int intc_irq0_pins[] = {
2289	/* IRQ */
2290	RCAR_GP_PIN(1, 25),
2291};
2292static const unsigned int intc_irq0_mux[] = {
2293	IRQ0_MARK,
2294};
2295static const unsigned int intc_irq1_pins[] = {
2296	/* IRQ */
2297	RCAR_GP_PIN(1, 27),
2298};
2299static const unsigned int intc_irq1_mux[] = {
2300	IRQ1_MARK,
2301};
2302static const unsigned int intc_irq2_pins[] = {
2303	/* IRQ */
2304	RCAR_GP_PIN(1, 29),
2305};
2306static const unsigned int intc_irq2_mux[] = {
2307	IRQ2_MARK,
2308};
2309static const unsigned int intc_irq3_pins[] = {
2310	/* IRQ */
2311	RCAR_GP_PIN(1, 23),
2312};
2313static const unsigned int intc_irq3_mux[] = {
2314	IRQ3_MARK,
2315};
2316/* - MLB+ ------------------------------------------------------------------- */
2317static const unsigned int mlb_3pin_pins[] = {
2318	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2319};
2320static const unsigned int mlb_3pin_mux[] = {
2321	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2322};
2323/* - MMCIF0 ----------------------------------------------------------------- */
2324static const unsigned int mmc0_data1_pins[] = {
2325	/* D[0] */
2326	RCAR_GP_PIN(3, 18),
2327};
2328static const unsigned int mmc0_data1_mux[] = {
2329	MMC0_D0_MARK,
2330};
2331static const unsigned int mmc0_data4_pins[] = {
2332	/* D[0:3] */
2333	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2334	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2335};
2336static const unsigned int mmc0_data4_mux[] = {
2337	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2338};
2339static const unsigned int mmc0_data8_pins[] = {
2340	/* D[0:7] */
2341	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2342	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2343	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2344	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2345};
2346static const unsigned int mmc0_data8_mux[] = {
2347	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2348	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2349};
2350static const unsigned int mmc0_ctrl_pins[] = {
2351	/* CLK, CMD */
2352	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2353};
2354static const unsigned int mmc0_ctrl_mux[] = {
2355	MMC0_CLK_MARK, MMC0_CMD_MARK,
2356};
2357/* - MMCIF1 ----------------------------------------------------------------- */
2358static const unsigned int mmc1_data1_pins[] = {
2359	/* D[0] */
2360	RCAR_GP_PIN(3, 26),
2361};
2362static const unsigned int mmc1_data1_mux[] = {
2363	MMC1_D0_MARK,
2364};
2365static const unsigned int mmc1_data4_pins[] = {
2366	/* D[0:3] */
2367	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2368	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2369};
2370static const unsigned int mmc1_data4_mux[] = {
2371	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2372};
2373static const unsigned int mmc1_data8_pins[] = {
2374	/* D[0:7] */
2375	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2376	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2377	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2378	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2379};
2380static const unsigned int mmc1_data8_mux[] = {
2381	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2382	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2383};
2384static const unsigned int mmc1_ctrl_pins[] = {
2385	/* CLK, CMD */
2386	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2387};
2388static const unsigned int mmc1_ctrl_mux[] = {
2389	MMC1_CLK_MARK, MMC1_CMD_MARK,
2390};
2391/* - MSIOF0 ----------------------------------------------------------------- */
2392static const unsigned int msiof0_clk_pins[] = {
2393	/* SCK */
2394	RCAR_GP_PIN(5, 12),
2395};
2396static const unsigned int msiof0_clk_mux[] = {
2397	MSIOF0_SCK_MARK,
2398};
2399static const unsigned int msiof0_sync_pins[] = {
2400	/* SYNC */
2401	RCAR_GP_PIN(5, 13),
2402};
2403static const unsigned int msiof0_sync_mux[] = {
2404	MSIOF0_SYNC_MARK,
2405};
2406static const unsigned int msiof0_ss1_pins[] = {
2407	/* SS1 */
2408	RCAR_GP_PIN(5, 14),
2409};
2410static const unsigned int msiof0_ss1_mux[] = {
2411	MSIOF0_SS1_MARK,
2412};
2413static const unsigned int msiof0_ss2_pins[] = {
2414	/* SS2 */
2415	RCAR_GP_PIN(5, 16),
2416};
2417static const unsigned int msiof0_ss2_mux[] = {
2418	MSIOF0_SS2_MARK,
2419};
2420static const unsigned int msiof0_rx_pins[] = {
2421	/* RXD */
2422	RCAR_GP_PIN(5, 17),
2423};
2424static const unsigned int msiof0_rx_mux[] = {
2425	MSIOF0_RXD_MARK,
2426};
2427static const unsigned int msiof0_tx_pins[] = {
2428	/* TXD */
2429	RCAR_GP_PIN(5, 15),
2430};
2431static const unsigned int msiof0_tx_mux[] = {
2432	MSIOF0_TXD_MARK,
2433};
2434
2435static const unsigned int msiof0_clk_b_pins[] = {
2436	/* SCK */
2437	RCAR_GP_PIN(1, 23),
2438};
2439static const unsigned int msiof0_clk_b_mux[] = {
2440	MSIOF0_SCK_B_MARK,
2441};
2442static const unsigned int msiof0_ss1_b_pins[] = {
2443	/* SS1 */
2444	RCAR_GP_PIN(1, 12),
2445};
2446static const unsigned int msiof0_ss1_b_mux[] = {
2447	MSIOF0_SS1_B_MARK,
2448};
2449static const unsigned int msiof0_ss2_b_pins[] = {
2450	/* SS2 */
2451	RCAR_GP_PIN(1, 10),
2452};
2453static const unsigned int msiof0_ss2_b_mux[] = {
2454	MSIOF0_SS2_B_MARK,
2455};
2456static const unsigned int msiof0_rx_b_pins[] = {
2457	/* RXD */
2458	RCAR_GP_PIN(1, 29),
2459};
2460static const unsigned int msiof0_rx_b_mux[] = {
2461	MSIOF0_RXD_B_MARK,
2462};
2463static const unsigned int msiof0_tx_b_pins[] = {
2464	/* TXD */
2465	RCAR_GP_PIN(1, 28),
2466};
2467static const unsigned int msiof0_tx_b_mux[] = {
2468	MSIOF0_TXD_B_MARK,
2469};
2470/* - MSIOF1 ----------------------------------------------------------------- */
2471static const unsigned int msiof1_clk_pins[] = {
2472	/* SCK */
2473	RCAR_GP_PIN(4, 8),
2474};
2475static const unsigned int msiof1_clk_mux[] = {
2476	MSIOF1_SCK_MARK,
2477};
2478static const unsigned int msiof1_sync_pins[] = {
2479	/* SYNC */
2480	RCAR_GP_PIN(4, 9),
2481};
2482static const unsigned int msiof1_sync_mux[] = {
2483	MSIOF1_SYNC_MARK,
2484};
2485static const unsigned int msiof1_ss1_pins[] = {
2486	/* SS1 */
2487	RCAR_GP_PIN(4, 10),
2488};
2489static const unsigned int msiof1_ss1_mux[] = {
2490	MSIOF1_SS1_MARK,
2491};
2492static const unsigned int msiof1_ss2_pins[] = {
2493	/* SS2 */
2494	RCAR_GP_PIN(4, 11),
2495};
2496static const unsigned int msiof1_ss2_mux[] = {
2497	MSIOF1_SS2_MARK,
2498};
2499static const unsigned int msiof1_rx_pins[] = {
2500	/* RXD */
2501	RCAR_GP_PIN(4, 13),
2502};
2503static const unsigned int msiof1_rx_mux[] = {
2504	MSIOF1_RXD_MARK,
2505};
2506static const unsigned int msiof1_tx_pins[] = {
2507	/* TXD */
2508	RCAR_GP_PIN(4, 12),
2509};
2510static const unsigned int msiof1_tx_mux[] = {
2511	MSIOF1_TXD_MARK,
2512};
2513
2514static const unsigned int msiof1_clk_b_pins[] = {
2515	/* SCK */
2516	RCAR_GP_PIN(1, 16),
2517};
2518static const unsigned int msiof1_clk_b_mux[] = {
2519	MSIOF1_SCK_B_MARK,
2520};
2521static const unsigned int msiof1_ss1_b_pins[] = {
2522	/* SS1 */
2523	RCAR_GP_PIN(0, 18),
2524};
2525static const unsigned int msiof1_ss1_b_mux[] = {
2526	MSIOF1_SS1_B_MARK,
2527};
2528static const unsigned int msiof1_ss2_b_pins[] = {
2529	/* SS2 */
2530	RCAR_GP_PIN(0, 19),
2531};
2532static const unsigned int msiof1_ss2_b_mux[] = {
2533	MSIOF1_SS2_B_MARK,
2534};
2535static const unsigned int msiof1_rx_b_pins[] = {
2536	/* RXD */
2537	RCAR_GP_PIN(1, 17),
2538};
2539static const unsigned int msiof1_rx_b_mux[] = {
2540	MSIOF1_RXD_B_MARK,
2541};
2542static const unsigned int msiof1_tx_b_pins[] = {
2543	/* TXD */
2544	RCAR_GP_PIN(0, 20),
2545};
2546static const unsigned int msiof1_tx_b_mux[] = {
2547	MSIOF1_TXD_B_MARK,
2548};
2549/* - MSIOF2 ----------------------------------------------------------------- */
2550static const unsigned int msiof2_clk_pins[] = {
2551	/* SCK */
2552	RCAR_GP_PIN(0, 27),
2553};
2554static const unsigned int msiof2_clk_mux[] = {
2555	MSIOF2_SCK_MARK,
2556};
2557static const unsigned int msiof2_sync_pins[] = {
2558	/* SYNC */
2559	RCAR_GP_PIN(0, 26),
2560};
2561static const unsigned int msiof2_sync_mux[] = {
2562	MSIOF2_SYNC_MARK,
2563};
2564static const unsigned int msiof2_ss1_pins[] = {
2565	/* SS1 */
2566	RCAR_GP_PIN(0, 30),
2567};
2568static const unsigned int msiof2_ss1_mux[] = {
2569	MSIOF2_SS1_MARK,
2570};
2571static const unsigned int msiof2_ss2_pins[] = {
2572	/* SS2 */
2573	RCAR_GP_PIN(0, 31),
2574};
2575static const unsigned int msiof2_ss2_mux[] = {
2576	MSIOF2_SS2_MARK,
2577};
2578static const unsigned int msiof2_rx_pins[] = {
2579	/* RXD */
2580	RCAR_GP_PIN(0, 29),
2581};
2582static const unsigned int msiof2_rx_mux[] = {
2583	MSIOF2_RXD_MARK,
2584};
2585static const unsigned int msiof2_tx_pins[] = {
2586	/* TXD */
2587	RCAR_GP_PIN(0, 28),
2588};
2589static const unsigned int msiof2_tx_mux[] = {
2590	MSIOF2_TXD_MARK,
2591};
2592/* - MSIOF3 ----------------------------------------------------------------- */
2593static const unsigned int msiof3_clk_pins[] = {
2594	/* SCK */
2595	RCAR_GP_PIN(5, 4),
2596};
2597static const unsigned int msiof3_clk_mux[] = {
2598	MSIOF3_SCK_MARK,
2599};
2600static const unsigned int msiof3_sync_pins[] = {
2601	/* SYNC */
2602	RCAR_GP_PIN(4, 30),
2603};
2604static const unsigned int msiof3_sync_mux[] = {
2605	MSIOF3_SYNC_MARK,
2606};
2607static const unsigned int msiof3_ss1_pins[] = {
2608	/* SS1 */
2609	RCAR_GP_PIN(4, 31),
2610};
2611static const unsigned int msiof3_ss1_mux[] = {
2612	MSIOF3_SS1_MARK,
2613};
2614static const unsigned int msiof3_ss2_pins[] = {
2615	/* SS2 */
2616	RCAR_GP_PIN(4, 27),
2617};
2618static const unsigned int msiof3_ss2_mux[] = {
2619	MSIOF3_SS2_MARK,
2620};
2621static const unsigned int msiof3_rx_pins[] = {
2622	/* RXD */
2623	RCAR_GP_PIN(5, 2),
2624};
2625static const unsigned int msiof3_rx_mux[] = {
2626	MSIOF3_RXD_MARK,
2627};
2628static const unsigned int msiof3_tx_pins[] = {
2629	/* TXD */
2630	RCAR_GP_PIN(5, 3),
2631};
2632static const unsigned int msiof3_tx_mux[] = {
2633	MSIOF3_TXD_MARK,
2634};
2635
2636static const unsigned int msiof3_clk_b_pins[] = {
2637	/* SCK */
2638	RCAR_GP_PIN(0, 0),
2639};
2640static const unsigned int msiof3_clk_b_mux[] = {
2641	MSIOF3_SCK_B_MARK,
2642};
2643static const unsigned int msiof3_sync_b_pins[] = {
2644	/* SYNC */
2645	RCAR_GP_PIN(0, 1),
2646};
2647static const unsigned int msiof3_sync_b_mux[] = {
2648	MSIOF3_SYNC_B_MARK,
2649};
2650static const unsigned int msiof3_rx_b_pins[] = {
2651	/* RXD */
2652	RCAR_GP_PIN(0, 2),
2653};
2654static const unsigned int msiof3_rx_b_mux[] = {
2655	MSIOF3_RXD_B_MARK,
2656};
2657static const unsigned int msiof3_tx_b_pins[] = {
2658	/* TXD */
2659	RCAR_GP_PIN(0, 3),
2660};
2661static const unsigned int msiof3_tx_b_mux[] = {
2662	MSIOF3_TXD_B_MARK,
2663};
2664/* - PWM -------------------------------------------------------------------- */
2665static const unsigned int pwm0_pins[] = {
2666	RCAR_GP_PIN(5, 29),
2667};
2668static const unsigned int pwm0_mux[] = {
2669	PWM0_MARK,
2670};
2671static const unsigned int pwm0_b_pins[] = {
2672	RCAR_GP_PIN(4, 30),
2673};
2674static const unsigned int pwm0_b_mux[] = {
2675	PWM0_B_MARK,
2676};
2677static const unsigned int pwm1_pins[] = {
2678	RCAR_GP_PIN(5, 30),
2679};
2680static const unsigned int pwm1_mux[] = {
2681	PWM1_MARK,
2682};
2683static const unsigned int pwm1_b_pins[] = {
2684	RCAR_GP_PIN(4, 31),
2685};
2686static const unsigned int pwm1_b_mux[] = {
2687	PWM1_B_MARK,
2688};
2689static const unsigned int pwm2_pins[] = {
2690	RCAR_GP_PIN(5, 31),
2691};
2692static const unsigned int pwm2_mux[] = {
2693	PWM2_MARK,
2694};
2695static const unsigned int pwm3_pins[] = {
2696	RCAR_GP_PIN(0, 16),
2697};
2698static const unsigned int pwm3_mux[] = {
2699	PWM3_MARK,
2700};
2701static const unsigned int pwm4_pins[] = {
2702	RCAR_GP_PIN(0, 17),
2703};
2704static const unsigned int pwm4_mux[] = {
2705	PWM4_MARK,
2706};
2707static const unsigned int pwm5_pins[] = {
2708	RCAR_GP_PIN(0, 18),
2709};
2710static const unsigned int pwm5_mux[] = {
2711	PWM5_MARK,
2712};
2713static const unsigned int pwm6_pins[] = {
2714	RCAR_GP_PIN(0, 19),
2715};
2716static const unsigned int pwm6_mux[] = {
2717	PWM6_MARK,
2718};
2719/* - QSPI ------------------------------------------------------------------- */
2720static const unsigned int qspi_ctrl_pins[] = {
2721	/* SPCLK, SSL */
2722	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2723};
2724static const unsigned int qspi_ctrl_mux[] = {
2725	SPCLK_MARK, SSL_MARK,
2726};
2727static const unsigned int qspi_data2_pins[] = {
2728	/* MOSI_IO0, MISO_IO1 */
2729	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2730};
2731static const unsigned int qspi_data2_mux[] = {
2732	MOSI_IO0_MARK, MISO_IO1_MARK,
2733};
2734static const unsigned int qspi_data4_pins[] = {
2735	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2736	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2737	RCAR_GP_PIN(1, 8),
2738};
2739static const unsigned int qspi_data4_mux[] = {
2740	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2741};
2742/* - SCIF0 ------------------------------------------------------------------ */
2743static const unsigned int scif0_data_pins[] = {
2744	/* RX, TX */
2745	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2746};
2747static const unsigned int scif0_data_mux[] = {
2748	RX0_MARK, TX0_MARK,
2749};
2750static const unsigned int scif0_clk_pins[] = {
2751	/* SCK */
2752	RCAR_GP_PIN(4, 27),
2753};
2754static const unsigned int scif0_clk_mux[] = {
2755	SCK0_MARK,
2756};
2757static const unsigned int scif0_ctrl_pins[] = {
2758	/* RTS, CTS */
2759	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2760};
2761static const unsigned int scif0_ctrl_mux[] = {
2762	RTS0_N_MARK, CTS0_N_MARK,
2763};
2764static const unsigned int scif0_data_b_pins[] = {
2765	/* RX, TX */
2766	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2767};
2768static const unsigned int scif0_data_b_mux[] = {
2769	RX0_B_MARK, TX0_B_MARK,
2770};
2771/* - SCIF1 ------------------------------------------------------------------ */
2772static const unsigned int scif1_data_pins[] = {
2773	/* RX, TX */
2774	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2775};
2776static const unsigned int scif1_data_mux[] = {
2777	RX1_MARK, TX1_MARK,
2778};
2779static const unsigned int scif1_clk_pins[] = {
2780	/* SCK */
2781	RCAR_GP_PIN(4, 20),
2782};
2783static const unsigned int scif1_clk_mux[] = {
2784	SCK1_MARK,
2785};
2786static const unsigned int scif1_ctrl_pins[] = {
2787	/* RTS, CTS */
2788	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2789};
2790static const unsigned int scif1_ctrl_mux[] = {
2791	RTS1_N_MARK, CTS1_N_MARK,
2792};
2793static const unsigned int scif1_data_b_pins[] = {
2794	/* RX, TX */
2795	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2796};
2797static const unsigned int scif1_data_b_mux[] = {
2798	RX1_B_MARK, TX1_B_MARK,
2799};
2800static const unsigned int scif1_data_c_pins[] = {
2801	/* RX, TX */
2802	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2803};
2804static const unsigned int scif1_data_c_mux[] = {
2805	RX1_C_MARK, TX1_C_MARK,
2806};
2807static const unsigned int scif1_data_d_pins[] = {
2808	/* RX, TX */
2809	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2810};
2811static const unsigned int scif1_data_d_mux[] = {
2812	RX1_D_MARK, TX1_D_MARK,
2813};
2814static const unsigned int scif1_clk_d_pins[] = {
2815	/* SCK */
2816	RCAR_GP_PIN(3, 17),
2817};
2818static const unsigned int scif1_clk_d_mux[] = {
2819	SCK1_D_MARK,
2820};
2821static const unsigned int scif1_data_e_pins[] = {
2822	/* RX, TX */
2823	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2824};
2825static const unsigned int scif1_data_e_mux[] = {
2826	RX1_E_MARK, TX1_E_MARK,
2827};
2828static const unsigned int scif1_clk_e_pins[] = {
2829	/* SCK */
2830	RCAR_GP_PIN(2, 20),
2831};
2832static const unsigned int scif1_clk_e_mux[] = {
2833	SCK1_E_MARK,
2834};
2835/* - SCIF2 ------------------------------------------------------------------ */
2836static const unsigned int scif2_data_pins[] = {
2837	/* RX, TX */
2838	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2839};
2840static const unsigned int scif2_data_mux[] = {
2841	RX2_MARK, TX2_MARK,
2842};
2843static const unsigned int scif2_clk_pins[] = {
2844	/* SCK */
2845	RCAR_GP_PIN(5, 4),
2846};
2847static const unsigned int scif2_clk_mux[] = {
2848	SCK2_MARK,
2849};
2850static const unsigned int scif2_data_b_pins[] = {
2851	/* RX, TX */
2852	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2853};
2854static const unsigned int scif2_data_b_mux[] = {
2855	RX2_B_MARK, TX2_B_MARK,
2856};
2857/* - SCIFA0 ----------------------------------------------------------------- */
2858static const unsigned int scifa0_data_pins[] = {
2859	/* RXD, TXD */
2860	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2861};
2862static const unsigned int scifa0_data_mux[] = {
2863	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2864};
2865static const unsigned int scifa0_clk_pins[] = {
2866	/* SCK */
2867	RCAR_GP_PIN(4, 27),
2868};
2869static const unsigned int scifa0_clk_mux[] = {
2870	SCIFA0_SCK_MARK,
2871};
2872static const unsigned int scifa0_ctrl_pins[] = {
2873	/* RTS, CTS */
2874	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2875};
2876static const unsigned int scifa0_ctrl_mux[] = {
2877	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2878};
2879static const unsigned int scifa0_data_b_pins[] = {
2880	/* RXD, TXD */
2881	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2882};
2883static const unsigned int scifa0_data_b_mux[] = {
2884	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2885};
2886static const unsigned int scifa0_clk_b_pins[] = {
2887	/* SCK */
2888	RCAR_GP_PIN(1, 19),
2889};
2890static const unsigned int scifa0_clk_b_mux[] = {
2891	SCIFA0_SCK_B_MARK,
2892};
2893static const unsigned int scifa0_ctrl_b_pins[] = {
2894	/* RTS, CTS */
2895	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2896};
2897static const unsigned int scifa0_ctrl_b_mux[] = {
2898	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2899};
2900/* - SCIFA1 ----------------------------------------------------------------- */
2901static const unsigned int scifa1_data_pins[] = {
2902	/* RXD, TXD */
2903	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2904};
2905static const unsigned int scifa1_data_mux[] = {
2906	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2907};
2908static const unsigned int scifa1_clk_pins[] = {
2909	/* SCK */
2910	RCAR_GP_PIN(4, 20),
2911};
2912static const unsigned int scifa1_clk_mux[] = {
2913	SCIFA1_SCK_MARK,
2914};
2915static const unsigned int scifa1_ctrl_pins[] = {
2916	/* RTS, CTS */
2917	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2918};
2919static const unsigned int scifa1_ctrl_mux[] = {
2920	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2921};
2922static const unsigned int scifa1_data_b_pins[] = {
2923	/* RXD, TXD */
2924	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2925};
2926static const unsigned int scifa1_data_b_mux[] = {
2927	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2928};
2929static const unsigned int scifa1_clk_b_pins[] = {
2930	/* SCK */
2931	RCAR_GP_PIN(0, 23),
2932};
2933static const unsigned int scifa1_clk_b_mux[] = {
2934	SCIFA1_SCK_B_MARK,
2935};
2936static const unsigned int scifa1_ctrl_b_pins[] = {
2937	/* RTS, CTS */
2938	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2939};
2940static const unsigned int scifa1_ctrl_b_mux[] = {
2941	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2942};
2943static const unsigned int scifa1_data_c_pins[] = {
2944	/* RXD, TXD */
2945	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2946};
2947static const unsigned int scifa1_data_c_mux[] = {
2948	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2949};
2950static const unsigned int scifa1_clk_c_pins[] = {
2951	/* SCK */
2952	RCAR_GP_PIN(0, 8),
2953};
2954static const unsigned int scifa1_clk_c_mux[] = {
2955	SCIFA1_SCK_C_MARK,
2956};
2957static const unsigned int scifa1_ctrl_c_pins[] = {
2958	/* RTS, CTS */
2959	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2960};
2961static const unsigned int scifa1_ctrl_c_mux[] = {
2962	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2963};
2964static const unsigned int scifa1_data_d_pins[] = {
2965	/* RXD, TXD */
2966	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2967};
2968static const unsigned int scifa1_data_d_mux[] = {
2969	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2970};
2971static const unsigned int scifa1_clk_d_pins[] = {
2972	/* SCK */
2973	RCAR_GP_PIN(2, 10),
2974};
2975static const unsigned int scifa1_clk_d_mux[] = {
2976	SCIFA1_SCK_D_MARK,
2977};
2978static const unsigned int scifa1_ctrl_d_pins[] = {
2979	/* RTS, CTS */
2980	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2981};
2982static const unsigned int scifa1_ctrl_d_mux[] = {
2983	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2984};
2985/* - SCIFA2 ----------------------------------------------------------------- */
2986static const unsigned int scifa2_data_pins[] = {
2987	/* RXD, TXD */
2988	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2989};
2990static const unsigned int scifa2_data_mux[] = {
2991	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2992};
2993static const unsigned int scifa2_clk_pins[] = {
2994	/* SCK */
2995	RCAR_GP_PIN(5, 4),
2996};
2997static const unsigned int scifa2_clk_mux[] = {
2998	SCIFA2_SCK_MARK,
2999};
3000static const unsigned int scifa2_ctrl_pins[] = {
3001	/* RTS, CTS */
3002	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3003};
3004static const unsigned int scifa2_ctrl_mux[] = {
3005	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3006};
3007static const unsigned int scifa2_data_b_pins[] = {
3008	/* RXD, TXD */
3009	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3010};
3011static const unsigned int scifa2_data_b_mux[] = {
3012	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3013};
3014static const unsigned int scifa2_data_c_pins[] = {
3015	/* RXD, TXD */
3016	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3017};
3018static const unsigned int scifa2_data_c_mux[] = {
3019	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3020};
3021static const unsigned int scifa2_clk_c_pins[] = {
3022	/* SCK */
3023	RCAR_GP_PIN(5, 29),
3024};
3025static const unsigned int scifa2_clk_c_mux[] = {
3026	SCIFA2_SCK_C_MARK,
3027};
3028/* - SCIFB0 ----------------------------------------------------------------- */
3029static const unsigned int scifb0_data_pins[] = {
3030	/* RXD, TXD */
3031	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3032};
3033static const unsigned int scifb0_data_mux[] = {
3034	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3035};
3036static const unsigned int scifb0_clk_pins[] = {
3037	/* SCK */
3038	RCAR_GP_PIN(4, 8),
3039};
3040static const unsigned int scifb0_clk_mux[] = {
3041	SCIFB0_SCK_MARK,
3042};
3043static const unsigned int scifb0_ctrl_pins[] = {
3044	/* RTS, CTS */
3045	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3046};
3047static const unsigned int scifb0_ctrl_mux[] = {
3048	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3049};
3050static const unsigned int scifb0_data_b_pins[] = {
3051	/* RXD, TXD */
3052	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3053};
3054static const unsigned int scifb0_data_b_mux[] = {
3055	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3056};
3057static const unsigned int scifb0_clk_b_pins[] = {
3058	/* SCK */
3059	RCAR_GP_PIN(3, 9),
3060};
3061static const unsigned int scifb0_clk_b_mux[] = {
3062	SCIFB0_SCK_B_MARK,
3063};
3064static const unsigned int scifb0_ctrl_b_pins[] = {
3065	/* RTS, CTS */
3066	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3067};
3068static const unsigned int scifb0_ctrl_b_mux[] = {
3069	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3070};
3071static const unsigned int scifb0_data_c_pins[] = {
3072	/* RXD, TXD */
3073	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3074};
3075static const unsigned int scifb0_data_c_mux[] = {
3076	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3077};
3078/* - SCIFB1 ----------------------------------------------------------------- */
3079static const unsigned int scifb1_data_pins[] = {
3080	/* RXD, TXD */
3081	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3082};
3083static const unsigned int scifb1_data_mux[] = {
3084	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3085};
3086static const unsigned int scifb1_clk_pins[] = {
3087	/* SCK */
3088	RCAR_GP_PIN(4, 14),
3089};
3090static const unsigned int scifb1_clk_mux[] = {
3091	SCIFB1_SCK_MARK,
3092};
3093static const unsigned int scifb1_ctrl_pins[] = {
3094	/* RTS, CTS */
3095	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3096};
3097static const unsigned int scifb1_ctrl_mux[] = {
3098	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3099};
3100static const unsigned int scifb1_data_b_pins[] = {
3101	/* RXD, TXD */
3102	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3103};
3104static const unsigned int scifb1_data_b_mux[] = {
3105	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3106};
3107static const unsigned int scifb1_clk_b_pins[] = {
3108	/* SCK */
3109	RCAR_GP_PIN(3, 1),
3110};
3111static const unsigned int scifb1_clk_b_mux[] = {
3112	SCIFB1_SCK_B_MARK,
3113};
3114static const unsigned int scifb1_ctrl_b_pins[] = {
3115	/* RTS, CTS */
3116	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3117};
3118static const unsigned int scifb1_ctrl_b_mux[] = {
3119	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3120};
3121static const unsigned int scifb1_data_c_pins[] = {
3122	/* RXD, TXD */
3123	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3124};
3125static const unsigned int scifb1_data_c_mux[] = {
3126	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3127};
3128static const unsigned int scifb1_data_d_pins[] = {
3129	/* RXD, TXD */
3130	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3131};
3132static const unsigned int scifb1_data_d_mux[] = {
3133	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3134};
3135static const unsigned int scifb1_data_e_pins[] = {
3136	/* RXD, TXD */
3137	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3138};
3139static const unsigned int scifb1_data_e_mux[] = {
3140	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3141};
3142static const unsigned int scifb1_clk_e_pins[] = {
3143	/* SCK */
3144	RCAR_GP_PIN(3, 17),
3145};
3146static const unsigned int scifb1_clk_e_mux[] = {
3147	SCIFB1_SCK_E_MARK,
3148};
3149static const unsigned int scifb1_data_f_pins[] = {
3150	/* RXD, TXD */
3151	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3152};
3153static const unsigned int scifb1_data_f_mux[] = {
3154	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3155};
3156static const unsigned int scifb1_data_g_pins[] = {
3157	/* RXD, TXD */
3158	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3159};
3160static const unsigned int scifb1_data_g_mux[] = {
3161	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3162};
3163static const unsigned int scifb1_clk_g_pins[] = {
3164	/* SCK */
3165	RCAR_GP_PIN(2, 20),
3166};
3167static const unsigned int scifb1_clk_g_mux[] = {
3168	SCIFB1_SCK_G_MARK,
3169};
3170/* - SCIFB2 ----------------------------------------------------------------- */
3171static const unsigned int scifb2_data_pins[] = {
3172	/* RXD, TXD */
3173	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3174};
3175static const unsigned int scifb2_data_mux[] = {
3176	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3177};
3178static const unsigned int scifb2_clk_pins[] = {
3179	/* SCK */
3180	RCAR_GP_PIN(4, 21),
3181};
3182static const unsigned int scifb2_clk_mux[] = {
3183	SCIFB2_SCK_MARK,
3184};
3185static const unsigned int scifb2_ctrl_pins[] = {
3186	/* RTS, CTS */
3187	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3188};
3189static const unsigned int scifb2_ctrl_mux[] = {
3190	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3191};
3192static const unsigned int scifb2_data_b_pins[] = {
3193	/* RXD, TXD */
3194	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3195};
3196static const unsigned int scifb2_data_b_mux[] = {
3197	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3198};
3199static const unsigned int scifb2_clk_b_pins[] = {
3200	/* SCK */
3201	RCAR_GP_PIN(0, 31),
3202};
3203static const unsigned int scifb2_clk_b_mux[] = {
3204	SCIFB2_SCK_B_MARK,
3205};
3206static const unsigned int scifb2_ctrl_b_pins[] = {
3207	/* RTS, CTS */
3208	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3209};
3210static const unsigned int scifb2_ctrl_b_mux[] = {
3211	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3212};
3213static const unsigned int scifb2_data_c_pins[] = {
3214	/* RXD, TXD */
3215	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3216};
3217static const unsigned int scifb2_data_c_mux[] = {
3218	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3219};
3220/* - SCIF Clock ------------------------------------------------------------- */
3221static const unsigned int scif_clk_pins[] = {
3222	/* SCIF_CLK */
3223	RCAR_GP_PIN(4, 26),
3224};
3225static const unsigned int scif_clk_mux[] = {
3226	SCIF_CLK_MARK,
3227};
3228static const unsigned int scif_clk_b_pins[] = {
3229	/* SCIF_CLK */
3230	RCAR_GP_PIN(5, 4),
3231};
3232static const unsigned int scif_clk_b_mux[] = {
3233	SCIF_CLK_B_MARK,
3234};
3235/* - SDHI0 ------------------------------------------------------------------ */
3236static const unsigned int sdhi0_data1_pins[] = {
3237	/* D0 */
3238	RCAR_GP_PIN(3, 2),
3239};
3240static const unsigned int sdhi0_data1_mux[] = {
3241	SD0_DAT0_MARK,
3242};
3243static const unsigned int sdhi0_data4_pins[] = {
3244	/* D[0:3] */
3245	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3246};
3247static const unsigned int sdhi0_data4_mux[] = {
3248	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3249};
3250static const unsigned int sdhi0_ctrl_pins[] = {
3251	/* CLK, CMD */
3252	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3253};
3254static const unsigned int sdhi0_ctrl_mux[] = {
3255	SD0_CLK_MARK, SD0_CMD_MARK,
3256};
3257static const unsigned int sdhi0_cd_pins[] = {
3258	/* CD */
3259	RCAR_GP_PIN(3, 6),
3260};
3261static const unsigned int sdhi0_cd_mux[] = {
3262	SD0_CD_MARK,
3263};
3264static const unsigned int sdhi0_wp_pins[] = {
3265	/* WP */
3266	RCAR_GP_PIN(3, 7),
3267};
3268static const unsigned int sdhi0_wp_mux[] = {
3269	SD0_WP_MARK,
3270};
3271/* - SDHI1 ------------------------------------------------------------------ */
3272static const unsigned int sdhi1_data1_pins[] = {
3273	/* D0 */
3274	RCAR_GP_PIN(3, 10),
3275};
3276static const unsigned int sdhi1_data1_mux[] = {
3277	SD1_DAT0_MARK,
3278};
3279static const unsigned int sdhi1_data4_pins[] = {
3280	/* D[0:3] */
3281	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3282};
3283static const unsigned int sdhi1_data4_mux[] = {
3284	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3285};
3286static const unsigned int sdhi1_ctrl_pins[] = {
3287	/* CLK, CMD */
3288	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3289};
3290static const unsigned int sdhi1_ctrl_mux[] = {
3291	SD1_CLK_MARK, SD1_CMD_MARK,
3292};
3293static const unsigned int sdhi1_cd_pins[] = {
3294	/* CD */
3295	RCAR_GP_PIN(3, 14),
3296};
3297static const unsigned int sdhi1_cd_mux[] = {
3298	SD1_CD_MARK,
3299};
3300static const unsigned int sdhi1_wp_pins[] = {
3301	/* WP */
3302	RCAR_GP_PIN(3, 15),
3303};
3304static const unsigned int sdhi1_wp_mux[] = {
3305	SD1_WP_MARK,
3306};
3307/* - SDHI2 ------------------------------------------------------------------ */
3308static const unsigned int sdhi2_data1_pins[] = {
3309	/* D0 */
3310	RCAR_GP_PIN(3, 18),
3311};
3312static const unsigned int sdhi2_data1_mux[] = {
3313	SD2_DAT0_MARK,
3314};
3315static const unsigned int sdhi2_data4_pins[] = {
3316	/* D[0:3] */
3317	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3318};
3319static const unsigned int sdhi2_data4_mux[] = {
3320	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3321};
3322static const unsigned int sdhi2_ctrl_pins[] = {
3323	/* CLK, CMD */
3324	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3325};
3326static const unsigned int sdhi2_ctrl_mux[] = {
3327	SD2_CLK_MARK, SD2_CMD_MARK,
3328};
3329static const unsigned int sdhi2_cd_pins[] = {
3330	/* CD */
3331	RCAR_GP_PIN(3, 22),
3332};
3333static const unsigned int sdhi2_cd_mux[] = {
3334	SD2_CD_MARK,
3335};
3336static const unsigned int sdhi2_wp_pins[] = {
3337	/* WP */
3338	RCAR_GP_PIN(3, 23),
3339};
3340static const unsigned int sdhi2_wp_mux[] = {
3341	SD2_WP_MARK,
3342};
3343/* - SDHI3 ------------------------------------------------------------------ */
3344static const unsigned int sdhi3_data1_pins[] = {
3345	/* D0 */
3346	RCAR_GP_PIN(3, 26),
3347};
3348static const unsigned int sdhi3_data1_mux[] = {
3349	SD3_DAT0_MARK,
3350};
3351static const unsigned int sdhi3_data4_pins[] = {
3352	/* D[0:3] */
3353	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3354};
3355static const unsigned int sdhi3_data4_mux[] = {
3356	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3357};
3358static const unsigned int sdhi3_ctrl_pins[] = {
3359	/* CLK, CMD */
3360	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3361};
3362static const unsigned int sdhi3_ctrl_mux[] = {
3363	SD3_CLK_MARK, SD3_CMD_MARK,
3364};
3365static const unsigned int sdhi3_cd_pins[] = {
3366	/* CD */
3367	RCAR_GP_PIN(3, 30),
3368};
3369static const unsigned int sdhi3_cd_mux[] = {
3370	SD3_CD_MARK,
3371};
3372static const unsigned int sdhi3_wp_pins[] = {
3373	/* WP */
3374	RCAR_GP_PIN(3, 31),
3375};
3376static const unsigned int sdhi3_wp_mux[] = {
3377	SD3_WP_MARK,
3378};
3379/* - SSI -------------------------------------------------------------------- */
3380static const unsigned int ssi0_data_pins[] = {
3381	/* SDATA0 */
3382	RCAR_GP_PIN(4, 5),
3383};
3384static const unsigned int ssi0_data_mux[] = {
3385	SSI_SDATA0_MARK,
3386};
3387static const unsigned int ssi0129_ctrl_pins[] = {
3388	/* SCK, WS */
3389	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3390};
3391static const unsigned int ssi0129_ctrl_mux[] = {
3392	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3393};
3394static const unsigned int ssi1_data_pins[] = {
3395	/* SDATA1 */
3396	RCAR_GP_PIN(4, 6),
3397};
3398static const unsigned int ssi1_data_mux[] = {
3399	SSI_SDATA1_MARK,
3400};
3401static const unsigned int ssi1_ctrl_pins[] = {
3402	/* SCK, WS */
3403	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3404};
3405static const unsigned int ssi1_ctrl_mux[] = {
3406	SSI_SCK1_MARK, SSI_WS1_MARK,
3407};
3408static const unsigned int ssi2_data_pins[] = {
3409	/* SDATA2 */
3410	RCAR_GP_PIN(4, 7),
3411};
3412static const unsigned int ssi2_data_mux[] = {
3413	SSI_SDATA2_MARK,
3414};
3415static const unsigned int ssi2_ctrl_pins[] = {
3416	/* SCK, WS */
3417	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3418};
3419static const unsigned int ssi2_ctrl_mux[] = {
3420	SSI_SCK2_MARK, SSI_WS2_MARK,
3421};
3422static const unsigned int ssi3_data_pins[] = {
3423	/* SDATA3 */
3424	RCAR_GP_PIN(4, 10),
3425};
3426static const unsigned int ssi3_data_mux[] = {
3427	SSI_SDATA3_MARK
3428};
3429static const unsigned int ssi34_ctrl_pins[] = {
3430	/* SCK, WS */
3431	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3432};
3433static const unsigned int ssi34_ctrl_mux[] = {
3434	SSI_SCK34_MARK, SSI_WS34_MARK,
3435};
3436static const unsigned int ssi4_data_pins[] = {
3437	/* SDATA4 */
3438	RCAR_GP_PIN(4, 13),
3439};
3440static const unsigned int ssi4_data_mux[] = {
3441	SSI_SDATA4_MARK,
3442};
3443static const unsigned int ssi4_ctrl_pins[] = {
3444	/* SCK, WS */
3445	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3446};
3447static const unsigned int ssi4_ctrl_mux[] = {
3448	SSI_SCK4_MARK, SSI_WS4_MARK,
3449};
3450static const unsigned int ssi5_pins[] = {
3451	/* SDATA5, SCK, WS */
3452	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3453};
3454static const unsigned int ssi5_mux[] = {
3455	SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3456};
3457static const unsigned int ssi5_b_pins[] = {
3458	/* SDATA5, SCK, WS */
3459	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3460};
3461static const unsigned int ssi5_b_mux[] = {
3462	SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3463};
3464static const unsigned int ssi5_c_pins[] = {
3465	/* SDATA5, SCK, WS */
3466	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3467};
3468static const unsigned int ssi5_c_mux[] = {
3469	SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3470};
3471static const unsigned int ssi6_pins[] = {
3472	/* SDATA6, SCK, WS */
3473	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3474};
3475static const unsigned int ssi6_mux[] = {
3476	SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3477};
3478static const unsigned int ssi6_b_pins[] = {
3479	/* SDATA6, SCK, WS */
3480	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3481};
3482static const unsigned int ssi6_b_mux[] = {
3483	SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3484};
3485static const unsigned int ssi7_data_pins[] = {
3486	/* SDATA7 */
3487	RCAR_GP_PIN(4, 22),
3488};
3489static const unsigned int ssi7_data_mux[] = {
3490	SSI_SDATA7_MARK,
3491};
3492static const unsigned int ssi7_b_data_pins[] = {
3493	/* SDATA7 */
3494	RCAR_GP_PIN(4, 22),
3495};
3496static const unsigned int ssi7_b_data_mux[] = {
3497	SSI_SDATA7_B_MARK,
3498};
3499static const unsigned int ssi7_c_data_pins[] = {
3500	/* SDATA7 */
3501	RCAR_GP_PIN(1, 26),
3502};
3503static const unsigned int ssi7_c_data_mux[] = {
3504	SSI_SDATA7_C_MARK,
3505};
3506static const unsigned int ssi78_ctrl_pins[] = {
3507	/* SCK, WS */
3508	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3509};
3510static const unsigned int ssi78_ctrl_mux[] = {
3511	SSI_SCK78_MARK, SSI_WS78_MARK,
3512};
3513static const unsigned int ssi78_b_ctrl_pins[] = {
3514	/* SCK, WS */
3515	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3516};
3517static const unsigned int ssi78_b_ctrl_mux[] = {
3518	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3519};
3520static const unsigned int ssi78_c_ctrl_pins[] = {
3521	/* SCK, WS */
3522	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3523};
3524static const unsigned int ssi78_c_ctrl_mux[] = {
3525	SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3526};
3527static const unsigned int ssi8_data_pins[] = {
3528	/* SDATA8 */
3529	RCAR_GP_PIN(4, 23),
3530};
3531static const unsigned int ssi8_data_mux[] = {
3532	SSI_SDATA8_MARK,
3533};
3534static const unsigned int ssi8_b_data_pins[] = {
3535	/* SDATA8 */
3536	RCAR_GP_PIN(4, 23),
3537};
3538static const unsigned int ssi8_b_data_mux[] = {
3539	SSI_SDATA8_B_MARK,
3540};
3541static const unsigned int ssi8_c_data_pins[] = {
3542	/* SDATA8 */
3543	RCAR_GP_PIN(1, 27),
3544};
3545static const unsigned int ssi8_c_data_mux[] = {
3546	SSI_SDATA8_C_MARK,
3547};
3548static const unsigned int ssi9_data_pins[] = {
3549	/* SDATA9 */
3550	RCAR_GP_PIN(4, 24),
3551};
3552static const unsigned int ssi9_data_mux[] = {
3553	SSI_SDATA9_MARK,
3554};
3555static const unsigned int ssi9_ctrl_pins[] = {
3556	/* SCK, WS */
3557	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3558};
3559static const unsigned int ssi9_ctrl_mux[] = {
3560	SSI_SCK9_MARK, SSI_WS9_MARK,
3561};
3562/* - TPU0 ------------------------------------------------------------------- */
3563static const unsigned int tpu0_to0_pins[] = {
3564	/* TO */
3565	RCAR_GP_PIN(0, 20),
3566};
3567static const unsigned int tpu0_to0_mux[] = {
3568	TPU0TO0_MARK,
3569};
3570static const unsigned int tpu0_to1_pins[] = {
3571	/* TO */
3572	RCAR_GP_PIN(0, 21),
3573};
3574static const unsigned int tpu0_to1_mux[] = {
3575	TPU0TO1_MARK,
3576};
3577static const unsigned int tpu0_to2_pins[] = {
3578	/* TO */
3579	RCAR_GP_PIN(0, 22),
3580};
3581static const unsigned int tpu0_to2_mux[] = {
3582	TPU0TO2_MARK,
3583};
3584static const unsigned int tpu0_to3_pins[] = {
3585	/* TO */
3586	RCAR_GP_PIN(0, 23),
3587};
3588static const unsigned int tpu0_to3_mux[] = {
3589	TPU0TO3_MARK,
3590};
3591/* - USB0 ------------------------------------------------------------------- */
3592static const unsigned int usb0_pins[] = {
3593	/* PWEN, OVC/VBUS */
3594	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3595};
3596static const unsigned int usb0_mux[] = {
3597	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3598};
3599static const unsigned int usb0_ovc_vbus_pins[] = {
3600	/* OVC/VBUS */
3601	RCAR_GP_PIN(5, 19),
3602};
3603static const unsigned int usb0_ovc_vbus_mux[] = {
3604	USB0_OVC_VBUS_MARK,
3605};
3606/* - USB1 ------------------------------------------------------------------- */
3607static const unsigned int usb1_pins[] = {
3608	/* PWEN, OVC */
3609	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3610};
3611static const unsigned int usb1_mux[] = {
3612	USB1_PWEN_MARK, USB1_OVC_MARK,
3613};
3614/* - USB2 ------------------------------------------------------------------- */
3615static const unsigned int usb2_pins[] = {
3616	/* PWEN, OVC */
3617	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3618};
3619static const unsigned int usb2_mux[] = {
3620	USB2_PWEN_MARK, USB2_OVC_MARK,
3621};
3622/* - VIN0 ------------------------------------------------------------------- */
3623static const union vin_data vin0_data_pins = {
3624	.data24 = {
3625		/* B */
3626		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3627		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3628		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3629		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3630		/* G */
3631		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3632		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3633		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3634		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3635		/* R */
3636		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3637		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3638		RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3639		RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3640	},
3641};
3642static const union vin_data vin0_data_mux = {
3643	.data24 = {
3644		/* B */
3645		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3646		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3647		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3648		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3649		/* G */
3650		VI0_G0_MARK, VI0_G1_MARK,
3651		VI0_G2_MARK, VI0_G3_MARK,
3652		VI0_G4_MARK, VI0_G5_MARK,
3653		VI0_G6_MARK, VI0_G7_MARK,
3654		/* R */
3655		VI0_R0_MARK, VI0_R1_MARK,
3656		VI0_R2_MARK, VI0_R3_MARK,
3657		VI0_R4_MARK, VI0_R5_MARK,
3658		VI0_R6_MARK, VI0_R7_MARK,
3659	},
3660};
3661static const unsigned int vin0_data18_pins[] = {
3662	/* B */
3663	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3664	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3665	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3666	/* G */
3667	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3668	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3669	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3670	/* R */
3671	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3672	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3673	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3674};
3675static const unsigned int vin0_data18_mux[] = {
3676	/* B */
3677	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3678	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3679	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3680	/* G */
3681	VI0_G2_MARK, VI0_G3_MARK,
3682	VI0_G4_MARK, VI0_G5_MARK,
3683	VI0_G6_MARK, VI0_G7_MARK,
3684	/* R */
3685	VI0_R2_MARK, VI0_R3_MARK,
3686	VI0_R4_MARK, VI0_R5_MARK,
3687	VI0_R6_MARK, VI0_R7_MARK,
3688};
3689static const unsigned int vin0_sync_pins[] = {
3690	RCAR_GP_PIN(0, 12), /* HSYNC */
3691	RCAR_GP_PIN(0, 13), /* VSYNC */
3692};
3693static const unsigned int vin0_sync_mux[] = {
3694	VI0_HSYNC_N_MARK,
3695	VI0_VSYNC_N_MARK,
3696};
3697static const unsigned int vin0_field_pins[] = {
3698	RCAR_GP_PIN(0, 15),
3699};
3700static const unsigned int vin0_field_mux[] = {
3701	VI0_FIELD_MARK,
3702};
3703static const unsigned int vin0_clkenb_pins[] = {
3704	RCAR_GP_PIN(0, 14),
3705};
3706static const unsigned int vin0_clkenb_mux[] = {
3707	VI0_CLKENB_MARK,
3708};
3709static const unsigned int vin0_clk_pins[] = {
3710	RCAR_GP_PIN(2, 0),
3711};
3712static const unsigned int vin0_clk_mux[] = {
3713	VI0_CLK_MARK,
3714};
3715/* - VIN1 ------------------------------------------------------------------- */
3716static const union vin_data vin1_data_pins = {
3717	.data24 = {
3718		/* B */
3719		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3720		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3721		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3722		RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3723		/* G */
3724		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3725		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3726		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3727		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3728		/* R */
3729		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3730		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3731		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3732		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3733	},
3734};
3735static const union vin_data vin1_data_mux = {
3736	.data24 = {
3737		/* B */
3738		VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3739		VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3740		VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3741		VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3742		/* G */
3743		VI1_G0_MARK, VI1_G1_MARK,
3744		VI1_G2_MARK, VI1_G3_MARK,
3745		VI1_G4_MARK, VI1_G5_MARK,
3746		VI1_G6_MARK, VI1_G7_MARK,
3747		/* R */
3748		VI1_R0_MARK, VI1_R1_MARK,
3749		VI1_R2_MARK, VI1_R3_MARK,
3750		VI1_R4_MARK, VI1_R5_MARK,
3751		VI1_R6_MARK, VI1_R7_MARK,
3752	},
3753};
3754static const unsigned int vin1_data18_pins[] = {
3755	/* B */
3756	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3757	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3758	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3759	/* G */
3760	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3761	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3762	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3763	/* R */
3764	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3765	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3766	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3767};
3768static const unsigned int vin1_data18_mux[] = {
3769	/* B */
3770	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3771	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3772	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3773	/* G */
3774	VI1_G2_MARK, VI1_G3_MARK,
3775	VI1_G4_MARK, VI1_G5_MARK,
3776	VI1_G6_MARK, VI1_G7_MARK,
3777	/* R */
3778	VI1_R2_MARK, VI1_R3_MARK,
3779	VI1_R4_MARK, VI1_R5_MARK,
3780	VI1_R6_MARK, VI1_R7_MARK,
3781};
3782static const unsigned int vin1_sync_pins[] = {
3783	RCAR_GP_PIN(1, 24), /* HSYNC */
3784	RCAR_GP_PIN(1, 25), /* VSYNC */
3785};
3786static const unsigned int vin1_sync_mux[] = {
3787	VI1_HSYNC_N_MARK,
3788	VI1_VSYNC_N_MARK,
3789};
3790static const unsigned int vin1_field_pins[] = {
3791	RCAR_GP_PIN(1, 13),
3792};
3793static const unsigned int vin1_field_mux[] = {
3794	VI1_FIELD_MARK,
3795};
3796static const unsigned int vin1_clkenb_pins[] = {
3797	RCAR_GP_PIN(1, 26),
3798};
3799static const unsigned int vin1_clkenb_mux[] = {
3800	VI1_CLKENB_MARK,
3801};
3802static const unsigned int vin1_clk_pins[] = {
3803	RCAR_GP_PIN(2, 9),
3804};
3805static const unsigned int vin1_clk_mux[] = {
3806	VI1_CLK_MARK,
3807};
3808/* - VIN2 ----------------------------------------------------------------- */
3809static const union vin_data vin2_data_pins = {
3810	.data24 = {
3811		/* B */
3812		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3813		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3814		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3815		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3816		/* G */
3817		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3818		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3819		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3820		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3821		/* R */
3822		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3823		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3824		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3825		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3826	},
3827};
3828static const union vin_data vin2_data_mux = {
3829	.data24 = {
3830		/* B */
3831		VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3832		VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3833		VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3834		VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3835		/* G */
3836		VI2_G0_MARK, VI2_G1_MARK,
3837		VI2_G2_MARK, VI2_G3_MARK,
3838		VI2_G4_MARK, VI2_G5_MARK,
3839		VI2_G6_MARK, VI2_G7_MARK,
3840		/* R */
3841		VI2_R0_MARK, VI2_R1_MARK,
3842		VI2_R2_MARK, VI2_R3_MARK,
3843		VI2_R4_MARK, VI2_R5_MARK,
3844		VI2_R6_MARK, VI2_R7_MARK,
3845	},
3846};
3847static const unsigned int vin2_data18_pins[] = {
3848	/* B */
3849	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3850	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3851	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3852	/* G */
3853	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3854	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3855	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3856	/* R */
3857	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3858	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3859	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3860};
3861static const unsigned int vin2_data18_mux[] = {
3862	/* B */
3863	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3864	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3865	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3866	/* G */
3867	VI2_G2_MARK, VI2_G3_MARK,
3868	VI2_G4_MARK, VI2_G5_MARK,
3869	VI2_G6_MARK, VI2_G7_MARK,
3870	/* R */
3871	VI2_R2_MARK, VI2_R3_MARK,
3872	VI2_R4_MARK, VI2_R5_MARK,
3873	VI2_R6_MARK, VI2_R7_MARK,
3874};
3875static const unsigned int vin2_sync_pins[] = {
3876	RCAR_GP_PIN(1, 16), /* HSYNC */
3877	RCAR_GP_PIN(1, 21), /* VSYNC */
3878};
3879static const unsigned int vin2_sync_mux[] = {
3880	VI2_HSYNC_N_MARK,
3881	VI2_VSYNC_N_MARK,
3882};
3883static const unsigned int vin2_field_pins[] = {
3884	RCAR_GP_PIN(1, 9),
3885};
3886static const unsigned int vin2_field_mux[] = {
3887	VI2_FIELD_MARK,
3888};
3889static const unsigned int vin2_clkenb_pins[] = {
3890	RCAR_GP_PIN(1, 8),
3891};
3892static const unsigned int vin2_clkenb_mux[] = {
3893	VI2_CLKENB_MARK,
3894};
3895static const unsigned int vin2_clk_pins[] = {
3896	RCAR_GP_PIN(1, 11),
3897};
3898static const unsigned int vin2_clk_mux[] = {
3899	VI2_CLK_MARK,
3900};
3901/* - VIN3 ----------------------------------------------------------------- */
3902static const unsigned int vin3_data8_pins[] = {
3903	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3904	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3905	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3906	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3907};
3908static const unsigned int vin3_data8_mux[] = {
3909	VI3_DATA0_MARK, VI3_DATA1_MARK,
3910	VI3_DATA2_MARK, VI3_DATA3_MARK,
3911	VI3_DATA4_MARK, VI3_DATA5_MARK,
3912	VI3_DATA6_MARK, VI3_DATA7_MARK,
3913};
3914static const unsigned int vin3_sync_pins[] = {
3915	RCAR_GP_PIN(1, 16), /* HSYNC */
3916	RCAR_GP_PIN(1, 17), /* VSYNC */
3917};
3918static const unsigned int vin3_sync_mux[] = {
3919	VI3_HSYNC_N_MARK,
3920	VI3_VSYNC_N_MARK,
3921};
3922static const unsigned int vin3_field_pins[] = {
3923	RCAR_GP_PIN(1, 15),
3924};
3925static const unsigned int vin3_field_mux[] = {
3926	VI3_FIELD_MARK,
3927};
3928static const unsigned int vin3_clkenb_pins[] = {
3929	RCAR_GP_PIN(1, 14),
3930};
3931static const unsigned int vin3_clkenb_mux[] = {
3932	VI3_CLKENB_MARK,
3933};
3934static const unsigned int vin3_clk_pins[] = {
3935	RCAR_GP_PIN(1, 23),
3936};
3937static const unsigned int vin3_clk_mux[] = {
3938	VI3_CLK_MARK,
3939};
3940
3941static const struct {
3942	struct sh_pfc_pin_group common[289];
3943	struct sh_pfc_pin_group automotive[1];
3944} pinmux_groups = {
3945	.common = {
3946		SH_PFC_PIN_GROUP(audio_clk_a),
3947		SH_PFC_PIN_GROUP(audio_clk_b),
3948		SH_PFC_PIN_GROUP(audio_clk_c),
3949		SH_PFC_PIN_GROUP(audio_clkout),
3950		SH_PFC_PIN_GROUP(audio_clkout_b),
3951		SH_PFC_PIN_GROUP(audio_clkout_c),
3952		SH_PFC_PIN_GROUP(audio_clkout_d),
3953		SH_PFC_PIN_GROUP(avb_link),
3954		SH_PFC_PIN_GROUP(avb_magic),
3955		SH_PFC_PIN_GROUP(avb_phy_int),
3956		SH_PFC_PIN_GROUP(avb_mdio),
3957		SH_PFC_PIN_GROUP(avb_mii),
3958		SH_PFC_PIN_GROUP(avb_gmii),
3959		SH_PFC_PIN_GROUP(du_rgb666),
3960		SH_PFC_PIN_GROUP(du_rgb888),
3961		SH_PFC_PIN_GROUP(du_clk_out_0),
3962		SH_PFC_PIN_GROUP(du_clk_out_1),
3963		SH_PFC_PIN_GROUP(du_sync_0),
3964		SH_PFC_PIN_GROUP(du_sync_1),
3965		SH_PFC_PIN_GROUP(du_cde),
3966		SH_PFC_PIN_GROUP(du0_clk_in),
3967		SH_PFC_PIN_GROUP(du1_clk_in),
3968		SH_PFC_PIN_GROUP(du2_clk_in),
3969		SH_PFC_PIN_GROUP(eth_link),
3970		SH_PFC_PIN_GROUP(eth_magic),
3971		SH_PFC_PIN_GROUP(eth_mdio),
3972		SH_PFC_PIN_GROUP(eth_rmii),
3973		SH_PFC_PIN_GROUP(hscif0_data),
3974		SH_PFC_PIN_GROUP(hscif0_clk),
3975		SH_PFC_PIN_GROUP(hscif0_ctrl),
3976		SH_PFC_PIN_GROUP(hscif0_data_b),
3977		SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3978		SH_PFC_PIN_GROUP(hscif0_data_c),
3979		SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3980		SH_PFC_PIN_GROUP(hscif0_data_d),
3981		SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3982		SH_PFC_PIN_GROUP(hscif0_data_e),
3983		SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3984		SH_PFC_PIN_GROUP(hscif0_data_f),
3985		SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3986		SH_PFC_PIN_GROUP(hscif1_data),
3987		SH_PFC_PIN_GROUP(hscif1_clk),
3988		SH_PFC_PIN_GROUP(hscif1_ctrl),
3989		SH_PFC_PIN_GROUP(hscif1_data_b),
3990		SH_PFC_PIN_GROUP(hscif1_clk_b),
3991		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3992		SH_PFC_PIN_GROUP(i2c0),
3993		SH_PFC_PIN_GROUP(i2c1),
3994		SH_PFC_PIN_GROUP(i2c1_b),
3995		SH_PFC_PIN_GROUP(i2c1_c),
3996		SH_PFC_PIN_GROUP(i2c2),
3997		SH_PFC_PIN_GROUP(i2c2_b),
3998		SH_PFC_PIN_GROUP(i2c2_c),
3999		SH_PFC_PIN_GROUP(i2c2_d),
4000		SH_PFC_PIN_GROUP(i2c2_e),
4001		SH_PFC_PIN_GROUP(i2c3),
4002		SH_PFC_PIN_GROUP(iic0),
4003		SH_PFC_PIN_GROUP(iic1),
4004		SH_PFC_PIN_GROUP(iic1_b),
4005		SH_PFC_PIN_GROUP(iic1_c),
4006		SH_PFC_PIN_GROUP(iic2),
4007		SH_PFC_PIN_GROUP(iic2_b),
4008		SH_PFC_PIN_GROUP(iic2_c),
4009		SH_PFC_PIN_GROUP(iic2_d),
4010		SH_PFC_PIN_GROUP(iic2_e),
4011		SH_PFC_PIN_GROUP(iic3),
4012		SH_PFC_PIN_GROUP(intc_irq0),
4013		SH_PFC_PIN_GROUP(intc_irq1),
4014		SH_PFC_PIN_GROUP(intc_irq2),
4015		SH_PFC_PIN_GROUP(intc_irq3),
4016		SH_PFC_PIN_GROUP(mmc0_data1),
4017		SH_PFC_PIN_GROUP(mmc0_data4),
4018		SH_PFC_PIN_GROUP(mmc0_data8),
4019		SH_PFC_PIN_GROUP(mmc0_ctrl),
4020		SH_PFC_PIN_GROUP(mmc1_data1),
4021		SH_PFC_PIN_GROUP(mmc1_data4),
4022		SH_PFC_PIN_GROUP(mmc1_data8),
4023		SH_PFC_PIN_GROUP(mmc1_ctrl),
4024		SH_PFC_PIN_GROUP(msiof0_clk),
4025		SH_PFC_PIN_GROUP(msiof0_sync),
4026		SH_PFC_PIN_GROUP(msiof0_ss1),
4027		SH_PFC_PIN_GROUP(msiof0_ss2),
4028		SH_PFC_PIN_GROUP(msiof0_rx),
4029		SH_PFC_PIN_GROUP(msiof0_tx),
4030		SH_PFC_PIN_GROUP(msiof0_clk_b),
4031		SH_PFC_PIN_GROUP(msiof0_ss1_b),
4032		SH_PFC_PIN_GROUP(msiof0_ss2_b),
4033		SH_PFC_PIN_GROUP(msiof0_rx_b),
4034		SH_PFC_PIN_GROUP(msiof0_tx_b),
4035		SH_PFC_PIN_GROUP(msiof1_clk),
4036		SH_PFC_PIN_GROUP(msiof1_sync),
4037		SH_PFC_PIN_GROUP(msiof1_ss1),
4038		SH_PFC_PIN_GROUP(msiof1_ss2),
4039		SH_PFC_PIN_GROUP(msiof1_rx),
4040		SH_PFC_PIN_GROUP(msiof1_tx),
4041		SH_PFC_PIN_GROUP(msiof1_clk_b),
4042		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4043		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4044		SH_PFC_PIN_GROUP(msiof1_rx_b),
4045		SH_PFC_PIN_GROUP(msiof1_tx_b),
4046		SH_PFC_PIN_GROUP(msiof2_clk),
4047		SH_PFC_PIN_GROUP(msiof2_sync),
4048		SH_PFC_PIN_GROUP(msiof2_ss1),
4049		SH_PFC_PIN_GROUP(msiof2_ss2),
4050		SH_PFC_PIN_GROUP(msiof2_rx),
4051		SH_PFC_PIN_GROUP(msiof2_tx),
4052		SH_PFC_PIN_GROUP(msiof3_clk),
4053		SH_PFC_PIN_GROUP(msiof3_sync),
4054		SH_PFC_PIN_GROUP(msiof3_ss1),
4055		SH_PFC_PIN_GROUP(msiof3_ss2),
4056		SH_PFC_PIN_GROUP(msiof3_rx),
4057		SH_PFC_PIN_GROUP(msiof3_tx),
4058		SH_PFC_PIN_GROUP(msiof3_clk_b),
4059		SH_PFC_PIN_GROUP(msiof3_sync_b),
4060		SH_PFC_PIN_GROUP(msiof3_rx_b),
4061		SH_PFC_PIN_GROUP(msiof3_tx_b),
4062		SH_PFC_PIN_GROUP(pwm0),
4063		SH_PFC_PIN_GROUP(pwm0_b),
4064		SH_PFC_PIN_GROUP(pwm1),
4065		SH_PFC_PIN_GROUP(pwm1_b),
4066		SH_PFC_PIN_GROUP(pwm2),
4067		SH_PFC_PIN_GROUP(pwm3),
4068		SH_PFC_PIN_GROUP(pwm4),
4069		SH_PFC_PIN_GROUP(pwm5),
4070		SH_PFC_PIN_GROUP(pwm6),
4071		SH_PFC_PIN_GROUP(qspi_ctrl),
4072		SH_PFC_PIN_GROUP(qspi_data2),
4073		SH_PFC_PIN_GROUP(qspi_data4),
4074		SH_PFC_PIN_GROUP(scif0_data),
4075		SH_PFC_PIN_GROUP(scif0_clk),
4076		SH_PFC_PIN_GROUP(scif0_ctrl),
4077		SH_PFC_PIN_GROUP(scif0_data_b),
4078		SH_PFC_PIN_GROUP(scif1_data),
4079		SH_PFC_PIN_GROUP(scif1_clk),
4080		SH_PFC_PIN_GROUP(scif1_ctrl),
4081		SH_PFC_PIN_GROUP(scif1_data_b),
4082		SH_PFC_PIN_GROUP(scif1_data_c),
4083		SH_PFC_PIN_GROUP(scif1_data_d),
4084		SH_PFC_PIN_GROUP(scif1_clk_d),
4085		SH_PFC_PIN_GROUP(scif1_data_e),
4086		SH_PFC_PIN_GROUP(scif1_clk_e),
4087		SH_PFC_PIN_GROUP(scif2_data),
4088		SH_PFC_PIN_GROUP(scif2_clk),
4089		SH_PFC_PIN_GROUP(scif2_data_b),
4090		SH_PFC_PIN_GROUP(scifa0_data),
4091		SH_PFC_PIN_GROUP(scifa0_clk),
4092		SH_PFC_PIN_GROUP(scifa0_ctrl),
4093		SH_PFC_PIN_GROUP(scifa0_data_b),
4094		SH_PFC_PIN_GROUP(scifa0_clk_b),
4095		SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4096		SH_PFC_PIN_GROUP(scifa1_data),
4097		SH_PFC_PIN_GROUP(scifa1_clk),
4098		SH_PFC_PIN_GROUP(scifa1_ctrl),
4099		SH_PFC_PIN_GROUP(scifa1_data_b),
4100		SH_PFC_PIN_GROUP(scifa1_clk_b),
4101		SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4102		SH_PFC_PIN_GROUP(scifa1_data_c),
4103		SH_PFC_PIN_GROUP(scifa1_clk_c),
4104		SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4105		SH_PFC_PIN_GROUP(scifa1_data_d),
4106		SH_PFC_PIN_GROUP(scifa1_clk_d),
4107		SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4108		SH_PFC_PIN_GROUP(scifa2_data),
4109		SH_PFC_PIN_GROUP(scifa2_clk),
4110		SH_PFC_PIN_GROUP(scifa2_ctrl),
4111		SH_PFC_PIN_GROUP(scifa2_data_b),
4112		SH_PFC_PIN_GROUP(scifa2_data_c),
4113		SH_PFC_PIN_GROUP(scifa2_clk_c),
4114		SH_PFC_PIN_GROUP(scifb0_data),
4115		SH_PFC_PIN_GROUP(scifb0_clk),
4116		SH_PFC_PIN_GROUP(scifb0_ctrl),
4117		SH_PFC_PIN_GROUP(scifb0_data_b),
4118		SH_PFC_PIN_GROUP(scifb0_clk_b),
4119		SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4120		SH_PFC_PIN_GROUP(scifb0_data_c),
4121		SH_PFC_PIN_GROUP(scifb1_data),
4122		SH_PFC_PIN_GROUP(scifb1_clk),
4123		SH_PFC_PIN_GROUP(scifb1_ctrl),
4124		SH_PFC_PIN_GROUP(scifb1_data_b),
4125		SH_PFC_PIN_GROUP(scifb1_clk_b),
4126		SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4127		SH_PFC_PIN_GROUP(scifb1_data_c),
4128		SH_PFC_PIN_GROUP(scifb1_data_d),
4129		SH_PFC_PIN_GROUP(scifb1_data_e),
4130		SH_PFC_PIN_GROUP(scifb1_clk_e),
4131		SH_PFC_PIN_GROUP(scifb1_data_f),
4132		SH_PFC_PIN_GROUP(scifb1_data_g),
4133		SH_PFC_PIN_GROUP(scifb1_clk_g),
4134		SH_PFC_PIN_GROUP(scifb2_data),
4135		SH_PFC_PIN_GROUP(scifb2_clk),
4136		SH_PFC_PIN_GROUP(scifb2_ctrl),
4137		SH_PFC_PIN_GROUP(scifb2_data_b),
4138		SH_PFC_PIN_GROUP(scifb2_clk_b),
4139		SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4140		SH_PFC_PIN_GROUP(scifb2_data_c),
4141		SH_PFC_PIN_GROUP(scif_clk),
4142		SH_PFC_PIN_GROUP(scif_clk_b),
4143		SH_PFC_PIN_GROUP(sdhi0_data1),
4144		SH_PFC_PIN_GROUP(sdhi0_data4),
4145		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4146		SH_PFC_PIN_GROUP(sdhi0_cd),
4147		SH_PFC_PIN_GROUP(sdhi0_wp),
4148		SH_PFC_PIN_GROUP(sdhi1_data1),
4149		SH_PFC_PIN_GROUP(sdhi1_data4),
4150		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4151		SH_PFC_PIN_GROUP(sdhi1_cd),
4152		SH_PFC_PIN_GROUP(sdhi1_wp),
4153		SH_PFC_PIN_GROUP(sdhi2_data1),
4154		SH_PFC_PIN_GROUP(sdhi2_data4),
4155		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4156		SH_PFC_PIN_GROUP(sdhi2_cd),
4157		SH_PFC_PIN_GROUP(sdhi2_wp),
4158		SH_PFC_PIN_GROUP(sdhi3_data1),
4159		SH_PFC_PIN_GROUP(sdhi3_data4),
4160		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4161		SH_PFC_PIN_GROUP(sdhi3_cd),
4162		SH_PFC_PIN_GROUP(sdhi3_wp),
4163		SH_PFC_PIN_GROUP(ssi0_data),
4164		SH_PFC_PIN_GROUP(ssi0129_ctrl),
4165		SH_PFC_PIN_GROUP(ssi1_data),
4166		SH_PFC_PIN_GROUP(ssi1_ctrl),
4167		SH_PFC_PIN_GROUP(ssi2_data),
4168		SH_PFC_PIN_GROUP(ssi2_ctrl),
4169		SH_PFC_PIN_GROUP(ssi3_data),
4170		SH_PFC_PIN_GROUP(ssi34_ctrl),
4171		SH_PFC_PIN_GROUP(ssi4_data),
4172		SH_PFC_PIN_GROUP(ssi4_ctrl),
4173		SH_PFC_PIN_GROUP(ssi5),
4174		SH_PFC_PIN_GROUP(ssi5_b),
4175		SH_PFC_PIN_GROUP(ssi5_c),
4176		SH_PFC_PIN_GROUP(ssi6),
4177		SH_PFC_PIN_GROUP(ssi6_b),
4178		SH_PFC_PIN_GROUP(ssi7_data),
4179		SH_PFC_PIN_GROUP(ssi7_b_data),
4180		SH_PFC_PIN_GROUP(ssi7_c_data),
4181		SH_PFC_PIN_GROUP(ssi78_ctrl),
4182		SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4183		SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4184		SH_PFC_PIN_GROUP(ssi8_data),
4185		SH_PFC_PIN_GROUP(ssi8_b_data),
4186		SH_PFC_PIN_GROUP(ssi8_c_data),
4187		SH_PFC_PIN_GROUP(ssi9_data),
4188		SH_PFC_PIN_GROUP(ssi9_ctrl),
4189		SH_PFC_PIN_GROUP(tpu0_to0),
4190		SH_PFC_PIN_GROUP(tpu0_to1),
4191		SH_PFC_PIN_GROUP(tpu0_to2),
4192		SH_PFC_PIN_GROUP(tpu0_to3),
4193		SH_PFC_PIN_GROUP(usb0),
4194		SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4195		SH_PFC_PIN_GROUP(usb1),
4196		SH_PFC_PIN_GROUP(usb2),
4197		VIN_DATA_PIN_GROUP(vin0_data, 24),
4198		VIN_DATA_PIN_GROUP(vin0_data, 20),
4199		SH_PFC_PIN_GROUP(vin0_data18),
4200		VIN_DATA_PIN_GROUP(vin0_data, 16),
4201		VIN_DATA_PIN_GROUP(vin0_data, 12),
4202		VIN_DATA_PIN_GROUP(vin0_data, 10),
4203		VIN_DATA_PIN_GROUP(vin0_data, 8),
4204		VIN_DATA_PIN_GROUP(vin0_data, 4),
4205		SH_PFC_PIN_GROUP(vin0_sync),
4206		SH_PFC_PIN_GROUP(vin0_field),
4207		SH_PFC_PIN_GROUP(vin0_clkenb),
4208		SH_PFC_PIN_GROUP(vin0_clk),
4209		VIN_DATA_PIN_GROUP(vin1_data, 24),
4210		VIN_DATA_PIN_GROUP(vin1_data, 20),
4211		SH_PFC_PIN_GROUP(vin1_data18),
4212		VIN_DATA_PIN_GROUP(vin1_data, 16),
4213		VIN_DATA_PIN_GROUP(vin1_data, 12),
4214		VIN_DATA_PIN_GROUP(vin1_data, 10),
4215		VIN_DATA_PIN_GROUP(vin1_data, 8),
4216		VIN_DATA_PIN_GROUP(vin1_data, 4),
4217		SH_PFC_PIN_GROUP(vin1_sync),
4218		SH_PFC_PIN_GROUP(vin1_field),
4219		SH_PFC_PIN_GROUP(vin1_clkenb),
4220		SH_PFC_PIN_GROUP(vin1_clk),
4221		VIN_DATA_PIN_GROUP(vin2_data, 24),
4222		SH_PFC_PIN_GROUP(vin2_data18),
4223		VIN_DATA_PIN_GROUP(vin2_data, 16),
4224		VIN_DATA_PIN_GROUP(vin2_data, 8),
4225		VIN_DATA_PIN_GROUP(vin2_data, 4),
4226		SH_PFC_PIN_GROUP(vin2_sync),
4227		SH_PFC_PIN_GROUP(vin2_field),
4228		SH_PFC_PIN_GROUP(vin2_clkenb),
4229		SH_PFC_PIN_GROUP(vin2_clk),
4230		SH_PFC_PIN_GROUP(vin3_data8),
4231		SH_PFC_PIN_GROUP(vin3_sync),
4232		SH_PFC_PIN_GROUP(vin3_field),
4233		SH_PFC_PIN_GROUP(vin3_clkenb),
4234		SH_PFC_PIN_GROUP(vin3_clk),
4235	},
4236	.automotive = {
4237		SH_PFC_PIN_GROUP(mlb_3pin),
4238	}
4239};
4240
4241static const char * const audio_clk_groups[] = {
4242	"audio_clk_a",
4243	"audio_clk_b",
4244	"audio_clk_c",
4245	"audio_clkout",
4246	"audio_clkout_b",
4247	"audio_clkout_c",
4248	"audio_clkout_d",
4249};
4250
4251static const char * const avb_groups[] = {
4252	"avb_link",
4253	"avb_magic",
4254	"avb_phy_int",
4255	"avb_mdio",
4256	"avb_mii",
4257	"avb_gmii",
4258};
4259
4260static const char * const du_groups[] = {
4261	"du_rgb666",
4262	"du_rgb888",
4263	"du_clk_out_0",
4264	"du_clk_out_1",
4265	"du_sync_0",
4266	"du_sync_1",
4267	"du_cde",
4268};
4269
4270static const char * const du0_groups[] = {
4271	"du0_clk_in",
4272};
4273
4274static const char * const du1_groups[] = {
4275	"du1_clk_in",
4276};
4277
4278static const char * const du2_groups[] = {
4279	"du2_clk_in",
4280};
4281
4282static const char * const eth_groups[] = {
4283	"eth_link",
4284	"eth_magic",
4285	"eth_mdio",
4286	"eth_rmii",
4287};
4288
4289static const char * const hscif0_groups[] = {
4290	"hscif0_data",
4291	"hscif0_clk",
4292	"hscif0_ctrl",
4293	"hscif0_data_b",
4294	"hscif0_ctrl_b",
4295	"hscif0_data_c",
4296	"hscif0_ctrl_c",
4297	"hscif0_data_d",
4298	"hscif0_ctrl_d",
4299	"hscif0_data_e",
4300	"hscif0_ctrl_e",
4301	"hscif0_data_f",
4302	"hscif0_ctrl_f",
4303};
4304
4305static const char * const hscif1_groups[] = {
4306	"hscif1_data",
4307	"hscif1_clk",
4308	"hscif1_ctrl",
4309	"hscif1_data_b",
4310	"hscif1_clk_b",
4311	"hscif1_ctrl_b",
4312};
4313
4314static const char * const i2c0_groups[] = {
4315	"i2c0",
4316};
4317
4318static const char * const i2c1_groups[] = {
4319	"i2c1",
4320	"i2c1_b",
4321	"i2c1_c",
4322};
4323
4324static const char * const i2c2_groups[] = {
4325	"i2c2",
4326	"i2c2_b",
4327	"i2c2_c",
4328	"i2c2_d",
4329	"i2c2_e",
4330};
4331
4332static const char * const i2c3_groups[] = {
4333	"i2c3",
4334};
4335
4336static const char * const iic0_groups[] = {
4337	"iic0",
4338};
4339
4340static const char * const iic1_groups[] = {
4341	"iic1",
4342	"iic1_b",
4343	"iic1_c",
4344};
4345
4346static const char * const iic2_groups[] = {
4347	"iic2",
4348	"iic2_b",
4349	"iic2_c",
4350	"iic2_d",
4351	"iic2_e",
4352};
4353
4354static const char * const iic3_groups[] = {
4355	"iic3",
4356};
4357
4358static const char * const intc_groups[] = {
4359	"intc_irq0",
4360	"intc_irq1",
4361	"intc_irq2",
4362	"intc_irq3",
4363};
4364
4365static const char * const mlb_groups[] = {
4366	"mlb_3pin",
4367};
4368
4369static const char * const mmc0_groups[] = {
4370	"mmc0_data1",
4371	"mmc0_data4",
4372	"mmc0_data8",
4373	"mmc0_ctrl",
4374};
4375
4376static const char * const mmc1_groups[] = {
4377	"mmc1_data1",
4378	"mmc1_data4",
4379	"mmc1_data8",
4380	"mmc1_ctrl",
4381};
4382
4383static const char * const msiof0_groups[] = {
4384	"msiof0_clk",
4385	"msiof0_sync",
4386	"msiof0_ss1",
4387	"msiof0_ss2",
4388	"msiof0_rx",
4389	"msiof0_tx",
4390	"msiof0_clk_b",
4391	"msiof0_ss1_b",
4392	"msiof0_ss2_b",
4393	"msiof0_rx_b",
4394	"msiof0_tx_b",
4395};
4396
4397static const char * const msiof1_groups[] = {
4398	"msiof1_clk",
4399	"msiof1_sync",
4400	"msiof1_ss1",
4401	"msiof1_ss2",
4402	"msiof1_rx",
4403	"msiof1_tx",
4404	"msiof1_clk_b",
4405	"msiof1_ss1_b",
4406	"msiof1_ss2_b",
4407	"msiof1_rx_b",
4408	"msiof1_tx_b",
4409};
4410
4411static const char * const msiof2_groups[] = {
4412	"msiof2_clk",
4413	"msiof2_sync",
4414	"msiof2_ss1",
4415	"msiof2_ss2",
4416	"msiof2_rx",
4417	"msiof2_tx",
4418};
4419
4420static const char * const msiof3_groups[] = {
4421	"msiof3_clk",
4422	"msiof3_sync",
4423	"msiof3_ss1",
4424	"msiof3_ss2",
4425	"msiof3_rx",
4426	"msiof3_tx",
4427	"msiof3_clk_b",
4428	"msiof3_sync_b",
4429	"msiof3_rx_b",
4430	"msiof3_tx_b",
4431};
4432
4433static const char * const pwm0_groups[] = {
4434	"pwm0",
4435	"pwm0_b",
4436};
4437
4438static const char * const pwm1_groups[] = {
4439	"pwm1",
4440	"pwm1_b",
4441};
4442
4443static const char * const pwm2_groups[] = {
4444	"pwm2",
4445};
4446
4447static const char * const pwm3_groups[] = {
4448	"pwm3",
4449};
4450
4451static const char * const pwm4_groups[] = {
4452	"pwm4",
4453};
4454
4455static const char * const pwm5_groups[] = {
4456	"pwm5",
4457};
4458
4459static const char * const pwm6_groups[] = {
4460	"pwm6",
4461};
4462
4463static const char * const qspi_groups[] = {
4464	"qspi_ctrl",
4465	"qspi_data2",
4466	"qspi_data4",
4467};
4468
4469static const char * const scif0_groups[] = {
4470	"scif0_data",
4471	"scif0_clk",
4472	"scif0_ctrl",
4473	"scif0_data_b",
4474};
4475
4476static const char * const scif1_groups[] = {
4477	"scif1_data",
4478	"scif1_clk",
4479	"scif1_ctrl",
4480	"scif1_data_b",
4481	"scif1_data_c",
4482	"scif1_data_d",
4483	"scif1_clk_d",
4484	"scif1_data_e",
4485	"scif1_clk_e",
4486};
4487
4488static const char * const scif2_groups[] = {
4489	"scif2_data",
4490	"scif2_clk",
4491	"scif2_data_b",
4492};
4493
4494static const char * const scifa0_groups[] = {
4495	"scifa0_data",
4496	"scifa0_clk",
4497	"scifa0_ctrl",
4498	"scifa0_data_b",
4499	"scifa0_clk_b",
4500	"scifa0_ctrl_b",
4501};
4502
4503static const char * const scifa1_groups[] = {
4504	"scifa1_data",
4505	"scifa1_clk",
4506	"scifa1_ctrl",
4507	"scifa1_data_b",
4508	"scifa1_clk_b",
4509	"scifa1_ctrl_b",
4510	"scifa1_data_c",
4511	"scifa1_clk_c",
4512	"scifa1_ctrl_c",
4513	"scifa1_data_d",
4514	"scifa1_clk_d",
4515	"scifa1_ctrl_d",
4516};
4517
4518static const char * const scifa2_groups[] = {
4519	"scifa2_data",
4520	"scifa2_clk",
4521	"scifa2_ctrl",
4522	"scifa2_data_b",
4523	"scifa2_data_c",
4524	"scifa2_clk_c",
4525};
4526
4527static const char * const scifb0_groups[] = {
4528	"scifb0_data",
4529	"scifb0_clk",
4530	"scifb0_ctrl",
4531	"scifb0_data_b",
4532	"scifb0_clk_b",
4533	"scifb0_ctrl_b",
4534	"scifb0_data_c",
4535};
4536
4537static const char * const scifb1_groups[] = {
4538	"scifb1_data",
4539	"scifb1_clk",
4540	"scifb1_ctrl",
4541	"scifb1_data_b",
4542	"scifb1_clk_b",
4543	"scifb1_ctrl_b",
4544	"scifb1_data_c",
4545	"scifb1_data_d",
4546	"scifb1_data_e",
4547	"scifb1_clk_e",
4548	"scifb1_data_f",
4549	"scifb1_data_g",
4550	"scifb1_clk_g",
4551};
4552
4553static const char * const scifb2_groups[] = {
4554	"scifb2_data",
4555	"scifb2_clk",
4556	"scifb2_ctrl",
4557	"scifb2_data_b",
4558	"scifb2_clk_b",
4559	"scifb2_ctrl_b",
4560	"scifb2_data_c",
4561};
4562
4563static const char * const scif_clk_groups[] = {
4564	"scif_clk",
4565	"scif_clk_b",
4566};
4567
4568static const char * const sdhi0_groups[] = {
4569	"sdhi0_data1",
4570	"sdhi0_data4",
4571	"sdhi0_ctrl",
4572	"sdhi0_cd",
4573	"sdhi0_wp",
4574};
4575
4576static const char * const sdhi1_groups[] = {
4577	"sdhi1_data1",
4578	"sdhi1_data4",
4579	"sdhi1_ctrl",
4580	"sdhi1_cd",
4581	"sdhi1_wp",
4582};
4583
4584static const char * const sdhi2_groups[] = {
4585	"sdhi2_data1",
4586	"sdhi2_data4",
4587	"sdhi2_ctrl",
4588	"sdhi2_cd",
4589	"sdhi2_wp",
4590};
4591
4592static const char * const sdhi3_groups[] = {
4593	"sdhi3_data1",
4594	"sdhi3_data4",
4595	"sdhi3_ctrl",
4596	"sdhi3_cd",
4597	"sdhi3_wp",
4598};
4599
4600static const char * const ssi_groups[] = {
4601	"ssi0_data",
4602	"ssi0129_ctrl",
4603	"ssi1_data",
4604	"ssi1_ctrl",
4605	"ssi2_data",
4606	"ssi2_ctrl",
4607	"ssi3_data",
4608	"ssi34_ctrl",
4609	"ssi4_data",
4610	"ssi4_ctrl",
4611	"ssi5",
4612	"ssi5_b",
4613	"ssi5_c",
4614	"ssi6",
4615	"ssi6_b",
4616	"ssi7_data",
4617	"ssi7_b_data",
4618	"ssi7_c_data",
4619	"ssi78_ctrl",
4620	"ssi78_b_ctrl",
4621	"ssi78_c_ctrl",
4622	"ssi8_data",
4623	"ssi8_b_data",
4624	"ssi8_c_data",
4625	"ssi9_data",
4626	"ssi9_ctrl",
4627};
4628
4629static const char * const tpu0_groups[] = {
4630	"tpu0_to0",
4631	"tpu0_to1",
4632	"tpu0_to2",
4633	"tpu0_to3",
4634};
4635
4636static const char * const usb0_groups[] = {
4637	"usb0",
4638	"usb0_ovc_vbus",
4639};
4640
4641static const char * const usb1_groups[] = {
4642	"usb1",
4643};
4644
4645static const char * const usb2_groups[] = {
4646	"usb2",
4647};
4648
4649static const char * const vin0_groups[] = {
4650	"vin0_data24",
4651	"vin0_data20",
4652	"vin0_data18",
4653	"vin0_data16",
4654	"vin0_data12",
4655	"vin0_data10",
4656	"vin0_data8",
4657	"vin0_data4",
4658	"vin0_sync",
4659	"vin0_field",
4660	"vin0_clkenb",
4661	"vin0_clk",
4662};
4663
4664static const char * const vin1_groups[] = {
4665	"vin1_data24",
4666	"vin1_data20",
4667	"vin1_data18",
4668	"vin1_data16",
4669	"vin1_data12",
4670	"vin1_data10",
4671	"vin1_data8",
4672	"vin1_data4",
4673	"vin1_sync",
4674	"vin1_field",
4675	"vin1_clkenb",
4676	"vin1_clk",
4677};
4678
4679static const char * const vin2_groups[] = {
4680	"vin2_data24",
4681	"vin2_data18",
4682	"vin2_data16",
4683	"vin2_data8",
4684	"vin2_data4",
4685	"vin2_sync",
4686	"vin2_field",
4687	"vin2_clkenb",
4688	"vin2_clk",
4689};
4690
4691static const char * const vin3_groups[] = {
4692	"vin3_data8",
4693	"vin3_sync",
4694	"vin3_field",
4695	"vin3_clkenb",
4696	"vin3_clk",
4697};
4698
4699static const struct {
4700	struct sh_pfc_function common[55];
4701	struct sh_pfc_function automotive[1];
4702} pinmux_functions = {
4703	.common = {
4704		SH_PFC_FUNCTION(audio_clk),
4705		SH_PFC_FUNCTION(avb),
4706		SH_PFC_FUNCTION(du),
4707		SH_PFC_FUNCTION(du0),
4708		SH_PFC_FUNCTION(du1),
4709		SH_PFC_FUNCTION(du2),
4710		SH_PFC_FUNCTION(eth),
4711		SH_PFC_FUNCTION(hscif0),
4712		SH_PFC_FUNCTION(hscif1),
4713		SH_PFC_FUNCTION(i2c0),
4714		SH_PFC_FUNCTION(i2c1),
4715		SH_PFC_FUNCTION(i2c2),
4716		SH_PFC_FUNCTION(i2c3),
4717		SH_PFC_FUNCTION(iic0),
4718		SH_PFC_FUNCTION(iic1),
4719		SH_PFC_FUNCTION(iic2),
4720		SH_PFC_FUNCTION(iic3),
4721		SH_PFC_FUNCTION(intc),
4722		SH_PFC_FUNCTION(mmc0),
4723		SH_PFC_FUNCTION(mmc1),
4724		SH_PFC_FUNCTION(msiof0),
4725		SH_PFC_FUNCTION(msiof1),
4726		SH_PFC_FUNCTION(msiof2),
4727		SH_PFC_FUNCTION(msiof3),
4728		SH_PFC_FUNCTION(pwm0),
4729		SH_PFC_FUNCTION(pwm1),
4730		SH_PFC_FUNCTION(pwm2),
4731		SH_PFC_FUNCTION(pwm3),
4732		SH_PFC_FUNCTION(pwm4),
4733		SH_PFC_FUNCTION(pwm5),
4734		SH_PFC_FUNCTION(pwm6),
4735		SH_PFC_FUNCTION(qspi),
4736		SH_PFC_FUNCTION(scif0),
4737		SH_PFC_FUNCTION(scif1),
4738		SH_PFC_FUNCTION(scif2),
4739		SH_PFC_FUNCTION(scifa0),
4740		SH_PFC_FUNCTION(scifa1),
4741		SH_PFC_FUNCTION(scifa2),
4742		SH_PFC_FUNCTION(scifb0),
4743		SH_PFC_FUNCTION(scifb1),
4744		SH_PFC_FUNCTION(scifb2),
4745		SH_PFC_FUNCTION(scif_clk),
4746		SH_PFC_FUNCTION(sdhi0),
4747		SH_PFC_FUNCTION(sdhi1),
4748		SH_PFC_FUNCTION(sdhi2),
4749		SH_PFC_FUNCTION(sdhi3),
4750		SH_PFC_FUNCTION(ssi),
4751		SH_PFC_FUNCTION(tpu0),
4752		SH_PFC_FUNCTION(usb0),
4753		SH_PFC_FUNCTION(usb1),
4754		SH_PFC_FUNCTION(usb2),
4755		SH_PFC_FUNCTION(vin0),
4756		SH_PFC_FUNCTION(vin1),
4757		SH_PFC_FUNCTION(vin2),
4758		SH_PFC_FUNCTION(vin3),
4759	},
4760	.automotive = {
4761		SH_PFC_FUNCTION(mlb),
4762	}
4763};
4764
4765static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4766	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4767		GP_0_31_FN, FN_IP3_17_15,
4768		GP_0_30_FN, FN_IP3_14_12,
4769		GP_0_29_FN, FN_IP3_11_8,
4770		GP_0_28_FN, FN_IP3_7_4,
4771		GP_0_27_FN, FN_IP3_3_0,
4772		GP_0_26_FN, FN_IP2_28_26,
4773		GP_0_25_FN, FN_IP2_25_22,
4774		GP_0_24_FN, FN_IP2_21_18,
4775		GP_0_23_FN, FN_IP2_17_15,
4776		GP_0_22_FN, FN_IP2_14_12,
4777		GP_0_21_FN, FN_IP2_11_9,
4778		GP_0_20_FN, FN_IP2_8_6,
4779		GP_0_19_FN, FN_IP2_5_3,
4780		GP_0_18_FN, FN_IP2_2_0,
4781		GP_0_17_FN, FN_IP1_29_28,
4782		GP_0_16_FN, FN_IP1_27_26,
4783		GP_0_15_FN, FN_IP1_25_22,
4784		GP_0_14_FN, FN_IP1_21_18,
4785		GP_0_13_FN, FN_IP1_17_15,
4786		GP_0_12_FN, FN_IP1_14_12,
4787		GP_0_11_FN, FN_IP1_11_8,
4788		GP_0_10_FN, FN_IP1_7_4,
4789		GP_0_9_FN, FN_IP1_3_0,
4790		GP_0_8_FN, FN_IP0_30_27,
4791		GP_0_7_FN, FN_IP0_26_23,
4792		GP_0_6_FN, FN_IP0_22_20,
4793		GP_0_5_FN, FN_IP0_19_16,
4794		GP_0_4_FN, FN_IP0_15_12,
4795		GP_0_3_FN, FN_IP0_11_9,
4796		GP_0_2_FN, FN_IP0_8_6,
4797		GP_0_1_FN, FN_IP0_5_3,
4798		GP_0_0_FN, FN_IP0_2_0 ))
4799	},
4800	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4801		0, 0,
4802		0, 0,
4803		GP_1_29_FN, FN_IP6_13_11,
4804		GP_1_28_FN, FN_IP6_10_9,
4805		GP_1_27_FN, FN_IP6_8_6,
4806		GP_1_26_FN, FN_IP6_5_3,
4807		GP_1_25_FN, FN_IP6_2_0,
4808		GP_1_24_FN, FN_IP5_29_27,
4809		GP_1_23_FN, FN_IP5_26_24,
4810		GP_1_22_FN, FN_IP5_23_21,
4811		GP_1_21_FN, FN_IP5_20_18,
4812		GP_1_20_FN, FN_IP5_17_15,
4813		GP_1_19_FN, FN_IP5_14_13,
4814		GP_1_18_FN, FN_IP5_12_10,
4815		GP_1_17_FN, FN_IP5_9_6,
4816		GP_1_16_FN, FN_IP5_5_3,
4817		GP_1_15_FN, FN_IP5_2_0,
4818		GP_1_14_FN, FN_IP4_29_27,
4819		GP_1_13_FN, FN_IP4_26_24,
4820		GP_1_12_FN, FN_IP4_23_21,
4821		GP_1_11_FN, FN_IP4_20_18,
4822		GP_1_10_FN, FN_IP4_17_15,
4823		GP_1_9_FN, FN_IP4_14_12,
4824		GP_1_8_FN, FN_IP4_11_9,
4825		GP_1_7_FN, FN_IP4_8_6,
4826		GP_1_6_FN, FN_IP4_5_3,
4827		GP_1_5_FN, FN_IP4_2_0,
4828		GP_1_4_FN, FN_IP3_31_29,
4829		GP_1_3_FN, FN_IP3_28_26,
4830		GP_1_2_FN, FN_IP3_25_23,
4831		GP_1_1_FN, FN_IP3_22_20,
4832		GP_1_0_FN, FN_IP3_19_18, ))
4833	},
4834	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4835		0, 0,
4836		0, 0,
4837		GP_2_29_FN, FN_IP7_15_13,
4838		GP_2_28_FN, FN_IP7_12_10,
4839		GP_2_27_FN, FN_IP7_9_8,
4840		GP_2_26_FN, FN_IP7_7_6,
4841		GP_2_25_FN, FN_IP7_5_3,
4842		GP_2_24_FN, FN_IP7_2_0,
4843		GP_2_23_FN, FN_IP6_31_29,
4844		GP_2_22_FN, FN_IP6_28_26,
4845		GP_2_21_FN, FN_IP6_25_23,
4846		GP_2_20_FN, FN_IP6_22_20,
4847		GP_2_19_FN, FN_IP6_19_17,
4848		GP_2_18_FN, FN_IP6_16_14,
4849		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4850		GP_2_16_FN, FN_IP8_27,
4851		GP_2_15_FN, FN_IP8_26,
4852		GP_2_14_FN, FN_IP8_25_24,
4853		GP_2_13_FN, FN_IP8_23_22,
4854		GP_2_12_FN, FN_IP8_21_20,
4855		GP_2_11_FN, FN_IP8_19_18,
4856		GP_2_10_FN, FN_IP8_17_16,
4857		GP_2_9_FN, FN_IP8_15_14,
4858		GP_2_8_FN, FN_IP8_13_12,
4859		GP_2_7_FN, FN_IP8_11_10,
4860		GP_2_6_FN, FN_IP8_9_8,
4861		GP_2_5_FN, FN_IP8_7_6,
4862		GP_2_4_FN, FN_IP8_5_4,
4863		GP_2_3_FN, FN_IP8_3_2,
4864		GP_2_2_FN, FN_IP8_1_0,
4865		GP_2_1_FN, FN_IP7_30_29,
4866		GP_2_0_FN, FN_IP7_28_27 ))
4867	},
4868	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4869		GP_3_31_FN, FN_IP11_21_18,
4870		GP_3_30_FN, FN_IP11_17_15,
4871		GP_3_29_FN, FN_IP11_14_13,
4872		GP_3_28_FN, FN_IP11_12_11,
4873		GP_3_27_FN, FN_IP11_10_9,
4874		GP_3_26_FN, FN_IP11_8_7,
4875		GP_3_25_FN, FN_IP11_6_5,
4876		GP_3_24_FN, FN_IP11_4,
4877		GP_3_23_FN, FN_IP11_3_0,
4878		GP_3_22_FN, FN_IP10_29_26,
4879		GP_3_21_FN, FN_IP10_25_23,
4880		GP_3_20_FN, FN_IP10_22_19,
4881		GP_3_19_FN, FN_IP10_18_15,
4882		GP_3_18_FN, FN_IP10_14_11,
4883		GP_3_17_FN, FN_IP10_10_7,
4884		GP_3_16_FN, FN_IP10_6_4,
4885		GP_3_15_FN, FN_IP10_3_0,
4886		GP_3_14_FN, FN_IP9_31_28,
4887		GP_3_13_FN, FN_IP9_27_26,
4888		GP_3_12_FN, FN_IP9_25_24,
4889		GP_3_11_FN, FN_IP9_23_22,
4890		GP_3_10_FN, FN_IP9_21_20,
4891		GP_3_9_FN, FN_IP9_19_18,
4892		GP_3_8_FN, FN_IP9_17_16,
4893		GP_3_7_FN, FN_IP9_15_12,
4894		GP_3_6_FN, FN_IP9_11_8,
4895		GP_3_5_FN, FN_IP9_7_6,
4896		GP_3_4_FN, FN_IP9_5_4,
4897		GP_3_3_FN, FN_IP9_3_2,
4898		GP_3_2_FN, FN_IP9_1_0,
4899		GP_3_1_FN, FN_IP8_30_29,
4900		GP_3_0_FN, FN_IP8_28 ))
4901	},
4902	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4903		GP_4_31_FN, FN_IP14_18_16,
4904		GP_4_30_FN, FN_IP14_15_12,
4905		GP_4_29_FN, FN_IP14_11_9,
4906		GP_4_28_FN, FN_IP14_8_6,
4907		GP_4_27_FN, FN_IP14_5_3,
4908		GP_4_26_FN, FN_IP14_2_0,
4909		GP_4_25_FN, FN_IP13_30_29,
4910		GP_4_24_FN, FN_IP13_28_26,
4911		GP_4_23_FN, FN_IP13_25_23,
4912		GP_4_22_FN, FN_IP13_22_19,
4913		GP_4_21_FN, FN_IP13_18_16,
4914		GP_4_20_FN, FN_IP13_15_13,
4915		GP_4_19_FN, FN_IP13_12_10,
4916		GP_4_18_FN, FN_IP13_9_7,
4917		GP_4_17_FN, FN_IP13_6_3,
4918		GP_4_16_FN, FN_IP13_2_0,
4919		GP_4_15_FN, FN_IP12_30_28,
4920		GP_4_14_FN, FN_IP12_27_25,
4921		GP_4_13_FN, FN_IP12_24_23,
4922		GP_4_12_FN, FN_IP12_22_20,
4923		GP_4_11_FN, FN_IP12_19_17,
4924		GP_4_10_FN, FN_IP12_16_14,
4925		GP_4_9_FN, FN_IP12_13_11,
4926		GP_4_8_FN, FN_IP12_10_8,
4927		GP_4_7_FN, FN_IP12_7_6,
4928		GP_4_6_FN, FN_IP12_5_4,
4929		GP_4_5_FN, FN_IP12_3_2,
4930		GP_4_4_FN, FN_IP12_1_0,
4931		GP_4_3_FN, FN_IP11_31_30,
4932		GP_4_2_FN, FN_IP11_29_27,
4933		GP_4_1_FN, FN_IP11_26_24,
4934		GP_4_0_FN, FN_IP11_23_22 ))
4935	},
4936	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4937		GP_5_31_FN, FN_IP7_24_22,
4938		GP_5_30_FN, FN_IP7_21_19,
4939		GP_5_29_FN, FN_IP7_18_16,
4940		GP_5_28_FN, FN_DU_DOTCLKIN2,
4941		GP_5_27_FN, FN_IP7_26_25,
4942		GP_5_26_FN, FN_DU_DOTCLKIN0,
4943		GP_5_25_FN, FN_AVS2,
4944		GP_5_24_FN, FN_AVS1,
4945		GP_5_23_FN, FN_USB2_OVC,
4946		GP_5_22_FN, FN_USB2_PWEN,
4947		GP_5_21_FN, FN_IP16_7,
4948		GP_5_20_FN, FN_IP16_6,
4949		GP_5_19_FN, FN_USB0_OVC_VBUS,
4950		GP_5_18_FN, FN_USB0_PWEN,
4951		GP_5_17_FN, FN_IP16_5_3,
4952		GP_5_16_FN, FN_IP16_2_0,
4953		GP_5_15_FN, FN_IP15_29_28,
4954		GP_5_14_FN, FN_IP15_27_26,
4955		GP_5_13_FN, FN_IP15_25_23,
4956		GP_5_12_FN, FN_IP15_22_20,
4957		GP_5_11_FN, FN_IP15_19_18,
4958		GP_5_10_FN, FN_IP15_17_16,
4959		GP_5_9_FN, FN_IP15_15_14,
4960		GP_5_8_FN, FN_IP15_13_12,
4961		GP_5_7_FN, FN_IP15_11_9,
4962		GP_5_6_FN, FN_IP15_8_6,
4963		GP_5_5_FN, FN_IP15_5_3,
4964		GP_5_4_FN, FN_IP15_2_0,
4965		GP_5_3_FN, FN_IP14_30_28,
4966		GP_5_2_FN, FN_IP14_27_25,
4967		GP_5_1_FN, FN_IP14_24_22,
4968		GP_5_0_FN, FN_IP14_21_19 ))
4969	},
4970	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4971			     GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
4972			     GROUP(
4973		/* IP0_31 [1] */
4974		0, 0,
4975		/* IP0_30_27 [4] */
4976		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4977		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4978		0, 0, 0, 0, 0, 0, 0, 0, 0,
4979		/* IP0_26_23 [4] */
4980		FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4981		FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4982		FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4983		/* IP0_22_20 [3] */
4984		FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4985		FN_I2C2_SCL_C, 0, 0,
4986		/* IP0_19_16 [4] */
4987		FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4988		FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4989		0, 0, 0, 0, 0, 0, 0, 0, 0,
4990		/* IP0_15_12 [4] */
4991		FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4992		FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4993		0, 0, 0, 0, 0, 0, 0, 0, 0,
4994		/* IP0_11_9 [3] */
4995		FN_D3, FN_MSIOF3_TXD_B,	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4996		0, 0, 0,
4997		/* IP0_8_6 [3] */
4998		FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4999		0, 0, 0,
5000		/* IP0_5_3 [3] */
5001		FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5002		0, 0, 0,
5003		/* IP0_2_0 [3] */
5004		FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5005		0, 0, 0, ))
5006	},
5007	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5008			     GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
5009			     GROUP(
5010		/* IP1_31_30 [2] */
5011		0, 0, 0, 0,
5012		/* IP1_29_28 [2] */
5013		FN_A1, FN_PWM4, 0, 0,
5014		/* IP1_27_26 [2] */
5015		FN_A0, FN_PWM3, 0, 0,
5016		/* IP1_25_22 [4] */
5017		FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5018		FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5019		0, 0, 0, 0, 0, 0, 0, 0, 0,
5020		/* IP1_21_18 [4] */
5021		FN_D14,	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5022		FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5023		0, 0, 0, 0, 0, 0, 0, 0, 0,
5024		/* IP1_17_15 [3] */
5025		FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5026		FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5027		0, 0, 0,
5028		/* IP1_14_12 [3] */
5029		FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5030		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5031		0, 0,
5032		/* IP1_11_8 [4] */
5033		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5034		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5035		0, 0, 0, 0, 0, 0, 0, 0, 0,
5036		/* IP1_7_4 [4] */
5037		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5038		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5039		0, 0, 0, 0, 0, 0, 0, 0, 0,
5040		/* IP1_3_0 [4] */
5041		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5042		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5043		0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5044	},
5045	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5046			     GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5047			     GROUP(
5048		/* IP2_31_29 [3] */
5049		0, 0, 0, 0, 0, 0, 0, 0,
5050		/* IP2_28_26 [3] */
5051		FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5052		FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5053		/* IP2_25_22 [4] */
5054		FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5055		FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5056		0, 0, 0, 0, 0, 0, 0, 0,
5057		/* IP2_21_18 [4] */
5058		FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5059		FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5060		0, 0, 0, 0, 0, 0, 0, 0,
5061		/* IP2_17_15 [3] */
5062		FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5063		0, 0, 0, 0,
5064		/* IP2_14_12 [3] */
5065		FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5066		/* IP2_11_9 [3] */
5067		FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5068		/* IP2_8_6 [3] */
5069		FN_A4, FN_MSIOF1_TXD_B,	FN_TPU0TO0, 0, 0, 0, 0, 0,
5070		/* IP2_5_3 [3] */
5071		FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5072		/* IP2_2_0 [3] */
5073		FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0,	))
5074	},
5075	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5076			     GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5077			     GROUP(
5078		/* IP3_31_29 [3] */
5079		FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5080		0, 0, 0,
5081		/* IP3_28_26 [3] */
5082		FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5083		0, 0, 0, 0,
5084		/* IP3_25_23 [3] */
5085		FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5086		/* IP3_22_20 [3] */
5087		FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5088		/* IP3_19_18 [2] */
5089		FN_A16, FN_ATAWR1_N, 0, 0,
5090		/* IP3_17_15 [3] */
5091		FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5092		0, 0, 0, 0,
5093		/* IP3_14_12 [3] */
5094		FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5095		0, 0, 0, 0,
5096		/* IP3_11_8 [4] */
5097		FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5098		FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5099		FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5100		/* IP3_7_4 [4] */
5101		FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5102		FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5103		0, 0, 0, 0, 0, 0, 0, 0, 0,
5104		/* IP3_3_0 [4] */
5105		FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5106		FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5107		0, 0, 0, 0, 0, 0, 0, 0, ))
5108	},
5109	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5110			     GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5111			     GROUP(
5112		/* IP4_31_30 [2] */
5113		0, 0, 0, 0,
5114		/* IP4_29_27 [3] */
5115		FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5116		FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5117		/* IP4_26_24 [3] */
5118		FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5119		FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5120		/* IP4_23_21 [3] */
5121		FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5122		FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5123		/* IP4_20_18 [3] */
5124		FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5125		FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5126		/* IP4_17_15 [3] */
5127		FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5128		0, 0, 0,
5129		/* IP4_14_12 [3] */
5130		FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5131		FN_VI2_FIELD_B, 0, 0,
5132		/* IP4_11_9 [3] */
5133		FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5134		FN_VI2_CLKENB_B, 0, 0,
5135		/* IP4_8_6 [3] */
5136		FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5137		/* IP4_5_3 [3] */
5138		FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5139		/* IP4_2_0 [3] */
5140		FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5141		))
5142	},
5143	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5144			     GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5145			     GROUP(
5146		/* IP5_31_30 [2] */
5147		0, 0, 0, 0,
5148		/* IP5_29_27 [3] */
5149		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5150		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5151		/* IP5_26_24 [3] */
5152		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5153		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5154		FN_MSIOF0_SCK_B, 0,
5155		/* IP5_23_21 [3] */
5156		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5157		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5158		/* IP5_20_18 [3] */
5159		FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5160		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5161		/* IP5_17_15 [3] */
5162		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5163		FN_INTC_IRQ4_N, 0, 0,
5164		/* IP5_14_13 [2] */
5165		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5166		/* IP5_12_10 [3] */
5167		FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5168		0, 0,
5169		/* IP5_9_6 [4] */
5170		FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5171		FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5172		FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5173		/* IP5_5_3 [3] */
5174		FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5175		FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5176		FN_INTC_EN0_N, FN_I2C1_SCL,
5177		/* IP5_2_0 [3] */
5178		FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5179		FN_VI2_R3, 0, 0, ))
5180	},
5181	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5182			     GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5183			     GROUP(
5184		/* IP6_31_29 [3] */
5185		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5186		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5187		/* IP6_28_26 [3] */
5188		FN_ETH_LINK, 0, FN_HTX0_E,
5189		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5190		/* IP6_25_23 [3] */
5191		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5192		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5193		/* IP6_22_20 [3] */
5194		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5195		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5196		/* IP6_19_17 [3] */
5197		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5198		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5199		/* IP6_16_14 [3] */
5200		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5201		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5202		FN_I2C2_SCL_E, 0,
5203		/* IP6_13_11 [3] */
5204		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5205		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5206		/* IP6_10_9 [2] */
5207		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5208		/* IP6_8_6 [3] */
5209		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5210		FN_SSI_SDATA8_C, 0, 0, 0,
5211		/* IP6_5_3 [3] */
5212		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5213		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5214		/* IP6_2_0 [3] */
5215		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5216		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5217	},
5218	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5219			     GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5220			     GROUP(
5221		/* IP7_31 [1] */
5222		0, 0,
5223		/* IP7_30_29 [2] */
5224		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5225		/* IP7_28_27 [2] */
5226		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5227		/* IP7_26_25 [2] */
5228		FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5229		/* IP7_24_22 [3] */
5230		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5231		0, 0, 0,
5232		/* IP7_21_19 [3] */
5233		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5234		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5235		/* IP7_18_16 [3] */
5236		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5237		FN_GLO_SS_C, 0, 0, 0,
5238		/* IP7_15_13 [3] */
5239		FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5240		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5241		/* IP7_12_10 [3] */
5242		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5243		FN_GLO_SCLK_C, 0, 0, 0,
5244		/* IP7_9_8 [2] */
5245		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5246		/* IP7_7_6 [2] */
5247		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5248		/* IP7_5_3 [3] */
5249		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5250		/* IP7_2_0 [3] */
5251		FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5252		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5253	},
5254	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5255			     GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5256				   2, 2, 2, 2, 2, 2),
5257			     GROUP(
5258		/* IP8_31 [1] */
5259		0, 0,
5260		/* IP8_30_29 [2] */
5261		FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5262		/* IP8_28 [1] */
5263		FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5264		/* IP8_27 [1] */
5265		FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5266		/* IP8_26 [1] */
5267		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5268		/* IP8_25_24 [2] */
5269		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5270		FN_AVB_MAGIC, 0,
5271		/* IP8_23_22 [2] */
5272		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5273		/* IP8_21_20 [2] */
5274		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5275		/* IP8_19_18 [2] */
5276		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5277		/* IP8_17_16 [2] */
5278		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5279		/* IP8_15_14 [2] */
5280		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5281		/* IP8_13_12 [2] */
5282		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5283		/* IP8_11_10 [2] */
5284		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5285		/* IP8_9_8 [2] */
5286		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5287		/* IP8_7_6 [2] */
5288		FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5289		/* IP8_5_4 [2] */
5290		FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5291		/* IP8_3_2 [2] */
5292		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5293		/* IP8_1_0 [2] */
5294		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5295	},
5296	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5297			     GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5298			     GROUP(
5299		/* IP9_31_28 [4] */
5300		FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5301		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5302		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5303		/* IP9_27_26 [2] */
5304		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5305		/* IP9_25_24 [2] */
5306		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5307		/* IP9_23_22 [2] */
5308		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5309		/* IP9_21_20 [2] */
5310		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5311		/* IP9_19_18 [2] */
5312		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5313		/* IP9_17_16 [2] */
5314		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5315		/* IP9_15_12 [4] */
5316		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5317		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5318		FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5319		/* IP9_11_8 [4] */
5320		FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5321		FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5322		FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5323		/* IP9_7_6 [2] */
5324		FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5325		/* IP9_5_4 [2] */
5326		FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5327		/* IP9_3_2 [2] */
5328		FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5329		/* IP9_1_0 [2] */
5330		FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5331	},
5332	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5333			     GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
5334			     GROUP(
5335		/* IP10_31_30 [2] */
5336		0, 0, 0, 0,
5337		/* IP10_29_26 [4] */
5338		FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5339		FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5340		FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5341		/* IP10_25_23 [3] */
5342		FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5343		FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5344		/* IP10_22_19 [4] */
5345		FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5346		FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5347		FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5348		/* IP10_18_15 [4] */
5349		FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5350		FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5351		FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5352		0, 0, 0, 0, 0, 0,
5353		/* IP10_14_11 [4] */
5354		FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5355		FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5356		FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5357		0, 0, 0, 0, 0, 0, 0,
5358		/* IP10_10_7 [4] */
5359		FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5360		FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5361		FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5362		0, 0, 0, 0, 0, 0, 0,
5363		/* IP10_6_4 [3] */
5364		FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5365		FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5366		FN_VI3_DATA0_B, 0,
5367		/* IP10_3_0 [4] */
5368		FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5369		FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5370		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5371	},
5372	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5373			     GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5374			     GROUP(
5375		/* IP11_31_30 [2] */
5376		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5377		/* IP11_29_27 [3] */
5378		FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5379		0, 0, 0,
5380		/* IP11_26_24 [3] */
5381		FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5382		0, 0, 0,
5383		/* IP11_23_22 [2] */
5384		FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5385		/* IP11_21_18 [4] */
5386		FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5387		0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5388		/* IP11_17_15 [3] */
5389		FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5390		FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5391		/* IP11_14_13 [2] */
5392		FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5393		/* IP11_12_11 [2] */
5394		FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5395		/* IP11_10_9 [2] */
5396		FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5397		/* IP11_8_7 [2] */
5398		FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5399		/* IP11_6_5 [2] */
5400		FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5401		/* IP11_4 [1] */
5402		FN_SD3_CLK, FN_MMC1_CLK,
5403		/* IP11_3_0 [4] */
5404		FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5405		FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5406		FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5407	},
5408	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5409			     GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5410			     GROUP(
5411		/* IP12_31 [1] */
5412		0, 0,
5413		/* IP12_30_28 [3] */
5414		FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5415		FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5416		FN_CAN_DEBUGOUT4, 0, 0,
5417		/* IP12_27_25 [3] */
5418		FN_SSI_SCK5, FN_SCIFB1_SCK,
5419		FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5420		FN_CAN_DEBUGOUT3, 0, 0,
5421		/* IP12_24_23 [2] */
5422		FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5423		FN_CAN_DEBUGOUT2,
5424		/* IP12_22_20 [3] */
5425		FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5426		FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5427		/* IP12_19_17 [3] */
5428		FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5429		FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5430		/* IP12_16_14 [3] */
5431		FN_SSI_SDATA3, FN_STP_ISCLK_0,
5432		FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5433		/* IP12_13_11 [3] */
5434		FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5435		FN_CAN_STEP0, 0, 0, 0,
5436		/* IP12_10_8 [3] */
5437		FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5438		FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5439		/* IP12_7_6 [2] */
5440		FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5441		/* IP12_5_4 [2] */
5442		FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5443		/* IP12_3_2 [2] */
5444		FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5445		/* IP12_1_0 [2] */
5446		FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5447	},
5448	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5449			     GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5450			     GROUP(
5451		/* IP13_31 [1] */
5452		0, 0,
5453		/* IP13_30_29 [2] */
5454		FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5455		/* IP13_28_26 [3] */
5456		FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5457		FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5458		/* IP13_25_23 [3] */
5459		FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5460		FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5461		/* IP13_22_19 [4] */
5462		FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5463		FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5464		0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5465		/* IP13_18_16 [3] */
5466		FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5467		FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5468		/* IP13_15_13 [3] */
5469		FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5470		FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5471		/* IP13_12_10 [3] */
5472		FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5473		FN_CAN_DEBUGOUT8, 0, 0,
5474		/* IP13_9_7 [3] */
5475		FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5476		FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5477		/* IP13_6_3 [4] */
5478		FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5479		FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5480		FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5481		/* IP13_2_0 [3] */
5482		FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5483		FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5484	},
5485	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5486			     GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5487			     GROUP(
5488		/* IP14_30 [1] */
5489		0, 0,
5490		/* IP14_30_28 [3] */
5491		FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5492		FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5493		FN_HRTS0_N_C, 0,
5494		/* IP14_27_25 [3] */
5495		FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5496		FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5497		/* IP14_24_22 [3] */
5498		FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5499		FN_LCDOUT9, 0, 0, 0,
5500		/* IP14_21_19 [3] */
5501		FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5502		FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5503		/* IP14_18_16 [3] */
5504		FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5505		FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5506		/* IP14_15_12 [4] */
5507		FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5508		FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5509		0, 0, 0, 0, 0, 0, 0,
5510		/* IP14_11_9 [3] */
5511		FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5512		0, 0, 0,
5513		/* IP14_8_6 [3] */
5514		FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5515		0, 0, 0,
5516		/* IP14_5_3 [3] */
5517		FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5518		FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5519		/* IP14_2_0 [3] */
5520		FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5521		FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5522		FN_REMOCON, 0, ))
5523	},
5524	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5525			     GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5526			     GROUP(
5527		/* IP15_31_30 [2] */
5528		0, 0, 0, 0,
5529		/* IP15_29_28 [2] */
5530		FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5531		/* IP15_27_26 [2] */
5532		FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5533		/* IP15_25_23 [3] */
5534		FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5535		FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5536		/* IP15_22_20 [3] */
5537		FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5538		FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5539		/* IP15_19_18 [2] */
5540		FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5541		/* IP15_17_16 [2] */
5542		FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5543		/* IP15_15_14 [2] */
5544		FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5545		/* IP15_13_12 [2] */
5546		FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5547		/* IP15_11_9 [3] */
5548		FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5549		0, 0, 0,
5550		/* IP15_8_6 [3] */
5551		FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5552		FN_IIC2_SDA, FN_I2C2_SDA, 0,
5553		/* IP15_5_3 [3] */
5554		FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5555		FN_IIC2_SCL, FN_I2C2_SCL, 0,
5556		/* IP15_2_0 [3] */
5557		FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5558		FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5559	},
5560	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5561			     GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
5562			     GROUP(
5563		/* IP16_31_28 [4] */
5564		0, 0, 0, 0, 0, 0, 0, 0,
5565		0, 0, 0, 0, 0, 0, 0, 0,
5566		/* IP16_27_24 [4] */
5567		0, 0, 0, 0, 0, 0, 0, 0,
5568		0, 0, 0, 0, 0, 0, 0, 0,
5569		/* IP16_23_20 [4] */
5570		0, 0, 0, 0, 0, 0, 0, 0,
5571		0, 0, 0, 0, 0, 0, 0, 0,
5572		/* IP16_19_16 [4] */
5573		0, 0, 0, 0, 0, 0, 0, 0,
5574		0, 0, 0, 0, 0, 0, 0, 0,
5575		/* IP16_15_12 [4] */
5576		0, 0, 0, 0, 0, 0, 0, 0,
5577		0, 0, 0, 0, 0, 0, 0, 0,
5578		/* IP16_11_8 [4] */
5579		0, 0, 0, 0, 0, 0, 0, 0,
5580		0, 0, 0, 0, 0, 0, 0, 0,
5581		/* IP16_7 [1] */
5582		FN_USB1_OVC, FN_TCLK1_B,
5583		/* IP16_6 [1] */
5584		FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5585		/* IP16_5_3 [3] */
5586		FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5587		FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5588		/* IP16_2_0 [3] */
5589		FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5590		FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5591	},
5592	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5593			     GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5594				   1, 1, 1, 2, 1, 1, 2, 1, 1),
5595			     GROUP(
5596		/* SEL_SCIF1 [3] */
5597		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5598		FN_SEL_SCIF1_4, 0, 0, 0,
5599		/* SEL_SCIFB [2] */
5600		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5601		/* SEL_SCIFB2 [2] */
5602		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5603		/* SEL_SCIFB1 [3] */
5604		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5605		FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5606		FN_SEL_SCIFB1_6, 0,
5607		/* SEL_SCIFA1 [2] */
5608		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5609		FN_SEL_SCIFA1_3,
5610		/* SEL_SCIF0 [1] */
5611		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5612		/* SEL_SCIFA [1] */
5613		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5614		/* SEL_SOF1 [1] */
5615		FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5616		/* SEL_SSI7 [2] */
5617		FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5618		/* SEL_SSI6 [1] */
5619		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5620		/* SEL_SSI5 [2] */
5621		FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5622		/* SEL_VI3 [1] */
5623		FN_SEL_VI3_0, FN_SEL_VI3_1,
5624		/* SEL_VI2 [1] */
5625		FN_SEL_VI2_0, FN_SEL_VI2_1,
5626		/* SEL_VI1 [1] */
5627		FN_SEL_VI1_0, FN_SEL_VI1_1,
5628		/* SEL_VI0 [1] */
5629		FN_SEL_VI0_0, FN_SEL_VI0_1,
5630		/* SEL_TSIF1 [2] */
5631		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5632		/* RESERVED [1] */
5633		0, 0,
5634		/* SEL_LBS [1] */
5635		FN_SEL_LBS_0, FN_SEL_LBS_1,
5636		/* SEL_TSIF0 [2] */
5637		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5638		/* SEL_SOF3 [1] */
5639		FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5640		/* SEL_SOF0 [1] */
5641		FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5642	},
5643	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5644			     GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
5645				   3, 3, 2, 3, 2, 2),
5646			     GROUP(
5647		/* RESERVED [3] */
5648		0, 0, 0, 0, 0, 0, 0, 0,
5649		/* SEL_TMU1 [1] */
5650		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5651		/* SEL_HSCIF1 [1] */
5652		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5653		/* SEL_SCIFCLK [1] */
5654		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5655		/* SEL_CAN0 [2] */
5656		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5657		/* SEL_CANCLK [1] */
5658		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5659		/* SEL_SCIFA2 [2] */
5660		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5661		/* SEL_CAN1 [1] */
5662		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5663		/* RESERVED [2] */
5664		0, 0, 0, 0,
5665		/* SEL_SCIF2 [1] */
5666		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5667		/* SEL_ADI [1] */
5668		FN_SEL_ADI_0, FN_SEL_ADI_1,
5669		/* SEL_SSP [1] */
5670		FN_SEL_SSP_0, FN_SEL_SSP_1,
5671		/* SEL_FM [3] */
5672		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5673		FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5674		/* SEL_HSCIF0 [3] */
5675		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5676		FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5677		/* SEL_GPS [2] */
5678		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5679		/* RESERVED [3] */
5680		0, 0, 0, 0, 0, 0, 0, 0,
5681		/* SEL_SIM [2] */
5682		FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5683		/* SEL_SSI8 [2] */
5684		FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5685	},
5686	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5687			     GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
5688			     GROUP(
5689		/* SEL_IICDVFS [1] */
5690		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5691		/* SEL_IIC0 [1] */
5692		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5693		/* RESERVED [2] */
5694		0, 0, 0, 0,
5695		/* RESERVED [4] */
5696		0, 0, 0, 0, 0, 0, 0, 0,
5697		0, 0, 0, 0, 0, 0, 0, 0,
5698		/* RESERVED [4] */
5699		0, 0, 0, 0, 0, 0, 0, 0,
5700		0, 0, 0, 0, 0, 0, 0, 0,
5701		/* RESERVED [2] */
5702		0, 0, 0, 0,
5703		/* SEL_IEB [2] */
5704		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5705		/* RESERVED [4] */
5706		0, 0, 0, 0, 0, 0, 0, 0,
5707		0, 0, 0, 0, 0, 0, 0, 0,
5708		/* RESERVED [2] */
5709		0, 0, 0, 0,
5710		/* SEL_IIC2 [3] */
5711		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5712		FN_SEL_IIC2_4, 0, 0, 0,
5713		/* SEL_IIC1 [2] */
5714		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5715		/* SEL_I2C2 [3] */
5716		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5717		FN_SEL_I2C2_4, 0, 0, 0,
5718		/* SEL_I2C1 [2] */
5719		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5720	},
5721	{ },
5722};
5723
5724static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5725{
5726	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5727		return -EINVAL;
5728
5729	*pocctrl = 0xe606008c;
5730
5731	return 31 - (pin & 0x1f);
5732}
5733
5734static const struct soc_device_attribute r8a7790_tdsel[] = {
5735	{ .soc_id = "r8a7790", .revision = "ES1.0" },
5736	{ /* sentinel */ }
5737};
5738
5739static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
5740{
5741	/* Initialize TDSEL on old revisions */
5742	if (soc_device_match(r8a7790_tdsel))
5743		sh_pfc_write(pfc, 0xe6060088, 0x00155554);
5744
5745	return 0;
5746}
5747
5748static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
5749	.init = r8a7790_pinmux_soc_init,
5750	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
5751};
5752
5753#ifdef CONFIG_PINCTRL_PFC_R8A7742
5754const struct sh_pfc_soc_info r8a7742_pinmux_info = {
5755	.name = "r8a77420_pfc",
5756	.ops = &r8a7790_pinmux_ops,
5757	.unlock_reg = 0xe6060000, /* PMMR */
5758
5759	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5760
5761	.pins = pinmux_pins,
5762	.nr_pins = ARRAY_SIZE(pinmux_pins),
5763	.groups = pinmux_groups.common,
5764	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
5765	.functions = pinmux_functions.common,
5766	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
5767
5768	.cfg_regs = pinmux_config_regs,
5769
5770	.pinmux_data = pinmux_data,
5771	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
5772};
5773#endif
5774
5775#ifdef CONFIG_PINCTRL_PFC_R8A7790
5776const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5777	.name = "r8a77900_pfc",
5778	.ops = &r8a7790_pinmux_ops,
5779	.unlock_reg = 0xe6060000, /* PMMR */
5780
5781	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5782
5783	.pins = pinmux_pins,
5784	.nr_pins = ARRAY_SIZE(pinmux_pins),
5785	.groups = pinmux_groups.common,
5786	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5787		ARRAY_SIZE(pinmux_groups.automotive),
5788	.functions = pinmux_functions.common,
5789	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5790		ARRAY_SIZE(pinmux_functions.automotive),
5791
5792	.cfg_regs = pinmux_config_regs,
5793
5794	.pinmux_data = pinmux_data,
5795	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
5796};
5797#endif