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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the Atmel PIO4 controller
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9#include <dt-bindings/pinctrl/at91.h>
10#include <linux/clk.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/slab.h>
22#include "core.h"
23#include "pinconf.h"
24#include "pinctrl-utils.h"
25
26/*
27 * Warning:
28 * In order to not introduce confusion between Atmel PIO groups and pinctrl
29 * framework groups, Atmel PIO groups will be called banks, line is kept to
30 * designed the pin id into this bank.
31 */
32
33#define ATMEL_PIO_MSKR 0x0000
34#define ATMEL_PIO_CFGR 0x0004
35#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
36#define ATMEL_PIO_DIR_MASK BIT(8)
37#define ATMEL_PIO_PUEN_MASK BIT(9)
38#define ATMEL_PIO_PDEN_MASK BIT(10)
39#define ATMEL_PIO_IFEN_MASK BIT(12)
40#define ATMEL_PIO_IFSCEN_MASK BIT(13)
41#define ATMEL_PIO_OPD_MASK BIT(14)
42#define ATMEL_PIO_SCHMITT_MASK BIT(15)
43#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
44#define ATMEL_PIO_DRVSTR_OFFSET 16
45#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
46#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
47#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
48#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
49#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
50#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
51#define ATMEL_PIO_PDSR 0x0008
52#define ATMEL_PIO_LOCKSR 0x000C
53#define ATMEL_PIO_SODR 0x0010
54#define ATMEL_PIO_CODR 0x0014
55#define ATMEL_PIO_ODSR 0x0018
56#define ATMEL_PIO_IER 0x0020
57#define ATMEL_PIO_IDR 0x0024
58#define ATMEL_PIO_IMR 0x0028
59#define ATMEL_PIO_ISR 0x002C
60#define ATMEL_PIO_IOFR 0x003C
61
62#define ATMEL_PIO_NPINS_PER_BANK 32
63#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
64#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
65#define ATMEL_PIO_BANK_OFFSET 0x40
66
67#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
68#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
69#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
70
71/* Custom pinconf parameters */
72#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
73
74struct atmel_pioctrl_data {
75 unsigned nbanks;
76};
77
78struct atmel_group {
79 const char *name;
80 u32 pin;
81};
82
83struct atmel_pin {
84 unsigned pin_id;
85 unsigned mux;
86 unsigned ioset;
87 unsigned bank;
88 unsigned line;
89 const char *device;
90};
91
92/**
93 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
94 * @reg_base: base address of the controller.
95 * @clk: clock of the controller.
96 * @nbanks: number of PIO groups, it can vary depending on the SoC.
97 * @pinctrl_dev: pinctrl device registered.
98 * @groups: groups table to provide group name and pin in the group to pinctrl.
99 * @group_names: group names table to provide all the group/pin names to
100 * pinctrl or gpio.
101 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
102 * fields are set at probe time. Other ones are set when parsing dt
103 * pinctrl.
104 * @npins: number of pins.
105 * @gpio_chip: gpio chip registered.
106 * @irq_domain: irq domain for the gpio controller.
107 * @irqs: table containing the hw irq number of the bank. The index of the
108 * table is the bank id.
109 * @pm_wakeup_sources: bitmap of wakeup sources (lines)
110 * @pm_suspend_backup: backup/restore register values on suspend/resume
111 * @dev: device entry for the Atmel PIO controller.
112 * @node: node of the Atmel PIO controller.
113 */
114struct atmel_pioctrl {
115 void __iomem *reg_base;
116 struct clk *clk;
117 unsigned nbanks;
118 struct pinctrl_dev *pinctrl_dev;
119 struct atmel_group *groups;
120 const char * const *group_names;
121 struct atmel_pin **pins;
122 unsigned npins;
123 struct gpio_chip *gpio_chip;
124 struct irq_domain *irq_domain;
125 int *irqs;
126 unsigned *pm_wakeup_sources;
127 struct {
128 u32 imr;
129 u32 odsr;
130 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
131 } *pm_suspend_backup;
132 struct device *dev;
133 struct device_node *node;
134};
135
136static const char * const atmel_functions[] = {
137 "GPIO", "A", "B", "C", "D", "E", "F", "G"
138};
139
140static const struct pinconf_generic_params atmel_custom_bindings[] = {
141 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
142};
143
144/* --- GPIO --- */
145static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
146 unsigned int bank, unsigned int reg)
147{
148 return readl_relaxed(atmel_pioctrl->reg_base
149 + ATMEL_PIO_BANK_OFFSET * bank + reg);
150}
151
152static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
153 unsigned int bank, unsigned int reg,
154 unsigned int val)
155{
156 writel_relaxed(val, atmel_pioctrl->reg_base
157 + ATMEL_PIO_BANK_OFFSET * bank + reg);
158}
159
160static void atmel_gpio_irq_ack(struct irq_data *d)
161{
162 /*
163 * Nothing to do, interrupt is cleared when reading the status
164 * register.
165 */
166}
167
168static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
169{
170 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
171 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
172 unsigned reg;
173
174 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
175 BIT(pin->line));
176 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
177 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
178
179 switch (type) {
180 case IRQ_TYPE_EDGE_RISING:
181 irq_set_handler_locked(d, handle_edge_irq);
182 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 irq_set_handler_locked(d, handle_edge_irq);
186 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 irq_set_handler_locked(d, handle_edge_irq);
190 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
191 break;
192 case IRQ_TYPE_LEVEL_LOW:
193 irq_set_handler_locked(d, handle_level_irq);
194 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
195 break;
196 case IRQ_TYPE_LEVEL_HIGH:
197 irq_set_handler_locked(d, handle_level_irq);
198 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
199 break;
200 case IRQ_TYPE_NONE:
201 default:
202 return -EINVAL;
203 }
204
205 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
206
207 return 0;
208}
209
210static void atmel_gpio_irq_mask(struct irq_data *d)
211{
212 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
213 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
214
215 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
216 BIT(pin->line));
217}
218
219static void atmel_gpio_irq_unmask(struct irq_data *d)
220{
221 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
222 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
223
224 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
225 BIT(pin->line));
226}
227
228#ifdef CONFIG_PM_SLEEP
229
230static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
231{
232 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
233 int bank = ATMEL_PIO_BANK(d->hwirq);
234 int line = ATMEL_PIO_LINE(d->hwirq);
235
236 /* The gpio controller has one interrupt line per bank. */
237 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
238
239 if (on)
240 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
241 else
242 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
243
244 return 0;
245}
246#else
247#define atmel_gpio_irq_set_wake NULL
248#endif /* CONFIG_PM_SLEEP */
249
250static struct irq_chip atmel_gpio_irq_chip = {
251 .name = "GPIO",
252 .irq_ack = atmel_gpio_irq_ack,
253 .irq_mask = atmel_gpio_irq_mask,
254 .irq_unmask = atmel_gpio_irq_unmask,
255 .irq_set_type = atmel_gpio_irq_set_type,
256 .irq_set_wake = atmel_gpio_irq_set_wake,
257};
258
259static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
260{
261 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
262
263 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
264}
265
266static void atmel_gpio_irq_handler(struct irq_desc *desc)
267{
268 unsigned int irq = irq_desc_get_irq(desc);
269 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
270 struct irq_chip *chip = irq_desc_get_chip(desc);
271 unsigned long isr;
272 int n, bank = -1;
273
274 /* Find from which bank is the irq received. */
275 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
276 if (atmel_pioctrl->irqs[n] == irq) {
277 bank = n;
278 break;
279 }
280 }
281
282 if (bank < 0) {
283 dev_err(atmel_pioctrl->dev,
284 "no bank associated to irq %u\n", irq);
285 return;
286 }
287
288 chained_irq_enter(chip, desc);
289
290 for (;;) {
291 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
292 ATMEL_PIO_ISR);
293 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
294 ATMEL_PIO_IMR);
295 if (!isr)
296 break;
297
298 for_each_set_bit(n, &isr, BITS_PER_LONG)
299 generic_handle_irq(atmel_gpio_to_irq(
300 atmel_pioctrl->gpio_chip,
301 bank * ATMEL_PIO_NPINS_PER_BANK + n));
302 }
303
304 chained_irq_exit(chip, desc);
305}
306
307static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
308{
309 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
310 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
311 unsigned reg;
312
313 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
314 BIT(pin->line));
315 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
316 reg &= ~ATMEL_PIO_DIR_MASK;
317 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
318
319 return 0;
320}
321
322static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
323{
324 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
325 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
326 unsigned reg;
327
328 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
329
330 return !!(reg & BIT(pin->line));
331}
332
333static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
334 unsigned long *bits)
335{
336 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
337 unsigned int bank;
338
339 bitmap_zero(bits, atmel_pioctrl->npins);
340
341 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
342 unsigned int word = bank;
343 unsigned int offset = 0;
344 unsigned int reg;
345
346#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
347 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
348 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
349#endif
350 if (!mask[word])
351 continue;
352
353 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
354 bits[word] |= mask[word] & (reg << offset);
355 }
356
357 return 0;
358}
359
360static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
361 int value)
362{
363 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
364 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
365 unsigned reg;
366
367 atmel_gpio_write(atmel_pioctrl, pin->bank,
368 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
369 BIT(pin->line));
370
371 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
372 BIT(pin->line));
373 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
374 reg |= ATMEL_PIO_DIR_MASK;
375 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
376
377 return 0;
378}
379
380static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
381{
382 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
383 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
384
385 atmel_gpio_write(atmel_pioctrl, pin->bank,
386 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
387 BIT(pin->line));
388}
389
390static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
391 unsigned long *bits)
392{
393 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
394 unsigned int bank;
395
396 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
397 unsigned int bitmask;
398 unsigned int word = bank;
399
400/*
401 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
402 * two 32bit words to handle the whole bitmask
403 */
404#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
405 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
406#endif
407 if (!mask[word])
408 continue;
409
410 bitmask = mask[word] & bits[word];
411 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
412
413 bitmask = mask[word] & ~bits[word];
414 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
415
416#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
417 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
418 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
419#endif
420 }
421}
422
423static struct gpio_chip atmel_gpio_chip = {
424 .direction_input = atmel_gpio_direction_input,
425 .get = atmel_gpio_get,
426 .get_multiple = atmel_gpio_get_multiple,
427 .direction_output = atmel_gpio_direction_output,
428 .set = atmel_gpio_set,
429 .set_multiple = atmel_gpio_set_multiple,
430 .to_irq = atmel_gpio_to_irq,
431 .base = 0,
432};
433
434/* --- PINCTRL --- */
435static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
436 unsigned pin_id)
437{
438 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
439 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
440 unsigned line = atmel_pioctrl->pins[pin_id]->line;
441 void __iomem *addr = atmel_pioctrl->reg_base
442 + bank * ATMEL_PIO_BANK_OFFSET;
443
444 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
445 /* Have to set MSKR first, to access the right pin CFGR. */
446 wmb();
447
448 return readl_relaxed(addr + ATMEL_PIO_CFGR);
449}
450
451static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
452 unsigned pin_id, u32 conf)
453{
454 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
455 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
456 unsigned line = atmel_pioctrl->pins[pin_id]->line;
457 void __iomem *addr = atmel_pioctrl->reg_base
458 + bank * ATMEL_PIO_BANK_OFFSET;
459
460 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
461 /* Have to set MSKR first, to access the right pin CFGR. */
462 wmb();
463 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
464}
465
466static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
467{
468 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
469
470 return atmel_pioctrl->npins;
471}
472
473static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
474 unsigned selector)
475{
476 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
477
478 return atmel_pioctrl->groups[selector].name;
479}
480
481static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
482 unsigned selector, const unsigned **pins,
483 unsigned *num_pins)
484{
485 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
486
487 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
488 *num_pins = 1;
489
490 return 0;
491}
492
493static struct atmel_group *
494atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
495{
496 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
497 int i;
498
499 for (i = 0; i < atmel_pioctrl->npins; i++) {
500 struct atmel_group *grp = atmel_pioctrl->groups + i;
501
502 if (grp->pin == pin)
503 return grp;
504 }
505
506 return NULL;
507}
508
509static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
510 struct device_node *np,
511 u32 pinfunc, const char **grp_name,
512 const char **func_name)
513{
514 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
515 unsigned pin_id, func_id;
516 struct atmel_group *grp;
517
518 pin_id = ATMEL_GET_PIN_NO(pinfunc);
519 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
520
521 if (func_id >= ARRAY_SIZE(atmel_functions))
522 return -EINVAL;
523
524 *func_name = atmel_functions[func_id];
525
526 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
527 if (!grp)
528 return -EINVAL;
529 *grp_name = grp->name;
530
531 atmel_pioctrl->pins[pin_id]->mux = func_id;
532 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
533 /* Want the device name not the group one. */
534 if (np->parent == atmel_pioctrl->node)
535 atmel_pioctrl->pins[pin_id]->device = np->name;
536 else
537 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
538
539 return 0;
540}
541
542static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
543 struct device_node *np,
544 struct pinctrl_map **map,
545 unsigned *reserved_maps,
546 unsigned *num_maps)
547{
548 unsigned num_pins, num_configs, reserve;
549 unsigned long *configs;
550 struct property *pins;
551 u32 pinfunc;
552 int ret, i;
553
554 pins = of_find_property(np, "pinmux", NULL);
555 if (!pins)
556 return -EINVAL;
557
558 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
559 &num_configs);
560 if (ret < 0) {
561 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
562 np);
563 return ret;
564 }
565
566 num_pins = pins->length / sizeof(u32);
567 if (!num_pins) {
568 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
569 ret = -EINVAL;
570 goto exit;
571 }
572
573 /*
574 * Reserve maps, at least there is a mux map and an optional conf
575 * map for each pin.
576 */
577 reserve = 1;
578 if (num_configs)
579 reserve++;
580 reserve *= num_pins;
581 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
582 reserve);
583 if (ret < 0)
584 goto exit;
585
586 for (i = 0; i < num_pins; i++) {
587 const char *group, *func;
588
589 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
590 if (ret)
591 goto exit;
592
593 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
594 &func);
595 if (ret)
596 goto exit;
597
598 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
599 group, func);
600
601 if (num_configs) {
602 ret = pinctrl_utils_add_map_configs(pctldev, map,
603 reserved_maps, num_maps, group,
604 configs, num_configs,
605 PIN_MAP_TYPE_CONFIGS_GROUP);
606 if (ret < 0)
607 goto exit;
608 }
609 }
610
611exit:
612 kfree(configs);
613 return ret;
614}
615
616static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
617 struct device_node *np_config,
618 struct pinctrl_map **map,
619 unsigned *num_maps)
620{
621 struct device_node *np;
622 unsigned reserved_maps;
623 int ret;
624
625 *map = NULL;
626 *num_maps = 0;
627 reserved_maps = 0;
628
629 /*
630 * If all the pins of a device have the same configuration (or no one),
631 * it is useless to add a subnode, so directly parse node referenced by
632 * phandle.
633 */
634 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
635 &reserved_maps, num_maps);
636 if (ret) {
637 for_each_child_of_node(np_config, np) {
638 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
639 &reserved_maps, num_maps);
640 if (ret < 0) {
641 of_node_put(np);
642 break;
643 }
644 }
645 }
646
647 if (ret < 0) {
648 pinctrl_utils_free_map(pctldev, *map, *num_maps);
649 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
650 np_config);
651 }
652
653 return ret;
654}
655
656static const struct pinctrl_ops atmel_pctlops = {
657 .get_groups_count = atmel_pctl_get_groups_count,
658 .get_group_name = atmel_pctl_get_group_name,
659 .get_group_pins = atmel_pctl_get_group_pins,
660 .dt_node_to_map = atmel_pctl_dt_node_to_map,
661 .dt_free_map = pinctrl_utils_free_map,
662};
663
664static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
665{
666 return ARRAY_SIZE(atmel_functions);
667}
668
669static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
670 unsigned selector)
671{
672 return atmel_functions[selector];
673}
674
675static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
676 unsigned selector,
677 const char * const **groups,
678 unsigned * const num_groups)
679{
680 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
681
682 *groups = atmel_pioctrl->group_names;
683 *num_groups = atmel_pioctrl->npins;
684
685 return 0;
686}
687
688static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
689 unsigned function,
690 unsigned group)
691{
692 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
693 unsigned pin;
694 u32 conf;
695
696 dev_dbg(pctldev->dev, "enable function %s group %s\n",
697 atmel_functions[function], atmel_pioctrl->groups[group].name);
698
699 pin = atmel_pioctrl->groups[group].pin;
700 conf = atmel_pin_config_read(pctldev, pin);
701 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
702 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
703 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
704 atmel_pin_config_write(pctldev, pin, conf);
705
706 return 0;
707}
708
709static const struct pinmux_ops atmel_pmxops = {
710 .get_functions_count = atmel_pmx_get_functions_count,
711 .get_function_name = atmel_pmx_get_function_name,
712 .get_function_groups = atmel_pmx_get_function_groups,
713 .set_mux = atmel_pmx_set_mux,
714};
715
716static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
717 unsigned group,
718 unsigned long *config)
719{
720 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
721 unsigned param = pinconf_to_config_param(*config), arg = 0;
722 struct atmel_group *grp = atmel_pioctrl->groups + group;
723 unsigned pin_id = grp->pin;
724 u32 res;
725
726 res = atmel_pin_config_read(pctldev, pin_id);
727
728 switch (param) {
729 case PIN_CONFIG_BIAS_PULL_UP:
730 if (!(res & ATMEL_PIO_PUEN_MASK))
731 return -EINVAL;
732 arg = 1;
733 break;
734 case PIN_CONFIG_BIAS_PULL_DOWN:
735 if ((res & ATMEL_PIO_PUEN_MASK) ||
736 (!(res & ATMEL_PIO_PDEN_MASK)))
737 return -EINVAL;
738 arg = 1;
739 break;
740 case PIN_CONFIG_BIAS_DISABLE:
741 if ((res & ATMEL_PIO_PUEN_MASK) ||
742 ((res & ATMEL_PIO_PDEN_MASK)))
743 return -EINVAL;
744 arg = 1;
745 break;
746 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
747 if (!(res & ATMEL_PIO_OPD_MASK))
748 return -EINVAL;
749 arg = 1;
750 break;
751 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
752 if (!(res & ATMEL_PIO_SCHMITT_MASK))
753 return -EINVAL;
754 arg = 1;
755 break;
756 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
757 if (!(res & ATMEL_PIO_DRVSTR_MASK))
758 return -EINVAL;
759 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
760 break;
761 default:
762 return -ENOTSUPP;
763 }
764
765 *config = pinconf_to_config_packed(param, arg);
766 return 0;
767}
768
769static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
770 unsigned group,
771 unsigned long *configs,
772 unsigned num_configs)
773{
774 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
775 struct atmel_group *grp = atmel_pioctrl->groups + group;
776 unsigned bank, pin, pin_id = grp->pin;
777 u32 mask, conf = 0;
778 int i;
779
780 conf = atmel_pin_config_read(pctldev, pin_id);
781
782 for (i = 0; i < num_configs; i++) {
783 unsigned param = pinconf_to_config_param(configs[i]);
784 unsigned arg = pinconf_to_config_argument(configs[i]);
785
786 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
787 __func__, pin_id, configs[i]);
788
789 switch (param) {
790 case PIN_CONFIG_BIAS_DISABLE:
791 conf &= (~ATMEL_PIO_PUEN_MASK);
792 conf &= (~ATMEL_PIO_PDEN_MASK);
793 break;
794 case PIN_CONFIG_BIAS_PULL_UP:
795 conf |= ATMEL_PIO_PUEN_MASK;
796 conf &= (~ATMEL_PIO_PDEN_MASK);
797 break;
798 case PIN_CONFIG_BIAS_PULL_DOWN:
799 conf |= ATMEL_PIO_PDEN_MASK;
800 conf &= (~ATMEL_PIO_PUEN_MASK);
801 break;
802 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
803 if (arg == 0)
804 conf &= (~ATMEL_PIO_OPD_MASK);
805 else
806 conf |= ATMEL_PIO_OPD_MASK;
807 break;
808 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
809 if (arg == 0)
810 conf |= ATMEL_PIO_SCHMITT_MASK;
811 else
812 conf &= (~ATMEL_PIO_SCHMITT_MASK);
813 break;
814 case PIN_CONFIG_INPUT_DEBOUNCE:
815 if (arg == 0) {
816 conf &= (~ATMEL_PIO_IFEN_MASK);
817 conf &= (~ATMEL_PIO_IFSCEN_MASK);
818 } else {
819 /*
820 * We don't care about the debounce value for several reasons:
821 * - can't have different debounce periods inside a same group,
822 * - the register to configure this period is a secure register.
823 * The debouncing filter can filter a pulse with a duration of less
824 * than 1/2 slow clock period.
825 */
826 conf |= ATMEL_PIO_IFEN_MASK;
827 conf |= ATMEL_PIO_IFSCEN_MASK;
828 }
829 break;
830 case PIN_CONFIG_OUTPUT:
831 conf |= ATMEL_PIO_DIR_MASK;
832 bank = ATMEL_PIO_BANK(pin_id);
833 pin = ATMEL_PIO_LINE(pin_id);
834 mask = 1 << pin;
835
836 if (arg == 0) {
837 writel_relaxed(mask, atmel_pioctrl->reg_base +
838 bank * ATMEL_PIO_BANK_OFFSET +
839 ATMEL_PIO_CODR);
840 } else {
841 writel_relaxed(mask, atmel_pioctrl->reg_base +
842 bank * ATMEL_PIO_BANK_OFFSET +
843 ATMEL_PIO_SODR);
844 }
845 break;
846 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
847 switch (arg) {
848 case ATMEL_PIO_DRVSTR_LO:
849 case ATMEL_PIO_DRVSTR_ME:
850 case ATMEL_PIO_DRVSTR_HI:
851 conf &= (~ATMEL_PIO_DRVSTR_MASK);
852 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
853 break;
854 default:
855 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
856 }
857 break;
858 default:
859 dev_warn(pctldev->dev,
860 "unsupported configuration parameter: %u\n",
861 param);
862 continue;
863 }
864 }
865
866 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
867 atmel_pin_config_write(pctldev, pin_id, conf);
868
869 return 0;
870}
871
872static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
873 struct seq_file *s, unsigned pin_id)
874{
875 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
876 u32 conf;
877
878 if (!atmel_pioctrl->pins[pin_id]->device)
879 return;
880
881 if (atmel_pioctrl->pins[pin_id])
882 seq_printf(s, " (%s, ioset %u) ",
883 atmel_pioctrl->pins[pin_id]->device,
884 atmel_pioctrl->pins[pin_id]->ioset);
885
886 conf = atmel_pin_config_read(pctldev, pin_id);
887 if (conf & ATMEL_PIO_PUEN_MASK)
888 seq_printf(s, "%s ", "pull-up");
889 if (conf & ATMEL_PIO_PDEN_MASK)
890 seq_printf(s, "%s ", "pull-down");
891 if (conf & ATMEL_PIO_IFEN_MASK)
892 seq_printf(s, "%s ", "debounce");
893 if (conf & ATMEL_PIO_OPD_MASK)
894 seq_printf(s, "%s ", "open-drain");
895 if (conf & ATMEL_PIO_SCHMITT_MASK)
896 seq_printf(s, "%s ", "schmitt");
897 if (conf & ATMEL_PIO_DRVSTR_MASK) {
898 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
899 case ATMEL_PIO_DRVSTR_ME:
900 seq_printf(s, "%s ", "medium-drive");
901 break;
902 case ATMEL_PIO_DRVSTR_HI:
903 seq_printf(s, "%s ", "high-drive");
904 break;
905 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
906 default:
907 seq_printf(s, "%s ", "low-drive");
908 }
909 }
910}
911
912static const struct pinconf_ops atmel_confops = {
913 .pin_config_group_get = atmel_conf_pin_config_group_get,
914 .pin_config_group_set = atmel_conf_pin_config_group_set,
915 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
916};
917
918static struct pinctrl_desc atmel_pinctrl_desc = {
919 .name = "atmel_pinctrl",
920 .confops = &atmel_confops,
921 .pctlops = &atmel_pctlops,
922 .pmxops = &atmel_pmxops,
923};
924
925static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
926{
927 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
928 int i, j;
929
930 /*
931 * For each bank, save IMR to restore it later and disable all GPIO
932 * interrupts excepting the ones marked as wakeup sources.
933 */
934 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
935 atmel_pioctrl->pm_suspend_backup[i].imr =
936 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
937 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
938 ~atmel_pioctrl->pm_wakeup_sources[i]);
939 atmel_pioctrl->pm_suspend_backup[i].odsr =
940 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
941 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
942 atmel_gpio_write(atmel_pioctrl, i,
943 ATMEL_PIO_MSKR, BIT(j));
944 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
945 atmel_gpio_read(atmel_pioctrl, i,
946 ATMEL_PIO_CFGR);
947 }
948 }
949
950 return 0;
951}
952
953static int __maybe_unused atmel_pctrl_resume(struct device *dev)
954{
955 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
956 int i, j;
957
958 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
959 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
960 atmel_pioctrl->pm_suspend_backup[i].imr);
961 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
962 atmel_pioctrl->pm_suspend_backup[i].odsr);
963 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
964 atmel_gpio_write(atmel_pioctrl, i,
965 ATMEL_PIO_MSKR, BIT(j));
966 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
967 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
968 }
969 }
970
971 return 0;
972}
973
974static const struct dev_pm_ops atmel_pctrl_pm_ops = {
975 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
976};
977
978/*
979 * The number of banks can be different from a SoC to another one.
980 * We can have up to 16 banks.
981 */
982static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
983 .nbanks = 4,
984};
985
986static const struct of_device_id atmel_pctrl_of_match[] = {
987 {
988 .compatible = "atmel,sama5d2-pinctrl",
989 .data = &atmel_sama5d2_pioctrl_data,
990 }, {
991 /* sentinel */
992 }
993};
994
995static int atmel_pinctrl_probe(struct platform_device *pdev)
996{
997 struct device *dev = &pdev->dev;
998 struct pinctrl_pin_desc *pin_desc;
999 const char **group_names;
1000 const struct of_device_id *match;
1001 int i, ret;
1002 struct resource *res;
1003 struct atmel_pioctrl *atmel_pioctrl;
1004 const struct atmel_pioctrl_data *atmel_pioctrl_data;
1005
1006 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1007 if (!atmel_pioctrl)
1008 return -ENOMEM;
1009 atmel_pioctrl->dev = dev;
1010 atmel_pioctrl->node = dev->of_node;
1011 platform_set_drvdata(pdev, atmel_pioctrl);
1012
1013 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
1014 if (!match) {
1015 dev_err(dev, "unknown compatible string\n");
1016 return -ENODEV;
1017 }
1018 atmel_pioctrl_data = match->data;
1019 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1020 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1021
1022 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1023 if (IS_ERR(atmel_pioctrl->reg_base))
1024 return PTR_ERR(atmel_pioctrl->reg_base);
1025
1026 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
1027 if (IS_ERR(atmel_pioctrl->clk)) {
1028 dev_err(dev, "failed to get clock\n");
1029 return PTR_ERR(atmel_pioctrl->clk);
1030 }
1031
1032 atmel_pioctrl->pins = devm_kcalloc(dev,
1033 atmel_pioctrl->npins,
1034 sizeof(*atmel_pioctrl->pins),
1035 GFP_KERNEL);
1036 if (!atmel_pioctrl->pins)
1037 return -ENOMEM;
1038
1039 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1040 GFP_KERNEL);
1041 if (!pin_desc)
1042 return -ENOMEM;
1043 atmel_pinctrl_desc.pins = pin_desc;
1044 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1045 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1046 atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1047
1048 /* One pin is one group since a pin can achieve all functions. */
1049 group_names = devm_kcalloc(dev,
1050 atmel_pioctrl->npins, sizeof(*group_names),
1051 GFP_KERNEL);
1052 if (!group_names)
1053 return -ENOMEM;
1054 atmel_pioctrl->group_names = group_names;
1055
1056 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1057 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1058 GFP_KERNEL);
1059 if (!atmel_pioctrl->groups)
1060 return -ENOMEM;
1061 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1062 struct atmel_group *group = atmel_pioctrl->groups + i;
1063 unsigned bank = ATMEL_PIO_BANK(i);
1064 unsigned line = ATMEL_PIO_LINE(i);
1065
1066 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1067 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1068 if (!atmel_pioctrl->pins[i])
1069 return -ENOMEM;
1070
1071 atmel_pioctrl->pins[i]->pin_id = i;
1072 atmel_pioctrl->pins[i]->bank = bank;
1073 atmel_pioctrl->pins[i]->line = line;
1074
1075 pin_desc[i].number = i;
1076 /* Pin naming convention: P(bank_name)(bank_pin_number). */
1077 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1078 bank + 'A', line);
1079
1080 group->name = group_names[i] = pin_desc[i].name;
1081 group->pin = pin_desc[i].number;
1082
1083 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1084 }
1085
1086 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1087 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
1088 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1089 atmel_pioctrl->gpio_chip->label = dev_name(dev);
1090 atmel_pioctrl->gpio_chip->parent = dev;
1091 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1092
1093 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1094 atmel_pioctrl->nbanks,
1095 sizeof(*atmel_pioctrl->pm_wakeup_sources),
1096 GFP_KERNEL);
1097 if (!atmel_pioctrl->pm_wakeup_sources)
1098 return -ENOMEM;
1099
1100 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1101 atmel_pioctrl->nbanks,
1102 sizeof(*atmel_pioctrl->pm_suspend_backup),
1103 GFP_KERNEL);
1104 if (!atmel_pioctrl->pm_suspend_backup)
1105 return -ENOMEM;
1106
1107 atmel_pioctrl->irqs = devm_kcalloc(dev,
1108 atmel_pioctrl->nbanks,
1109 sizeof(*atmel_pioctrl->irqs),
1110 GFP_KERNEL);
1111 if (!atmel_pioctrl->irqs)
1112 return -ENOMEM;
1113
1114 /* There is one controller but each bank has its own irq line. */
1115 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1116 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1117 if (!res) {
1118 dev_err(dev, "missing irq resource for group %c\n",
1119 'A' + i);
1120 return -EINVAL;
1121 }
1122 atmel_pioctrl->irqs[i] = res->start;
1123 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1124 irq_set_handler_data(res->start, atmel_pioctrl);
1125 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1126 }
1127
1128 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1129 atmel_pioctrl->gpio_chip->ngpio,
1130 &irq_domain_simple_ops, NULL);
1131 if (!atmel_pioctrl->irq_domain) {
1132 dev_err(dev, "can't add the irq domain\n");
1133 return -ENODEV;
1134 }
1135 atmel_pioctrl->irq_domain->name = "atmel gpio";
1136
1137 for (i = 0; i < atmel_pioctrl->npins; i++) {
1138 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1139
1140 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1141 handle_simple_irq);
1142 irq_set_chip_data(irq, atmel_pioctrl);
1143 dev_dbg(dev,
1144 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1145 i, irq);
1146 }
1147
1148 ret = clk_prepare_enable(atmel_pioctrl->clk);
1149 if (ret) {
1150 dev_err(dev, "failed to prepare and enable clock\n");
1151 goto clk_prepare_enable_error;
1152 }
1153
1154 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1155 &atmel_pinctrl_desc,
1156 atmel_pioctrl);
1157 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1158 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1159 dev_err(dev, "pinctrl registration failed\n");
1160 goto clk_unprep;
1161 }
1162
1163 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1164 if (ret) {
1165 dev_err(dev, "failed to add gpiochip\n");
1166 goto clk_unprep;
1167 }
1168
1169 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1170 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1171 if (ret) {
1172 dev_err(dev, "failed to add gpio pin range\n");
1173 goto gpiochip_add_pin_range_error;
1174 }
1175
1176 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1177
1178 return 0;
1179
1180gpiochip_add_pin_range_error:
1181 gpiochip_remove(atmel_pioctrl->gpio_chip);
1182
1183clk_unprep:
1184 clk_disable_unprepare(atmel_pioctrl->clk);
1185
1186clk_prepare_enable_error:
1187 irq_domain_remove(atmel_pioctrl->irq_domain);
1188
1189 return ret;
1190}
1191
1192static struct platform_driver atmel_pinctrl_driver = {
1193 .driver = {
1194 .name = "pinctrl-at91-pio4",
1195 .of_match_table = atmel_pctrl_of_match,
1196 .pm = &atmel_pctrl_pm_ops,
1197 .suppress_bind_attrs = true,
1198 },
1199 .probe = atmel_pinctrl_probe,
1200};
1201builtin_platform_driver(atmel_pinctrl_driver);