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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Cannon Lake PCH pinctrl/GPIO driver
4 *
5 * Copyright (C) 2017, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13
14#include <linux/pinctrl/pinctrl.h>
15
16#include "pinctrl-intel.h"
17
18#define CNL_PAD_OWN 0x020
19#define CNL_PADCFGLOCK 0x080
20#define CNL_LP_HOSTSW_OWN 0x0b0
21#define CNL_H_HOSTSW_OWN 0x0c0
22#define CNL_GPI_IS 0x100
23#define CNL_GPI_IE 0x120
24
25#define CNL_GPP(r, s, e, g) \
26 { \
27 .reg_num = (r), \
28 .base = (s), \
29 .size = ((e) - (s) + 1), \
30 .gpio_base = (g), \
31 }
32
33#define CNL_COMMUNITY(b, s, e, o, g) \
34 { \
35 .barno = (b), \
36 .padown_offset = CNL_PAD_OWN, \
37 .padcfglock_offset = CNL_PADCFGLOCK, \
38 .hostown_offset = (o), \
39 .is_offset = CNL_GPI_IS, \
40 .ie_offset = CNL_GPI_IE, \
41 .pin_base = (s), \
42 .npins = ((e) - (s) + 1), \
43 .gpps = (g), \
44 .ngpps = ARRAY_SIZE(g), \
45 }
46
47#define CNLLP_COMMUNITY(b, s, e, g) \
48 CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
49
50#define CNLH_COMMUNITY(b, s, e, g) \
51 CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
52
53/* Cannon Lake-H */
54static const struct pinctrl_pin_desc cnlh_pins[] = {
55 /* GPP_A */
56 PINCTRL_PIN(0, "RCINB"),
57 PINCTRL_PIN(1, "LAD_0"),
58 PINCTRL_PIN(2, "LAD_1"),
59 PINCTRL_PIN(3, "LAD_2"),
60 PINCTRL_PIN(4, "LAD_3"),
61 PINCTRL_PIN(5, "LFRAMEB"),
62 PINCTRL_PIN(6, "SERIRQ"),
63 PINCTRL_PIN(7, "PIRQAB"),
64 PINCTRL_PIN(8, "CLKRUNB"),
65 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
66 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
67 PINCTRL_PIN(11, "PMEB"),
68 PINCTRL_PIN(12, "BM_BUSYB"),
69 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
70 PINCTRL_PIN(14, "SUS_STATB"),
71 PINCTRL_PIN(15, "SUSACKB"),
72 PINCTRL_PIN(16, "CLKOUT_48"),
73 PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
74 PINCTRL_PIN(18, "ISH_GP_0"),
75 PINCTRL_PIN(19, "ISH_GP_1"),
76 PINCTRL_PIN(20, "ISH_GP_2"),
77 PINCTRL_PIN(21, "ISH_GP_3"),
78 PINCTRL_PIN(22, "ISH_GP_4"),
79 PINCTRL_PIN(23, "ISH_GP_5"),
80 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
81 /* GPP_B */
82 PINCTRL_PIN(25, "GSPI0_CS1B"),
83 PINCTRL_PIN(26, "GSPI1_CS1B"),
84 PINCTRL_PIN(27, "VRALERTB"),
85 PINCTRL_PIN(28, "CPU_GP_2"),
86 PINCTRL_PIN(29, "CPU_GP_3"),
87 PINCTRL_PIN(30, "SRCCLKREQB_0"),
88 PINCTRL_PIN(31, "SRCCLKREQB_1"),
89 PINCTRL_PIN(32, "SRCCLKREQB_2"),
90 PINCTRL_PIN(33, "SRCCLKREQB_3"),
91 PINCTRL_PIN(34, "SRCCLKREQB_4"),
92 PINCTRL_PIN(35, "SRCCLKREQB_5"),
93 PINCTRL_PIN(36, "SSP_MCLK"),
94 PINCTRL_PIN(37, "SLP_S0B"),
95 PINCTRL_PIN(38, "PLTRSTB"),
96 PINCTRL_PIN(39, "SPKR"),
97 PINCTRL_PIN(40, "GSPI0_CS0B"),
98 PINCTRL_PIN(41, "GSPI0_CLK"),
99 PINCTRL_PIN(42, "GSPI0_MISO"),
100 PINCTRL_PIN(43, "GSPI0_MOSI"),
101 PINCTRL_PIN(44, "GSPI1_CS0B"),
102 PINCTRL_PIN(45, "GSPI1_CLK"),
103 PINCTRL_PIN(46, "GSPI1_MISO"),
104 PINCTRL_PIN(47, "GSPI1_MOSI"),
105 PINCTRL_PIN(48, "SML1ALERTB"),
106 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
107 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
108 /* GPP_C */
109 PINCTRL_PIN(51, "SMBCLK"),
110 PINCTRL_PIN(52, "SMBDATA"),
111 PINCTRL_PIN(53, "SMBALERTB"),
112 PINCTRL_PIN(54, "SML0CLK"),
113 PINCTRL_PIN(55, "SML0DATA"),
114 PINCTRL_PIN(56, "SML0ALERTB"),
115 PINCTRL_PIN(57, "SML1CLK"),
116 PINCTRL_PIN(58, "SML1DATA"),
117 PINCTRL_PIN(59, "UART0_RXD"),
118 PINCTRL_PIN(60, "UART0_TXD"),
119 PINCTRL_PIN(61, "UART0_RTSB"),
120 PINCTRL_PIN(62, "UART0_CTSB"),
121 PINCTRL_PIN(63, "UART1_RXD"),
122 PINCTRL_PIN(64, "UART1_TXD"),
123 PINCTRL_PIN(65, "UART1_RTSB"),
124 PINCTRL_PIN(66, "UART1_CTSB"),
125 PINCTRL_PIN(67, "I2C0_SDA"),
126 PINCTRL_PIN(68, "I2C0_SCL"),
127 PINCTRL_PIN(69, "I2C1_SDA"),
128 PINCTRL_PIN(70, "I2C1_SCL"),
129 PINCTRL_PIN(71, "UART2_RXD"),
130 PINCTRL_PIN(72, "UART2_TXD"),
131 PINCTRL_PIN(73, "UART2_RTSB"),
132 PINCTRL_PIN(74, "UART2_CTSB"),
133 /* GPP_D */
134 PINCTRL_PIN(75, "SPI1_CSB"),
135 PINCTRL_PIN(76, "SPI1_CLK"),
136 PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
137 PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
138 PINCTRL_PIN(79, "ISH_I2C2_SDA"),
139 PINCTRL_PIN(80, "SSP2_SFRM"),
140 PINCTRL_PIN(81, "SSP2_TXD"),
141 PINCTRL_PIN(82, "SSP2_RXD"),
142 PINCTRL_PIN(83, "SSP2_SCLK"),
143 PINCTRL_PIN(84, "ISH_SPI_CSB"),
144 PINCTRL_PIN(85, "ISH_SPI_CLK"),
145 PINCTRL_PIN(86, "ISH_SPI_MISO"),
146 PINCTRL_PIN(87, "ISH_SPI_MOSI"),
147 PINCTRL_PIN(88, "ISH_UART0_RXD"),
148 PINCTRL_PIN(89, "ISH_UART0_TXD"),
149 PINCTRL_PIN(90, "ISH_UART0_RTSB"),
150 PINCTRL_PIN(91, "ISH_UART0_CTSB"),
151 PINCTRL_PIN(92, "DMIC_CLK_1"),
152 PINCTRL_PIN(93, "DMIC_DATA_1"),
153 PINCTRL_PIN(94, "DMIC_CLK_0"),
154 PINCTRL_PIN(95, "DMIC_DATA_0"),
155 PINCTRL_PIN(96, "SPI1_IO_2"),
156 PINCTRL_PIN(97, "SPI1_IO_3"),
157 PINCTRL_PIN(98, "ISH_I2C2_SCL"),
158 /* GPP_G */
159 PINCTRL_PIN(99, "SD3_CMD"),
160 PINCTRL_PIN(100, "SD3_D0"),
161 PINCTRL_PIN(101, "SD3_D1"),
162 PINCTRL_PIN(102, "SD3_D2"),
163 PINCTRL_PIN(103, "SD3_D3"),
164 PINCTRL_PIN(104, "SD3_CDB"),
165 PINCTRL_PIN(105, "SD3_CLK"),
166 PINCTRL_PIN(106, "SD3_WP"),
167 /* AZA */
168 PINCTRL_PIN(107, "HDA_BCLK"),
169 PINCTRL_PIN(108, "HDA_RSTB"),
170 PINCTRL_PIN(109, "HDA_SYNC"),
171 PINCTRL_PIN(110, "HDA_SDO"),
172 PINCTRL_PIN(111, "HDA_SDI_0"),
173 PINCTRL_PIN(112, "HDA_SDI_1"),
174 PINCTRL_PIN(113, "SSP1_SFRM"),
175 PINCTRL_PIN(114, "SSP1_TXD"),
176 /* vGPIO */
177 PINCTRL_PIN(115, "CNV_BTEN"),
178 PINCTRL_PIN(116, "CNV_GNEN"),
179 PINCTRL_PIN(117, "CNV_WFEN"),
180 PINCTRL_PIN(118, "CNV_WCEN"),
181 PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
182 PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
183 PINCTRL_PIN(121, "vSD3_CD_B"),
184 PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
185 PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
186 PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
187 PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
188 PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
189 PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
190 PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
191 PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
192 PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
193 PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
194 PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
195 PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
196 PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
197 PINCTRL_PIN(135, "vUART0_TXD"),
198 PINCTRL_PIN(136, "vUART0_RXD"),
199 PINCTRL_PIN(137, "vUART0_CTS_B"),
200 PINCTRL_PIN(138, "vUART0_RTSB"),
201 PINCTRL_PIN(139, "vISH_UART0_TXD"),
202 PINCTRL_PIN(140, "vISH_UART0_RXD"),
203 PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
204 PINCTRL_PIN(142, "vISH_UART0_RTSB"),
205 PINCTRL_PIN(143, "vISH_UART1_TXD"),
206 PINCTRL_PIN(144, "vISH_UART1_RXD"),
207 PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
208 PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
209 PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
210 PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
211 PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
212 PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
213 PINCTRL_PIN(151, "vSSP2_SCLK"),
214 PINCTRL_PIN(152, "vSSP2_SFRM"),
215 PINCTRL_PIN(153, "vSSP2_TXD"),
216 PINCTRL_PIN(154, "vSSP2_RXD"),
217 /* GPP_K */
218 PINCTRL_PIN(155, "FAN_TACH_0"),
219 PINCTRL_PIN(156, "FAN_TACH_1"),
220 PINCTRL_PIN(157, "FAN_TACH_2"),
221 PINCTRL_PIN(158, "FAN_TACH_3"),
222 PINCTRL_PIN(159, "FAN_TACH_4"),
223 PINCTRL_PIN(160, "FAN_TACH_5"),
224 PINCTRL_PIN(161, "FAN_TACH_6"),
225 PINCTRL_PIN(162, "FAN_TACH_7"),
226 PINCTRL_PIN(163, "FAN_PWM_0"),
227 PINCTRL_PIN(164, "FAN_PWM_1"),
228 PINCTRL_PIN(165, "FAN_PWM_2"),
229 PINCTRL_PIN(166, "FAN_PWM_3"),
230 PINCTRL_PIN(167, "GSXDOUT"),
231 PINCTRL_PIN(168, "GSXSLOAD"),
232 PINCTRL_PIN(169, "GSXDIN"),
233 PINCTRL_PIN(170, "GSXSRESETB"),
234 PINCTRL_PIN(171, "GSXCLK"),
235 PINCTRL_PIN(172, "ADR_COMPLETE"),
236 PINCTRL_PIN(173, "NMIB"),
237 PINCTRL_PIN(174, "SMIB"),
238 PINCTRL_PIN(175, "CORE_VID_0"),
239 PINCTRL_PIN(176, "CORE_VID_1"),
240 PINCTRL_PIN(177, "IMGCLKOUT_0"),
241 PINCTRL_PIN(178, "IMGCLKOUT_1"),
242 /* GPP_H */
243 PINCTRL_PIN(179, "SRCCLKREQB_6"),
244 PINCTRL_PIN(180, "SRCCLKREQB_7"),
245 PINCTRL_PIN(181, "SRCCLKREQB_8"),
246 PINCTRL_PIN(182, "SRCCLKREQB_9"),
247 PINCTRL_PIN(183, "SRCCLKREQB_10"),
248 PINCTRL_PIN(184, "SRCCLKREQB_11"),
249 PINCTRL_PIN(185, "SRCCLKREQB_12"),
250 PINCTRL_PIN(186, "SRCCLKREQB_13"),
251 PINCTRL_PIN(187, "SRCCLKREQB_14"),
252 PINCTRL_PIN(188, "SRCCLKREQB_15"),
253 PINCTRL_PIN(189, "SML2CLK"),
254 PINCTRL_PIN(190, "SML2DATA"),
255 PINCTRL_PIN(191, "SML2ALERTB"),
256 PINCTRL_PIN(192, "SML3CLK"),
257 PINCTRL_PIN(193, "SML3DATA"),
258 PINCTRL_PIN(194, "SML3ALERTB"),
259 PINCTRL_PIN(195, "SML4CLK"),
260 PINCTRL_PIN(196, "SML4DATA"),
261 PINCTRL_PIN(197, "SML4ALERTB"),
262 PINCTRL_PIN(198, "ISH_I2C0_SDA"),
263 PINCTRL_PIN(199, "ISH_I2C0_SCL"),
264 PINCTRL_PIN(200, "ISH_I2C1_SDA"),
265 PINCTRL_PIN(201, "ISH_I2C1_SCL"),
266 PINCTRL_PIN(202, "TIME_SYNC_0"),
267 /* GPP_E */
268 PINCTRL_PIN(203, "SATAXPCIE_0"),
269 PINCTRL_PIN(204, "SATAXPCIE_1"),
270 PINCTRL_PIN(205, "SATAXPCIE_2"),
271 PINCTRL_PIN(206, "CPU_GP_0"),
272 PINCTRL_PIN(207, "SATA_DEVSLP_0"),
273 PINCTRL_PIN(208, "SATA_DEVSLP_1"),
274 PINCTRL_PIN(209, "SATA_DEVSLP_2"),
275 PINCTRL_PIN(210, "CPU_GP_1"),
276 PINCTRL_PIN(211, "SATA_LEDB"),
277 PINCTRL_PIN(212, "USB2_OCB_0"),
278 PINCTRL_PIN(213, "USB2_OCB_1"),
279 PINCTRL_PIN(214, "USB2_OCB_2"),
280 PINCTRL_PIN(215, "USB2_OCB_3"),
281 /* GPP_F */
282 PINCTRL_PIN(216, "SATAXPCIE_3"),
283 PINCTRL_PIN(217, "SATAXPCIE_4"),
284 PINCTRL_PIN(218, "SATAXPCIE_5"),
285 PINCTRL_PIN(219, "SATAXPCIE_6"),
286 PINCTRL_PIN(220, "SATAXPCIE_7"),
287 PINCTRL_PIN(221, "SATA_DEVSLP_3"),
288 PINCTRL_PIN(222, "SATA_DEVSLP_4"),
289 PINCTRL_PIN(223, "SATA_DEVSLP_5"),
290 PINCTRL_PIN(224, "SATA_DEVSLP_6"),
291 PINCTRL_PIN(225, "SATA_DEVSLP_7"),
292 PINCTRL_PIN(226, "SATA_SCLOCK"),
293 PINCTRL_PIN(227, "SATA_SLOAD"),
294 PINCTRL_PIN(228, "SATA_SDATAOUT1"),
295 PINCTRL_PIN(229, "SATA_SDATAOUT0"),
296 PINCTRL_PIN(230, "EXT_PWR_GATEB"),
297 PINCTRL_PIN(231, "USB2_OCB_4"),
298 PINCTRL_PIN(232, "USB2_OCB_5"),
299 PINCTRL_PIN(233, "USB2_OCB_6"),
300 PINCTRL_PIN(234, "USB2_OCB_7"),
301 PINCTRL_PIN(235, "L_VDDEN"),
302 PINCTRL_PIN(236, "L_BKLTEN"),
303 PINCTRL_PIN(237, "L_BKLTCTL"),
304 PINCTRL_PIN(238, "DDPF_CTRLCLK"),
305 PINCTRL_PIN(239, "DDPF_CTRLDATA"),
306 /* SPI */
307 PINCTRL_PIN(240, "SPI0_IO_2"),
308 PINCTRL_PIN(241, "SPI0_IO_3"),
309 PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
310 PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
311 PINCTRL_PIN(244, "SPI0_TPM_CSB"),
312 PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
313 PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
314 PINCTRL_PIN(247, "SPI0_CLK"),
315 PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
316 /* CPU */
317 PINCTRL_PIN(249, "HDACPU_SDI"),
318 PINCTRL_PIN(250, "HDACPU_SDO"),
319 PINCTRL_PIN(251, "HDACPU_SCLK"),
320 PINCTRL_PIN(252, "PM_SYNC"),
321 PINCTRL_PIN(253, "PECI"),
322 PINCTRL_PIN(254, "CPUPWRGD"),
323 PINCTRL_PIN(255, "THRMTRIPB"),
324 PINCTRL_PIN(256, "PLTRST_CPUB"),
325 PINCTRL_PIN(257, "PM_DOWN"),
326 PINCTRL_PIN(258, "TRIGGER_IN"),
327 PINCTRL_PIN(259, "TRIGGER_OUT"),
328 /* JTAG */
329 PINCTRL_PIN(260, "JTAG_TDO"),
330 PINCTRL_PIN(261, "JTAGX"),
331 PINCTRL_PIN(262, "PRDYB"),
332 PINCTRL_PIN(263, "PREQB"),
333 PINCTRL_PIN(264, "CPU_TRSTB"),
334 PINCTRL_PIN(265, "JTAG_TDI"),
335 PINCTRL_PIN(266, "JTAG_TMS"),
336 PINCTRL_PIN(267, "JTAG_TCK"),
337 PINCTRL_PIN(268, "ITP_PMODE"),
338 /* GPP_I */
339 PINCTRL_PIN(269, "DDSP_HPD_0"),
340 PINCTRL_PIN(270, "DDSP_HPD_1"),
341 PINCTRL_PIN(271, "DDSP_HPD_2"),
342 PINCTRL_PIN(272, "DDSP_HPD_3"),
343 PINCTRL_PIN(273, "EDP_HPD"),
344 PINCTRL_PIN(274, "DDPB_CTRLCLK"),
345 PINCTRL_PIN(275, "DDPB_CTRLDATA"),
346 PINCTRL_PIN(276, "DDPC_CTRLCLK"),
347 PINCTRL_PIN(277, "DDPC_CTRLDATA"),
348 PINCTRL_PIN(278, "DDPD_CTRLCLK"),
349 PINCTRL_PIN(279, "DDPD_CTRLDATA"),
350 PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
351 PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
352 PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
353 PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
354 PINCTRL_PIN(284, "SYS_PWROK"),
355 PINCTRL_PIN(285, "SYS_RESETB"),
356 PINCTRL_PIN(286, "MLK_RSTB"),
357 /* GPP_J */
358 PINCTRL_PIN(287, "CNV_PA_BLANKING"),
359 PINCTRL_PIN(288, "CNV_GNSS_FTA"),
360 PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
361 PINCTRL_PIN(290, "CNV_RF_RESET_B"),
362 PINCTRL_PIN(291, "CNV_BRI_DT"),
363 PINCTRL_PIN(292, "CNV_BRI_RSP"),
364 PINCTRL_PIN(293, "CNV_RGI_DT"),
365 PINCTRL_PIN(294, "CNV_RGI_RSP"),
366 PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
367 PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
368 PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
369 PINCTRL_PIN(298, "A4WP_PRESENT"),
370};
371
372static const struct intel_padgroup cnlh_community0_gpps[] = {
373 CNL_GPP(0, 0, 24, 0), /* GPP_A */
374 CNL_GPP(1, 25, 50, 32), /* GPP_B */
375};
376
377static const struct intel_padgroup cnlh_community1_gpps[] = {
378 CNL_GPP(0, 51, 74, 64), /* GPP_C */
379 CNL_GPP(1, 75, 98, 96), /* GPP_D */
380 CNL_GPP(2, 99, 106, 128), /* GPP_G */
381 CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
382 CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
383 CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
384};
385
386static const struct intel_padgroup cnlh_community3_gpps[] = {
387 CNL_GPP(0, 155, 178, 192), /* GPP_K */
388 CNL_GPP(1, 179, 202, 224), /* GPP_H */
389 CNL_GPP(2, 203, 215, 256), /* GPP_E */
390 CNL_GPP(3, 216, 239, 288), /* GPP_F */
391 CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
392};
393
394static const struct intel_padgroup cnlh_community4_gpps[] = {
395 CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
396 CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
397 CNL_GPP(2, 269, 286, 320), /* GPP_I */
398 CNL_GPP(3, 287, 298, 352), /* GPP_J */
399};
400
401static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
402static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
403static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
404
405static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
406static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
407static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
408
409static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
410static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
411static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
412static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
413
414static const struct intel_pingroup cnlh_groups[] = {
415 PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
416 PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
417 PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
418 PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
419 PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
420 PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
421 PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
422 PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
423 PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
424 PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
425};
426
427static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
428static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
429static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
430static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
431static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
432static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
433static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
434static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
435static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
436static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
437
438static const struct intel_function cnlh_functions[] = {
439 FUNCTION("spi0", cnlh_spi0_groups),
440 FUNCTION("spi1", cnlh_spi1_groups),
441 FUNCTION("spi2", cnlh_spi2_groups),
442 FUNCTION("uart0", cnlh_uart0_groups),
443 FUNCTION("uart1", cnlh_uart1_groups),
444 FUNCTION("uart2", cnlh_uart2_groups),
445 FUNCTION("i2c0", cnlh_i2c0_groups),
446 FUNCTION("i2c1", cnlh_i2c1_groups),
447 FUNCTION("i2c2", cnlh_i2c2_groups),
448 FUNCTION("i2c3", cnlh_i2c3_groups),
449};
450
451static const struct intel_community cnlh_communities[] = {
452 CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
453 CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
454 CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
455 CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
456};
457
458static const struct intel_pinctrl_soc_data cnlh_soc_data = {
459 .pins = cnlh_pins,
460 .npins = ARRAY_SIZE(cnlh_pins),
461 .groups = cnlh_groups,
462 .ngroups = ARRAY_SIZE(cnlh_groups),
463 .functions = cnlh_functions,
464 .nfunctions = ARRAY_SIZE(cnlh_functions),
465 .communities = cnlh_communities,
466 .ncommunities = ARRAY_SIZE(cnlh_communities),
467};
468
469/* Cannon Lake-LP */
470static const struct pinctrl_pin_desc cnllp_pins[] = {
471 /* GPP_A */
472 PINCTRL_PIN(0, "RCINB"),
473 PINCTRL_PIN(1, "LAD_0"),
474 PINCTRL_PIN(2, "LAD_1"),
475 PINCTRL_PIN(3, "LAD_2"),
476 PINCTRL_PIN(4, "LAD_3"),
477 PINCTRL_PIN(5, "LFRAMEB"),
478 PINCTRL_PIN(6, "SERIRQ"),
479 PINCTRL_PIN(7, "PIRQAB"),
480 PINCTRL_PIN(8, "CLKRUNB"),
481 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
482 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
483 PINCTRL_PIN(11, "PMEB"),
484 PINCTRL_PIN(12, "BM_BUSYB"),
485 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
486 PINCTRL_PIN(14, "SUS_STATB"),
487 PINCTRL_PIN(15, "SUSACKB"),
488 PINCTRL_PIN(16, "SD_1P8_SEL"),
489 PINCTRL_PIN(17, "SD_PWR_EN_B"),
490 PINCTRL_PIN(18, "ISH_GP_0"),
491 PINCTRL_PIN(19, "ISH_GP_1"),
492 PINCTRL_PIN(20, "ISH_GP_2"),
493 PINCTRL_PIN(21, "ISH_GP_3"),
494 PINCTRL_PIN(22, "ISH_GP_4"),
495 PINCTRL_PIN(23, "ISH_GP_5"),
496 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
497 /* GPP_B */
498 PINCTRL_PIN(25, "CORE_VID_0"),
499 PINCTRL_PIN(26, "CORE_VID_1"),
500 PINCTRL_PIN(27, "VRALERTB"),
501 PINCTRL_PIN(28, "CPU_GP_2"),
502 PINCTRL_PIN(29, "CPU_GP_3"),
503 PINCTRL_PIN(30, "SRCCLKREQB_0"),
504 PINCTRL_PIN(31, "SRCCLKREQB_1"),
505 PINCTRL_PIN(32, "SRCCLKREQB_2"),
506 PINCTRL_PIN(33, "SRCCLKREQB_3"),
507 PINCTRL_PIN(34, "SRCCLKREQB_4"),
508 PINCTRL_PIN(35, "SRCCLKREQB_5"),
509 PINCTRL_PIN(36, "EXT_PWR_GATEB"),
510 PINCTRL_PIN(37, "SLP_S0B"),
511 PINCTRL_PIN(38, "PLTRSTB"),
512 PINCTRL_PIN(39, "SPKR"),
513 PINCTRL_PIN(40, "GSPI0_CS0B"),
514 PINCTRL_PIN(41, "GSPI0_CLK"),
515 PINCTRL_PIN(42, "GSPI0_MISO"),
516 PINCTRL_PIN(43, "GSPI0_MOSI"),
517 PINCTRL_PIN(44, "GSPI1_CS0B"),
518 PINCTRL_PIN(45, "GSPI1_CLK"),
519 PINCTRL_PIN(46, "GSPI1_MISO"),
520 PINCTRL_PIN(47, "GSPI1_MOSI"),
521 PINCTRL_PIN(48, "SML1ALERTB"),
522 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
523 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
524 /* GPP_G */
525 PINCTRL_PIN(51, "SD3_CMD"),
526 PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
527 PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
528 PINCTRL_PIN(54, "SD3_D2"),
529 PINCTRL_PIN(55, "SD3_D3"),
530 PINCTRL_PIN(56, "SD3_CDB"),
531 PINCTRL_PIN(57, "SD3_CLK"),
532 PINCTRL_PIN(58, "SD3_WP"),
533 /* SPI */
534 PINCTRL_PIN(59, "SPI0_IO_2"),
535 PINCTRL_PIN(60, "SPI0_IO_3"),
536 PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
537 PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
538 PINCTRL_PIN(63, "SPI0_TPM_CSB"),
539 PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
540 PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
541 PINCTRL_PIN(66, "SPI0_CLK"),
542 PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
543 /* GPP_D */
544 PINCTRL_PIN(68, "SPI1_CSB"),
545 PINCTRL_PIN(69, "SPI1_CLK"),
546 PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
547 PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
548 PINCTRL_PIN(72, "IMGCLKOUT_0"),
549 PINCTRL_PIN(73, "ISH_I2C0_SDA"),
550 PINCTRL_PIN(74, "ISH_I2C0_SCL"),
551 PINCTRL_PIN(75, "ISH_I2C1_SDA"),
552 PINCTRL_PIN(76, "ISH_I2C1_SCL"),
553 PINCTRL_PIN(77, "ISH_SPI_CSB"),
554 PINCTRL_PIN(78, "ISH_SPI_CLK"),
555 PINCTRL_PIN(79, "ISH_SPI_MISO"),
556 PINCTRL_PIN(80, "ISH_SPI_MOSI"),
557 PINCTRL_PIN(81, "ISH_UART0_RXD"),
558 PINCTRL_PIN(82, "ISH_UART0_TXD"),
559 PINCTRL_PIN(83, "ISH_UART0_RTSB"),
560 PINCTRL_PIN(84, "ISH_UART0_CTSB"),
561 PINCTRL_PIN(85, "DMIC_CLK_1"),
562 PINCTRL_PIN(86, "DMIC_DATA_1"),
563 PINCTRL_PIN(87, "DMIC_CLK_0"),
564 PINCTRL_PIN(88, "DMIC_DATA_0"),
565 PINCTRL_PIN(89, "SPI1_IO_2"),
566 PINCTRL_PIN(90, "SPI1_IO_3"),
567 PINCTRL_PIN(91, "SSP_MCLK"),
568 PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
569 /* GPP_F */
570 PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
571 PINCTRL_PIN(94, "CNV_GNSS_FTA"),
572 PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
573 PINCTRL_PIN(96, "EMMC_HIP_MON"),
574 PINCTRL_PIN(97, "CNV_BRI_DT"),
575 PINCTRL_PIN(98, "CNV_BRI_RSP"),
576 PINCTRL_PIN(99, "CNV_RGI_DT"),
577 PINCTRL_PIN(100, "CNV_RGI_RSP"),
578 PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
579 PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
580 PINCTRL_PIN(103, "GPP_F_10"),
581 PINCTRL_PIN(104, "EMMC_CMD"),
582 PINCTRL_PIN(105, "EMMC_DATA_0"),
583 PINCTRL_PIN(106, "EMMC_DATA_1"),
584 PINCTRL_PIN(107, "EMMC_DATA_2"),
585 PINCTRL_PIN(108, "EMMC_DATA_3"),
586 PINCTRL_PIN(109, "EMMC_DATA_4"),
587 PINCTRL_PIN(110, "EMMC_DATA_5"),
588 PINCTRL_PIN(111, "EMMC_DATA_6"),
589 PINCTRL_PIN(112, "EMMC_DATA_7"),
590 PINCTRL_PIN(113, "EMMC_RCLK"),
591 PINCTRL_PIN(114, "EMMC_CLK"),
592 PINCTRL_PIN(115, "EMMC_RESETB"),
593 PINCTRL_PIN(116, "A4WP_PRESENT"),
594 /* GPP_H */
595 PINCTRL_PIN(117, "SSP2_SCLK"),
596 PINCTRL_PIN(118, "SSP2_SFRM"),
597 PINCTRL_PIN(119, "SSP2_TXD"),
598 PINCTRL_PIN(120, "SSP2_RXD"),
599 PINCTRL_PIN(121, "I2C2_SDA"),
600 PINCTRL_PIN(122, "I2C2_SCL"),
601 PINCTRL_PIN(123, "I2C3_SDA"),
602 PINCTRL_PIN(124, "I2C3_SCL"),
603 PINCTRL_PIN(125, "I2C4_SDA"),
604 PINCTRL_PIN(126, "I2C4_SCL"),
605 PINCTRL_PIN(127, "I2C5_SDA"),
606 PINCTRL_PIN(128, "I2C5_SCL"),
607 PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
608 PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
609 PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
610 PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
611 PINCTRL_PIN(133, "DDPF_CTRLCLK"),
612 PINCTRL_PIN(134, "DDPF_CTRLDATA"),
613 PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
614 PINCTRL_PIN(136, "TIMESYNC_0"),
615 PINCTRL_PIN(137, "IMGCLKOUT_1"),
616 PINCTRL_PIN(138, "GPPC_H_21"),
617 PINCTRL_PIN(139, "GPPC_H_22"),
618 PINCTRL_PIN(140, "GPPC_H_23"),
619 /* vGPIO */
620 PINCTRL_PIN(141, "CNV_BTEN"),
621 PINCTRL_PIN(142, "CNV_GNEN"),
622 PINCTRL_PIN(143, "CNV_WFEN"),
623 PINCTRL_PIN(144, "CNV_WCEN"),
624 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
625 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
626 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
627 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
628 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
629 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
630 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
631 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
632 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
633 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
634 PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
635 PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
636 PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
637 PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
638 PINCTRL_PIN(159, "vUART0_TXD"),
639 PINCTRL_PIN(160, "vUART0_RXD"),
640 PINCTRL_PIN(161, "vUART0_CTS_B"),
641 PINCTRL_PIN(162, "vUART0_RTS_B"),
642 PINCTRL_PIN(163, "vISH_UART0_TXD"),
643 PINCTRL_PIN(164, "vISH_UART0_RXD"),
644 PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
645 PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
646 PINCTRL_PIN(167, "vISH_UART1_TXD"),
647 PINCTRL_PIN(168, "vISH_UART1_RXD"),
648 PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
649 PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
650 PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
651 PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
652 PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
653 PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
654 PINCTRL_PIN(175, "vSSP2_SCLK"),
655 PINCTRL_PIN(176, "vSSP2_SFRM"),
656 PINCTRL_PIN(177, "vSSP2_TXD"),
657 PINCTRL_PIN(178, "vSSP2_RXD"),
658 PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
659 PINCTRL_PIN(180, "vSD3_CD_B"),
660 /* GPP_C */
661 PINCTRL_PIN(181, "SMBCLK"),
662 PINCTRL_PIN(182, "SMBDATA"),
663 PINCTRL_PIN(183, "SMBALERTB"),
664 PINCTRL_PIN(184, "SML0CLK"),
665 PINCTRL_PIN(185, "SML0DATA"),
666 PINCTRL_PIN(186, "SML0ALERTB"),
667 PINCTRL_PIN(187, "SML1CLK"),
668 PINCTRL_PIN(188, "SML1DATA"),
669 PINCTRL_PIN(189, "UART0_RXD"),
670 PINCTRL_PIN(190, "UART0_TXD"),
671 PINCTRL_PIN(191, "UART0_RTSB"),
672 PINCTRL_PIN(192, "UART0_CTSB"),
673 PINCTRL_PIN(193, "UART1_RXD"),
674 PINCTRL_PIN(194, "UART1_TXD"),
675 PINCTRL_PIN(195, "UART1_RTSB"),
676 PINCTRL_PIN(196, "UART1_CTSB"),
677 PINCTRL_PIN(197, "I2C0_SDA"),
678 PINCTRL_PIN(198, "I2C0_SCL"),
679 PINCTRL_PIN(199, "I2C1_SDA"),
680 PINCTRL_PIN(200, "I2C1_SCL"),
681 PINCTRL_PIN(201, "UART2_RXD"),
682 PINCTRL_PIN(202, "UART2_TXD"),
683 PINCTRL_PIN(203, "UART2_RTSB"),
684 PINCTRL_PIN(204, "UART2_CTSB"),
685 /* GPP_E */
686 PINCTRL_PIN(205, "SATAXPCIE_0"),
687 PINCTRL_PIN(206, "SATAXPCIE_1"),
688 PINCTRL_PIN(207, "SATAXPCIE_2"),
689 PINCTRL_PIN(208, "CPU_GP_0"),
690 PINCTRL_PIN(209, "SATA_DEVSLP_0"),
691 PINCTRL_PIN(210, "SATA_DEVSLP_1"),
692 PINCTRL_PIN(211, "SATA_DEVSLP_2"),
693 PINCTRL_PIN(212, "CPU_GP_1"),
694 PINCTRL_PIN(213, "SATA_LEDB"),
695 PINCTRL_PIN(214, "USB2_OCB_0"),
696 PINCTRL_PIN(215, "USB2_OCB_1"),
697 PINCTRL_PIN(216, "USB2_OCB_2"),
698 PINCTRL_PIN(217, "USB2_OCB_3"),
699 PINCTRL_PIN(218, "DDSP_HPD_0"),
700 PINCTRL_PIN(219, "DDSP_HPD_1"),
701 PINCTRL_PIN(220, "DDSP_HPD_2"),
702 PINCTRL_PIN(221, "DDSP_HPD_3"),
703 PINCTRL_PIN(222, "EDP_HPD"),
704 PINCTRL_PIN(223, "DDPB_CTRLCLK"),
705 PINCTRL_PIN(224, "DDPB_CTRLDATA"),
706 PINCTRL_PIN(225, "DDPC_CTRLCLK"),
707 PINCTRL_PIN(226, "DDPC_CTRLDATA"),
708 PINCTRL_PIN(227, "DDPD_CTRLCLK"),
709 PINCTRL_PIN(228, "DDPD_CTRLDATA"),
710 /* JTAG */
711 PINCTRL_PIN(229, "JTAG_TDO"),
712 PINCTRL_PIN(230, "JTAGX"),
713 PINCTRL_PIN(231, "PRDYB"),
714 PINCTRL_PIN(232, "PREQB"),
715 PINCTRL_PIN(233, "CPU_TRSTB"),
716 PINCTRL_PIN(234, "JTAG_TDI"),
717 PINCTRL_PIN(235, "JTAG_TMS"),
718 PINCTRL_PIN(236, "JTAG_TCK"),
719 PINCTRL_PIN(237, "ITP_PMODE"),
720 /* HVCMOS */
721 PINCTRL_PIN(238, "L_BKLTEN"),
722 PINCTRL_PIN(239, "L_BKLTCTL"),
723 PINCTRL_PIN(240, "L_VDDEN"),
724 PINCTRL_PIN(241, "SYS_PWROK"),
725 PINCTRL_PIN(242, "SYS_RESETB"),
726 PINCTRL_PIN(243, "MLK_RSTB"),
727};
728
729static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
730static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
731static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
732static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
733static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
734static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
735
736static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
737static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
738static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
739static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
740static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
741static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
742
743static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
744static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
745static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
746
747static const struct intel_pingroup cnllp_groups[] = {
748 PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
749 PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
750 PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
751 PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
752 PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
753 PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
754 PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
755 PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
756 PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
757 PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
758 PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
759 PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
760};
761
762static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
763static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
764static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
765static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
766static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
767static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
768static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
769static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
770static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
771static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
772static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
773static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
774
775static const struct intel_function cnllp_functions[] = {
776 FUNCTION("spi0", cnllp_spi0_groups),
777 FUNCTION("spi1", cnllp_spi1_groups),
778 FUNCTION("spi2", cnllp_spi2_groups),
779 FUNCTION("i2c0", cnllp_i2c0_groups),
780 FUNCTION("i2c1", cnllp_i2c1_groups),
781 FUNCTION("i2c2", cnllp_i2c2_groups),
782 FUNCTION("i2c3", cnllp_i2c3_groups),
783 FUNCTION("i2c4", cnllp_i2c4_groups),
784 FUNCTION("i2c5", cnllp_i2c5_groups),
785 FUNCTION("uart0", cnllp_uart0_groups),
786 FUNCTION("uart1", cnllp_uart1_groups),
787 FUNCTION("uart2", cnllp_uart2_groups),
788};
789
790static const struct intel_padgroup cnllp_community0_gpps[] = {
791 CNL_GPP(0, 0, 24, 0), /* GPP_A */
792 CNL_GPP(1, 25, 50, 32), /* GPP_B */
793 CNL_GPP(2, 51, 58, 64), /* GPP_G */
794 CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
795};
796
797static const struct intel_padgroup cnllp_community1_gpps[] = {
798 CNL_GPP(0, 68, 92, 96), /* GPP_D */
799 CNL_GPP(1, 93, 116, 128), /* GPP_F */
800 CNL_GPP(2, 117, 140, 160), /* GPP_H */
801 CNL_GPP(3, 141, 172, 192), /* vGPIO */
802 CNL_GPP(4, 173, 180, 224), /* vGPIO */
803};
804
805static const struct intel_padgroup cnllp_community4_gpps[] = {
806 CNL_GPP(0, 181, 204, 256), /* GPP_C */
807 CNL_GPP(1, 205, 228, 288), /* GPP_E */
808 CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
809 CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
810};
811
812static const struct intel_community cnllp_communities[] = {
813 CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
814 CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
815 CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
816};
817
818static const struct intel_pinctrl_soc_data cnllp_soc_data = {
819 .pins = cnllp_pins,
820 .npins = ARRAY_SIZE(cnllp_pins),
821 .groups = cnllp_groups,
822 .ngroups = ARRAY_SIZE(cnllp_groups),
823 .functions = cnllp_functions,
824 .nfunctions = ARRAY_SIZE(cnllp_functions),
825 .communities = cnllp_communities,
826 .ncommunities = ARRAY_SIZE(cnllp_communities),
827};
828
829static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
830 { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
831 { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
832 { }
833};
834MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
835
836static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
837
838static struct platform_driver cnl_pinctrl_driver = {
839 .probe = intel_pinctrl_probe_by_hid,
840 .driver = {
841 .name = "cannonlake-pinctrl",
842 .acpi_match_table = cnl_pinctrl_acpi_match,
843 .pm = &cnl_pinctrl_pm_ops,
844 },
845};
846
847module_platform_driver(cnl_pinctrl_driver);
848
849MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
850MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
851MODULE_LICENSE("GPL v2");