1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
   4 */
   5
   6#include <linux/signal.h>
   7#include <linux/slab.h>
   8#include <linux/module.h>
   9#include <linux/netdevice.h>
  10#include <linux/etherdevice.h>
  11#include <linux/mii.h>
  12#include <linux/ethtool.h>
  13#include <linux/usb.h>
  14#include <linux/crc32.h>
  15#include <linux/if_vlan.h>
  16#include <linux/uaccess.h>
  17#include <linux/list.h>
  18#include <linux/ip.h>
  19#include <linux/ipv6.h>
  20#include <net/ip6_checksum.h>
  21#include <uapi/linux/mdio.h>
  22#include <linux/mdio.h>
  23#include <linux/usb/cdc.h>
  24#include <linux/suspend.h>
  25#include <linux/atomic.h>
  26#include <linux/acpi.h>
  27#include <linux/firmware.h>
  28#include <crypto/hash.h>
  29
  30/* Information for net-next */
  31#define NETNEXT_VERSION		"11"
  32
  33/* Information for net */
  34#define NET_VERSION		"11"
  35
  36#define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
  37#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  38#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  39#define MODULENAME "r8152"
  40
  41#define R8152_PHY_ID		32
  42
  43#define PLA_IDR			0xc000
  44#define PLA_RCR			0xc010
  45#define PLA_RMS			0xc016
  46#define PLA_RXFIFO_CTRL0	0xc0a0
  47#define PLA_RXFIFO_CTRL1	0xc0a4
  48#define PLA_RXFIFO_CTRL2	0xc0a8
  49#define PLA_DMY_REG0		0xc0b0
  50#define PLA_FMC			0xc0b4
  51#define PLA_CFG_WOL		0xc0b6
  52#define PLA_TEREDO_CFG		0xc0bc
  53#define PLA_TEREDO_WAKE_BASE	0xc0c4
  54#define PLA_MAR			0xcd00
  55#define PLA_BACKUP		0xd000
  56#define PLA_BDC_CR		0xd1a0
  57#define PLA_TEREDO_TIMER	0xd2cc
  58#define PLA_REALWOW_TIMER	0xd2e8
  59#define PLA_UPHY_TIMER		0xd388
  60#define PLA_SUSPEND_FLAG	0xd38a
  61#define PLA_INDICATE_FALG	0xd38c
  62#define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */
  63#define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */
  64#define PLA_EXTRA_STATUS	0xd398
  65#define PLA_EFUSE_DATA		0xdd00
  66#define PLA_EFUSE_CMD		0xdd02
  67#define PLA_LEDSEL		0xdd90
  68#define PLA_LED_FEATURE		0xdd92
  69#define PLA_PHYAR		0xde00
  70#define PLA_BOOT_CTRL		0xe004
  71#define PLA_LWAKE_CTRL_REG	0xe007
  72#define PLA_GPHY_INTR_IMR	0xe022
  73#define PLA_EEE_CR		0xe040
  74#define PLA_EEEP_CR		0xe080
  75#define PLA_MAC_PWR_CTRL	0xe0c0
  76#define PLA_MAC_PWR_CTRL2	0xe0ca
  77#define PLA_MAC_PWR_CTRL3	0xe0cc
  78#define PLA_MAC_PWR_CTRL4	0xe0ce
  79#define PLA_WDT6_CTRL		0xe428
  80#define PLA_TCR0		0xe610
  81#define PLA_TCR1		0xe612
  82#define PLA_MTPS		0xe615
  83#define PLA_TXFIFO_CTRL		0xe618
  84#define PLA_RSTTALLY		0xe800
  85#define PLA_CR			0xe813
  86#define PLA_CRWECR		0xe81c
  87#define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
  88#define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
  89#define PLA_CONFIG5		0xe822
  90#define PLA_PHY_PWR		0xe84c
  91#define PLA_OOB_CTRL		0xe84f
  92#define PLA_CPCR		0xe854
  93#define PLA_MISC_0		0xe858
  94#define PLA_MISC_1		0xe85a
  95#define PLA_OCP_GPHY_BASE	0xe86c
  96#define PLA_TALLYCNT		0xe890
  97#define PLA_SFF_STS_7		0xe8de
  98#define PLA_PHYSTATUS		0xe908
  99#define PLA_CONFIG6		0xe90a /* CONFIG6 */
 100#define PLA_BP_BA		0xfc26
 101#define PLA_BP_0		0xfc28
 102#define PLA_BP_1		0xfc2a
 103#define PLA_BP_2		0xfc2c
 104#define PLA_BP_3		0xfc2e
 105#define PLA_BP_4		0xfc30
 106#define PLA_BP_5		0xfc32
 107#define PLA_BP_6		0xfc34
 108#define PLA_BP_7		0xfc36
 109#define PLA_BP_EN		0xfc38
 110
 111#define USB_USB2PHY		0xb41e
 112#define USB_SSPHYLINK1		0xb426
 113#define USB_SSPHYLINK2		0xb428
 114#define USB_U2P3_CTRL		0xb460
 115#define USB_CSR_DUMMY1		0xb464
 116#define USB_CSR_DUMMY2		0xb466
 117#define USB_DEV_STAT		0xb808
 118#define USB_CONNECT_TIMER	0xcbf8
 119#define USB_MSC_TIMER		0xcbfc
 120#define USB_BURST_SIZE		0xcfc0
 121#define USB_FW_FIX_EN0		0xcfca
 122#define USB_FW_FIX_EN1		0xcfcc
 123#define USB_LPM_CONFIG		0xcfd8
 124#define USB_CSTMR		0xcfef	/* RTL8153A */
 125#define USB_FW_CTRL		0xd334	/* RTL8153B */
 126#define USB_FC_TIMER		0xd340
 127#define USB_USB_CTRL		0xd406
 128#define USB_PHY_CTRL		0xd408
 129#define USB_TX_AGG		0xd40a
 130#define USB_RX_BUF_TH		0xd40c
 131#define USB_USB_TIMER		0xd428
 132#define USB_RX_EARLY_TIMEOUT	0xd42c
 133#define USB_RX_EARLY_SIZE	0xd42e
 134#define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
 135#define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
 136#define USB_TX_DMA		0xd434
 137#define USB_UPT_RXDMA_OWN	0xd437
 138#define USB_TOLERANCE		0xd490
 139#define USB_LPM_CTRL		0xd41a
 140#define USB_BMU_RESET		0xd4b0
 141#define USB_U1U2_TIMER		0xd4da
 142#define USB_FW_TASK		0xd4e8	/* RTL8153B */
 143#define USB_UPS_CTRL		0xd800
 144#define USB_POWER_CUT		0xd80a
 145#define USB_MISC_0		0xd81a
 146#define USB_MISC_1		0xd81f
 147#define USB_AFE_CTRL2		0xd824
 148#define USB_UPS_CFG		0xd842
 149#define USB_UPS_FLAGS		0xd848
 150#define USB_WDT1_CTRL		0xe404
 151#define USB_WDT11_CTRL		0xe43c
 152#define USB_BP_BA		PLA_BP_BA
 153#define USB_BP_0		PLA_BP_0
 154#define USB_BP_1		PLA_BP_1
 155#define USB_BP_2		PLA_BP_2
 156#define USB_BP_3		PLA_BP_3
 157#define USB_BP_4		PLA_BP_4
 158#define USB_BP_5		PLA_BP_5
 159#define USB_BP_6		PLA_BP_6
 160#define USB_BP_7		PLA_BP_7
 161#define USB_BP_EN		PLA_BP_EN	/* RTL8153A */
 162#define USB_BP_8		0xfc38		/* RTL8153B */
 163#define USB_BP_9		0xfc3a
 164#define USB_BP_10		0xfc3c
 165#define USB_BP_11		0xfc3e
 166#define USB_BP_12		0xfc40
 167#define USB_BP_13		0xfc42
 168#define USB_BP_14		0xfc44
 169#define USB_BP_15		0xfc46
 170#define USB_BP2_EN		0xfc48
 171
 172/* OCP Registers */
 173#define OCP_ALDPS_CONFIG	0x2010
 174#define OCP_EEE_CONFIG1		0x2080
 175#define OCP_EEE_CONFIG2		0x2092
 176#define OCP_EEE_CONFIG3		0x2094
 177#define OCP_BASE_MII		0xa400
 178#define OCP_EEE_AR		0xa41a
 179#define OCP_EEE_DATA		0xa41c
 180#define OCP_PHY_STATUS		0xa420
 181#define OCP_NCTL_CFG		0xa42c
 182#define OCP_POWER_CFG		0xa430
 183#define OCP_EEE_CFG		0xa432
 184#define OCP_SRAM_ADDR		0xa436
 185#define OCP_SRAM_DATA		0xa438
 186#define OCP_DOWN_SPEED		0xa442
 187#define OCP_EEE_ABLE		0xa5c4
 188#define OCP_EEE_ADV		0xa5d0
 189#define OCP_EEE_LPABLE		0xa5d2
 190#define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
 191#define OCP_PHY_PATCH_STAT	0xb800
 192#define OCP_PHY_PATCH_CMD	0xb820
 193#define OCP_PHY_LOCK		0xb82e
 194#define OCP_ADC_IOFFSET		0xbcfc
 195#define OCP_ADC_CFG		0xbc06
 196#define OCP_SYSCLK_CFG		0xc416
 197
 198/* SRAM Register */
 199#define SRAM_GREEN_CFG		0x8011
 200#define SRAM_LPF_CFG		0x8012
 201#define SRAM_10M_AMP1		0x8080
 202#define SRAM_10M_AMP2		0x8082
 203#define SRAM_IMPEDANCE		0x8084
 204#define SRAM_PHY_LOCK		0xb82e
 205
 206/* PLA_RCR */
 207#define RCR_AAP			0x00000001
 208#define RCR_APM			0x00000002
 209#define RCR_AM			0x00000004
 210#define RCR_AB			0x00000008
 211#define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
 212
 213/* PLA_RXFIFO_CTRL0 */
 214#define RXFIFO_THR1_NORMAL	0x00080002
 215#define RXFIFO_THR1_OOB		0x01800003
 216
 217/* PLA_RXFIFO_CTRL1 */
 218#define RXFIFO_THR2_FULL	0x00000060
 219#define RXFIFO_THR2_HIGH	0x00000038
 220#define RXFIFO_THR2_OOB		0x0000004a
 221#define RXFIFO_THR2_NORMAL	0x00a0
 222
 223/* PLA_RXFIFO_CTRL2 */
 224#define RXFIFO_THR3_FULL	0x00000078
 225#define RXFIFO_THR3_HIGH	0x00000048
 226#define RXFIFO_THR3_OOB		0x0000005a
 227#define RXFIFO_THR3_NORMAL	0x0110
 228
 229/* PLA_TXFIFO_CTRL */
 230#define TXFIFO_THR_NORMAL	0x00400008
 231#define TXFIFO_THR_NORMAL2	0x01000008
 232
 233/* PLA_DMY_REG0 */
 234#define ECM_ALDPS		0x0002
 235
 236/* PLA_FMC */
 237#define FMC_FCR_MCU_EN		0x0001
 238
 239/* PLA_EEEP_CR */
 240#define EEEP_CR_EEEP_TX		0x0002
 241
 242/* PLA_WDT6_CTRL */
 243#define WDT6_SET_MODE		0x0010
 244
 245/* PLA_TCR0 */
 246#define TCR0_TX_EMPTY		0x0800
 247#define TCR0_AUTO_FIFO		0x0080
 248
 249/* PLA_TCR1 */
 250#define VERSION_MASK		0x7cf0
 251
 252/* PLA_MTPS */
 253#define MTPS_JUMBO		(12 * 1024 / 64)
 254#define MTPS_DEFAULT		(6 * 1024 / 64)
 255
 256/* PLA_RSTTALLY */
 257#define TALLY_RESET		0x0001
 258
 259/* PLA_CR */
 260#define CR_RST			0x10
 261#define CR_RE			0x08
 262#define CR_TE			0x04
 263
 264/* PLA_CRWECR */
 265#define CRWECR_NORAML		0x00
 266#define CRWECR_CONFIG		0xc0
 267
 268/* PLA_OOB_CTRL */
 269#define NOW_IS_OOB		0x80
 270#define TXFIFO_EMPTY		0x20
 271#define RXFIFO_EMPTY		0x10
 272#define LINK_LIST_READY		0x02
 273#define DIS_MCU_CLROOB		0x01
 274#define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
 275
 276/* PLA_MISC_1 */
 277#define RXDY_GATED_EN		0x0008
 278
 279/* PLA_SFF_STS_7 */
 280#define RE_INIT_LL		0x8000
 281#define MCU_BORW_EN		0x4000
 282
 283/* PLA_CPCR */
 284#define CPCR_RX_VLAN		0x0040
 285
 286/* PLA_CFG_WOL */
 287#define MAGIC_EN		0x0001
 288
 289/* PLA_TEREDO_CFG */
 290#define TEREDO_SEL		0x8000
 291#define TEREDO_WAKE_MASK	0x7f00
 292#define TEREDO_RS_EVENT_MASK	0x00fe
 293#define OOB_TEREDO_EN		0x0001
 294
 295/* PLA_BDC_CR */
 296#define ALDPS_PROXY_MODE	0x0001
 297
 298/* PLA_EFUSE_CMD */
 299#define EFUSE_READ_CMD		BIT(15)
 300#define EFUSE_DATA_BIT16	BIT(7)
 301
 302/* PLA_CONFIG34 */
 303#define LINK_ON_WAKE_EN		0x0010
 304#define LINK_OFF_WAKE_EN	0x0008
 305
 306/* PLA_CONFIG6 */
 307#define LANWAKE_CLR_EN		BIT(0)
 308
 309/* PLA_CONFIG5 */
 310#define BWF_EN			0x0040
 311#define MWF_EN			0x0020
 312#define UWF_EN			0x0010
 313#define LAN_WAKE_EN		0x0002
 314
 315/* PLA_LED_FEATURE */
 316#define LED_MODE_MASK		0x0700
 317
 318/* PLA_PHY_PWR */
 319#define TX_10M_IDLE_EN		0x0080
 320#define PFM_PWM_SWITCH		0x0040
 321#define TEST_IO_OFF		BIT(4)
 322
 323/* PLA_MAC_PWR_CTRL */
 324#define D3_CLK_GATED_EN		0x00004000
 325#define MCU_CLK_RATIO		0x07010f07
 326#define MCU_CLK_RATIO_MASK	0x0f0f0f0f
 327#define ALDPS_SPDWN_RATIO	0x0f87
 328
 329/* PLA_MAC_PWR_CTRL2 */
 330#define EEE_SPDWN_RATIO		0x8007
 331#define MAC_CLK_SPDWN_EN	BIT(15)
 332
 333/* PLA_MAC_PWR_CTRL3 */
 334#define PLA_MCU_SPDWN_EN	BIT(14)
 335#define PKT_AVAIL_SPDWN_EN	0x0100
 336#define SUSPEND_SPDWN_EN	0x0004
 337#define U1U2_SPDWN_EN		0x0002
 338#define L1_SPDWN_EN		0x0001
 339
 340/* PLA_MAC_PWR_CTRL4 */
 341#define PWRSAVE_SPDWN_EN	0x1000
 342#define RXDV_SPDWN_EN		0x0800
 343#define TX10MIDLE_EN		0x0100
 344#define TP100_SPDWN_EN		0x0020
 345#define TP500_SPDWN_EN		0x0010
 346#define TP1000_SPDWN_EN		0x0008
 347#define EEE_SPDWN_EN		0x0001
 348
 349/* PLA_GPHY_INTR_IMR */
 350#define GPHY_STS_MSK		0x0001
 351#define SPEED_DOWN_MSK		0x0002
 352#define SPDWN_RXDV_MSK		0x0004
 353#define SPDWN_LINKCHG_MSK	0x0008
 354
 355/* PLA_PHYAR */
 356#define PHYAR_FLAG		0x80000000
 357
 358/* PLA_EEE_CR */
 359#define EEE_RX_EN		0x0001
 360#define EEE_TX_EN		0x0002
 361
 362/* PLA_BOOT_CTRL */
 363#define AUTOLOAD_DONE		0x0002
 364
 365/* PLA_LWAKE_CTRL_REG */
 366#define LANWAKE_PIN		BIT(7)
 367
 368/* PLA_SUSPEND_FLAG */
 369#define LINK_CHG_EVENT		BIT(0)
 370
 371/* PLA_INDICATE_FALG */
 372#define UPCOMING_RUNTIME_D3	BIT(0)
 373
 374/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
 375#define DEBUG_OE		BIT(0)
 376#define DEBUG_LTSSM		0x0082
 377
 378/* PLA_EXTRA_STATUS */
 379#define CUR_LINK_OK		BIT(15)
 380#define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */
 381#define LINK_CHANGE_FLAG	BIT(8)
 382#define POLL_LINK_CHG		BIT(0)
 383
 384/* USB_USB2PHY */
 385#define USB2PHY_SUSPEND		0x0001
 386#define USB2PHY_L1		0x0002
 387
 388/* USB_SSPHYLINK1 */
 389#define DELAY_PHY_PWR_CHG	BIT(1)
 390
 391/* USB_SSPHYLINK2 */
 392#define pwd_dn_scale_mask	0x3ffe
 393#define pwd_dn_scale(x)		((x) << 1)
 394
 395/* USB_CSR_DUMMY1 */
 396#define DYNAMIC_BURST		0x0001
 397
 398/* USB_CSR_DUMMY2 */
 399#define EP4_FULL_FC		0x0001
 400
 401/* USB_DEV_STAT */
 402#define STAT_SPEED_MASK		0x0006
 403#define STAT_SPEED_HIGH		0x0000
 404#define STAT_SPEED_FULL		0x0002
 405
 406/* USB_FW_FIX_EN0 */
 407#define FW_FIX_SUSPEND		BIT(14)
 408
 409/* USB_FW_FIX_EN1 */
 410#define FW_IP_RESET_EN		BIT(9)
 411
 412/* USB_LPM_CONFIG */
 413#define LPM_U1U2_EN		BIT(0)
 414
 415/* USB_TX_AGG */
 416#define TX_AGG_MAX_THRESHOLD	0x03
 417
 418/* USB_RX_BUF_TH */
 419#define RX_THR_SUPPER		0x0c350180
 420#define RX_THR_HIGH		0x7a120180
 421#define RX_THR_SLOW		0xffff0180
 422#define RX_THR_B		0x00010001
 423
 424/* USB_TX_DMA */
 425#define TEST_MODE_DISABLE	0x00000001
 426#define TX_SIZE_ADJUST1		0x00000100
 427
 428/* USB_BMU_RESET */
 429#define BMU_RESET_EP_IN		0x01
 430#define BMU_RESET_EP_OUT	0x02
 431
 432/* USB_UPT_RXDMA_OWN */
 433#define OWN_UPDATE		BIT(0)
 434#define OWN_CLEAR		BIT(1)
 435
 436/* USB_FW_TASK */
 437#define FC_PATCH_TASK		BIT(1)
 438
 439/* USB_UPS_CTRL */
 440#define POWER_CUT		0x0100
 441
 442/* USB_PM_CTRL_STATUS */
 443#define RESUME_INDICATE		0x0001
 444
 445/* USB_CSTMR */
 446#define FORCE_SUPER		BIT(0)
 447
 448/* USB_FW_CTRL */
 449#define FLOW_CTRL_PATCH_OPT	BIT(1)
 450
 451/* USB_FC_TIMER */
 452#define CTRL_TIMER_EN		BIT(15)
 453
 454/* USB_USB_CTRL */
 455#define RX_AGG_DISABLE		0x0010
 456#define RX_ZERO_EN		0x0080
 457
 458/* USB_U2P3_CTRL */
 459#define U2P3_ENABLE		0x0001
 460
 461/* USB_POWER_CUT */
 462#define PWR_EN			0x0001
 463#define PHASE2_EN		0x0008
 464#define UPS_EN			BIT(4)
 465#define USP_PREWAKE		BIT(5)
 466
 467/* USB_MISC_0 */
 468#define PCUT_STATUS		0x0001
 469
 470/* USB_RX_EARLY_TIMEOUT */
 471#define COALESCE_SUPER		 85000U
 472#define COALESCE_HIGH		250000U
 473#define COALESCE_SLOW		524280U
 474
 475/* USB_WDT1_CTRL */
 476#define WTD1_EN			BIT(0)
 477
 478/* USB_WDT11_CTRL */
 479#define TIMER11_EN		0x0001
 480
 481/* USB_LPM_CTRL */
 482/* bit 4 ~ 5: fifo empty boundary */
 483#define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
 484/* bit 2 ~ 3: LMP timer */
 485#define LPM_TIMER_MASK		0x0c
 486#define LPM_TIMER_500MS		0x04	/* 500 ms */
 487#define LPM_TIMER_500US		0x0c	/* 500 us */
 488#define ROK_EXIT_LPM		0x02
 489
 490/* USB_AFE_CTRL2 */
 491#define SEN_VAL_MASK		0xf800
 492#define SEN_VAL_NORMAL		0xa000
 493#define SEL_RXIDLE		0x0100
 494
 495/* USB_UPS_CFG */
 496#define SAW_CNT_1MS_MASK	0x0fff
 497
 498/* USB_UPS_FLAGS */
 499#define UPS_FLAGS_R_TUNE		BIT(0)
 500#define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
 501#define UPS_FLAGS_250M_CKDIV		BIT(2)
 502#define UPS_FLAGS_EN_ALDPS		BIT(3)
 503#define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
 504#define ups_flags_speed(x)		((x) << 16)
 505#define UPS_FLAGS_EN_EEE		BIT(20)
 506#define UPS_FLAGS_EN_500M_EEE		BIT(21)
 507#define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
 508#define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)
 509#define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
 510#define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
 511#define UPS_FLAGS_EN_GREEN		BIT(26)
 512#define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
 513
 514enum spd_duplex {
 515	NWAY_10M_HALF,
 516	NWAY_10M_FULL,
 517	NWAY_100M_HALF,
 518	NWAY_100M_FULL,
 519	NWAY_1000M_FULL,
 520	FORCE_10M_HALF,
 521	FORCE_10M_FULL,
 522	FORCE_100M_HALF,
 523	FORCE_100M_FULL,
 524};
 525
 526/* OCP_ALDPS_CONFIG */
 527#define ENPWRSAVE		0x8000
 528#define ENPDNPS			0x0200
 529#define LINKENA			0x0100
 530#define DIS_SDSAVE		0x0010
 531
 532/* OCP_PHY_STATUS */
 533#define PHY_STAT_MASK		0x0007
 534#define PHY_STAT_EXT_INIT	2
 535#define PHY_STAT_LAN_ON		3
 536#define PHY_STAT_PWRDN		5
 537
 538/* OCP_NCTL_CFG */
 539#define PGA_RETURN_EN		BIT(1)
 540
 541/* OCP_POWER_CFG */
 542#define EEE_CLKDIV_EN		0x8000
 543#define EN_ALDPS		0x0004
 544#define EN_10M_PLLOFF		0x0001
 545
 546/* OCP_EEE_CONFIG1 */
 547#define RG_TXLPI_MSK_HFDUP	0x8000
 548#define RG_MATCLR_EN		0x4000
 549#define EEE_10_CAP		0x2000
 550#define EEE_NWAY_EN		0x1000
 551#define TX_QUIET_EN		0x0200
 552#define RX_QUIET_EN		0x0100
 553#define sd_rise_time_mask	0x0070
 554#define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
 555#define RG_RXLPI_MSK_HFDUP	0x0008
 556#define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
 557
 558/* OCP_EEE_CONFIG2 */
 559#define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
 560#define RG_DACQUIET_EN		0x0400
 561#define RG_LDVQUIET_EN		0x0200
 562#define RG_CKRSEL		0x0020
 563#define RG_EEEPRG_EN		0x0010
 564
 565/* OCP_EEE_CONFIG3 */
 566#define fast_snr_mask		0xff80
 567#define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
 568#define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
 569#define MSK_PH			0x0006	/* bit 0 ~ 3 */
 570
 571/* OCP_EEE_AR */
 572/* bit[15:14] function */
 573#define FUN_ADDR		0x0000
 574#define FUN_DATA		0x4000
 575/* bit[4:0] device addr */
 576
 577/* OCP_EEE_CFG */
 578#define CTAP_SHORT_EN		0x0040
 579#define EEE10_EN		0x0010
 580
 581/* OCP_DOWN_SPEED */
 582#define EN_EEE_CMODE		BIT(14)
 583#define EN_EEE_1000		BIT(13)
 584#define EN_EEE_100		BIT(12)
 585#define EN_10M_CLKDIV		BIT(11)
 586#define EN_10M_BGOFF		0x0080
 587
 588/* OCP_PHY_STATE */
 589#define TXDIS_STATE		0x01
 590#define ABD_STATE		0x02
 591
 592/* OCP_PHY_PATCH_STAT */
 593#define PATCH_READY		BIT(6)
 594
 595/* OCP_PHY_PATCH_CMD */
 596#define PATCH_REQUEST		BIT(4)
 597
 598/* OCP_PHY_LOCK */
 599#define PATCH_LOCK		BIT(0)
 600
 601/* OCP_ADC_CFG */
 602#define CKADSEL_L		0x0100
 603#define ADC_EN			0x0080
 604#define EN_EMI_L		0x0040
 605
 606/* OCP_SYSCLK_CFG */
 607#define clk_div_expo(x)		(min(x, 5) << 8)
 608
 609/* SRAM_GREEN_CFG */
 610#define GREEN_ETH_EN		BIT(15)
 611#define R_TUNE_EN		BIT(11)
 612
 613/* SRAM_LPF_CFG */
 614#define LPF_AUTO_TUNE		0x8000
 615
 616/* SRAM_10M_AMP1 */
 617#define GDAC_IB_UPALL		0x0008
 618
 619/* SRAM_10M_AMP2 */
 620#define AMP_DN			0x0200
 621
 622/* SRAM_IMPEDANCE */
 623#define RX_DRIVING_MASK		0x6000
 624
 625/* SRAM_PHY_LOCK */
 626#define PHY_PATCH_LOCK		0x0001
 627
 628/* MAC PASSTHRU */
 629#define AD_MASK			0xfee0
 630#define BND_MASK		0x0004
 631#define BD_MASK			0x0001
 632#define EFUSE			0xcfdb
 633#define PASS_THRU_MASK		0x1
 634
 635#define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */
 636
 637enum rtl_register_content {
 638	_1000bps	= 0x10,
 639	_100bps		= 0x08,
 640	_10bps		= 0x04,
 641	LINK_STATUS	= 0x02,
 642	FULL_DUP	= 0x01,
 643};
 644
 645#define RTL8152_MAX_TX		4
 646#define RTL8152_MAX_RX		10
 647#define INTBUFSIZE		2
 648#define TX_ALIGN		4
 649#define RX_ALIGN		8
 650
 651#define RTL8152_RX_MAX_PENDING	4096
 652#define RTL8152_RXFG_HEADSZ	256
 653
 654#define INTR_LINK		0x0004
 655
 656#define RTL8152_REQT_READ	0xc0
 657#define RTL8152_REQT_WRITE	0x40
 658#define RTL8152_REQ_GET_REGS	0x05
 659#define RTL8152_REQ_SET_REGS	0x05
 660
 661#define BYTE_EN_DWORD		0xff
 662#define BYTE_EN_WORD		0x33
 663#define BYTE_EN_BYTE		0x11
 664#define BYTE_EN_SIX_BYTES	0x3f
 665#define BYTE_EN_START_MASK	0x0f
 666#define BYTE_EN_END_MASK	0xf0
 667
 668#define RTL8153_MAX_PACKET	9216 /* 9K */
 669#define RTL8153_MAX_MTU		(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
 670				 ETH_FCS_LEN)
 671#define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
 672#define RTL8153_RMS		RTL8153_MAX_PACKET
 673#define RTL8152_TX_TIMEOUT	(5 * HZ)
 674#define RTL8152_NAPI_WEIGHT	64
 675#define rx_reserved_size(x)	((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
 676				 sizeof(struct rx_desc) + RX_ALIGN)
 677
 678/* rtl8152 flags */
 679enum rtl8152_flags {
 680	RTL8152_UNPLUG = 0,
 681	RTL8152_SET_RX_MODE,
 682	WORK_ENABLE,
 683	RTL8152_LINK_CHG,
 684	SELECTIVE_SUSPEND,
 685	PHY_RESET,
 686	SCHEDULE_TASKLET,
 687	GREEN_ETHERNET,
 688	DELL_TB_RX_AGG_BUG,
 689	LENOVO_MACPASSTHRU,
 690};
 691
 692/* Define these values to match your device */
 693#define VENDOR_ID_REALTEK		0x0bda
 694#define VENDOR_ID_MICROSOFT		0x045e
 695#define VENDOR_ID_SAMSUNG		0x04e8
 696#define VENDOR_ID_LENOVO		0x17ef
 697#define VENDOR_ID_LINKSYS		0x13b1
 698#define VENDOR_ID_NVIDIA		0x0955
 699#define VENDOR_ID_TPLINK		0x2357
 700
 701#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082
 702#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387
 703
 704#define MCU_TYPE_PLA			0x0100
 705#define MCU_TYPE_USB			0x0000
 706
 707struct tally_counter {
 708	__le64	tx_packets;
 709	__le64	rx_packets;
 710	__le64	tx_errors;
 711	__le32	rx_errors;
 712	__le16	rx_missed;
 713	__le16	align_errors;
 714	__le32	tx_one_collision;
 715	__le32	tx_multi_collision;
 716	__le64	rx_unicast;
 717	__le64	rx_broadcast;
 718	__le32	rx_multicast;
 719	__le16	tx_aborted;
 720	__le16	tx_underrun;
 721};
 722
 723struct rx_desc {
 724	__le32 opts1;
 725#define RX_LEN_MASK			0x7fff
 726
 727	__le32 opts2;
 728#define RD_UDP_CS			BIT(23)
 729#define RD_TCP_CS			BIT(22)
 730#define RD_IPV6_CS			BIT(20)
 731#define RD_IPV4_CS			BIT(19)
 732
 733	__le32 opts3;
 734#define IPF				BIT(23) /* IP checksum fail */
 735#define UDPF				BIT(22) /* UDP checksum fail */
 736#define TCPF				BIT(21) /* TCP checksum fail */
 737#define RX_VLAN_TAG			BIT(16)
 738
 739	__le32 opts4;
 740	__le32 opts5;
 741	__le32 opts6;
 742};
 743
 744struct tx_desc {
 745	__le32 opts1;
 746#define TX_FS			BIT(31) /* First segment of a packet */
 747#define TX_LS			BIT(30) /* Final segment of a packet */
 748#define GTSENDV4		BIT(28)
 749#define GTSENDV6		BIT(27)
 750#define GTTCPHO_SHIFT		18
 751#define GTTCPHO_MAX		0x7fU
 752#define TX_LEN_MAX		0x3ffffU
 753
 754	__le32 opts2;
 755#define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
 756#define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
 757#define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
 758#define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
 759#define MSS_SHIFT		17
 760#define MSS_MAX			0x7ffU
 761#define TCPHO_SHIFT		17
 762#define TCPHO_MAX		0x7ffU
 763#define TX_VLAN_TAG		BIT(16)
 764};
 765
 766struct r8152;
 767
 768struct rx_agg {
 769	struct list_head list, info_list;
 770	struct urb *urb;
 771	struct r8152 *context;
 772	struct page *page;
 773	void *buffer;
 774};
 775
 776struct tx_agg {
 777	struct list_head list;
 778	struct urb *urb;
 779	struct r8152 *context;
 780	void *buffer;
 781	void *head;
 782	u32 skb_num;
 783	u32 skb_len;
 784};
 785
 786struct r8152 {
 787	unsigned long flags;
 788	struct usb_device *udev;
 789	struct napi_struct napi;
 790	struct usb_interface *intf;
 791	struct net_device *netdev;
 792	struct urb *intr_urb;
 793	struct tx_agg tx_info[RTL8152_MAX_TX];
 794	struct list_head rx_info, rx_used;
 795	struct list_head rx_done, tx_free;
 796	struct sk_buff_head tx_queue, rx_queue;
 797	spinlock_t rx_lock, tx_lock;
 798	struct delayed_work schedule, hw_phy_work;
 799	struct mii_if_info mii;
 800	struct mutex control;	/* use for hw setting */
 801#ifdef CONFIG_PM_SLEEP
 802	struct notifier_block pm_notifier;
 803#endif
 804	struct tasklet_struct tx_tl;
 805
 806	struct rtl_ops {
 807		void (*init)(struct r8152 *tp);
 808		int (*enable)(struct r8152 *tp);
 809		void (*disable)(struct r8152 *tp);
 810		void (*up)(struct r8152 *tp);
 811		void (*down)(struct r8152 *tp);
 812		void (*unload)(struct r8152 *tp);
 813		int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
 814		int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
 815		bool (*in_nway)(struct r8152 *tp);
 816		void (*hw_phy_cfg)(struct r8152 *tp);
 817		void (*autosuspend_en)(struct r8152 *tp, bool enable);
 818	} rtl_ops;
 819
 820	struct ups_info {
 821		u32 _10m_ckdiv:1;
 822		u32 _250m_ckdiv:1;
 823		u32 aldps:1;
 824		u32 lite_mode:2;
 825		u32 speed_duplex:4;
 826		u32 eee:1;
 827		u32 eee_lite:1;
 828		u32 eee_ckdiv:1;
 829		u32 eee_plloff_100:1;
 830		u32 eee_plloff_giga:1;
 831		u32 eee_cmod_lv:1;
 832		u32 green:1;
 833		u32 flow_control:1;
 834		u32 ctap_short_off:1;
 835	} ups_info;
 836
 837#define RTL_VER_SIZE		32
 838
 839	struct rtl_fw {
 840		const char *fw_name;
 841		const struct firmware *fw;
 842
 843		char version[RTL_VER_SIZE];
 844		int (*pre_fw)(struct r8152 *tp);
 845		int (*post_fw)(struct r8152 *tp);
 846
 847		bool retry;
 848	} rtl_fw;
 849
 850	atomic_t rx_count;
 851
 852	bool eee_en;
 853	int intr_interval;
 854	u32 saved_wolopts;
 855	u32 msg_enable;
 856	u32 tx_qlen;
 857	u32 coalesce;
 858	u32 advertising;
 859	u32 rx_buf_sz;
 860	u32 rx_copybreak;
 861	u32 rx_pending;
 862
 863	u16 ocp_base;
 864	u16 speed;
 865	u16 eee_adv;
 866	u8 *intr_buff;
 867	u8 version;
 868	u8 duplex;
 869	u8 autoneg;
 870};
 871
 872/**
 873 * struct fw_block - block type and total length
 874 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
 875 *	RTL_FW_USB and so on.
 876 * @length: total length of the current block.
 877 */
 878struct fw_block {
 879	__le32 type;
 880	__le32 length;
 881} __packed;
 882
 883/**
 884 * struct fw_header - header of the firmware file
 885 * @checksum: checksum of sha256 which is calculated from the whole file
 886 *	except the checksum field of the file. That is, calculate sha256
 887 *	from the version field to the end of the file.
 888 * @version: version of this firmware.
 889 * @blocks: the first firmware block of the file
 890 */
 891struct fw_header {
 892	u8 checksum[32];
 893	char version[RTL_VER_SIZE];
 894	struct fw_block blocks[];
 895} __packed;
 896
 897/**
 898 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
 899 *	The layout of the firmware block is:
 900 *	<struct fw_mac> + <info> + <firmware data>.
 901 * @fw_offset: offset of the firmware binary data. The start address of
 902 *	the data would be the address of struct fw_mac + @fw_offset.
 903 * @fw_reg: the register to load the firmware. Depends on chip.
 904 * @bp_ba_addr: the register to write break point base address. Depends on
 905 *	chip.
 906 * @bp_ba_value: break point base address. Depends on chip.
 907 * @bp_en_addr: the register to write break point enabled mask. Depends
 908 *	on chip.
 909 * @bp_en_value: break point enabled mask. Depends on the firmware.
 910 * @bp_start: the start register of break points. Depends on chip.
 911 * @bp_num: the break point number which needs to be set for this firmware.
 912 *	Depends on the firmware.
 913 * @bp: break points. Depends on firmware.
 914 * @fw_ver_reg: the register to store the fw version.
 915 * @fw_ver_data: the firmware version of the current type.
 916 * @info: additional information for debugging, and is followed by the
 917 *	binary data of firmware.
 918 */
 919struct fw_mac {
 920	struct fw_block blk_hdr;
 921	__le16 fw_offset;
 922	__le16 fw_reg;
 923	__le16 bp_ba_addr;
 924	__le16 bp_ba_value;
 925	__le16 bp_en_addr;
 926	__le16 bp_en_value;
 927	__le16 bp_start;
 928	__le16 bp_num;
 929	__le16 bp[16]; /* any value determined by firmware */
 930	__le32 reserved;
 931	__le16 fw_ver_reg;
 932	u8 fw_ver_data;
 933	char info[];
 934} __packed;
 935
 936/**
 937 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
 938 *	This is used to set patch key when loading the firmware of PHY.
 939 * @key_reg: the register to write the patch key.
 940 * @key_data: patch key.
 941 */
 942struct fw_phy_patch_key {
 943	struct fw_block blk_hdr;
 944	__le16 key_reg;
 945	__le16 key_data;
 946	__le32 reserved;
 947} __packed;
 948
 949/**
 950 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
 951 *	The layout of the firmware block is:
 952 *	<struct fw_phy_nc> + <info> + <firmware data>.
 953 * @fw_offset: offset of the firmware binary data. The start address of
 954 *	the data would be the address of struct fw_phy_nc + @fw_offset.
 955 * @fw_reg: the register to load the firmware. Depends on chip.
 956 * @ba_reg: the register to write the base address. Depends on chip.
 957 * @ba_data: base address. Depends on chip.
 958 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
 959 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
 960 * @mode_reg: the regitster of switching the mode.
 961 * @mod_pre: the mode needing to be set before loading the firmware.
 962 * @mod_post: the mode to be set when finishing to load the firmware.
 963 * @bp_start: the start register of break points. Depends on chip.
 964 * @bp_num: the break point number which needs to be set for this firmware.
 965 *	Depends on the firmware.
 966 * @bp: break points. Depends on firmware.
 967 * @info: additional information for debugging, and is followed by the
 968 *	binary data of firmware.
 969 */
 970struct fw_phy_nc {
 971	struct fw_block blk_hdr;
 972	__le16 fw_offset;
 973	__le16 fw_reg;
 974	__le16 ba_reg;
 975	__le16 ba_data;
 976	__le16 patch_en_addr;
 977	__le16 patch_en_value;
 978	__le16 mode_reg;
 979	__le16 mode_pre;
 980	__le16 mode_post;
 981	__le16 reserved;
 982	__le16 bp_start;
 983	__le16 bp_num;
 984	__le16 bp[4];
 985	char info[];
 986} __packed;
 987
 988enum rtl_fw_type {
 989	RTL_FW_END = 0,
 990	RTL_FW_PLA,
 991	RTL_FW_USB,
 992	RTL_FW_PHY_START,
 993	RTL_FW_PHY_STOP,
 994	RTL_FW_PHY_NC,
 995};
 996
 997enum rtl_version {
 998	RTL_VER_UNKNOWN = 0,
 999	RTL_VER_01,
1000	RTL_VER_02,
1001	RTL_VER_03,
1002	RTL_VER_04,
1003	RTL_VER_05,
1004	RTL_VER_06,
1005	RTL_VER_07,
1006	RTL_VER_08,
1007	RTL_VER_09,
1008	RTL_VER_MAX
1009};
1010
1011enum tx_csum_stat {
1012	TX_CSUM_SUCCESS = 0,
1013	TX_CSUM_TSO,
1014	TX_CSUM_NONE
1015};
1016
1017#define RTL_ADVERTISED_10_HALF			BIT(0)
1018#define RTL_ADVERTISED_10_FULL			BIT(1)
1019#define RTL_ADVERTISED_100_HALF			BIT(2)
1020#define RTL_ADVERTISED_100_FULL			BIT(3)
1021#define RTL_ADVERTISED_1000_HALF		BIT(4)
1022#define RTL_ADVERTISED_1000_FULL		BIT(5)
1023
1024/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1025 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1026 */
1027static const int multicast_filter_limit = 32;
1028static unsigned int agg_buf_sz = 16384;
1029
1030#define RTL_LIMITED_TSO_SIZE	(agg_buf_sz - sizeof(struct tx_desc) - \
1031				 VLAN_ETH_HLEN - ETH_FCS_LEN)
1032
1033static
1034int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1035{
1036	int ret;
1037	void *tmp;
1038
1039	tmp = kmalloc(size, GFP_KERNEL);
1040	if (!tmp)
1041		return -ENOMEM;
1042
1043	ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1044			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1045			      value, index, tmp, size, 500);
1046	if (ret < 0)
1047		memset(data, 0xff, size);
1048	else
1049		memcpy(data, tmp, size);
1050
1051	kfree(tmp);
1052
1053	return ret;
1054}
1055
1056static
1057int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1058{
1059	int ret;
1060	void *tmp;
1061
1062	tmp = kmemdup(data, size, GFP_KERNEL);
1063	if (!tmp)
1064		return -ENOMEM;
1065
1066	ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1067			      RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1068			      value, index, tmp, size, 500);
1069
1070	kfree(tmp);
1071
1072	return ret;
1073}
1074
1075static void rtl_set_unplug(struct r8152 *tp)
1076{
1077	if (tp->udev->state == USB_STATE_NOTATTACHED) {
1078		set_bit(RTL8152_UNPLUG, &tp->flags);
1079		smp_mb__after_atomic();
1080	}
1081}
1082
1083static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1084			    void *data, u16 type)
1085{
1086	u16 limit = 64;
1087	int ret = 0;
1088
1089	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1090		return -ENODEV;
1091
1092	/* both size and indix must be 4 bytes align */
1093	if ((size & 3) || !size || (index & 3) || !data)
1094		return -EPERM;
1095
1096	if ((u32)index + (u32)size > 0xffff)
1097		return -EPERM;
1098
1099	while (size) {
1100		if (size > limit) {
1101			ret = get_registers(tp, index, type, limit, data);
1102			if (ret < 0)
1103				break;
1104
1105			index += limit;
1106			data += limit;
1107			size -= limit;
1108		} else {
1109			ret = get_registers(tp, index, type, size, data);
1110			if (ret < 0)
1111				break;
1112
1113			index += size;
1114			data += size;
1115			size = 0;
1116			break;
1117		}
1118	}
1119
1120	if (ret == -ENODEV)
1121		rtl_set_unplug(tp);
1122
1123	return ret;
1124}
1125
1126static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1127			     u16 size, void *data, u16 type)
1128{
1129	int ret;
1130	u16 byteen_start, byteen_end, byen;
1131	u16 limit = 512;
1132
1133	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1134		return -ENODEV;
1135
1136	/* both size and indix must be 4 bytes align */
1137	if ((size & 3) || !size || (index & 3) || !data)
1138		return -EPERM;
1139
1140	if ((u32)index + (u32)size > 0xffff)
1141		return -EPERM;
1142
1143	byteen_start = byteen & BYTE_EN_START_MASK;
1144	byteen_end = byteen & BYTE_EN_END_MASK;
1145
1146	byen = byteen_start | (byteen_start << 4);
1147	ret = set_registers(tp, index, type | byen, 4, data);
1148	if (ret < 0)
1149		goto error1;
1150
1151	index += 4;
1152	data += 4;
1153	size -= 4;
1154
1155	if (size) {
1156		size -= 4;
1157
1158		while (size) {
1159			if (size > limit) {
1160				ret = set_registers(tp, index,
1161						    type | BYTE_EN_DWORD,
1162						    limit, data);
1163				if (ret < 0)
1164					goto error1;
1165
1166				index += limit;
1167				data += limit;
1168				size -= limit;
1169			} else {
1170				ret = set_registers(tp, index,
1171						    type | BYTE_EN_DWORD,
1172						    size, data);
1173				if (ret < 0)
1174					goto error1;
1175
1176				index += size;
1177				data += size;
1178				size = 0;
1179				break;
1180			}
1181		}
1182
1183		byen = byteen_end | (byteen_end >> 4);
1184		ret = set_registers(tp, index, type | byen, 4, data);
1185		if (ret < 0)
1186			goto error1;
1187	}
1188
1189error1:
1190	if (ret == -ENODEV)
1191		rtl_set_unplug(tp);
1192
1193	return ret;
1194}
1195
1196static inline
1197int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1198{
1199	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1200}
1201
1202static inline
1203int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1204{
1205	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1206}
1207
1208static inline
1209int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1210{
1211	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1212}
1213
1214static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1215{
1216	__le32 data;
1217
1218	generic_ocp_read(tp, index, sizeof(data), &data, type);
1219
1220	return __le32_to_cpu(data);
1221}
1222
1223static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1224{
1225	__le32 tmp = __cpu_to_le32(data);
1226
1227	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1228}
1229
1230static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1231{
1232	u32 data;
1233	__le32 tmp;
1234	u16 byen = BYTE_EN_WORD;
1235	u8 shift = index & 2;
1236
1237	index &= ~3;
1238	byen <<= shift;
1239
1240	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1241
1242	data = __le32_to_cpu(tmp);
1243	data >>= (shift * 8);
1244	data &= 0xffff;
1245
1246	return (u16)data;
1247}
1248
1249static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1250{
1251	u32 mask = 0xffff;
1252	__le32 tmp;
1253	u16 byen = BYTE_EN_WORD;
1254	u8 shift = index & 2;
1255
1256	data &= mask;
1257
1258	if (index & 2) {
1259		byen <<= shift;
1260		mask <<= (shift * 8);
1261		data <<= (shift * 8);
1262		index &= ~3;
1263	}
1264
1265	tmp = __cpu_to_le32(data);
1266
1267	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1268}
1269
1270static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1271{
1272	u32 data;
1273	__le32 tmp;
1274	u8 shift = index & 3;
1275
1276	index &= ~3;
1277
1278	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1279
1280	data = __le32_to_cpu(tmp);
1281	data >>= (shift * 8);
1282	data &= 0xff;
1283
1284	return (u8)data;
1285}
1286
1287static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1288{
1289	u32 mask = 0xff;
1290	__le32 tmp;
1291	u16 byen = BYTE_EN_BYTE;
1292	u8 shift = index & 3;
1293
1294	data &= mask;
1295
1296	if (index & 3) {
1297		byen <<= shift;
1298		mask <<= (shift * 8);
1299		data <<= (shift * 8);
1300		index &= ~3;
1301	}
1302
1303	tmp = __cpu_to_le32(data);
1304
1305	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1306}
1307
1308static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1309{
1310	u16 ocp_base, ocp_index;
1311
1312	ocp_base = addr & 0xf000;
1313	if (ocp_base != tp->ocp_base) {
1314		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1315		tp->ocp_base = ocp_base;
1316	}
1317
1318	ocp_index = (addr & 0x0fff) | 0xb000;
1319	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1320}
1321
1322static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1323{
1324	u16 ocp_base, ocp_index;
1325
1326	ocp_base = addr & 0xf000;
1327	if (ocp_base != tp->ocp_base) {
1328		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1329		tp->ocp_base = ocp_base;
1330	}
1331
1332	ocp_index = (addr & 0x0fff) | 0xb000;
1333	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1334}
1335
1336static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1337{
1338	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1339}
1340
1341static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1342{
1343	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1344}
1345
1346static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1347{
1348	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1349	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1350}
1351
1352static u16 sram_read(struct r8152 *tp, u16 addr)
1353{
1354	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1355	return ocp_reg_read(tp, OCP_SRAM_DATA);
1356}
1357
1358static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1359{
1360	struct r8152 *tp = netdev_priv(netdev);
1361	int ret;
1362
1363	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1364		return -ENODEV;
1365
1366	if (phy_id != R8152_PHY_ID)
1367		return -EINVAL;
1368
1369	ret = r8152_mdio_read(tp, reg);
1370
1371	return ret;
1372}
1373
1374static
1375void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1376{
1377	struct r8152 *tp = netdev_priv(netdev);
1378
1379	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1380		return;
1381
1382	if (phy_id != R8152_PHY_ID)
1383		return;
1384
1385	r8152_mdio_write(tp, reg, val);
1386}
1387
1388static int
1389r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1390
1391static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1392{
1393	struct r8152 *tp = netdev_priv(netdev);
1394	struct sockaddr *addr = p;
1395	int ret = -EADDRNOTAVAIL;
1396
1397	if (!is_valid_ether_addr(addr->sa_data))
1398		goto out1;
1399
1400	ret = usb_autopm_get_interface(tp->intf);
1401	if (ret < 0)
1402		goto out1;
1403
1404	mutex_lock(&tp->control);
1405
1406	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1407
1408	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1409	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1410	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1411
1412	mutex_unlock(&tp->control);
1413
1414	usb_autopm_put_interface(tp->intf);
1415out1:
1416	return ret;
1417}
1418
1419/* Devices containing proper chips can support a persistent
1420 * host system provided MAC address.
1421 * Examples of this are Dell TB15 and Dell WD15 docks
1422 */
1423static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1424{
1425	acpi_status status;
1426	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1427	union acpi_object *obj;
1428	int ret = -EINVAL;
1429	u32 ocp_data;
1430	unsigned char buf[6];
1431	char *mac_obj_name;
1432	acpi_object_type mac_obj_type;
1433	int mac_strlen;
1434
1435	if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1436		mac_obj_name = "\\MACA";
1437		mac_obj_type = ACPI_TYPE_STRING;
1438		mac_strlen = 0x16;
1439	} else {
1440		/* test for -AD variant of RTL8153 */
1441		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1442		if ((ocp_data & AD_MASK) == 0x1000) {
1443			/* test for MAC address pass-through bit */
1444			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1445			if ((ocp_data & PASS_THRU_MASK) != 1) {
1446				netif_dbg(tp, probe, tp->netdev,
1447						"No efuse for RTL8153-AD MAC pass through\n");
1448				return -ENODEV;
1449			}
1450		} else {
1451			/* test for RTL8153-BND and RTL8153-BD */
1452			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1453			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1454				netif_dbg(tp, probe, tp->netdev,
1455						"Invalid variant for MAC pass through\n");
1456				return -ENODEV;
1457			}
1458		}
1459
1460		mac_obj_name = "\\_SB.AMAC";
1461		mac_obj_type = ACPI_TYPE_BUFFER;
1462		mac_strlen = 0x17;
1463	}
1464
1465	/* returns _AUXMAC_#AABBCCDDEEFF# */
1466	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1467	obj = (union acpi_object *)buffer.pointer;
1468	if (!ACPI_SUCCESS(status))
1469		return -ENODEV;
1470	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1471		netif_warn(tp, probe, tp->netdev,
1472			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1473			   obj->type, obj->string.length);
1474		goto amacout;
1475	}
1476
1477	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1478	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1479		netif_warn(tp, probe, tp->netdev,
1480			   "Invalid header when reading pass-thru MAC addr\n");
1481		goto amacout;
1482	}
1483	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1484	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1485		netif_warn(tp, probe, tp->netdev,
1486			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1487			   ret, buf);
1488		ret = -EINVAL;
1489		goto amacout;
1490	}
1491	memcpy(sa->sa_data, buf, 6);
1492	netif_info(tp, probe, tp->netdev,
1493		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1494
1495amacout:
1496	kfree(obj);
1497	return ret;
1498}
1499
1500static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1501{
1502	struct net_device *dev = tp->netdev;
1503	int ret;
1504
1505	sa->sa_family = dev->type;
1506
1507	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1508	if (ret < 0) {
1509		if (tp->version == RTL_VER_01) {
1510			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1511		} else {
1512			/* if device doesn't support MAC pass through this will
1513			 * be expected to be non-zero
1514			 */
1515			ret = vendor_mac_passthru_addr_read(tp, sa);
1516			if (ret < 0)
1517				ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1518						   sa->sa_data);
1519		}
1520	}
1521
1522	if (ret < 0) {
1523		netif_err(tp, probe, dev, "Get ether addr fail\n");
1524	} else if (!is_valid_ether_addr(sa->sa_data)) {
1525		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1526			  sa->sa_data);
1527		eth_hw_addr_random(dev);
1528		ether_addr_copy(sa->sa_data, dev->dev_addr);
1529		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1530			   sa->sa_data);
1531		return 0;
1532	}
1533
1534	return ret;
1535}
1536
1537static int set_ethernet_addr(struct r8152 *tp)
1538{
1539	struct net_device *dev = tp->netdev;
1540	struct sockaddr sa;
1541	int ret;
1542
1543	ret = determine_ethernet_addr(tp, &sa);
1544	if (ret < 0)
1545		return ret;
1546
1547	if (tp->version == RTL_VER_01)
1548		ether_addr_copy(dev->dev_addr, sa.sa_data);
1549	else
1550		ret = rtl8152_set_mac_address(dev, &sa);
1551
1552	return ret;
1553}
1554
1555static void read_bulk_callback(struct urb *urb)
1556{
1557	struct net_device *netdev;
1558	int status = urb->status;
1559	struct rx_agg *agg;
1560	struct r8152 *tp;
1561	unsigned long flags;
1562
1563	agg = urb->context;
1564	if (!agg)
1565		return;
1566
1567	tp = agg->context;
1568	if (!tp)
1569		return;
1570
1571	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1572		return;
1573
1574	if (!test_bit(WORK_ENABLE, &tp->flags))
1575		return;
1576
1577	netdev = tp->netdev;
1578
1579	/* When link down, the driver would cancel all bulks. */
1580	/* This avoid the re-submitting bulk */
1581	if (!netif_carrier_ok(netdev))
1582		return;
1583
1584	usb_mark_last_busy(tp->udev);
1585
1586	switch (status) {
1587	case 0:
1588		if (urb->actual_length < ETH_ZLEN)
1589			break;
1590
1591		spin_lock_irqsave(&tp->rx_lock, flags);
1592		list_add_tail(&agg->list, &tp->rx_done);
1593		spin_unlock_irqrestore(&tp->rx_lock, flags);
1594		napi_schedule(&tp->napi);
1595		return;
1596	case -ESHUTDOWN:
1597		rtl_set_unplug(tp);
1598		netif_device_detach(tp->netdev);
1599		return;
1600	case -ENOENT:
1601		return;	/* the urb is in unlink state */
1602	case -ETIME:
1603		if (net_ratelimit())
1604			netdev_warn(netdev, "maybe reset is needed?\n");
1605		break;
1606	default:
1607		if (net_ratelimit())
1608			netdev_warn(netdev, "Rx status %d\n", status);
1609		break;
1610	}
1611
1612	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1613}
1614
1615static void write_bulk_callback(struct urb *urb)
1616{
1617	struct net_device_stats *stats;
1618	struct net_device *netdev;
1619	struct tx_agg *agg;
1620	struct r8152 *tp;
1621	unsigned long flags;
1622	int status = urb->status;
1623
1624	agg = urb->context;
1625	if (!agg)
1626		return;
1627
1628	tp = agg->context;
1629	if (!tp)
1630		return;
1631
1632	netdev = tp->netdev;
1633	stats = &netdev->stats;
1634	if (status) {
1635		if (net_ratelimit())
1636			netdev_warn(netdev, "Tx status %d\n", status);
1637		stats->tx_errors += agg->skb_num;
1638	} else {
1639		stats->tx_packets += agg->skb_num;
1640		stats->tx_bytes += agg->skb_len;
1641	}
1642
1643	spin_lock_irqsave(&tp->tx_lock, flags);
1644	list_add_tail(&agg->list, &tp->tx_free);
1645	spin_unlock_irqrestore(&tp->tx_lock, flags);
1646
1647	usb_autopm_put_interface_async(tp->intf);
1648
1649	if (!netif_carrier_ok(netdev))
1650		return;
1651
1652	if (!test_bit(WORK_ENABLE, &tp->flags))
1653		return;
1654
1655	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1656		return;
1657
1658	if (!skb_queue_empty(&tp->tx_queue))
1659		tasklet_schedule(&tp->tx_tl);
1660}
1661
1662static void intr_callback(struct urb *urb)
1663{
1664	struct r8152 *tp;
1665	__le16 *d;
1666	int status = urb->status;
1667	int res;
1668
1669	tp = urb->context;
1670	if (!tp)
1671		return;
1672
1673	if (!test_bit(WORK_ENABLE, &tp->flags))
1674		return;
1675
1676	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1677		return;
1678
1679	switch (status) {
1680	case 0:			/* success */
1681		break;
1682	case -ECONNRESET:	/* unlink */
1683	case -ESHUTDOWN:
1684		netif_device_detach(tp->netdev);
1685		fallthrough;
1686	case -ENOENT:
1687	case -EPROTO:
1688		netif_info(tp, intr, tp->netdev,
1689			   "Stop submitting intr, status %d\n", status);
1690		return;
1691	case -EOVERFLOW:
1692		netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1693		goto resubmit;
1694	/* -EPIPE:  should clear the halt */
1695	default:
1696		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1697		goto resubmit;
1698	}
1699
1700	d = urb->transfer_buffer;
1701	if (INTR_LINK & __le16_to_cpu(d[0])) {
1702		if (!netif_carrier_ok(tp->netdev)) {
1703			set_bit(RTL8152_LINK_CHG, &tp->flags);
1704			schedule_delayed_work(&tp->schedule, 0);
1705		}
1706	} else {
1707		if (netif_carrier_ok(tp->netdev)) {
1708			netif_stop_queue(tp->netdev);
1709			set_bit(RTL8152_LINK_CHG, &tp->flags);
1710			schedule_delayed_work(&tp->schedule, 0);
1711		}
1712	}
1713
1714resubmit:
1715	res = usb_submit_urb(urb, GFP_ATOMIC);
1716	if (res == -ENODEV) {
1717		rtl_set_unplug(tp);
1718		netif_device_detach(tp->netdev);
1719	} else if (res) {
1720		netif_err(tp, intr, tp->netdev,
1721			  "can't resubmit intr, status %d\n", res);
1722	}
1723}
1724
1725static inline void *rx_agg_align(void *data)
1726{
1727	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1728}
1729
1730static inline void *tx_agg_align(void *data)
1731{
1732	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1733}
1734
1735static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1736{
1737	list_del(&agg->info_list);
1738
1739	usb_free_urb(agg->urb);
1740	put_page(agg->page);
1741	kfree(agg);
1742
1743	atomic_dec(&tp->rx_count);
1744}
1745
1746static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1747{
1748	struct net_device *netdev = tp->netdev;
1749	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1750	unsigned int order = get_order(tp->rx_buf_sz);
1751	struct rx_agg *rx_agg;
1752	unsigned long flags;
1753
1754	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1755	if (!rx_agg)
1756		return NULL;
1757
1758	rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1759	if (!rx_agg->page)
1760		goto free_rx;
1761
1762	rx_agg->buffer = page_address(rx_agg->page);
1763
1764	rx_agg->urb = usb_alloc_urb(0, mflags);
1765	if (!rx_agg->urb)
1766		goto free_buf;
1767
1768	rx_agg->context = tp;
1769
1770	INIT_LIST_HEAD(&rx_agg->list);
1771	INIT_LIST_HEAD(&rx_agg->info_list);
1772	spin_lock_irqsave(&tp->rx_lock, flags);
1773	list_add_tail(&rx_agg->info_list, &tp->rx_info);
1774	spin_unlock_irqrestore(&tp->rx_lock, flags);
1775
1776	atomic_inc(&tp->rx_count);
1777
1778	return rx_agg;
1779
1780free_buf:
1781	__free_pages(rx_agg->page, order);
1782free_rx:
1783	kfree(rx_agg);
1784	return NULL;
1785}
1786
1787static void free_all_mem(struct r8152 *tp)
1788{
1789	struct rx_agg *agg, *agg_next;
1790	unsigned long flags;
1791	int i;
1792
1793	spin_lock_irqsave(&tp->rx_lock, flags);
1794
1795	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1796		free_rx_agg(tp, agg);
1797
1798	spin_unlock_irqrestore(&tp->rx_lock, flags);
1799
1800	WARN_ON(atomic_read(&tp->rx_count));
1801
1802	for (i = 0; i < RTL8152_MAX_TX; i++) {
1803		usb_free_urb(tp->tx_info[i].urb);
1804		tp->tx_info[i].urb = NULL;
1805
1806		kfree(tp->tx_info[i].buffer);
1807		tp->tx_info[i].buffer = NULL;
1808		tp->tx_info[i].head = NULL;
1809	}
1810
1811	usb_free_urb(tp->intr_urb);
1812	tp->intr_urb = NULL;
1813
1814	kfree(tp->intr_buff);
1815	tp->intr_buff = NULL;
1816}
1817
1818static int alloc_all_mem(struct r8152 *tp)
1819{
1820	struct net_device *netdev = tp->netdev;
1821	struct usb_interface *intf = tp->intf;
1822	struct usb_host_interface *alt = intf->cur_altsetting;
1823	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1824	int node, i;
1825
1826	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1827
1828	spin_lock_init(&tp->rx_lock);
1829	spin_lock_init(&tp->tx_lock);
1830	INIT_LIST_HEAD(&tp->rx_info);
1831	INIT_LIST_HEAD(&tp->tx_free);
1832	INIT_LIST_HEAD(&tp->rx_done);
1833	skb_queue_head_init(&tp->tx_queue);
1834	skb_queue_head_init(&tp->rx_queue);
1835	atomic_set(&tp->rx_count, 0);
1836
1837	for (i = 0; i < RTL8152_MAX_RX; i++) {
1838		if (!alloc_rx_agg(tp, GFP_KERNEL))
1839			goto err1;
1840	}
1841
1842	for (i = 0; i < RTL8152_MAX_TX; i++) {
1843		struct urb *urb;
1844		u8 *buf;
1845
1846		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1847		if (!buf)
1848			goto err1;
1849
1850		if (buf != tx_agg_align(buf)) {
1851			kfree(buf);
1852			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1853					   node);
1854			if (!buf)
1855				goto err1;
1856		}
1857
1858		urb = usb_alloc_urb(0, GFP_KERNEL);
1859		if (!urb) {
1860			kfree(buf);
1861			goto err1;
1862		}
1863
1864		INIT_LIST_HEAD(&tp->tx_info[i].list);
1865		tp->tx_info[i].context = tp;
1866		tp->tx_info[i].urb = urb;
1867		tp->tx_info[i].buffer = buf;
1868		tp->tx_info[i].head = tx_agg_align(buf);
1869
1870		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1871	}
1872
1873	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1874	if (!tp->intr_urb)
1875		goto err1;
1876
1877	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1878	if (!tp->intr_buff)
1879		goto err1;
1880
1881	tp->intr_interval = (int)ep_intr->desc.bInterval;
1882	usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1883			 tp->intr_buff, INTBUFSIZE, intr_callback,
1884			 tp, tp->intr_interval);
1885
1886	return 0;
1887
1888err1:
1889	free_all_mem(tp);
1890	return -ENOMEM;
1891}
1892
1893static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1894{
1895	struct tx_agg *agg = NULL;
1896	unsigned long flags;
1897
1898	if (list_empty(&tp->tx_free))
1899		return NULL;
1900
1901	spin_lock_irqsave(&tp->tx_lock, flags);
1902	if (!list_empty(&tp->tx_free)) {
1903		struct list_head *cursor;
1904
1905		cursor = tp->tx_free.next;
1906		list_del_init(cursor);
1907		agg = list_entry(cursor, struct tx_agg, list);
1908	}
1909	spin_unlock_irqrestore(&tp->tx_lock, flags);
1910
1911	return agg;
1912}
1913
1914/* r8152_csum_workaround()
1915 * The hw limits the value of the transport offset. When the offset is out of
1916 * range, calculate the checksum by sw.
1917 */
1918static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1919				  struct sk_buff_head *list)
1920{
1921	if (skb_shinfo(skb)->gso_size) {
1922		netdev_features_t features = tp->netdev->features;
1923		struct sk_buff *segs, *seg, *next;
1924		struct sk_buff_head seg_list;
1925
1926		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1927		segs = skb_gso_segment(skb, features);
1928		if (IS_ERR(segs) || !segs)
1929			goto drop;
1930
1931		__skb_queue_head_init(&seg_list);
1932
1933		skb_list_walk_safe(segs, seg, next) {
1934			skb_mark_not_on_list(seg);
1935			__skb_queue_tail(&seg_list, seg);
1936		}
1937
1938		skb_queue_splice(&seg_list, list);
1939		dev_kfree_skb(skb);
1940	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1941		if (skb_checksum_help(skb) < 0)
1942			goto drop;
1943
1944		__skb_queue_head(list, skb);
1945	} else {
1946		struct net_device_stats *stats;
1947
1948drop:
1949		stats = &tp->netdev->stats;
1950		stats->tx_dropped++;
1951		dev_kfree_skb(skb);
1952	}
1953}
1954
1955static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1956{
1957	if (skb_vlan_tag_present(skb)) {
1958		u32 opts2;
1959
1960		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1961		desc->opts2 |= cpu_to_le32(opts2);
1962	}
1963}
1964
1965static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1966{
1967	u32 opts2 = le32_to_cpu(desc->opts2);
1968
1969	if (opts2 & RX_VLAN_TAG)
1970		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1971				       swab16(opts2 & 0xffff));
1972}
1973
1974static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1975			 struct sk_buff *skb, u32 len, u32 transport_offset)
1976{
1977	u32 mss = skb_shinfo(skb)->gso_size;
1978	u32 opts1, opts2 = 0;
1979	int ret = TX_CSUM_SUCCESS;
1980
1981	WARN_ON_ONCE(len > TX_LEN_MAX);
1982
1983	opts1 = len | TX_FS | TX_LS;
1984
1985	if (mss) {
1986		if (transport_offset > GTTCPHO_MAX) {
1987			netif_warn(tp, tx_err, tp->netdev,
1988				   "Invalid transport offset 0x%x for TSO\n",
1989				   transport_offset);
1990			ret = TX_CSUM_TSO;
1991			goto unavailable;
1992		}
1993
1994		switch (vlan_get_protocol(skb)) {
1995		case htons(ETH_P_IP):
1996			opts1 |= GTSENDV4;
1997			break;
1998
1999		case htons(ETH_P_IPV6):
2000			if (skb_cow_head(skb, 0)) {
2001				ret = TX_CSUM_TSO;
2002				goto unavailable;
2003			}
2004			tcp_v6_gso_csum_prep(skb);
2005			opts1 |= GTSENDV6;
2006			break;
2007
2008		default:
2009			WARN_ON_ONCE(1);
2010			break;
2011		}
2012
2013		opts1 |= transport_offset << GTTCPHO_SHIFT;
2014		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2015	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2016		u8 ip_protocol;
2017
2018		if (transport_offset > TCPHO_MAX) {
2019			netif_warn(tp, tx_err, tp->netdev,
2020				   "Invalid transport offset 0x%x\n",
2021				   transport_offset);
2022			ret = TX_CSUM_NONE;
2023			goto unavailable;
2024		}
2025
2026		switch (vlan_get_protocol(skb)) {
2027		case htons(ETH_P_IP):
2028			opts2 |= IPV4_CS;
2029			ip_protocol = ip_hdr(skb)->protocol;
2030			break;
2031
2032		case htons(ETH_P_IPV6):
2033			opts2 |= IPV6_CS;
2034			ip_protocol = ipv6_hdr(skb)->nexthdr;
2035			break;
2036
2037		default:
2038			ip_protocol = IPPROTO_RAW;
2039			break;
2040		}
2041
2042		if (ip_protocol == IPPROTO_TCP)
2043			opts2 |= TCP_CS;
2044		else if (ip_protocol == IPPROTO_UDP)
2045			opts2 |= UDP_CS;
2046		else
2047			WARN_ON_ONCE(1);
2048
2049		opts2 |= transport_offset << TCPHO_SHIFT;
2050	}
2051
2052	desc->opts2 = cpu_to_le32(opts2);
2053	desc->opts1 = cpu_to_le32(opts1);
2054
2055unavailable:
2056	return ret;
2057}
2058
2059static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2060{
2061	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2062	int remain, ret;
2063	u8 *tx_data;
2064
2065	__skb_queue_head_init(&skb_head);
2066	spin_lock(&tx_queue->lock);
2067	skb_queue_splice_init(tx_queue, &skb_head);
2068	spin_unlock(&tx_queue->lock);
2069
2070	tx_data = agg->head;
2071	agg->skb_num = 0;
2072	agg->skb_len = 0;
2073	remain = agg_buf_sz;
2074
2075	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2076		struct tx_desc *tx_desc;
2077		struct sk_buff *skb;
2078		unsigned int len;
2079		u32 offset;
2080
2081		skb = __skb_dequeue(&skb_head);
2082		if (!skb)
2083			break;
2084
2085		len = skb->len + sizeof(*tx_desc);
2086
2087		if (len > remain) {
2088			__skb_queue_head(&skb_head, skb);
2089			break;
2090		}
2091
2092		tx_data = tx_agg_align(tx_data);
2093		tx_desc = (struct tx_desc *)tx_data;
2094
2095		offset = (u32)skb_transport_offset(skb);
2096
2097		if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2098			r8152_csum_workaround(tp, skb, &skb_head);
2099			continue;
2100		}
2101
2102		rtl_tx_vlan_tag(tx_desc, skb);
2103
2104		tx_data += sizeof(*tx_desc);
2105
2106		len = skb->len;
2107		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2108			struct net_device_stats *stats = &tp->netdev->stats;
2109
2110			stats->tx_dropped++;
2111			dev_kfree_skb_any(skb);
2112			tx_data -= sizeof(*tx_desc);
2113			continue;
2114		}
2115
2116		tx_data += len;
2117		agg->skb_len += len;
2118		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2119
2120		dev_kfree_skb_any(skb);
2121
2122		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2123
2124		if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2125			break;
2126	}
2127
2128	if (!skb_queue_empty(&skb_head)) {
2129		spin_lock(&tx_queue->lock);
2130		skb_queue_splice(&skb_head, tx_queue);
2131		spin_unlock(&tx_queue->lock);
2132	}
2133
2134	netif_tx_lock(tp->netdev);
2135
2136	if (netif_queue_stopped(tp->netdev) &&
2137	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2138		netif_wake_queue(tp->netdev);
2139
2140	netif_tx_unlock(tp->netdev);
2141
2142	ret = usb_autopm_get_interface_async(tp->intf);
2143	if (ret < 0)
2144		goto out_tx_fill;
2145
2146	usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2147			  agg->head, (int)(tx_data - (u8 *)agg->head),
2148			  (usb_complete_t)write_bulk_callback, agg);
2149
2150	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2151	if (ret < 0)
2152		usb_autopm_put_interface_async(tp->intf);
2153
2154out_tx_fill:
2155	return ret;
2156}
2157
2158static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2159{
2160	u8 checksum = CHECKSUM_NONE;
2161	u32 opts2, opts3;
2162
2163	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2164		goto return_result;
2165
2166	opts2 = le32_to_cpu(rx_desc->opts2);
2167	opts3 = le32_to_cpu(rx_desc->opts3);
2168
2169	if (opts2 & RD_IPV4_CS) {
2170		if (opts3 & IPF)
2171			checksum = CHECKSUM_NONE;
2172		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2173			checksum = CHECKSUM_UNNECESSARY;
2174		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2175			checksum = CHECKSUM_UNNECESSARY;
2176	} else if (opts2 & RD_IPV6_CS) {
2177		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2178			checksum = CHECKSUM_UNNECESSARY;
2179		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2180			checksum = CHECKSUM_UNNECESSARY;
2181	}
2182
2183return_result:
2184	return checksum;
2185}
2186
2187static inline bool rx_count_exceed(struct r8152 *tp)
2188{
2189	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2190}
2191
2192static inline int agg_offset(struct rx_agg *agg, void *addr)
2193{
2194	return (int)(addr - agg->buffer);
2195}
2196
2197static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2198{
2199	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2200	unsigned long flags;
2201
2202	spin_lock_irqsave(&tp->rx_lock, flags);
2203
2204	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2205		if (page_count(agg->page) == 1) {
2206			if (!agg_free) {
2207				list_del_init(&agg->list);
2208				agg_free = agg;
2209				continue;
2210			}
2211			if (rx_count_exceed(tp)) {
2212				list_del_init(&agg->list);
2213				free_rx_agg(tp, agg);
2214			}
2215			break;
2216		}
2217	}
2218
2219	spin_unlock_irqrestore(&tp->rx_lock, flags);
2220
2221	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2222		agg_free = alloc_rx_agg(tp, mflags);
2223
2224	return agg_free;
2225}
2226
2227static int rx_bottom(struct r8152 *tp, int budget)
2228{
2229	unsigned long flags;
2230	struct list_head *cursor, *next, rx_queue;
2231	int ret = 0, work_done = 0;
2232	struct napi_struct *napi = &tp->napi;
2233
2234	if (!skb_queue_empty(&tp->rx_queue)) {
2235		while (work_done < budget) {
2236			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2237			struct net_device *netdev = tp->netdev;
2238			struct net_device_stats *stats = &netdev->stats;
2239			unsigned int pkt_len;
2240
2241			if (!skb)
2242				break;
2243
2244			pkt_len = skb->len;
2245			napi_gro_receive(napi, skb);
2246			work_done++;
2247			stats->rx_packets++;
2248			stats->rx_bytes += pkt_len;
2249		}
2250	}
2251
2252	if (list_empty(&tp->rx_done))
2253		goto out1;
2254
2255	INIT_LIST_HEAD(&rx_queue);
2256	spin_lock_irqsave(&tp->rx_lock, flags);
2257	list_splice_init(&tp->rx_done, &rx_queue);
2258	spin_unlock_irqrestore(&tp->rx_lock, flags);
2259
2260	list_for_each_safe(cursor, next, &rx_queue) {
2261		struct rx_desc *rx_desc;
2262		struct rx_agg *agg, *agg_free;
2263		int len_used = 0;
2264		struct urb *urb;
2265		u8 *rx_data;
2266
2267		list_del_init(cursor);
2268
2269		agg = list_entry(cursor, struct rx_agg, list);
2270		urb = agg->urb;
2271		if (urb->actual_length < ETH_ZLEN)
2272			goto submit;
2273
2274		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2275
2276		rx_desc = agg->buffer;
2277		rx_data = agg->buffer;
2278		len_used += sizeof(struct rx_desc);
2279
2280		while (urb->actual_length > len_used) {
2281			struct net_device *netdev = tp->netdev;
2282			struct net_device_stats *stats = &netdev->stats;
2283			unsigned int pkt_len, rx_frag_head_sz;
2284			struct sk_buff *skb;
2285
2286			/* limite the skb numbers for rx_queue */
2287			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2288				break;
2289
2290			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2291			if (pkt_len < ETH_ZLEN)
2292				break;
2293
2294			len_used += pkt_len;
2295			if (urb->actual_length < len_used)
2296				break;
2297
2298			pkt_len -= ETH_FCS_LEN;
2299			rx_data += sizeof(struct rx_desc);
2300
2301			if (!agg_free || tp->rx_copybreak > pkt_len)
2302				rx_frag_head_sz = pkt_len;
2303			else
2304				rx_frag_head_sz = tp->rx_copybreak;
2305
2306			skb = napi_alloc_skb(napi, rx_frag_head_sz);
2307			if (!skb) {
2308				stats->rx_dropped++;
2309				goto find_next_rx;
2310			}
2311
2312			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2313			memcpy(skb->data, rx_data, rx_frag_head_sz);
2314			skb_put(skb, rx_frag_head_sz);
2315			pkt_len -= rx_frag_head_sz;
2316			rx_data += rx_frag_head_sz;
2317			if (pkt_len) {
2318				skb_add_rx_frag(skb, 0, agg->page,
2319						agg_offset(agg, rx_data),
2320						pkt_len,
2321						SKB_DATA_ALIGN(pkt_len));
2322				get_page(agg->page);
2323			}
2324
2325			skb->protocol = eth_type_trans(skb, netdev);
2326			rtl_rx_vlan_tag(rx_desc, skb);
2327			if (work_done < budget) {
2328				work_done++;
2329				stats->rx_packets++;
2330				stats->rx_bytes += skb->len;
2331				napi_gro_receive(napi, skb);
2332			} else {
2333				__skb_queue_tail(&tp->rx_queue, skb);
2334			}
2335
2336find_next_rx:
2337			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2338			rx_desc = (struct rx_desc *)rx_data;
2339			len_used = agg_offset(agg, rx_data);
2340			len_used += sizeof(struct rx_desc);
2341		}
2342
2343		WARN_ON(!agg_free && page_count(agg->page) > 1);
2344
2345		if (agg_free) {
2346			spin_lock_irqsave(&tp->rx_lock, flags);
2347			if (page_count(agg->page) == 1) {
2348				list_add(&agg_free->list, &tp->rx_used);
2349			} else {
2350				list_add_tail(&agg->list, &tp->rx_used);
2351				agg = agg_free;
2352				urb = agg->urb;
2353			}
2354			spin_unlock_irqrestore(&tp->rx_lock, flags);
2355		}
2356
2357submit:
2358		if (!ret) {
2359			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2360		} else {
2361			urb->actual_length = 0;
2362			list_add_tail(&agg->list, next);
2363		}
2364	}
2365
2366	if (!list_empty(&rx_queue)) {
2367		spin_lock_irqsave(&tp->rx_lock, flags);
2368		list_splice_tail(&rx_queue, &tp->rx_done);
2369		spin_unlock_irqrestore(&tp->rx_lock, flags);
2370	}
2371
2372out1:
2373	return work_done;
2374}
2375
2376static void tx_bottom(struct r8152 *tp)
2377{
2378	int res;
2379
2380	do {
2381		struct net_device *netdev = tp->netdev;
2382		struct tx_agg *agg;
2383
2384		if (skb_queue_empty(&tp->tx_queue))
2385			break;
2386
2387		agg = r8152_get_tx_agg(tp);
2388		if (!agg)
2389			break;
2390
2391		res = r8152_tx_agg_fill(tp, agg);
2392		if (!res)
2393			continue;
2394
2395		if (res == -ENODEV) {
2396			rtl_set_unplug(tp);
2397			netif_device_detach(netdev);
2398		} else {
2399			struct net_device_stats *stats = &netdev->stats;
2400			unsigned long flags;
2401
2402			netif_warn(tp, tx_err, netdev,
2403				   "failed tx_urb %d\n", res);
2404			stats->tx_dropped += agg->skb_num;
2405
2406			spin_lock_irqsave(&tp->tx_lock, flags);
2407			list_add_tail(&agg->list, &tp->tx_free);
2408			spin_unlock_irqrestore(&tp->tx_lock, flags);
2409		}
2410	} while (res == 0);
2411}
2412
2413static void bottom_half(unsigned long data)
2414{
2415	struct r8152 *tp;
2416
2417	tp = (struct r8152 *)data;
2418
2419	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2420		return;
2421
2422	if (!test_bit(WORK_ENABLE, &tp->flags))
2423		return;
2424
2425	/* When link down, the driver would cancel all bulks. */
2426	/* This avoid the re-submitting bulk */
2427	if (!netif_carrier_ok(tp->netdev))
2428		return;
2429
2430	clear_bit(SCHEDULE_TASKLET, &tp->flags);
2431
2432	tx_bottom(tp);
2433}
2434
2435static int r8152_poll(struct napi_struct *napi, int budget)
2436{
2437	struct r8152 *tp = container_of(napi, struct r8152, napi);
2438	int work_done;
2439
2440	work_done = rx_bottom(tp, budget);
2441
2442	if (work_done < budget) {
2443		if (!napi_complete_done(napi, work_done))
2444			goto out;
2445		if (!list_empty(&tp->rx_done))
2446			napi_schedule(napi);
2447	}
2448
2449out:
2450	return work_done;
2451}
2452
2453static
2454int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2455{
2456	int ret;
2457
2458	/* The rx would be stopped, so skip submitting */
2459	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2460	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2461		return 0;
2462
2463	usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2464			  agg->buffer, tp->rx_buf_sz,
2465			  (usb_complete_t)read_bulk_callback, agg);
2466
2467	ret = usb_submit_urb(agg->urb, mem_flags);
2468	if (ret == -ENODEV) {
2469		rtl_set_unplug(tp);
2470		netif_device_detach(tp->netdev);
2471	} else if (ret) {
2472		struct urb *urb = agg->urb;
2473		unsigned long flags;
2474
2475		urb->actual_length = 0;
2476		spin_lock_irqsave(&tp->rx_lock, flags);
2477		list_add_tail(&agg->list, &tp->rx_done);
2478		spin_unlock_irqrestore(&tp->rx_lock, flags);
2479
2480		netif_err(tp, rx_err, tp->netdev,
2481			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2482
2483		napi_schedule(&tp->napi);
2484	}
2485
2486	return ret;
2487}
2488
2489static void rtl_drop_queued_tx(struct r8152 *tp)
2490{
2491	struct net_device_stats *stats = &tp->netdev->stats;
2492	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2493	struct sk_buff *skb;
2494
2495	if (skb_queue_empty(tx_queue))
2496		return;
2497
2498	__skb_queue_head_init(&skb_head);
2499	spin_lock_bh(&tx_queue->lock);
2500	skb_queue_splice_init(tx_queue, &skb_head);
2501	spin_unlock_bh(&tx_queue->lock);
2502
2503	while ((skb = __skb_dequeue(&skb_head))) {
2504		dev_kfree_skb(skb);
2505		stats->tx_dropped++;
2506	}
2507}
2508
2509static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2510{
2511	struct r8152 *tp = netdev_priv(netdev);
2512
2513	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2514
2515	usb_queue_reset_device(tp->intf);
2516}
2517
2518static void rtl8152_set_rx_mode(struct net_device *netdev)
2519{
2520	struct r8152 *tp = netdev_priv(netdev);
2521
2522	if (netif_carrier_ok(netdev)) {
2523		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2524		schedule_delayed_work(&tp->schedule, 0);
2525	}
2526}
2527
2528static void _rtl8152_set_rx_mode(struct net_device *netdev)
2529{
2530	struct r8152 *tp = netdev_priv(netdev);
2531	u32 mc_filter[2];	/* Multicast hash filter */
2532	__le32 tmp[2];
2533	u32 ocp_data;
2534
2535	netif_stop_queue(netdev);
2536	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2537	ocp_data &= ~RCR_ACPT_ALL;
2538	ocp_data |= RCR_AB | RCR_APM;
2539
2540	if (netdev->flags & IFF_PROMISC) {
2541		/* Unconditionally log net taps. */
2542		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2543		ocp_data |= RCR_AM | RCR_AAP;
2544		mc_filter[1] = 0xffffffff;
2545		mc_filter[0] = 0xffffffff;
2546	} else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2547		   (netdev->flags & IFF_ALLMULTI)) {
2548		/* Too many to filter perfectly -- accept all multicasts. */
2549		ocp_data |= RCR_AM;
2550		mc_filter[1] = 0xffffffff;
2551		mc_filter[0] = 0xffffffff;
2552	} else {
2553		struct netdev_hw_addr *ha;
2554
2555		mc_filter[1] = 0;
2556		mc_filter[0] = 0;
2557		netdev_for_each_mc_addr(ha, netdev) {
2558			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2559
2560			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2561			ocp_data |= RCR_AM;
2562		}
2563	}
2564
2565	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2566	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2567
2568	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2569	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2570	netif_wake_queue(netdev);
2571}
2572
2573static netdev_features_t
2574rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2575		       netdev_features_t features)
2576{
2577	u32 mss = skb_shinfo(skb)->gso_size;
2578	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2579	int offset = skb_transport_offset(skb);
2580
2581	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2582		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2583	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2584		features &= ~NETIF_F_GSO_MASK;
2585
2586	return features;
2587}
2588
2589static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2590				      struct net_device *netdev)
2591{
2592	struct r8152 *tp = netdev_priv(netdev);
2593
2594	skb_tx_timestamp(skb);
2595
2596	skb_queue_tail(&tp->tx_queue, skb);
2597
2598	if (!list_empty(&tp->tx_free)) {
2599		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2600			set_bit(SCHEDULE_TASKLET, &tp->flags);
2601			schedule_delayed_work(&tp->schedule, 0);
2602		} else {
2603			usb_mark_last_busy(tp->udev);
2604			tasklet_schedule(&tp->tx_tl);
2605		}
2606	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2607		netif_stop_queue(netdev);
2608	}
2609
2610	return NETDEV_TX_OK;
2611}
2612
2613static void r8152b_reset_packet_filter(struct r8152 *tp)
2614{
2615	u32	ocp_data;
2616
2617	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2618	ocp_data &= ~FMC_FCR_MCU_EN;
2619	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2620	ocp_data |= FMC_FCR_MCU_EN;
2621	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2622}
2623
2624static void rtl8152_nic_reset(struct r8152 *tp)
2625{
2626	int	i;
2627
2628	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2629
2630	for (i = 0; i < 1000; i++) {
2631		if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2632			break;
2633		usleep_range(100, 400);
2634	}
2635}
2636
2637static void set_tx_qlen(struct r8152 *tp)
2638{
2639	struct net_device *netdev = tp->netdev;
2640
2641	tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2642				    sizeof(struct tx_desc));
2643}
2644
2645static inline u8 rtl8152_get_speed(struct r8152 *tp)
2646{
2647	return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2648}
2649
2650static void rtl_set_eee_plus(struct r8152 *tp)
2651{
2652	u32 ocp_data;
2653	u8 speed;
2654
2655	speed = rtl8152_get_speed(tp);
2656	if (speed & _10bps) {
2657		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2658		ocp_data |= EEEP_CR_EEEP_TX;
2659		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2660	} else {
2661		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2662		ocp_data &= ~EEEP_CR_EEEP_TX;
2663		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2664	}
2665}
2666
2667static void rxdy_gated_en(struct r8152 *tp, bool enable)
2668{
2669	u32 ocp_data;
2670
2671	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2672	if (enable)
2673		ocp_data |= RXDY_GATED_EN;
2674	else
2675		ocp_data &= ~RXDY_GATED_EN;
2676	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2677}
2678
2679static int rtl_start_rx(struct r8152 *tp)
2680{
2681	struct rx_agg *agg, *agg_next;
2682	struct list_head tmp_list;
2683	unsigned long flags;
2684	int ret = 0, i = 0;
2685
2686	INIT_LIST_HEAD(&tmp_list);
2687
2688	spin_lock_irqsave(&tp->rx_lock, flags);
2689
2690	INIT_LIST_HEAD(&tp->rx_done);
2691	INIT_LIST_HEAD(&tp->rx_used);
2692
2693	list_splice_init(&tp->rx_info, &tmp_list);
2694
2695	spin_unlock_irqrestore(&tp->rx_lock, flags);
2696
2697	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2698		INIT_LIST_HEAD(&agg->list);
2699
2700		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2701		if (++i > RTL8152_MAX_RX) {
2702			spin_lock_irqsave(&tp->rx_lock, flags);
2703			list_add_tail(&agg->list, &tp->rx_used);
2704			spin_unlock_irqrestore(&tp->rx_lock, flags);
2705		} else if (unlikely(ret < 0)) {
2706			spin_lock_irqsave(&tp->rx_lock, flags);
2707			list_add_tail(&agg->list, &tp->rx_done);
2708			spin_unlock_irqrestore(&tp->rx_lock, flags);
2709		} else {
2710			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2711		}
2712	}
2713
2714	spin_lock_irqsave(&tp->rx_lock, flags);
2715	WARN_ON(!list_empty(&tp->rx_info));
2716	list_splice(&tmp_list, &tp->rx_info);
2717	spin_unlock_irqrestore(&tp->rx_lock, flags);
2718
2719	return ret;
2720}
2721
2722static int rtl_stop_rx(struct r8152 *tp)
2723{
2724	struct rx_agg *agg, *agg_next;
2725	struct list_head tmp_list;
2726	unsigned long flags;
2727
2728	INIT_LIST_HEAD(&tmp_list);
2729
2730	/* The usb_kill_urb() couldn't be used in atomic.
2731	 * Therefore, move the list of rx_info to a tmp one.
2732	 * Then, list_for_each_entry_safe could be used without
2733	 * spin lock.
2734	 */
2735
2736	spin_lock_irqsave(&tp->rx_lock, flags);
2737	list_splice_init(&tp->rx_info, &tmp_list);
2738	spin_unlock_irqrestore(&tp->rx_lock, flags);
2739
2740	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2741		/* At least RTL8152_MAX_RX rx_agg have the page_count being
2742		 * equal to 1, so the other ones could be freed safely.
2743		 */
2744		if (page_count(agg->page) > 1)
2745			free_rx_agg(tp, agg);
2746		else
2747			usb_kill_urb(agg->urb);
2748	}
2749
2750	/* Move back the list of temp to the rx_info */
2751	spin_lock_irqsave(&tp->rx_lock, flags);
2752	WARN_ON(!list_empty(&tp->rx_info));
2753	list_splice(&tmp_list, &tp->rx_info);
2754	spin_unlock_irqrestore(&tp->rx_lock, flags);
2755
2756	while (!skb_queue_empty(&tp->rx_queue))
2757		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2758
2759	return 0;
2760}
2761
2762static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2763{
2764	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2765		       OWN_UPDATE | OWN_CLEAR);
2766}
2767
2768static int rtl_enable(struct r8152 *tp)
2769{
2770	u32 ocp_data;
2771
2772	r8152b_reset_packet_filter(tp);
2773
2774	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2775	ocp_data |= CR_RE | CR_TE;
2776	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2777
2778	switch (tp->version) {
2779	case RTL_VER_08:
2780	case RTL_VER_09:
2781		r8153b_rx_agg_chg_indicate(tp);
2782		break;
2783	default:
2784		break;
2785	}
2786
2787	rxdy_gated_en(tp, false);
2788
2789	return 0;
2790}
2791
2792static int rtl8152_enable(struct r8152 *tp)
2793{
2794	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2795		return -ENODEV;
2796
2797	set_tx_qlen(tp);
2798	rtl_set_eee_plus(tp);
2799
2800	return rtl_enable(tp);
2801}
2802
2803static void r8153_set_rx_early_timeout(struct r8152 *tp)
2804{
2805	u32 ocp_data = tp->coalesce / 8;
2806
2807	switch (tp->version) {
2808	case RTL_VER_03:
2809	case RTL_VER_04:
2810	case RTL_VER_05:
2811	case RTL_VER_06:
2812		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2813			       ocp_data);
2814		break;
2815
2816	case RTL_VER_08:
2817	case RTL_VER_09:
2818		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2819		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2820		 */
2821		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2822			       128 / 8);
2823		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2824			       ocp_data);
2825		break;
2826
2827	default:
2828		break;
2829	}
2830}
2831
2832static void r8153_set_rx_early_size(struct r8152 *tp)
2833{
2834	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2835
2836	switch (tp->version) {
2837	case RTL_VER_03:
2838	case RTL_VER_04:
2839	case RTL_VER_05:
2840	case RTL_VER_06:
2841		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2842			       ocp_data / 4);
2843		break;
2844	case RTL_VER_08:
2845	case RTL_VER_09:
2846		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2847			       ocp_data / 8);
2848		break;
2849	default:
2850		WARN_ON_ONCE(1);
2851		break;
2852	}
2853}
2854
2855static int rtl8153_enable(struct r8152 *tp)
2856{
2857	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2858		return -ENODEV;
2859
2860	set_tx_qlen(tp);
2861	rtl_set_eee_plus(tp);
2862	r8153_set_rx_early_timeout(tp);
2863	r8153_set_rx_early_size(tp);
2864
2865	if (tp->version == RTL_VER_09) {
2866		u32 ocp_data;
2867
2868		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2869		ocp_data &= ~FC_PATCH_TASK;
2870		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2871		usleep_range(1000, 2000);
2872		ocp_data |= FC_PATCH_TASK;
2873		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2874	}
2875
2876	return rtl_enable(tp);
2877}
2878
2879static void rtl_disable(struct r8152 *tp)
2880{
2881	u32 ocp_data;
2882	int i;
2883
2884	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2885		rtl_drop_queued_tx(tp);
2886		return;
2887	}
2888
2889	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2890	ocp_data &= ~RCR_ACPT_ALL;
2891	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2892
2893	rtl_drop_queued_tx(tp);
2894
2895	for (i = 0; i < RTL8152_MAX_TX; i++)
2896		usb_kill_urb(tp->tx_info[i].urb);
2897
2898	rxdy_gated_en(tp, true);
2899
2900	for (i = 0; i < 1000; i++) {
2901		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2902		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2903			break;
2904		usleep_range(1000, 2000);
2905	}
2906
2907	for (i = 0; i < 1000; i++) {
2908		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2909			break;
2910		usleep_range(1000, 2000);
2911	}
2912
2913	rtl_stop_rx(tp);
2914
2915	rtl8152_nic_reset(tp);
2916}
2917
2918static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2919{
2920	u32 ocp_data;
2921
2922	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2923	if (enable)
2924		ocp_data |= POWER_CUT;
2925	else
2926		ocp_data &= ~POWER_CUT;
2927	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2928
2929	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2930	ocp_data &= ~RESUME_INDICATE;
2931	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2932}
2933
2934static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2935{
2936	u32 ocp_data;
2937
2938	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2939	if (enable)
2940		ocp_data |= CPCR_RX_VLAN;
2941	else
2942		ocp_data &= ~CPCR_RX_VLAN;
2943	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2944}
2945
2946static int rtl8152_set_features(struct net_device *dev,
2947				netdev_features_t features)
2948{
2949	netdev_features_t changed = features ^ dev->features;
2950	struct r8152 *tp = netdev_priv(dev);
2951	int ret;
2952
2953	ret = usb_autopm_get_interface(tp->intf);
2954	if (ret < 0)
2955		goto out;
2956
2957	mutex_lock(&tp->control);
2958
2959	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2960		if (features & NETIF_F_HW_VLAN_CTAG_RX)
2961			rtl_rx_vlan_en(tp, true);
2962		else
2963			rtl_rx_vlan_en(tp, false);
2964	}
2965
2966	mutex_unlock(&tp->control);
2967
2968	usb_autopm_put_interface(tp->intf);
2969
2970out:
2971	return ret;
2972}
2973
2974#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2975
2976static u32 __rtl_get_wol(struct r8152 *tp)
2977{
2978	u32 ocp_data;
2979	u32 wolopts = 0;
2980
2981	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2982	if (ocp_data & LINK_ON_WAKE_EN)
2983		wolopts |= WAKE_PHY;
2984
2985	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2986	if (ocp_data & UWF_EN)
2987		wolopts |= WAKE_UCAST;
2988	if (ocp_data & BWF_EN)
2989		wolopts |= WAKE_BCAST;
2990	if (ocp_data & MWF_EN)
2991		wolopts |= WAKE_MCAST;
2992
2993	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2994	if (ocp_data & MAGIC_EN)
2995		wolopts |= WAKE_MAGIC;
2996
2997	return wolopts;
2998}
2999
3000static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3001{
3002	u32 ocp_data;
3003
3004	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3005
3006	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3007	ocp_data &= ~LINK_ON_WAKE_EN;
3008	if (wolopts & WAKE_PHY)
3009		ocp_data |= LINK_ON_WAKE_EN;
3010	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3011
3012	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3013	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3014	if (wolopts & WAKE_UCAST)
3015		ocp_data |= UWF_EN;
3016	if (wolopts & WAKE_BCAST)
3017		ocp_data |= BWF_EN;
3018	if (wolopts & WAKE_MCAST)
3019		ocp_data |= MWF_EN;
3020	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3021
3022	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3023
3024	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3025	ocp_data &= ~MAGIC_EN;
3026	if (wolopts & WAKE_MAGIC)
3027		ocp_data |= MAGIC_EN;
3028	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3029
3030	if (wolopts & WAKE_ANY)
3031		device_set_wakeup_enable(&tp->udev->dev, true);
3032	else
3033		device_set_wakeup_enable(&tp->udev->dev, false);
3034}
3035
3036static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3037{
3038	/* MAC clock speed down */
3039	if (enable) {
3040		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3041			       ALDPS_SPDWN_RATIO);
3042		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3043			       EEE_SPDWN_RATIO);
3044		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3045			       PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3046			       U1U2_SPDWN_EN | L1_SPDWN_EN);
3047		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3048			       PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3049			       TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3050			       TP1000_SPDWN_EN);
3051	} else {
3052		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3053		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3054		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3055		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3056	}
3057}
3058
3059static void r8153_u1u2en(struct r8152 *tp, bool enable)
3060{
3061	u8 u1u2[8];
3062
3063	if (enable)
3064		memset(u1u2, 0xff, sizeof(u1u2));
3065	else
3066		memset(u1u2, 0x00, sizeof(u1u2));
3067
3068	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3069}
3070
3071static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3072{
3073	u32 ocp_data;
3074
3075	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3076	if (enable)
3077		ocp_data |= LPM_U1U2_EN;
3078	else
3079		ocp_data &= ~LPM_U1U2_EN;
3080
3081	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3082}
3083
3084static void r8153_u2p3en(struct r8152 *tp, bool enable)
3085{
3086	u32 ocp_data;
3087
3088	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3089	if (enable)
3090		ocp_data |= U2P3_ENABLE;
3091	else
3092		ocp_data &= ~U2P3_ENABLE;
3093	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3094}
3095
3096static void r8153b_ups_flags(struct r8152 *tp)
3097{
3098	u32 ups_flags = 0;
3099
3100	if (tp->ups_info.green)
3101		ups_flags |= UPS_FLAGS_EN_GREEN;
3102
3103	if (tp->ups_info.aldps)
3104		ups_flags |= UPS_FLAGS_EN_ALDPS;
3105
3106	if (tp->ups_info.eee)
3107		ups_flags |= UPS_FLAGS_EN_EEE;
3108
3109	if (tp->ups_info.flow_control)
3110		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3111
3112	if (tp->ups_info.eee_ckdiv)
3113		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3114
3115	if (tp->ups_info.eee_cmod_lv)
3116		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3117
3118	if (tp->ups_info._10m_ckdiv)
3119		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3120
3121	if (tp->ups_info.eee_plloff_100)
3122		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3123
3124	if (tp->ups_info.eee_plloff_giga)
3125		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3126
3127	if (tp->ups_info._250m_ckdiv)
3128		ups_flags |= UPS_FLAGS_250M_CKDIV;
3129
3130	if (tp->ups_info.ctap_short_off)
3131		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3132
3133	switch (tp->ups_info.speed_duplex) {
3134	case NWAY_10M_HALF:
3135		ups_flags |= ups_flags_speed(1);
3136		break;
3137	case NWAY_10M_FULL:
3138		ups_flags |= ups_flags_speed(2);
3139		break;
3140	case NWAY_100M_HALF:
3141		ups_flags |= ups_flags_speed(3);
3142		break;
3143	case NWAY_100M_FULL:
3144		ups_flags |= ups_flags_speed(4);
3145		break;
3146	case NWAY_1000M_FULL:
3147		ups_flags |= ups_flags_speed(5);
3148		break;
3149	case FORCE_10M_HALF:
3150		ups_flags |= ups_flags_speed(6);
3151		break;
3152	case FORCE_10M_FULL:
3153		ups_flags |= ups_flags_speed(7);
3154		break;
3155	case FORCE_100M_HALF:
3156		ups_flags |= ups_flags_speed(8);
3157		break;
3158	case FORCE_100M_FULL:
3159		ups_flags |= ups_flags_speed(9);
3160		break;
3161	default:
3162		break;
3163	}
3164
3165	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3166}
3167
3168static void r8153b_green_en(struct r8152 *tp, bool enable)
3169{
3170	u16 data;
3171
3172	if (enable) {
3173		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
3174		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
3175		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
3176	} else {
3177		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
3178		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
3179		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
3180	}
3181
3182	data = sram_read(tp, SRAM_GREEN_CFG);
3183	data |= GREEN_ETH_EN;
3184	sram_write(tp, SRAM_GREEN_CFG, data);
3185
3186	tp->ups_info.green = enable;
3187}
3188
3189static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3190{
3191	u16 data;
3192	int i;
3193
3194	for (i = 0; i < 500; i++) {
3195		data = ocp_reg_read(tp, OCP_PHY_STATUS);
3196		data &= PHY_STAT_MASK;
3197		if (desired) {
3198			if (data == desired)
3199				break;
3200		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3201			   data == PHY_STAT_EXT_INIT) {
3202			break;
3203		}
3204
3205		msleep(20);
3206		if (test_bit(RTL8152_UNPLUG, &tp->flags))
3207			break;
3208	}
3209
3210	return data;
3211}
3212
3213static void r8153b_ups_en(struct r8152 *tp, bool enable)
3214{
3215	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3216
3217	if (enable) {
3218		r8153b_ups_flags(tp);
3219
3220		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3221		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3222
3223		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3224		ocp_data |= BIT(0);
3225		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3226	} else {
3227		u16 data;
3228
3229		ocp_data &= ~(UPS_EN | USP_PREWAKE);
3230		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3231
3232		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3233		ocp_data &= ~BIT(0);
3234		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3235
3236		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3237		ocp_data &= ~PCUT_STATUS;
3238		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3239
3240		data = r8153_phy_status(tp, 0);
3241
3242		switch (data) {
3243		case PHY_STAT_PWRDN:
3244		case PHY_STAT_EXT_INIT:
3245			r8153b_green_en(tp,
3246					test_bit(GREEN_ETHERNET, &tp->flags));
3247
3248			data = r8152_mdio_read(tp, MII_BMCR);
3249			data &= ~BMCR_PDOWN;
3250			data |= BMCR_RESET;
3251			r8152_mdio_write(tp, MII_BMCR, data);
3252
3253			data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3254			fallthrough;
3255
3256		default:
3257			if (data != PHY_STAT_LAN_ON)
3258				netif_warn(tp, link, tp->netdev,
3259					   "PHY not ready");
3260			break;
3261		}
3262	}
3263}
3264
3265static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3266{
3267	u32 ocp_data;
3268
3269	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3270	if (enable)
3271		ocp_data |= PWR_EN | PHASE2_EN;
3272	else
3273		ocp_data &= ~(PWR_EN | PHASE2_EN);
3274	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3275
3276	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3277	ocp_data &= ~PCUT_STATUS;
3278	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3279}
3280
3281static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3282{
3283	u32 ocp_data;
3284
3285	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3286	if (enable)
3287		ocp_data |= PWR_EN | PHASE2_EN;
3288	else
3289		ocp_data &= ~PWR_EN;
3290	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3291
3292	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3293	ocp_data &= ~PCUT_STATUS;
3294	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3295}
3296
3297static void r8153_queue_wake(struct r8152 *tp, bool enable)
3298{
3299	u32 ocp_data;
3300
3301	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3302	if (enable)
3303		ocp_data |= UPCOMING_RUNTIME_D3;
3304	else
3305		ocp_data &= ~UPCOMING_RUNTIME_D3;
3306	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3307
3308	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3309	ocp_data &= ~LINK_CHG_EVENT;
3310	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3311
3312	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3313	ocp_data &= ~LINK_CHANGE_FLAG;
3314	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3315}
3316
3317static bool rtl_can_wakeup(struct r8152 *tp)
3318{
3319	struct usb_device *udev = tp->udev;
3320
3321	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3322}
3323
3324static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3325{
3326	if (enable) {
3327		u32 ocp_data;
3328
3329		__rtl_set_wol(tp, WAKE_ANY);
3330
3331		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3332
3333		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3334		ocp_data |= LINK_OFF_WAKE_EN;
3335		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3336
3337		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3338	} else {
3339		u32 ocp_data;
3340
3341		__rtl_set_wol(tp, tp->saved_wolopts);
3342
3343		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3344
3345		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3346		ocp_data &= ~LINK_OFF_WAKE_EN;
3347		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3348
3349		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3350	}
3351}
3352
3353static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3354{
3355	if (enable) {
3356		r8153_u1u2en(tp, false);
3357		r8153_u2p3en(tp, false);
3358		r8153_mac_clk_spd(tp, true);
3359		rtl_runtime_suspend_enable(tp, true);
3360	} else {
3361		rtl_runtime_suspend_enable(tp, false);
3362		r8153_mac_clk_spd(tp, false);
3363
3364		switch (tp->version) {
3365		case RTL_VER_03:
3366		case RTL_VER_04:
3367			break;
3368		case RTL_VER_05:
3369		case RTL_VER_06:
3370		default:
3371			r8153_u2p3en(tp, true);
3372			break;
3373		}
3374
3375		r8153_u1u2en(tp, true);
3376	}
3377}
3378
3379static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3380{
3381	if (enable) {
3382		r8153_queue_wake(tp, true);
3383		r8153b_u1u2en(tp, false);
3384		r8153_u2p3en(tp, false);
3385		rtl_runtime_suspend_enable(tp, true);
3386		r8153b_ups_en(tp, true);
3387	} else {
3388		r8153b_ups_en(tp, false);
3389		r8153_queue_wake(tp, false);
3390		rtl_runtime_suspend_enable(tp, false);
3391		if (tp->udev->speed != USB_SPEED_HIGH)
3392			r8153b_u1u2en(tp, true);
3393	}
3394}
3395
3396static void r8153_teredo_off(struct r8152 *tp)
3397{
3398	u32 ocp_data;
3399
3400	switch (tp->version) {
3401	case RTL_VER_01:
3402	case RTL_VER_02:
3403	case RTL_VER_03:
3404	case RTL_VER_04:
3405	case RTL_VER_05:
3406	case RTL_VER_06:
3407	case RTL_VER_07:
3408		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3409		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3410			      OOB_TEREDO_EN);
3411		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3412		break;
3413
3414	case RTL_VER_08:
3415	case RTL_VER_09:
3416		/* The bit 0 ~ 7 are relative with teredo settings. They are
3417		 * W1C (write 1 to clear), so set all 1 to disable it.
3418		 */
3419		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3420		break;
3421
3422	default:
3423		break;
3424	}
3425
3426	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3427	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3428	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3429}
3430
3431static void rtl_reset_bmu(struct r8152 *tp)
3432{
3433	u32 ocp_data;
3434
3435	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3436	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3437	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3438	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3439	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3440}
3441
3442/* Clear the bp to stop the firmware before loading a new one */
3443static void rtl_clear_bp(struct r8152 *tp, u16 type)
3444{
3445	switch (tp->version) {
3446	case RTL_VER_01:
3447	case RTL_VER_02:
3448	case RTL_VER_07:
3449		break;
3450	case RTL_VER_03:
3451	case RTL_VER_04:
3452	case RTL_VER_05:
3453	case RTL_VER_06:
3454		ocp_write_byte(tp, type, PLA_BP_EN, 0);
3455		break;
3456	case RTL_VER_08:
3457	case RTL_VER_09:
3458	default:
3459		if (type == MCU_TYPE_USB) {
3460			ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3461
3462			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3463			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3464			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3465			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3466			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3467			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3468			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3469			ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3470		} else {
3471			ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3472		}
3473		break;
3474	}
3475
3476	ocp_write_word(tp, type, PLA_BP_0, 0);
3477	ocp_write_word(tp, type, PLA_BP_1, 0);
3478	ocp_write_word(tp, type, PLA_BP_2, 0);
3479	ocp_write_word(tp, type, PLA_BP_3, 0);
3480	ocp_write_word(tp, type, PLA_BP_4, 0);
3481	ocp_write_word(tp, type, PLA_BP_5, 0);
3482	ocp_write_word(tp, type, PLA_BP_6, 0);
3483	ocp_write_word(tp, type, PLA_BP_7, 0);
3484
3485	/* wait 3 ms to make sure the firmware is stopped */
3486	usleep_range(3000, 6000);
3487	ocp_write_word(tp, type, PLA_BP_BA, 0);
3488}
3489
3490static int r8153_patch_request(struct r8152 *tp, bool request)
3491{
3492	u16 data;
3493	int i;
3494
3495	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3496	if (request)
3497		data |= PATCH_REQUEST;
3498	else
3499		data &= ~PATCH_REQUEST;
3500	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3501
3502	for (i = 0; request && i < 5000; i++) {
3503		usleep_range(1000, 2000);
3504		if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3505			break;
3506	}
3507
3508	if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3509		netif_err(tp, drv, tp->netdev, "patch request fail\n");
3510		r8153_patch_request(tp, false);
3511		return -ETIME;
3512	} else {
3513		return 0;
3514	}
3515}
3516
3517static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3518{
3519	if (r8153_patch_request(tp, true)) {
3520		dev_err(&tp->intf->dev, "patch request fail\n");
3521		return -ETIME;
3522	}
3523
3524	sram_write(tp, key_addr, patch_key);
3525	sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3526
3527	return 0;
3528}
3529
3530static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3531{
3532	u16 data;
3533
3534	sram_write(tp, 0x0000, 0x0000);
3535
3536	data = ocp_reg_read(tp, OCP_PHY_LOCK);
3537	data &= ~PATCH_LOCK;
3538	ocp_reg_write(tp, OCP_PHY_LOCK, data);
3539
3540	sram_write(tp, key_addr, 0x0000);
3541
3542	r8153_patch_request(tp, false);
3543
3544	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3545
3546	return 0;
3547}
3548
3549static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3550{
3551	u32 length;
3552	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3553	bool rc = false;
3554
3555	switch (tp->version) {
3556	case RTL_VER_04:
3557	case RTL_VER_05:
3558	case RTL_VER_06:
3559		fw_reg = 0xa014;
3560		ba_reg = 0xa012;
3561		patch_en_addr = 0xa01a;
3562		mode_reg = 0xb820;
3563		bp_start = 0xa000;
3564		break;
3565	default:
3566		goto out;
3567	}
3568
3569	fw_offset = __le16_to_cpu(phy->fw_offset);
3570	if (fw_offset < sizeof(*phy)) {
3571		dev_err(&tp->intf->dev, "fw_offset too small\n");
3572		goto out;
3573	}
3574
3575	length = __le32_to_cpu(phy->blk_hdr.length);
3576	if (length < fw_offset) {
3577		dev_err(&tp->intf->dev, "invalid fw_offset\n");
3578		goto out;
3579	}
3580
3581	length -= __le16_to_cpu(phy->fw_offset);
3582	if (!length || (length & 1)) {
3583		dev_err(&tp->intf->dev, "invalid block length\n");
3584		goto out;
3585	}
3586
3587	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3588		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3589		goto out;
3590	}
3591
3592	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3593		dev_err(&tp->intf->dev, "invalid base address register\n");
3594		goto out;
3595	}
3596
3597	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3598		dev_err(&tp->intf->dev,
3599			"invalid patch mode enabled register\n");
3600		goto out;
3601	}
3602
3603	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3604		dev_err(&tp->intf->dev,
3605			"invalid register to switch the mode\n");
3606		goto out;
3607	}
3608
3609	if (__le16_to_cpu(phy->bp_start) != bp_start) {
3610		dev_err(&tp->intf->dev,
3611			"invalid start register of break point\n");
3612		goto out;
3613	}
3614
3615	if (__le16_to_cpu(phy->bp_num) > 4) {
3616		dev_err(&tp->intf->dev, "invalid break point number\n");
3617		goto out;
3618	}
3619
3620	rc = true;
3621out:
3622	return rc;
3623}
3624
3625static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3626{
3627	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3628	bool rc = false;
3629	u32 length, type;
3630	int i, max_bp;
3631
3632	type = __le32_to_cpu(mac->blk_hdr.type);
3633	if (type == RTL_FW_PLA) {
3634		switch (tp->version) {
3635		case RTL_VER_01:
3636		case RTL_VER_02:
3637		case RTL_VER_07:
3638			fw_reg = 0xf800;
3639			bp_ba_addr = PLA_BP_BA;
3640			bp_en_addr = 0;
3641			bp_start = PLA_BP_0;
3642			max_bp = 8;
3643			break;
3644		case RTL_VER_03:
3645		case RTL_VER_04:
3646		case RTL_VER_05:
3647		case RTL_VER_06:
3648		case RTL_VER_08:
3649		case RTL_VER_09:
3650			fw_reg = 0xf800;
3651			bp_ba_addr = PLA_BP_BA;
3652			bp_en_addr = PLA_BP_EN;
3653			bp_start = PLA_BP_0;
3654			max_bp = 8;
3655			break;
3656		default:
3657			goto out;
3658		}
3659	} else if (type == RTL_FW_USB) {
3660		switch (tp->version) {
3661		case RTL_VER_03:
3662		case RTL_VER_04:
3663		case RTL_VER_05:
3664		case RTL_VER_06:
3665			fw_reg = 0xf800;
3666			bp_ba_addr = USB_BP_BA;
3667			bp_en_addr = USB_BP_EN;
3668			bp_start = USB_BP_0;
3669			max_bp = 8;
3670			break;
3671		case RTL_VER_08:
3672		case RTL_VER_09:
3673			fw_reg = 0xe600;
3674			bp_ba_addr = USB_BP_BA;
3675			bp_en_addr = USB_BP2_EN;
3676			bp_start = USB_BP_0;
3677			max_bp = 16;
3678			break;
3679		case RTL_VER_01:
3680		case RTL_VER_02:
3681		case RTL_VER_07:
3682		default:
3683			goto out;
3684		}
3685	} else {
3686		goto out;
3687	}
3688
3689	fw_offset = __le16_to_cpu(mac->fw_offset);
3690	if (fw_offset < sizeof(*mac)) {
3691		dev_err(&tp->intf->dev, "fw_offset too small\n");
3692		goto out;
3693	}
3694
3695	length = __le32_to_cpu(mac->blk_hdr.length);
3696	if (length < fw_offset) {
3697		dev_err(&tp->intf->dev, "invalid fw_offset\n");
3698		goto out;
3699	}
3700
3701	length -= fw_offset;
3702	if (length < 4 || (length & 3)) {
3703		dev_err(&tp->intf->dev, "invalid block length\n");
3704		goto out;
3705	}
3706
3707	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3708		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3709		goto out;
3710	}
3711
3712	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3713		dev_err(&tp->intf->dev, "invalid base address register\n");
3714		goto out;
3715	}
3716
3717	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3718		dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3719		goto out;
3720	}
3721
3722	if (__le16_to_cpu(mac->bp_start) != bp_start) {
3723		dev_err(&tp->intf->dev,
3724			"invalid start register of break point\n");
3725		goto out;
3726	}
3727
3728	if (__le16_to_cpu(mac->bp_num) > max_bp) {
3729		dev_err(&tp->intf->dev, "invalid break point number\n");
3730		goto out;
3731	}
3732
3733	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3734		if (mac->bp[i]) {
3735			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3736			goto out;
3737		}
3738	}
3739
3740	rc = true;
3741out:
3742	return rc;
3743}
3744
3745/* Verify the checksum for the firmware file. It is calculated from the version
3746 * field to the end of the file. Compare the result with the checksum field to
3747 * make sure the file is correct.
3748 */
3749static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3750				       struct fw_header *fw_hdr, size_t size)
3751{
3752	unsigned char checksum[sizeof(fw_hdr->checksum)];
3753	struct crypto_shash *alg;
3754	struct shash_desc *sdesc;
3755	size_t len;
3756	long rc;
3757
3758	alg = crypto_alloc_shash("sha256", 0, 0);
3759	if (IS_ERR(alg)) {
3760		rc = PTR_ERR(alg);
3761		goto out;
3762	}
3763
3764	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3765		rc = -EFAULT;
3766		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3767			crypto_shash_digestsize(alg));
3768		goto free_shash;
3769	}
3770
3771	len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3772	sdesc = kmalloc(len, GFP_KERNEL);
3773	if (!sdesc) {
3774		rc = -ENOMEM;
3775		goto free_shash;
3776	}
3777	sdesc->tfm = alg;
3778
3779	len = size - sizeof(fw_hdr->checksum);
3780	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3781	kfree(sdesc);
3782	if (rc)
3783		goto free_shash;
3784
3785	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3786		dev_err(&tp->intf->dev, "checksum fail\n");
3787		rc = -EFAULT;
3788	}
3789
3790free_shash:
3791	crypto_free_shash(alg);
3792out:
3793	return rc;
3794}
3795
3796static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3797{
3798	const struct firmware *fw = rtl_fw->fw;
3799	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3800	struct fw_mac *pla = NULL, *usb = NULL;
3801	struct fw_phy_patch_key *start = NULL;
3802	struct fw_phy_nc *phy_nc = NULL;
3803	struct fw_block *stop = NULL;
3804	long ret = -EFAULT;
3805	int i;
3806
3807	if (fw->size < sizeof(*fw_hdr)) {
3808		dev_err(&tp->intf->dev, "file too small\n");
3809		goto fail;
3810	}
3811
3812	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3813	if (ret)
3814		goto fail;
3815
3816	ret = -EFAULT;
3817
3818	for (i = sizeof(*fw_hdr); i < fw->size;) {
3819		struct fw_block *block = (struct fw_block *)&fw->data[i];
3820		u32 type;
3821
3822		if ((i + sizeof(*block)) > fw->size)
3823			goto fail;
3824
3825		type = __le32_to_cpu(block->type);
3826		switch (type) {
3827		case RTL_FW_END:
3828			if (__le32_to_cpu(block->length) != sizeof(*block))
3829				goto fail;
3830			goto fw_end;
3831		case RTL_FW_PLA:
3832			if (pla) {
3833				dev_err(&tp->intf->dev,
3834					"multiple PLA firmware encountered");
3835				goto fail;
3836			}
3837
3838			pla = (struct fw_mac *)block;
3839			if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3840				dev_err(&tp->intf->dev,
3841					"check PLA firmware failed\n");
3842				goto fail;
3843			}
3844			break;
3845		case RTL_FW_USB:
3846			if (usb) {
3847				dev_err(&tp->intf->dev,
3848					"multiple USB firmware encountered");
3849				goto fail;
3850			}
3851
3852			usb = (struct fw_mac *)block;
3853			if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3854				dev_err(&tp->intf->dev,
3855					"check USB firmware failed\n");
3856				goto fail;
3857			}
3858			break;
3859		case RTL_FW_PHY_START:
3860			if (start || phy_nc || stop) {
3861				dev_err(&tp->intf->dev,
3862					"check PHY_START fail\n");
3863				goto fail;
3864			}
3865
3866			if (__le32_to_cpu(block->length) != sizeof(*start)) {
3867				dev_err(&tp->intf->dev,
3868					"Invalid length for PHY_START\n");
3869				goto fail;
3870			}
3871
3872			start = (struct fw_phy_patch_key *)block;
3873			break;
3874		case RTL_FW_PHY_STOP:
3875			if (stop || !start) {
3876				dev_err(&tp->intf->dev,
3877					"Check PHY_STOP fail\n");
3878				goto fail;
3879			}
3880
3881			if (__le32_to_cpu(block->length) != sizeof(*block)) {
3882				dev_err(&tp->intf->dev,
3883					"Invalid length for PHY_STOP\n");
3884				goto fail;
3885			}
3886
3887			stop = block;
3888			break;
3889		case RTL_FW_PHY_NC:
3890			if (!start || stop) {
3891				dev_err(&tp->intf->dev,
3892					"check PHY_NC fail\n");
3893				goto fail;
3894			}
3895
3896			if (phy_nc) {
3897				dev_err(&tp->intf->dev,
3898					"multiple PHY NC encountered\n");
3899				goto fail;
3900			}
3901
3902			phy_nc = (struct fw_phy_nc *)block;
3903			if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3904				dev_err(&tp->intf->dev,
3905					"check PHY NC firmware failed\n");
3906				goto fail;
3907			}
3908
3909			break;
3910		default:
3911			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3912				 type);
3913			break;
3914		}
3915
3916		/* next block */
3917		i += ALIGN(__le32_to_cpu(block->length), 8);
3918	}
3919
3920fw_end:
3921	if ((phy_nc || start) && !stop) {
3922		dev_err(&tp->intf->dev, "without PHY_STOP\n");
3923		goto fail;
3924	}
3925
3926	return 0;
3927fail:
3928	return ret;
3929}
3930
3931static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3932{
3933	u16 mode_reg, bp_index;
3934	u32 length, i, num;
3935	__le16 *data;
3936
3937	mode_reg = __le16_to_cpu(phy->mode_reg);
3938	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3939	sram_write(tp, __le16_to_cpu(phy->ba_reg),
3940		   __le16_to_cpu(phy->ba_data));
3941
3942	length = __le32_to_cpu(phy->blk_hdr.length);
3943	length -= __le16_to_cpu(phy->fw_offset);
3944	num = length / 2;
3945	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3946
3947	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3948	for (i = 0; i < num; i++)
3949		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3950
3951	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3952		   __le16_to_cpu(phy->patch_en_value));
3953
3954	bp_index = __le16_to_cpu(phy->bp_start);
3955	num = __le16_to_cpu(phy->bp_num);
3956	for (i = 0; i < num; i++) {
3957		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3958		bp_index += 2;
3959	}
3960
3961	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3962
3963	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3964}
3965
3966static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3967{
3968	u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3969	u32 length;
3970	u8 *data;
3971	int i;
3972
3973	switch (__le32_to_cpu(mac->blk_hdr.type)) {
3974	case RTL_FW_PLA:
3975		type = MCU_TYPE_PLA;
3976		break;
3977	case RTL_FW_USB:
3978		type = MCU_TYPE_USB;
3979		break;
3980	default:
3981		return;
3982	}
3983
3984	rtl_clear_bp(tp, type);
3985
3986	/* Enable backup/restore of MACDBG. This is required after clearing PLA
3987	 * break points and before applying the PLA firmware.
3988	 */
3989	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3990	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3991		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3992		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3993	}
3994
3995	length = __le32_to_cpu(mac->blk_hdr.length);
3996	length -= __le16_to_cpu(mac->fw_offset);
3997
3998	data = (u8 *)mac;
3999	data += __le16_to_cpu(mac->fw_offset);
4000
4001	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4002			  type);
4003
4004	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
4005		       __le16_to_cpu(mac->bp_ba_value));
4006
4007	bp_index = __le16_to_cpu(mac->bp_start);
4008	bp_num = __le16_to_cpu(mac->bp_num);
4009	for (i = 0; i < bp_num; i++) {
4010		ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4011		bp_index += 2;
4012	}
4013
4014	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4015	if (bp_en_addr)
4016		ocp_write_word(tp, type, bp_en_addr,
4017			       __le16_to_cpu(mac->bp_en_value));
4018
4019	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4020	if (fw_ver_reg)
4021		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4022			       mac->fw_ver_data);
4023
4024	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4025}
4026
4027static void rtl8152_apply_firmware(struct r8152 *tp)
4028{
4029	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4030	const struct firmware *fw;
4031	struct fw_header *fw_hdr;
4032	struct fw_phy_patch_key *key;
4033	u16 key_addr = 0;
4034	int i;
4035
4036	if (IS_ERR_OR_NULL(rtl_fw->fw))
4037		return;
4038
4039	fw = rtl_fw->fw;
4040	fw_hdr = (struct fw_header *)fw->data;
4041
4042	if (rtl_fw->pre_fw)
4043		rtl_fw->pre_fw(tp);
4044
4045	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4046		struct fw_block *block = (struct fw_block *)&fw->data[i];
4047
4048		switch (__le32_to_cpu(block->type)) {
4049		case RTL_FW_END:
4050			goto post_fw;
4051		case RTL_FW_PLA:
4052		case RTL_FW_USB:
4053			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4054			break;
4055		case RTL_FW_PHY_START:
4056			key = (struct fw_phy_patch_key *)block;
4057			key_addr = __le16_to_cpu(key->key_reg);
4058			r8153_pre_ram_code(tp, key_addr,
4059					   __le16_to_cpu(key->key_data));
4060			break;
4061		case RTL_FW_PHY_STOP:
4062			WARN_ON(!key_addr);
4063			r8153_post_ram_code(tp, key_addr);
4064			break;
4065		case RTL_FW_PHY_NC:
4066			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4067			break;
4068		default:
4069			break;
4070		}
4071
4072		i += ALIGN(__le32_to_cpu(block->length), 8);
4073	}
4074
4075post_fw:
4076	if (rtl_fw->post_fw)
4077		rtl_fw->post_fw(tp);
4078
4079	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4080	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4081}
4082
4083static void rtl8152_release_firmware(struct r8152 *tp)
4084{
4085	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4086
4087	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4088		release_firmware(rtl_fw->fw);
4089		rtl_fw->fw = NULL;
4090	}
4091}
4092
4093static int rtl8152_request_firmware(struct r8152 *tp)
4094{
4095	struct rtl_fw *rtl_fw = &tp->rtl_fw;
4096	long rc;
4097
4098	if (rtl_fw->fw || !rtl_fw->fw_name) {
4099		dev_info(&tp->intf->dev, "skip request firmware\n");
4100		rc = 0;
4101		goto result;
4102	}
4103
4104	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4105	if (rc < 0)
4106		goto result;
4107
4108	rc = rtl8152_check_firmware(tp, rtl_fw);
4109	if (rc < 0)
4110		release_firmware(rtl_fw->fw);
4111
4112result:
4113	if (rc) {
4114		rtl_fw->fw = ERR_PTR(rc);
4115
4116		dev_warn(&tp->intf->dev,
4117			 "unable to load firmware patch %s (%ld)\n",
4118			 rtl_fw->fw_name, rc);
4119	}
4120
4121	return rc;
4122}
4123
4124static void r8152_aldps_en(struct r8152 *tp, bool enable)
4125{
4126	if (enable) {
4127		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4128						    LINKENA | DIS_SDSAVE);
4129	} else {
4130		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4131						    DIS_SDSAVE);
4132		msleep(20);
4133	}
4134}
4135
4136static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4137{
4138	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4139	ocp_reg_write(tp, OCP_EEE_DATA, reg);
4140	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4141}
4142
4143static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4144{
4145	u16 data;
4146
4147	r8152_mmd_indirect(tp, dev, reg);
4148	data = ocp_reg_read(tp, OCP_EEE_DATA);
4149	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4150
4151	return data;
4152}
4153
4154static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4155{
4156	r8152_mmd_indirect(tp, dev, reg);
4157	ocp_reg_write(tp, OCP_EEE_DATA, data);
4158	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4159}
4160
4161static void r8152_eee_en(struct r8152 *tp, bool enable)
4162{
4163	u16 config1, config2, config3;
4164	u32 ocp_data;
4165
4166	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4167	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4168	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4169	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4170
4171	if (enable) {
4172		ocp_data |= EEE_RX_EN | EEE_TX_EN;
4173		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4174		config1 |= sd_rise_time(1);
4175		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4176		config3 |= fast_snr(42);
4177	} else {
4178		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4179		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4180			     RX_QUIET_EN);
4181		config1 |= sd_rise_time(7);
4182		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4183		config3 |= fast_snr(511);
4184	}
4185
4186	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4187	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4188	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4189	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4190}
4191
4192static void r8153_eee_en(struct r8152 *tp, bool enable)
4193{
4194	u32 ocp_data;
4195	u16 config;
4196
4197	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4198	config = ocp_reg_read(tp, OCP_EEE_CFG);
4199
4200	if (enable) {
4201		ocp_data |= EEE_RX_EN | EEE_TX_EN;
4202		config |= EEE10_EN;
4203	} else {
4204		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4205		config &= ~EEE10_EN;
4206	}
4207
4208	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4209	ocp_reg_write(tp, OCP_EEE_CFG, config);
4210
4211	tp->ups_info.eee = enable;
4212}
4213
4214static void rtl_eee_enable(struct r8152 *tp, bool enable)
4215{
4216	switch (tp->version) {
4217	case RTL_VER_01:
4218	case RTL_VER_02:
4219	case RTL_VER_07:
4220		if (enable) {
4221			r8152_eee_en(tp, true);
4222			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4223					tp->eee_adv);
4224		} else {
4225			r8152_eee_en(tp, false);
4226			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4227		}
4228		break;
4229	case RTL_VER_03:
4230	case RTL_VER_04:
4231	case RTL_VER_05:
4232	case RTL_VER_06:
4233	case RTL_VER_08:
4234	case RTL_VER_09:
4235		if (enable) {
4236			r8153_eee_en(tp, true);
4237			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4238		} else {
4239			r8153_eee_en(tp, false);
4240			ocp_reg_write(tp, OCP_EEE_ADV, 0);
4241		}
4242		break;
4243	default:
4244		break;
4245	}
4246}
4247
4248static void r8152b_enable_fc(struct r8152 *tp)
4249{
4250	u16 anar;
4251
4252	anar = r8152_mdio_read(tp, MII_ADVERTISE);
4253	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4254	r8152_mdio_write(tp, MII_ADVERTISE, anar);
4255
4256	tp->ups_info.flow_control = true;
4257}
4258
4259static void rtl8152_disable(struct r8152 *tp)
4260{
4261	r8152_aldps_en(tp, false);
4262	rtl_disable(tp);
4263	r8152_aldps_en(tp, true);
4264}
4265
4266static void r8152b_hw_phy_cfg(struct r8152 *tp)
4267{
4268	rtl8152_apply_firmware(tp);
4269	rtl_eee_enable(tp, tp->eee_en);
4270	r8152_aldps_en(tp, true);
4271	r8152b_enable_fc(tp);
4272
4273	set_bit(PHY_RESET, &tp->flags);
4274}
4275
4276static void wait_oob_link_list_ready(struct r8152 *tp)
4277{
4278	u32 ocp_data;
4279	int i;
4280
4281	for (i = 0; i < 1000; i++) {
4282		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4283		if (ocp_data & LINK_LIST_READY)
4284			break;
4285		usleep_range(1000, 2000);
4286	}
4287}
4288
4289static void r8152b_exit_oob(struct r8152 *tp)
4290{
4291	u32 ocp_data;
4292
4293	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4294	ocp_data &= ~RCR_ACPT_ALL;
4295	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4296
4297	rxdy_gated_en(tp, true);
4298	r8153_teredo_off(tp);
4299	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4300	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4301
4302	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4303	ocp_data &= ~NOW_IS_OOB;
4304	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4305
4306	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4307	ocp_data &= ~MCU_BORW_EN;
4308	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4309
4310	wait_oob_link_list_ready(tp);
4311
4312	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4313	ocp_data |= RE_INIT_LL;
4314	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4315
4316	wait_oob_link_list_ready(tp);
4317
4318	rtl8152_nic_reset(tp);
4319
4320	/* rx share fifo credit full threshold */
4321	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4322
4323	if (tp->udev->speed == USB_SPEED_FULL ||
4324	    tp->udev->speed == USB_SPEED_LOW) {
4325		/* rx share fifo credit near full threshold */
4326		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4327				RXFIFO_THR2_FULL);
4328		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4329				RXFIFO_THR3_FULL);
4330	} else {
4331		/* rx share fifo credit near full threshold */
4332		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4333				RXFIFO_THR2_HIGH);
4334		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4335				RXFIFO_THR3_HIGH);
4336	}
4337
4338	/* TX share fifo free credit full threshold */
4339	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4340
4341	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4342	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4343	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4344			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4345
4346	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4347
4348	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4349
4350	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4351	ocp_data |= TCR0_AUTO_FIFO;
4352	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4353}
4354
4355static void r8152b_enter_oob(struct r8152 *tp)
4356{
4357	u32 ocp_data;
4358
4359	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4360	ocp_data &= ~NOW_IS_OOB;
4361	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4362
4363	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4364	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4365	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4366
4367	rtl_disable(tp);
4368
4369	wait_oob_link_list_ready(tp);
4370
4371	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4372	ocp_data |= RE_INIT_LL;
4373	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4374
4375	wait_oob_link_list_ready(tp);
4376
4377	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4378
4379	rtl_rx_vlan_en(tp, true);
4380
4381	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4382	ocp_data |= ALDPS_PROXY_MODE;
4383	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4384
4385	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4386	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4387	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4388
4389	rxdy_gated_en(tp, false);
4390
4391	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4392	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4393	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4394}
4395
4396static int r8153_pre_firmware_1(struct r8152 *tp)
4397{
4398	int i;
4399
4400	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
4401	for (i = 0; i < 104; i++) {
4402		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4403
4404		if (!(ocp_data & WTD1_EN))
4405			break;
4406		usleep_range(1000, 2000);
4407	}
4408
4409	return 0;
4410}
4411
4412static int r8153_post_firmware_1(struct r8152 *tp)
4413{
4414	/* set USB_BP_4 to support USB_SPEED_SUPER only */
4415	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4416		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4417
4418	/* reset UPHY timer to 36 ms */
4419	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4420
4421	return 0;
4422}
4423
4424static int r8153_pre_firmware_2(struct r8152 *tp)
4425{
4426	u32 ocp_data;
4427
4428	r8153_pre_firmware_1(tp);
4429
4430	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4431	ocp_data &= ~FW_FIX_SUSPEND;
4432	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4433
4434	return 0;
4435}
4436
4437static int r8153_post_firmware_2(struct r8152 *tp)
4438{
4439	u32 ocp_data;
4440
4441	/* enable bp0 if support USB_SPEED_SUPER only */
4442	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4443		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4444		ocp_data |= BIT(0);
4445		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4446	}
4447
4448	/* reset UPHY timer to 36 ms */
4449	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4450
4451	/* enable U3P3 check, set the counter to 4 */
4452	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4453
4454	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4455	ocp_data |= FW_FIX_SUSPEND;
4456	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4457
4458	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4459	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4460	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4461
4462	return 0;
4463}
4464
4465static int r8153_post_firmware_3(struct r8152 *tp)
4466{
4467	u32 ocp_data;
4468
4469	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4470	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4471	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4472
4473	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4474	ocp_data |= FW_IP_RESET_EN;
4475	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4476
4477	return 0;
4478}
4479
4480static int r8153b_pre_firmware_1(struct r8152 *tp)
4481{
4482	/* enable fc timer and set timer to 1 second. */
4483	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4484		       CTRL_TIMER_EN | (1000 / 8));
4485
4486	return 0;
4487}
4488
4489static int r8153b_post_firmware_1(struct r8152 *tp)
4490{
4491	u32 ocp_data;
4492
4493	/* enable bp0 for RTL8153-BND */
4494	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4495	if (ocp_data & BND_MASK) {
4496		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4497		ocp_data |= BIT(0);
4498		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4499	}
4500
4501	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4502	ocp_data |= FLOW_CTRL_PATCH_OPT;
4503	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4504
4505	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4506	ocp_data |= FC_PATCH_TASK;
4507	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4508
4509	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4510	ocp_data |= FW_IP_RESET_EN;
4511	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4512
4513	return 0;
4514}
4515
4516static void r8153_aldps_en(struct r8152 *tp, bool enable)
4517{
4518	u16 data;
4519
4520	data = ocp_reg_read(tp, OCP_POWER_CFG);
4521	if (enable) {
4522		data |= EN_ALDPS;
4523		ocp_reg_write(tp, OCP_POWER_CFG, data);
4524	} else {
4525		int i;
4526
4527		data &= ~EN_ALDPS;
4528		ocp_reg_write(tp, OCP_POWER_CFG, data);
4529		for (i = 0; i < 20; i++) {
4530			usleep_range(1000, 2000);
4531			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4532				break;
4533		}
4534	}
4535
4536	tp->ups_info.aldps = enable;
4537}
4538
4539static void r8153_hw_phy_cfg(struct r8152 *tp)
4540{
4541	u32 ocp_data;
4542	u16 data;
4543
4544	/* disable ALDPS before updating the PHY parameters */
4545	r8153_aldps_en(tp, false);
4546
4547	/* disable EEE before updating the PHY parameters */
4548	rtl_eee_enable(tp, false);
4549
4550	rtl8152_apply_firmware(tp);
4551
4552	if (tp->version == RTL_VER_03) {
4553		data = ocp_reg_read(tp, OCP_EEE_CFG);
4554		data &= ~CTAP_SHORT_EN;
4555		ocp_reg_write(tp, OCP_EEE_CFG, data);
4556	}
4557
4558	data = ocp_reg_read(tp, OCP_POWER_CFG);
4559	data |= EEE_CLKDIV_EN;
4560	ocp_reg_write(tp, OCP_POWER_CFG, data);
4561
4562	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4563	data |= EN_10M_BGOFF;
4564	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4565	data = ocp_reg_read(tp, OCP_POWER_CFG);
4566	data |= EN_10M_PLLOFF;
4567	ocp_reg_write(tp, OCP_POWER_CFG, data);
4568	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4569
4570	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4571	ocp_data |= PFM_PWM_SWITCH;
4572	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4573
4574	/* Enable LPF corner auto tune */
4575	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4576
4577	/* Adjust 10M Amplitude */
4578	sram_write(tp, SRAM_10M_AMP1, 0x00af);
4579	sram_write(tp, SRAM_10M_AMP2, 0x0208);
4580
4581	if (tp->eee_en)
4582		rtl_eee_enable(tp, true);
4583
4584	r8153_aldps_en(tp, true);
4585	r8152b_enable_fc(tp);
4586
4587	switch (tp->version) {
4588	case RTL_VER_03:
4589	case RTL_VER_04:
4590		break;
4591	case RTL_VER_05:
4592	case RTL_VER_06:
4593	default:
4594		r8153_u2p3en(tp, true);
4595		break;
4596	}
4597
4598	set_bit(PHY_RESET, &tp->flags);
4599}
4600
4601static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4602{
4603	u32 ocp_data;
4604
4605	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4606	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4607	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
4608	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4609
4610	return ocp_data;
4611}
4612
4613static void r8153b_hw_phy_cfg(struct r8152 *tp)
4614{
4615	u32 ocp_data;
4616	u16 data;
4617
4618	/* disable ALDPS before updating the PHY parameters */
4619	r8153_aldps_en(tp, false);
4620
4621	/* disable EEE before updating the PHY parameters */
4622	rtl_eee_enable(tp, false);
4623
4624	rtl8152_apply_firmware(tp);
4625
4626	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4627
4628	data = sram_read(tp, SRAM_GREEN_CFG);
4629	data |= R_TUNE_EN;
4630	sram_write(tp, SRAM_GREEN_CFG, data);
4631	data = ocp_reg_read(tp, OCP_NCTL_CFG);
4632	data |= PGA_RETURN_EN;
4633	ocp_reg_write(tp, OCP_NCTL_CFG, data);
4634
4635	/* ADC Bias Calibration:
4636	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4637	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4638	 * ADC ioffset.
4639	 */
4640	ocp_data = r8152_efuse_read(tp, 0x7d);
4641	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4642	if (data != 0xffff)
4643		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4644
4645	/* ups mode tx-link-pulse timing adjustment:
4646	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4647	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4648	 */
4649	ocp_data = ocp_reg_read(tp, 0xc426);
4650	ocp_data &= 0x3fff;
4651	if (ocp_data) {
4652		u32 swr_cnt_1ms_ini;
4653
4654		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4655		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4656		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4657		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4658	}
4659
4660	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4661	ocp_data |= PFM_PWM_SWITCH;
4662	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4663
4664	/* Advnace EEE */
4665	if (!r8153_patch_request(tp, true)) {
4666		data = ocp_reg_read(tp, OCP_POWER_CFG);
4667		data |= EEE_CLKDIV_EN;
4668		ocp_reg_write(tp, OCP_POWER_CFG, data);
4669		tp->ups_info.eee_ckdiv = true;
4670
4671		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4672		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4673		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4674		tp->ups_info.eee_cmod_lv = true;
4675		tp->ups_info._10m_ckdiv = true;
4676		tp->ups_info.eee_plloff_giga = true;
4677
4678		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4679		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4680		tp->ups_info._250m_ckdiv = true;
4681
4682		r8153_patch_request(tp, false);
4683	}
4684
4685	if (tp->eee_en)
4686		rtl_eee_enable(tp, true);
4687
4688	r8153_aldps_en(tp, true);
4689	r8152b_enable_fc(tp);
4690
4691	set_bit(PHY_RESET, &tp->flags);
4692}
4693
4694static void r8153_first_init(struct r8152 *tp)
4695{
4696	u32 ocp_data;
4697
4698	r8153_mac_clk_spd(tp, false);
4699	rxdy_gated_en(tp, true);
4700	r8153_teredo_off(tp);
4701
4702	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4703	ocp_data &= ~RCR_ACPT_ALL;
4704	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4705
4706	rtl8152_nic_reset(tp);
4707	rtl_reset_bmu(tp);
4708
4709	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4710	ocp_data &= ~NOW_IS_OOB;
4711	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4712
4713	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4714	ocp_data &= ~MCU_BORW_EN;
4715	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4716
4717	wait_oob_link_list_ready(tp);
4718
4719	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4720	ocp_data |= RE_INIT_LL;
4721	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4722
4723	wait_oob_link_list_ready(tp);
4724
4725	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4726
4727	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4728	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4729	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4730
4731	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4732	ocp_data |= TCR0_AUTO_FIFO;
4733	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4734
4735	rtl8152_nic_reset(tp);
4736
4737	/* rx share fifo credit full threshold */
4738	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4739	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4740	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4741	/* TX share fifo free credit full threshold */
4742	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4743}
4744
4745static void r8153_enter_oob(struct r8152 *tp)
4746{
4747	u32 ocp_data;
4748
4749	r8153_mac_clk_spd(tp, true);
4750
4751	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4752	ocp_data &= ~NOW_IS_OOB;
4753	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4754
4755	rtl_disable(tp);
4756	rtl_reset_bmu(tp);
4757
4758	wait_oob_link_list_ready(tp);
4759
4760	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4761	ocp_data |= RE_INIT_LL;
4762	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4763
4764	wait_oob_link_list_ready(tp);
4765
4766	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4767	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4768
4769	switch (tp->version) {
4770	case RTL_VER_03:
4771	case RTL_VER_04:
4772	case RTL_VER_05:
4773	case RTL_VER_06:
4774		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4775		ocp_data &= ~TEREDO_WAKE_MASK;
4776		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4777		break;
4778
4779	case RTL_VER_08:
4780	case RTL_VER_09:
4781		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
4782		 * type. Set it to zero. bits[7:0] are the W1C bits about
4783		 * the events. Set them to all 1 to clear them.
4784		 */
4785		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4786		break;
4787
4788	default:
4789		break;
4790	}
4791
4792	rtl_rx_vlan_en(tp, true);
4793
4794	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4795	ocp_data |= ALDPS_PROXY_MODE;
4796	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4797
4798	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4799	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4800	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4801
4802	rxdy_gated_en(tp, false);
4803
4804	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4805	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4806	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4807}
4808
4809static void rtl8153_disable(struct r8152 *tp)
4810{
4811	r8153_aldps_en(tp, false);
4812	rtl_disable(tp);
4813	rtl_reset_bmu(tp);
4814	r8153_aldps_en(tp, true);
4815}
4816
4817static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4818			     u32 advertising)
4819{
4820	u16 bmcr;
4821	int ret = 0;
4822
4823	if (autoneg == AUTONEG_DISABLE) {
4824		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4825			return -EINVAL;
4826
4827		switch (speed) {
4828		case SPEED_10:
4829			bmcr = BMCR_SPEED10;
4830			if (duplex == DUPLEX_FULL) {
4831				bmcr |= BMCR_FULLDPLX;
4832				tp->ups_info.speed_duplex = FORCE_10M_FULL;
4833			} else {
4834				tp->ups_info.speed_duplex = FORCE_10M_HALF;
4835			}
4836			break;
4837		case SPEED_100:
4838			bmcr = BMCR_SPEED100;
4839			if (duplex == DUPLEX_FULL) {
4840				bmcr |= BMCR_FULLDPLX;
4841				tp->ups_info.speed_duplex = FORCE_100M_FULL;
4842			} else {
4843				tp->ups_info.speed_duplex = FORCE_100M_HALF;
4844			}
4845			break;
4846		case SPEED_1000:
4847			if (tp->mii.supports_gmii) {
4848				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4849				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4850				break;
4851			}
4852			fallthrough;
4853		default:
4854			ret = -EINVAL;
4855			goto out;
4856		}
4857
4858		if (duplex == DUPLEX_FULL)
4859			tp->mii.full_duplex = 1;
4860		else
4861			tp->mii.full_duplex = 0;
4862
4863		tp->mii.force_media = 1;
4864	} else {
4865		u16 anar, tmp1;
4866		u32 support;
4867
4868		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4869			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4870
4871		if (tp->mii.supports_gmii)
4872			support |= RTL_ADVERTISED_1000_FULL;
4873
4874		if (!(advertising & support))
4875			return -EINVAL;
4876
4877		anar = r8152_mdio_read(tp, MII_ADVERTISE);
4878		tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4879				ADVERTISE_100HALF | ADVERTISE_100FULL);
4880		if (advertising & RTL_ADVERTISED_10_HALF) {
4881			tmp1 |= ADVERTISE_10HALF;
4882			tp->ups_info.speed_duplex = NWAY_10M_HALF;
4883		}
4884		if (advertising & RTL_ADVERTISED_10_FULL) {
4885			tmp1 |= ADVERTISE_10FULL;
4886			tp->ups_info.speed_duplex = NWAY_10M_FULL;
4887		}
4888
4889		if (advertising & RTL_ADVERTISED_100_HALF) {
4890			tmp1 |= ADVERTISE_100HALF;
4891			tp->ups_info.speed_duplex = NWAY_100M_HALF;
4892		}
4893		if (advertising & RTL_ADVERTISED_100_FULL) {
4894			tmp1 |= ADVERTISE_100FULL;
4895			tp->ups_info.speed_duplex = NWAY_100M_FULL;
4896		}
4897
4898		if (anar != tmp1) {
4899			r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4900			tp->mii.advertising = tmp1;
4901		}
4902
4903		if (tp->mii.supports_gmii) {
4904			u16 gbcr;
4905
4906			gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4907			tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4908					ADVERTISE_1000HALF);
4909
4910			if (advertising & RTL_ADVERTISED_1000_FULL) {
4911				tmp1 |= ADVERTISE_1000FULL;
4912				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4913			}
4914
4915			if (gbcr != tmp1)
4916				r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4917		}
4918
4919		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4920
4921		tp->mii.force_media = 0;
4922	}
4923
4924	if (test_and_clear_bit(PHY_RESET, &tp->flags))
4925		bmcr |= BMCR_RESET;
4926
4927	r8152_mdio_write(tp, MII_BMCR, bmcr);
4928
4929	if (bmcr & BMCR_RESET) {
4930		int i;
4931
4932		for (i = 0; i < 50; i++) {
4933			msleep(20);
4934			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4935				break;
4936		}
4937	}
4938
4939out:
4940	return ret;
4941}
4942
4943static void rtl8152_up(struct r8152 *tp)
4944{
4945	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4946		return;
4947
4948	r8152_aldps_en(tp, false);
4949	r8152b_exit_oob(tp);
4950	r8152_aldps_en(tp, true);
4951}
4952
4953static void rtl8152_down(struct r8152 *tp)
4954{
4955	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4956		rtl_drop_queued_tx(tp);
4957		return;
4958	}
4959
4960	r8152_power_cut_en(tp, false);
4961	r8152_aldps_en(tp, false);
4962	r8152b_enter_oob(tp);
4963	r8152_aldps_en(tp, true);
4964}
4965
4966static void rtl8153_up(struct r8152 *tp)
4967{
4968	u32 ocp_data;
4969
4970	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4971		return;
4972
4973	r8153_u1u2en(tp, false);
4974	r8153_u2p3en(tp, false);
4975	r8153_aldps_en(tp, false);
4976	r8153_first_init(tp);
4977
4978	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
4979	ocp_data |= LANWAKE_CLR_EN;
4980	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
4981
4982	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
4983	ocp_data &= ~LANWAKE_PIN;
4984	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
4985
4986	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
4987	ocp_data &= ~DELAY_PHY_PWR_CHG;
4988	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
4989
4990	r8153_aldps_en(tp, true);
4991
4992	switch (tp->version) {
4993	case RTL_VER_03:
4994	case RTL_VER_04:
4995		break;
4996	case RTL_VER_05:
4997	case RTL_VER_06:
4998	default:
4999		r8153_u2p3en(tp, true);
5000		break;
5001	}
5002
5003	r8153_u1u2en(tp, true);
5004}
5005
5006static void rtl8153_down(struct r8152 *tp)
5007{
5008	u32 ocp_data;
5009
5010	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5011		rtl_drop_queued_tx(tp);
5012		return;
5013	}
5014
5015	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5016	ocp_data &= ~LANWAKE_CLR_EN;
5017	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5018
5019	r8153_u1u2en(tp, false);
5020	r8153_u2p3en(tp, false);
5021	r8153_power_cut_en(tp, false);
5022	r8153_aldps_en(tp, false);
5023	r8153_enter_oob(tp);
5024	r8153_aldps_en(tp, true);
5025}
5026
5027static void rtl8153b_up(struct r8152 *tp)
5028{
5029	u32 ocp_data;
5030
5031	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5032		return;
5033
5034	r8153b_u1u2en(tp, false);
5035	r8153_u2p3en(tp, false);
5036	r8153_aldps_en(tp, false);
5037
5038	r8153_first_init(tp);
5039	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5040
5041	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5042	ocp_data &= ~PLA_MCU_SPDWN_EN;
5043	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5044
5045	r8153_aldps_en(tp, true);
5046
5047	if (tp->udev->speed != USB_SPEED_HIGH)
5048		r8153b_u1u2en(tp, true);
5049}
5050
5051static void rtl8153b_down(struct r8152 *tp)
5052{
5053	u32 ocp_data;
5054
5055	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5056		rtl_drop_queued_tx(tp);
5057		return;
5058	}
5059
5060	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5061	ocp_data |= PLA_MCU_SPDWN_EN;
5062	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5063
5064	r8153b_u1u2en(tp, false);
5065	r8153_u2p3en(tp, false);
5066	r8153b_power_cut_en(tp, false);
5067	r8153_aldps_en(tp, false);
5068	r8153_enter_oob(tp);
5069	r8153_aldps_en(tp, true);
5070}
5071
5072static bool rtl8152_in_nway(struct r8152 *tp)
5073{
5074	u16 nway_state;
5075
5076	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5077	tp->ocp_base = 0x2000;
5078	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
5079	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5080
5081	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5082	if (nway_state & 0xc000)
5083		return false;
5084	else
5085		return true;
5086}
5087
5088static bool rtl8153_in_nway(struct r8152 *tp)
5089{
5090	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5091
5092	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5093		return false;
5094	else
5095		return true;
5096}
5097
5098static void set_carrier(struct r8152 *tp)
5099{
5100	struct net_device *netdev = tp->netdev;
5101	struct napi_struct *napi = &tp->napi;
5102	u8 speed;
5103
5104	speed = rtl8152_get_speed(tp);
5105
5106	if (speed & LINK_STATUS) {
5107		if (!netif_carrier_ok(netdev)) {
5108			tp->rtl_ops.enable(tp);
5109			netif_stop_queue(netdev);
5110			napi_disable(napi);
5111			netif_carrier_on(netdev);
5112			rtl_start_rx(tp);
5113			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5114			_rtl8152_set_rx_mode(netdev);
5115			napi_enable(&tp->napi);
5116			netif_wake_queue(netdev);
5117			netif_info(tp, link, netdev, "carrier on\n");
5118		} else if (netif_queue_stopped(netdev) &&
5119			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5120			netif_wake_queue(netdev);
5121		}
5122	} else {
5123		if (netif_carrier_ok(netdev)) {
5124			netif_carrier_off(netdev);
5125			tasklet_disable(&tp->tx_tl);
5126			napi_disable(napi);
5127			tp->rtl_ops.disable(tp);
5128			napi_enable(napi);
5129			tasklet_enable(&tp->tx_tl);
5130			netif_info(tp, link, netdev, "carrier off\n");
5131		}
5132	}
5133}
5134
5135static void rtl_work_func_t(struct work_struct *work)
5136{
5137	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5138
5139	/* If the device is unplugged or !netif_running(), the workqueue
5140	 * doesn't need to wake the device, and could return directly.
5141	 */
5142	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5143		return;
5144
5145	if (usb_autopm_get_interface(tp->intf) < 0)
5146		return;
5147
5148	if (!test_bit(WORK_ENABLE, &tp->flags))
5149		goto out1;
5150
5151	if (!mutex_trylock(&tp->control)) {
5152		schedule_delayed_work(&tp->schedule, 0);
5153		goto out1;
5154	}
5155
5156	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5157		set_carrier(tp);
5158
5159	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5160		_rtl8152_set_rx_mode(tp->netdev);
5161
5162	/* don't schedule tasket before linking */
5163	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5164	    netif_carrier_ok(tp->netdev))
5165		tasklet_schedule(&tp->tx_tl);
5166
5167	mutex_unlock(&tp->control);
5168
5169out1:
5170	usb_autopm_put_interface(tp->intf);
5171}
5172
5173static void rtl_hw_phy_work_func_t(struct work_struct *work)
5174{
5175	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5176
5177	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5178		return;
5179
5180	if (usb_autopm_get_interface(tp->intf) < 0)
5181		return;
5182
5183	mutex_lock(&tp->control);
5184
5185	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5186		tp->rtl_fw.retry = false;
5187		tp->rtl_fw.fw = NULL;
5188
5189		/* Delay execution in case request_firmware() is not ready yet.
5190		 */
5191		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5192		goto ignore_once;
5193	}
5194
5195	tp->rtl_ops.hw_phy_cfg(tp);
5196
5197	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5198			  tp->advertising);
5199
5200ignore_once:
5201	mutex_unlock(&tp->control);
5202
5203	usb_autopm_put_interface(tp->intf);
5204}
5205
5206#ifdef CONFIG_PM_SLEEP
5207static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5208			void *data)
5209{
5210	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5211
5212	switch (action) {
5213	case PM_HIBERNATION_PREPARE:
5214	case PM_SUSPEND_PREPARE:
5215		usb_autopm_get_interface(tp->intf);
5216		break;
5217
5218	case PM_POST_HIBERNATION:
5219	case PM_POST_SUSPEND:
5220		usb_autopm_put_interface(tp->intf);
5221		break;
5222
5223	case PM_POST_RESTORE:
5224	case PM_RESTORE_PREPARE:
5225	default:
5226		break;
5227	}
5228
5229	return NOTIFY_DONE;
5230}
5231#endif
5232
5233static int rtl8152_open(struct net_device *netdev)
5234{
5235	struct r8152 *tp = netdev_priv(netdev);
5236	int res = 0;
5237
5238	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5239		cancel_delayed_work_sync(&tp->hw_phy_work);
5240		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5241	}
5242
5243	res = alloc_all_mem(tp);
5244	if (res)
5245		goto out;
5246
5247	res = usb_autopm_get_interface(tp->intf);
5248	if (res < 0)
5249		goto out_free;
5250
5251	mutex_lock(&tp->control);
5252
5253	tp->rtl_ops.up(tp);
5254
5255	netif_carrier_off(netdev);
5256	netif_start_queue(netdev);
5257	set_bit(WORK_ENABLE, &tp->flags);
5258
5259	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5260	if (res) {
5261		if (res == -ENODEV)
5262			netif_device_detach(tp->netdev);
5263		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5264			   res);
5265		goto out_unlock;
5266	}
5267	napi_enable(&tp->napi);
5268	tasklet_enable(&tp->tx_tl);
5269
5270	mutex_unlock(&tp->control);
5271
5272	usb_autopm_put_interface(tp->intf);
5273#ifdef CONFIG_PM_SLEEP
5274	tp->pm_notifier.notifier_call = rtl_notifier;
5275	register_pm_notifier(&tp->pm_notifier);
5276#endif
5277	return 0;
5278
5279out_unlock:
5280	mutex_unlock(&tp->control);
5281	usb_autopm_put_interface(tp->intf);
5282out_free:
5283	free_all_mem(tp);
5284out:
5285	return res;
5286}
5287
5288static int rtl8152_close(struct net_device *netdev)
5289{
5290	struct r8152 *tp = netdev_priv(netdev);
5291	int res = 0;
5292
5293#ifdef CONFIG_PM_SLEEP
5294	unregister_pm_notifier(&tp->pm_notifier);
5295#endif
5296	tasklet_disable(&tp->tx_tl);
5297	clear_bit(WORK_ENABLE, &tp->flags);
5298	usb_kill_urb(tp->intr_urb);
5299	cancel_delayed_work_sync(&tp->schedule);
5300	napi_disable(&tp->napi);
5301	netif_stop_queue(netdev);
5302
5303	res = usb_autopm_get_interface(tp->intf);
5304	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5305		rtl_drop_queued_tx(tp);
5306		rtl_stop_rx(tp);
5307	} else {
5308		mutex_lock(&tp->control);
5309
5310		tp->rtl_ops.down(tp);
5311
5312		mutex_unlock(&tp->control);
5313
5314		usb_autopm_put_interface(tp->intf);
5315	}
5316
5317	free_all_mem(tp);
5318
5319	return res;
5320}
5321
5322static void rtl_tally_reset(struct r8152 *tp)
5323{
5324	u32 ocp_data;
5325
5326	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5327	ocp_data |= TALLY_RESET;
5328	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5329}
5330
5331static void r8152b_init(struct r8152 *tp)
5332{
5333	u32 ocp_data;
5334	u16 data;
5335
5336	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5337		return;
5338
5339	data = r8152_mdio_read(tp, MII_BMCR);
5340	if (data & BMCR_PDOWN) {
5341		data &= ~BMCR_PDOWN;
5342		r8152_mdio_write(tp, MII_BMCR, data);
5343	}
5344
5345	r8152_aldps_en(tp, false);
5346
5347	if (tp->version == RTL_VER_01) {
5348		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5349		ocp_data &= ~LED_MODE_MASK;
5350		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5351	}
5352
5353	r8152_power_cut_en(tp, false);
5354
5355	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5356	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5357	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5358	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5359	ocp_data &= ~MCU_CLK_RATIO_MASK;
5360	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5361	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5362	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5363		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5364	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5365
5366	rtl_tally_reset(tp);
5367
5368	/* enable rx aggregation */
5369	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5370	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5371	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5372}
5373
5374static void r8153_init(struct r8152 *tp)
5375{
5376	u32 ocp_data;
5377	u16 data;
5378	int i;
5379
5380	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5381		return;
5382
5383	r8153_u1u2en(tp, false);
5384
5385	for (i = 0; i < 500; i++) {
5386		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5387		    AUTOLOAD_DONE)
5388			break;
5389
5390		msleep(20);
5391		if (test_bit(RTL8152_UNPLUG, &tp->flags))
5392			break;
5393	}
5394
5395	data = r8153_phy_status(tp, 0);
5396
5397	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5398	    tp->version == RTL_VER_05)
5399		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5400
5401	data = r8152_mdio_read(tp, MII_BMCR);
5402	if (data & BMCR_PDOWN) {
5403		data &= ~BMCR_PDOWN;
5404		r8152_mdio_write(tp, MII_BMCR, data);
5405	}
5406
5407	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5408
5409	r8153_u2p3en(tp, false);
5410
5411	if (tp->version == RTL_VER_04) {
5412		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5413		ocp_data &= ~pwd_dn_scale_mask;
5414		ocp_data |= pwd_dn_scale(96);
5415		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5416
5417		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5418		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5419		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5420	} else if (tp->version == RTL_VER_05) {
5421		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5422		ocp_data &= ~ECM_ALDPS;
5423		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5424
5425		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5426		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5427			ocp_data &= ~DYNAMIC_BURST;
5428		else
5429			ocp_data |= DYNAMIC_BURST;
5430		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5431	} else if (tp->version == RTL_VER_06) {
5432		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5433		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5434			ocp_data &= ~DYNAMIC_BURST;
5435		else
5436			ocp_data |= DYNAMIC_BURST;
5437		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5438
5439		r8153_queue_wake(tp, false);
5440
5441		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5442		if (rtl8152_get_speed(tp) & LINK_STATUS)
5443			ocp_data |= CUR_LINK_OK;
5444		else
5445			ocp_data &= ~CUR_LINK_OK;
5446		ocp_data |= POLL_LINK_CHG;
5447		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5448	}
5449
5450	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5451	ocp_data |= EP4_FULL_FC;
5452	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5453
5454	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5455	ocp_data &= ~TIMER11_EN;
5456	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5457
5458	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5459	ocp_data &= ~LED_MODE_MASK;
5460	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5461
5462	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5463	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5464		ocp_data |= LPM_TIMER_500MS;
5465	else
5466		ocp_data |= LPM_TIMER_500US;
5467	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5468
5469	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5470	ocp_data &= ~SEN_VAL_MASK;
5471	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5472	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5473
5474	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5475
5476	r8153_power_cut_en(tp, false);
5477	rtl_runtime_suspend_enable(tp, false);
5478	r8153_u1u2en(tp, true);
5479	r8153_mac_clk_spd(tp, false);
5480	usb_enable_lpm(tp->udev);
5481
5482	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
5483	ocp_data |= LANWAKE_CLR_EN;
5484	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
5485
5486	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
5487	ocp_data &= ~LANWAKE_PIN;
5488	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
5489
5490	/* rx aggregation */
5491	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5492	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5493	if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5494		ocp_data |= RX_AGG_DISABLE;
5495
5496	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5497
5498	rtl_tally_reset(tp);
5499
5500	switch (tp->udev->speed) {
5501	case USB_SPEED_SUPER:
5502	case USB_SPEED_SUPER_PLUS:
5503		tp->coalesce = COALESCE_SUPER;
5504		break;
5505	case USB_SPEED_HIGH:
5506		tp->coalesce = COALESCE_HIGH;
5507		break;
5508	default:
5509		tp->coalesce = COALESCE_SLOW;
5510		break;
5511	}
5512}
5513
5514static void r8153b_init(struct r8152 *tp)
5515{
5516	u32 ocp_data;
5517	u16 data;
5518	int i;
5519
5520	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5521		return;
5522
5523	r8153b_u1u2en(tp, false);
5524
5525	for (i = 0; i < 500; i++) {
5526		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5527		    AUTOLOAD_DONE)
5528			break;
5529
5530		msleep(20);
5531		if (test_bit(RTL8152_UNPLUG, &tp->flags))
5532			break;
5533	}
5534
5535	data = r8153_phy_status(tp, 0);
5536
5537	data = r8152_mdio_read(tp, MII_BMCR);
5538	if (data & BMCR_PDOWN) {
5539		data &= ~BMCR_PDOWN;
5540		r8152_mdio_write(tp, MII_BMCR, data);
5541	}
5542
5543	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5544
5545	r8153_u2p3en(tp, false);
5546
5547	/* MSC timer = 0xfff * 8ms = 32760 ms */
5548	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5549
5550	/* U1/U2/L1 idle timer. 500 us */
5551	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5552
5553	r8153b_power_cut_en(tp, false);
5554	r8153b_ups_en(tp, false);
5555	r8153_queue_wake(tp, false);
5556	rtl_runtime_suspend_enable(tp, false);
5557
5558	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5559	if (rtl8152_get_speed(tp) & LINK_STATUS)
5560		ocp_data |= CUR_LINK_OK;
5561	else
5562		ocp_data &= ~CUR_LINK_OK;
5563	ocp_data |= POLL_LINK_CHG;
5564	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5565
5566	if (tp->udev->speed != USB_SPEED_HIGH)
5567		r8153b_u1u2en(tp, true);
5568	usb_enable_lpm(tp->udev);
5569
5570	/* MAC clock speed down */
5571	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5572	ocp_data |= MAC_CLK_SPDWN_EN;
5573	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5574
5575	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5576	ocp_data &= ~PLA_MCU_SPDWN_EN;
5577	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5578
5579	if (tp->version == RTL_VER_09) {
5580		/* Disable Test IO for 32QFN */
5581		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5582			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5583			ocp_data |= TEST_IO_OFF;
5584			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5585		}
5586	}
5587
5588	set_bit(GREEN_ETHERNET, &tp->flags);
5589
5590	/* rx aggregation */
5591	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5592	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5593	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5594
5595	rtl_tally_reset(tp);
5596
5597	tp->coalesce = 15000;	/* 15 us */
5598}
5599
5600static int rtl8152_pre_reset(struct usb_interface *intf)
5601{
5602	struct r8152 *tp = usb_get_intfdata(intf);
5603	struct net_device *netdev;
5604
5605	if (!tp)
5606		return 0;
5607
5608	netdev = tp->netdev;
5609	if (!netif_running(netdev))
5610		return 0;
5611
5612	netif_stop_queue(netdev);
5613	tasklet_disable(&tp->tx_tl);
5614	clear_bit(WORK_ENABLE, &tp->flags);
5615	usb_kill_urb(tp->intr_urb);
5616	cancel_delayed_work_sync(&tp->schedule);
5617	napi_disable(&tp->napi);
5618	if (netif_carrier_ok(netdev)) {
5619		mutex_lock(&tp->control);
5620		tp->rtl_ops.disable(tp);
5621		mutex_unlock(&tp->control);
5622	}
5623
5624	return 0;
5625}
5626
5627static int rtl8152_post_reset(struct usb_interface *intf)
5628{
5629	struct r8152 *tp = usb_get_intfdata(intf);
5630	struct net_device *netdev;
5631	struct sockaddr sa;
5632
5633	if (!tp)
5634		return 0;
5635
5636	/* reset the MAC adddress in case of policy change */
5637	if (determine_ethernet_addr(tp, &sa) >= 0) {
5638		rtnl_lock();
5639		dev_set_mac_address (tp->netdev, &sa, NULL);
5640		rtnl_unlock();
5641	}
5642
5643	netdev = tp->netdev;
5644	if (!netif_running(netdev))
5645		return 0;
5646
5647	set_bit(WORK_ENABLE, &tp->flags);
5648	if (netif_carrier_ok(netdev)) {
5649		mutex_lock(&tp->control);
5650		tp->rtl_ops.enable(tp);
5651		rtl_start_rx(tp);
5652		_rtl8152_set_rx_mode(netdev);
5653		mutex_unlock(&tp->control);
5654	}
5655
5656	napi_enable(&tp->napi);
5657	tasklet_enable(&tp->tx_tl);
5658	netif_wake_queue(netdev);
5659	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5660
5661	if (!list_empty(&tp->rx_done))
5662		napi_schedule(&tp->napi);
5663
5664	return 0;
5665}
5666
5667static bool delay_autosuspend(struct r8152 *tp)
5668{
5669	bool sw_linking = !!netif_carrier_ok(tp->netdev);
5670	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5671
5672	/* This means a linking change occurs and the driver doesn't detect it,
5673	 * yet. If the driver has disabled tx/rx and hw is linking on, the
5674	 * device wouldn't wake up by receiving any packet.
5675	 */
5676	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5677		return true;
5678
5679	/* If the linking down is occurred by nway, the device may miss the
5680	 * linking change event. And it wouldn't wake when linking on.
5681	 */
5682	if (!sw_linking && tp->rtl_ops.in_nway(tp))
5683		return true;
5684	else if (!skb_queue_empty(&tp->tx_queue))
5685		return true;
5686	else
5687		return false;
5688}
5689
5690static int rtl8152_runtime_resume(struct r8152 *tp)
5691{
5692	struct net_device *netdev = tp->netdev;
5693
5694	if (netif_running(netdev) && netdev->flags & IFF_UP) {
5695		struct napi_struct *napi = &tp->napi;
5696
5697		tp->rtl_ops.autosuspend_en(tp, false);
5698		napi_disable(napi);
5699		set_bit(WORK_ENABLE, &tp->flags);
5700
5701		if (netif_carrier_ok(netdev)) {
5702			if (rtl8152_get_speed(tp) & LINK_STATUS) {
5703				rtl_start_rx(tp);
5704			} else {
5705				netif_carrier_off(netdev);
5706				tp->rtl_ops.disable(tp);
5707				netif_info(tp, link, netdev, "linking down\n");
5708			}
5709		}
5710
5711		napi_enable(napi);
5712		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5713		smp_mb__after_atomic();
5714
5715		if (!list_empty(&tp->rx_done))
5716			napi_schedule(&tp->napi);
5717
5718		usb_submit_urb(tp->intr_urb, GFP_NOIO);
5719	} else {
5720		if (netdev->flags & IFF_UP)
5721			tp->rtl_ops.autosuspend_en(tp, false);
5722
5723		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5724	}
5725
5726	return 0;
5727}
5728
5729static int rtl8152_system_resume(struct r8152 *tp)
5730{
5731	struct net_device *netdev = tp->netdev;
5732
5733	netif_device_attach(netdev);
5734
5735	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5736		tp->rtl_ops.up(tp);
5737		netif_carrier_off(netdev);
5738		set_bit(WORK_ENABLE, &tp->flags);
5739		usb_submit_urb(tp->intr_urb, GFP_NOIO);
5740	}
5741
5742	return 0;
5743}
5744
5745static int rtl8152_runtime_suspend(struct r8152 *tp)
5746{
5747	struct net_device *netdev = tp->netdev;
5748	int ret = 0;
5749
5750	set_bit(SELECTIVE_SUSPEND, &tp->flags);
5751	smp_mb__after_atomic();
5752
5753	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5754		u32 rcr = 0;
5755
5756		if (netif_carrier_ok(netdev)) {
5757			u32 ocp_data;
5758
5759			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5760			ocp_data = rcr & ~RCR_ACPT_ALL;
5761			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5762			rxdy_gated_en(tp, true);
5763			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5764						 PLA_OOB_CTRL);
5765			if (!(ocp_data & RXFIFO_EMPTY)) {
5766				rxdy_gated_en(tp, false);
5767				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5768				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5769				smp_mb__after_atomic();
5770				ret = -EBUSY;
5771				goto out1;
5772			}
5773		}
5774
5775		clear_bit(WORK_ENABLE, &tp->flags);
5776		usb_kill_urb(tp->intr_urb);
5777
5778		tp->rtl_ops.autosuspend_en(tp, true);
5779
5780		if (netif_carrier_ok(netdev)) {
5781			struct napi_struct *napi = &tp->napi;
5782
5783			napi_disable(napi);
5784			rtl_stop_rx(tp);
5785			rxdy_gated_en(tp, false);
5786			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5787			napi_enable(napi);
5788		}
5789
5790		if (delay_autosuspend(tp)) {
5791			rtl8152_runtime_resume(tp);
5792			ret = -EBUSY;
5793		}
5794	}
5795
5796out1:
5797	return ret;
5798}
5799
5800static int rtl8152_system_suspend(struct r8152 *tp)
5801{
5802	struct net_device *netdev = tp->netdev;
5803
5804	netif_device_detach(netdev);
5805
5806	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5807		struct napi_struct *napi = &tp->napi;
5808
5809		clear_bit(WORK_ENABLE, &tp->flags);
5810		usb_kill_urb(tp->intr_urb);
5811		tasklet_disable(&tp->tx_tl);
5812		napi_disable(napi);
5813		cancel_delayed_work_sync(&tp->schedule);
5814		tp->rtl_ops.down(tp);
5815		napi_enable(napi);
5816		tasklet_enable(&tp->tx_tl);
5817	}
5818
5819	return 0;
5820}
5821
5822static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5823{
5824	struct r8152 *tp = usb_get_intfdata(intf);
5825	int ret;
5826
5827	mutex_lock(&tp->control);
5828
5829	if (PMSG_IS_AUTO(message))
5830		ret = rtl8152_runtime_suspend(tp);
5831	else
5832		ret = rtl8152_system_suspend(tp);
5833
5834	mutex_unlock(&tp->control);
5835
5836	return ret;
5837}
5838
5839static int rtl8152_resume(struct usb_interface *intf)
5840{
5841	struct r8152 *tp = usb_get_intfdata(intf);
5842	int ret;
5843
5844	mutex_lock(&tp->control);
5845
5846	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5847		ret = rtl8152_runtime_resume(tp);
5848	else
5849		ret = rtl8152_system_resume(tp);
5850
5851	mutex_unlock(&tp->control);
5852
5853	return ret;
5854}
5855
5856static int rtl8152_reset_resume(struct usb_interface *intf)
5857{
5858	struct r8152 *tp = usb_get_intfdata(intf);
5859
5860	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5861	tp->rtl_ops.init(tp);
5862	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5863	set_ethernet_addr(tp);
5864	return rtl8152_resume(intf);
5865}
5866
5867static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5868{
5869	struct r8152 *tp = netdev_priv(dev);
5870
5871	if (usb_autopm_get_interface(tp->intf) < 0)
5872		return;
5873
5874	if (!rtl_can_wakeup(tp)) {
5875		wol->supported = 0;
5876		wol->wolopts = 0;
5877	} else {
5878		mutex_lock(&tp->control);
5879		wol->supported = WAKE_ANY;
5880		wol->wolopts = __rtl_get_wol(tp);
5881		mutex_unlock(&tp->control);
5882	}
5883
5884	usb_autopm_put_interface(tp->intf);
5885}
5886
5887static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5888{
5889	struct r8152 *tp = netdev_priv(dev);
5890	int ret;
5891
5892	if (!rtl_can_wakeup(tp))
5893		return -EOPNOTSUPP;
5894
5895	if (wol->wolopts & ~WAKE_ANY)
5896		return -EINVAL;
5897
5898	ret = usb_autopm_get_interface(tp->intf);
5899	if (ret < 0)
5900		goto out_set_wol;
5901
5902	mutex_lock(&tp->control);
5903
5904	__rtl_set_wol(tp, wol->wolopts);
5905	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5906
5907	mutex_unlock(&tp->control);
5908
5909	usb_autopm_put_interface(tp->intf);
5910
5911out_set_wol:
5912	return ret;
5913}
5914
5915static u32 rtl8152_get_msglevel(struct net_device *dev)
5916{
5917	struct r8152 *tp = netdev_priv(dev);
5918
5919	return tp->msg_enable;
5920}
5921
5922static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5923{
5924	struct r8152 *tp = netdev_priv(dev);
5925
5926	tp->msg_enable = value;
5927}
5928
5929static void rtl8152_get_drvinfo(struct net_device *netdev,
5930				struct ethtool_drvinfo *info)
5931{
5932	struct r8152 *tp = netdev_priv(netdev);
5933
5934	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5935	strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5936	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5937	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5938		strlcpy(info->fw_version, tp->rtl_fw.version,
5939			sizeof(info->fw_version));
5940}
5941
5942static
5943int rtl8152_get_link_ksettings(struct net_device *netdev,
5944			       struct ethtool_link_ksettings *cmd)
5945{
5946	struct r8152 *tp = netdev_priv(netdev);
5947	int ret;
5948
5949	if (!tp->mii.mdio_read)
5950		return -EOPNOTSUPP;
5951
5952	ret = usb_autopm_get_interface(tp->intf);
5953	if (ret < 0)
5954		goto out;
5955
5956	mutex_lock(&tp->control);
5957
5958	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5959
5960	mutex_unlock(&tp->control);
5961
5962	usb_autopm_put_interface(tp->intf);
5963
5964out:
5965	return ret;
5966}
5967
5968static int rtl8152_set_link_ksettings(struct net_device *dev,
5969				      const struct ethtool_link_ksettings *cmd)
5970{
5971	struct r8152 *tp = netdev_priv(dev);
5972	u32 advertising = 0;
5973	int ret;
5974
5975	ret = usb_autopm_get_interface(tp->intf);
5976	if (ret < 0)
5977		goto out;
5978
5979	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5980		     cmd->link_modes.advertising))
5981		advertising |= RTL_ADVERTISED_10_HALF;
5982
5983	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5984		     cmd->link_modes.advertising))
5985		advertising |= RTL_ADVERTISED_10_FULL;
5986
5987	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5988		     cmd->link_modes.advertising))
5989		advertising |= RTL_ADVERTISED_100_HALF;
5990
5991	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5992		     cmd->link_modes.advertising))
5993		advertising |= RTL_ADVERTISED_100_FULL;
5994
5995	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5996		     cmd->link_modes.advertising))
5997		advertising |= RTL_ADVERTISED_1000_HALF;
5998
5999	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
6000		     cmd->link_modes.advertising))
6001		advertising |= RTL_ADVERTISED_1000_FULL;
6002
6003	mutex_lock(&tp->control);
6004
6005	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
6006				cmd->base.duplex, advertising);
6007	if (!ret) {
6008		tp->autoneg = cmd->base.autoneg;
6009		tp->speed = cmd->base.speed;
6010		tp->duplex = cmd->base.duplex;
6011		tp->advertising = advertising;
6012	}
6013
6014	mutex_unlock(&tp->control);
6015
6016	usb_autopm_put_interface(tp->intf);
6017
6018out:
6019	return ret;
6020}
6021
6022static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
6023	"tx_packets",
6024	"rx_packets",
6025	"tx_errors",
6026	"rx_errors",
6027	"rx_missed",
6028	"align_errors",
6029	"tx_single_collisions",
6030	"tx_multi_collisions",
6031	"rx_unicast",
6032	"rx_broadcast",
6033	"rx_multicast",
6034	"tx_aborted",
6035	"tx_underrun",
6036};
6037
6038static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6039{
6040	switch (sset) {
6041	case ETH_SS_STATS:
6042		return ARRAY_SIZE(rtl8152_gstrings);
6043	default:
6044		return -EOPNOTSUPP;
6045	}
6046}
6047
6048static void rtl8152_get_ethtool_stats(struct net_device *dev,
6049				      struct ethtool_stats *stats, u64 *data)
6050{
6051	struct r8152 *tp = netdev_priv(dev);
6052	struct tally_counter tally;
6053
6054	if (usb_autopm_get_interface(tp->intf) < 0)
6055		return;
6056
6057	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6058
6059	usb_autopm_put_interface(tp->intf);
6060
6061	data[0] = le64_to_cpu(tally.tx_packets);
6062	data[1] = le64_to_cpu(tally.rx_packets);
6063	data[2] = le64_to_cpu(tally.tx_errors);
6064	data[3] = le32_to_cpu(tally.rx_errors);
6065	data[4] = le16_to_cpu(tally.rx_missed);
6066	data[5] = le16_to_cpu(tally.align_errors);
6067	data[6] = le32_to_cpu(tally.tx_one_collision);
6068	data[7] = le32_to_cpu(tally.tx_multi_collision);
6069	data[8] = le64_to_cpu(tally.rx_unicast);
6070	data[9] = le64_to_cpu(tally.rx_broadcast);
6071	data[10] = le32_to_cpu(tally.rx_multicast);
6072	data[11] = le16_to_cpu(tally.tx_aborted);
6073	data[12] = le16_to_cpu(tally.tx_underrun);
6074}
6075
6076static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6077{
6078	switch (stringset) {
6079	case ETH_SS_STATS:
6080		memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6081		break;
6082	}
6083}
6084
6085static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6086{
6087	u32 lp, adv, supported = 0;
6088	u16 val;
6089
6090	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6091	supported = mmd_eee_cap_to_ethtool_sup_t(val);
6092
6093	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6094	adv = mmd_eee_adv_to_ethtool_adv_t(val);
6095
6096	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6097	lp = mmd_eee_adv_to_ethtool_adv_t(val);
6098
6099	eee->eee_enabled = tp->eee_en;
6100	eee->eee_active = !!(supported & adv & lp);
6101	eee->supported = supported;
6102	eee->advertised = tp->eee_adv;
6103	eee->lp_advertised = lp;
6104
6105	return 0;
6106}
6107
6108static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6109{
6110	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6111
6112	tp->eee_en = eee->eee_enabled;
6113	tp->eee_adv = val;
6114
6115	rtl_eee_enable(tp, tp->eee_en);
6116
6117	return 0;
6118}
6119
6120static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6121{
6122	u32 lp, adv, supported = 0;
6123	u16 val;
6124
6125	val = ocp_reg_read(tp, OCP_EEE_ABLE);
6126	supported = mmd_eee_cap_to_ethtool_sup_t(val);
6127
6128	val = ocp_reg_read(tp, OCP_EEE_ADV);
6129	adv = mmd_eee_adv_to_ethtool_adv_t(val);
6130
6131	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6132	lp = mmd_eee_adv_to_ethtool_adv_t(val);
6133
6134	eee->eee_enabled = tp->eee_en;
6135	eee->eee_active = !!(supported & adv & lp);
6136	eee->supported = supported;
6137	eee->advertised = tp->eee_adv;
6138	eee->lp_advertised = lp;
6139
6140	return 0;
6141}
6142
6143static int
6144rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6145{
6146	struct r8152 *tp = netdev_priv(net);
6147	int ret;
6148
6149	ret = usb_autopm_get_interface(tp->intf);
6150	if (ret < 0)
6151		goto out;
6152
6153	mutex_lock(&tp->control);
6154
6155	ret = tp->rtl_ops.eee_get(tp, edata);
6156
6157	mutex_unlock(&tp->control);
6158
6159	usb_autopm_put_interface(tp->intf);
6160
6161out:
6162	return ret;
6163}
6164
6165static int
6166rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6167{
6168	struct r8152 *tp = netdev_priv(net);
6169	int ret;
6170
6171	ret = usb_autopm_get_interface(tp->intf);
6172	if (ret < 0)
6173		goto out;
6174
6175	mutex_lock(&tp->control);
6176
6177	ret = tp->rtl_ops.eee_set(tp, edata);
6178	if (!ret)
6179		ret = mii_nway_restart(&tp->mii);
6180
6181	mutex_unlock(&tp->control);
6182
6183	usb_autopm_put_interface(tp->intf);
6184
6185out:
6186	return ret;
6187}
6188
6189static int rtl8152_nway_reset(struct net_device *dev)
6190{
6191	struct r8152 *tp = netdev_priv(dev);
6192	int ret;
6193
6194	ret = usb_autopm_get_interface(tp->intf);
6195	if (ret < 0)
6196		goto out;
6197
6198	mutex_lock(&tp->control);
6199
6200	ret = mii_nway_restart(&tp->mii);
6201
6202	mutex_unlock(&tp->control);
6203
6204	usb_autopm_put_interface(tp->intf);
6205
6206out:
6207	return ret;
6208}
6209
6210static int rtl8152_get_coalesce(struct net_device *netdev,
6211				struct ethtool_coalesce *coalesce)
6212{
6213	struct r8152 *tp = netdev_priv(netdev);
6214
6215	switch (tp->version) {
6216	case RTL_VER_01:
6217	case RTL_VER_02:
6218	case RTL_VER_07:
6219		return -EOPNOTSUPP;
6220	default:
6221		break;
6222	}
6223
6224	coalesce->rx_coalesce_usecs = tp->coalesce;
6225
6226	return 0;
6227}
6228
6229static int rtl8152_set_coalesce(struct net_device *netdev,
6230				struct ethtool_coalesce *coalesce)
6231{
6232	struct r8152 *tp = netdev_priv(netdev);
6233	int ret;
6234
6235	switch (tp->version) {
6236	case RTL_VER_01:
6237	case RTL_VER_02:
6238	case RTL_VER_07:
6239		return -EOPNOTSUPP;
6240	default:
6241		break;
6242	}
6243
6244	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6245		return -EINVAL;
6246
6247	ret = usb_autopm_get_interface(tp->intf);
6248	if (ret < 0)
6249		return ret;
6250
6251	mutex_lock(&tp->control);
6252
6253	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6254		tp->coalesce = coalesce->rx_coalesce_usecs;
6255
6256		if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6257			netif_stop_queue(netdev);
6258			napi_disable(&tp->napi);
6259			tp->rtl_ops.disable(tp);
6260			tp->rtl_ops.enable(tp);
6261			rtl_start_rx(tp);
6262			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6263			_rtl8152_set_rx_mode(netdev);
6264			napi_enable(&tp->napi);
6265			netif_wake_queue(netdev);
6266		}
6267	}
6268
6269	mutex_unlock(&tp->control);
6270
6271	usb_autopm_put_interface(tp->intf);
6272
6273	return ret;
6274}
6275
6276static int rtl8152_get_tunable(struct net_device *netdev,
6277			       const struct ethtool_tunable *tunable, void *d)
6278{
6279	struct r8152 *tp = netdev_priv(netdev);
6280
6281	switch (tunable->id) {
6282	case ETHTOOL_RX_COPYBREAK:
6283		*(u32 *)d = tp->rx_copybreak;
6284		break;
6285	default:
6286		return -EOPNOTSUPP;
6287	}
6288
6289	return 0;
6290}
6291
6292static int rtl8152_set_tunable(struct net_device *netdev,
6293			       const struct ethtool_tunable *tunable,
6294			       const void *d)
6295{
6296	struct r8152 *tp = netdev_priv(netdev);
6297	u32 val;
6298
6299	switch (tunable->id) {
6300	case ETHTOOL_RX_COPYBREAK:
6301		val = *(u32 *)d;
6302		if (val < ETH_ZLEN) {
6303			netif_err(tp, rx_err, netdev,
6304				  "Invalid rx copy break value\n");
6305			return -EINVAL;
6306		}
6307
6308		if (tp->rx_copybreak != val) {
6309			if (netdev->flags & IFF_UP) {
6310				mutex_lock(&tp->control);
6311				napi_disable(&tp->napi);
6312				tp->rx_copybreak = val;
6313				napi_enable(&tp->napi);
6314				mutex_unlock(&tp->control);
6315			} else {
6316				tp->rx_copybreak = val;
6317			}
6318		}
6319		break;
6320	default:
6321		return -EOPNOTSUPP;
6322	}
6323
6324	return 0;
6325}
6326
6327static void rtl8152_get_ringparam(struct net_device *netdev,
6328				  struct ethtool_ringparam *ring)
6329{
6330	struct r8152 *tp = netdev_priv(netdev);
6331
6332	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6333	ring->rx_pending = tp->rx_pending;
6334}
6335
6336static int rtl8152_set_ringparam(struct net_device *netdev,
6337				 struct ethtool_ringparam *ring)
6338{
6339	struct r8152 *tp = netdev_priv(netdev);
6340
6341	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6342		return -EINVAL;
6343
6344	if (tp->rx_pending != ring->rx_pending) {
6345		if (netdev->flags & IFF_UP) {
6346			mutex_lock(&tp->control);
6347			napi_disable(&tp->napi);
6348			tp->rx_pending = ring->rx_pending;
6349			napi_enable(&tp->napi);
6350			mutex_unlock(&tp->control);
6351		} else {
6352			tp->rx_pending = ring->rx_pending;
6353		}
6354	}
6355
6356	return 0;
6357}
6358
6359static const struct ethtool_ops ops = {
6360	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
6361	.get_drvinfo = rtl8152_get_drvinfo,
6362	.get_link = ethtool_op_get_link,
6363	.nway_reset = rtl8152_nway_reset,
6364	.get_msglevel = rtl8152_get_msglevel,
6365	.set_msglevel = rtl8152_set_msglevel,
6366	.get_wol = rtl8152_get_wol,
6367	.set_wol = rtl8152_set_wol,
6368	.get_strings = rtl8152_get_strings,
6369	.get_sset_count = rtl8152_get_sset_count,
6370	.get_ethtool_stats = rtl8152_get_ethtool_stats,
6371	.get_coalesce = rtl8152_get_coalesce,
6372	.set_coalesce = rtl8152_set_coalesce,
6373	.get_eee = rtl_ethtool_get_eee,
6374	.set_eee = rtl_ethtool_set_eee,
6375	.get_link_ksettings = rtl8152_get_link_ksettings,
6376	.set_link_ksettings = rtl8152_set_link_ksettings,
6377	.get_tunable = rtl8152_get_tunable,
6378	.set_tunable = rtl8152_set_tunable,
6379	.get_ringparam = rtl8152_get_ringparam,
6380	.set_ringparam = rtl8152_set_ringparam,
6381};
6382
6383static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6384{
6385	struct r8152 *tp = netdev_priv(netdev);
6386	struct mii_ioctl_data *data = if_mii(rq);
6387	int res;
6388
6389	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6390		return -ENODEV;
6391
6392	res = usb_autopm_get_interface(tp->intf);
6393	if (res < 0)
6394		goto out;
6395
6396	switch (cmd) {
6397	case SIOCGMIIPHY:
6398		data->phy_id = R8152_PHY_ID; /* Internal PHY */
6399		break;
6400
6401	case SIOCGMIIREG:
6402		mutex_lock(&tp->control);
6403		data->val_out = r8152_mdio_read(tp, data->reg_num);
6404		mutex_unlock(&tp->control);
6405		break;
6406
6407	case SIOCSMIIREG:
6408		if (!capable(CAP_NET_ADMIN)) {
6409			res = -EPERM;
6410			break;
6411		}
6412		mutex_lock(&tp->control);
6413		r8152_mdio_write(tp, data->reg_num, data->val_in);
6414		mutex_unlock(&tp->control);
6415		break;
6416
6417	default:
6418		res = -EOPNOTSUPP;
6419	}
6420
6421	usb_autopm_put_interface(tp->intf);
6422
6423out:
6424	return res;
6425}
6426
6427static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6428{
6429	struct r8152 *tp = netdev_priv(dev);
6430	int ret;
6431
6432	switch (tp->version) {
6433	case RTL_VER_01:
6434	case RTL_VER_02:
6435	case RTL_VER_07:
6436		dev->mtu = new_mtu;
6437		return 0;
6438	default:
6439		break;
6440	}
6441
6442	ret = usb_autopm_get_interface(tp->intf);
6443	if (ret < 0)
6444		return ret;
6445
6446	mutex_lock(&tp->control);
6447
6448	dev->mtu = new_mtu;
6449
6450	if (netif_running(dev)) {
6451		u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6452
6453		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6454
6455		if (netif_carrier_ok(dev))
6456			r8153_set_rx_early_size(tp);
6457	}
6458
6459	mutex_unlock(&tp->control);
6460
6461	usb_autopm_put_interface(tp->intf);
6462
6463	return ret;
6464}
6465
6466static const struct net_device_ops rtl8152_netdev_ops = {
6467	.ndo_open		= rtl8152_open,
6468	.ndo_stop		= rtl8152_close,
6469	.ndo_do_ioctl		= rtl8152_ioctl,
6470	.ndo_start_xmit		= rtl8152_start_xmit,
6471	.ndo_tx_timeout		= rtl8152_tx_timeout,
6472	.ndo_set_features	= rtl8152_set_features,
6473	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
6474	.ndo_set_mac_address	= rtl8152_set_mac_address,
6475	.ndo_change_mtu		= rtl8152_change_mtu,
6476	.ndo_validate_addr	= eth_validate_addr,
6477	.ndo_features_check	= rtl8152_features_check,
6478};
6479
6480static void rtl8152_unload(struct r8152 *tp)
6481{
6482	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6483		return;
6484
6485	if (tp->version != RTL_VER_01)
6486		r8152_power_cut_en(tp, true);
6487}
6488
6489static void rtl8153_unload(struct r8152 *tp)
6490{
6491	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6492		return;
6493
6494	r8153_power_cut_en(tp, false);
6495}
6496
6497static void rtl8153b_unload(struct r8152 *tp)
6498{
6499	if (test_bit(RTL8152_UNPLUG, &tp->flags))
6500		return;
6501
6502	r8153b_power_cut_en(tp, false);
6503}
6504
6505static int rtl_ops_init(struct r8152 *tp)
6506{
6507	struct rtl_ops *ops = &tp->rtl_ops;
6508	int ret = 0;
6509
6510	switch (tp->version) {
6511	case RTL_VER_01:
6512	case RTL_VER_02:
6513	case RTL_VER_07:
6514		ops->init		= r8152b_init;
6515		ops->enable		= rtl8152_enable;
6516		ops->disable		= rtl8152_disable;
6517		ops->up			= rtl8152_up;
6518		ops->down		= rtl8152_down;
6519		ops->unload		= rtl8152_unload;
6520		ops->eee_get		= r8152_get_eee;
6521		ops->eee_set		= r8152_set_eee;
6522		ops->in_nway		= rtl8152_in_nway;
6523		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
6524		ops->autosuspend_en	= rtl_runtime_suspend_enable;
6525		tp->rx_buf_sz		= 16 * 1024;
6526		tp->eee_en		= true;
6527		tp->eee_adv		= MDIO_EEE_100TX;
6528		break;
6529
6530	case RTL_VER_03:
6531	case RTL_VER_04:
6532	case RTL_VER_05:
6533	case RTL_VER_06:
6534		ops->init		= r8153_init;
6535		ops->enable		= rtl8153_enable;
6536		ops->disable		= rtl8153_disable;
6537		ops->up			= rtl8153_up;
6538		ops->down		= rtl8153_down;
6539		ops->unload		= rtl8153_unload;
6540		ops->eee_get		= r8153_get_eee;
6541		ops->eee_set		= r8152_set_eee;
6542		ops->in_nway		= rtl8153_in_nway;
6543		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
6544		ops->autosuspend_en	= rtl8153_runtime_enable;
6545		tp->rx_buf_sz		= 32 * 1024;
6546		tp->eee_en		= true;
6547		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
6548		break;
6549
6550	case RTL_VER_08:
6551	case RTL_VER_09:
6552		ops->init		= r8153b_init;
6553		ops->enable		= rtl8153_enable;
6554		ops->disable		= rtl8153_disable;
6555		ops->up			= rtl8153b_up;
6556		ops->down		= rtl8153b_down;
6557		ops->unload		= rtl8153b_unload;
6558		ops->eee_get		= r8153_get_eee;
6559		ops->eee_set		= r8152_set_eee;
6560		ops->in_nway		= rtl8153_in_nway;
6561		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
6562		ops->autosuspend_en	= rtl8153b_runtime_enable;
6563		tp->rx_buf_sz		= 32 * 1024;
6564		tp->eee_en		= true;
6565		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
6566		break;
6567
6568	default:
6569		ret = -ENODEV;
6570		netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6571		break;
6572	}
6573
6574	return ret;
6575}
6576
6577#define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"
6578#define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"
6579#define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"
6580#define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"
6581
6582MODULE_FIRMWARE(FIRMWARE_8153A_2);
6583MODULE_FIRMWARE(FIRMWARE_8153A_3);
6584MODULE_FIRMWARE(FIRMWARE_8153A_4);
6585MODULE_FIRMWARE(FIRMWARE_8153B_2);
6586
6587static int rtl_fw_init(struct r8152 *tp)
6588{
6589	struct rtl_fw *rtl_fw = &tp->rtl_fw;
6590
6591	switch (tp->version) {
6592	case RTL_VER_04:
6593		rtl_fw->fw_name		= FIRMWARE_8153A_2;
6594		rtl_fw->pre_fw		= r8153_pre_firmware_1;
6595		rtl_fw->post_fw		= r8153_post_firmware_1;
6596		break;
6597	case RTL_VER_05:
6598		rtl_fw->fw_name		= FIRMWARE_8153A_3;
6599		rtl_fw->pre_fw		= r8153_pre_firmware_2;
6600		rtl_fw->post_fw		= r8153_post_firmware_2;
6601		break;
6602	case RTL_VER_06:
6603		rtl_fw->fw_name		= FIRMWARE_8153A_4;
6604		rtl_fw->post_fw		= r8153_post_firmware_3;
6605		break;
6606	case RTL_VER_09:
6607		rtl_fw->fw_name		= FIRMWARE_8153B_2;
6608		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
6609		rtl_fw->post_fw		= r8153b_post_firmware_1;
6610		break;
6611	default:
6612		break;
6613	}
6614
6615	return 0;
6616}
6617
6618static u8 rtl_get_version(struct usb_interface *intf)
6619{
6620	struct usb_device *udev = interface_to_usbdev(intf);
6621	u32 ocp_data = 0;
6622	__le32 *tmp;
6623	u8 version;
6624	int ret;
6625
6626	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6627	if (!tmp)
6628		return 0;
6629
6630	ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6631			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6632			      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6633	if (ret > 0)
6634		ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6635
6636	kfree(tmp);
6637
6638	switch (ocp_data) {
6639	case 0x4c00:
6640		version = RTL_VER_01;
6641		break;
6642	case 0x4c10:
6643		version = RTL_VER_02;
6644		break;
6645	case 0x5c00:
6646		version = RTL_VER_03;
6647		break;
6648	case 0x5c10:
6649		version = RTL_VER_04;
6650		break;
6651	case 0x5c20:
6652		version = RTL_VER_05;
6653		break;
6654	case 0x5c30:
6655		version = RTL_VER_06;
6656		break;
6657	case 0x4800:
6658		version = RTL_VER_07;
6659		break;
6660	case 0x6000:
6661		version = RTL_VER_08;
6662		break;
6663	case 0x6010:
6664		version = RTL_VER_09;
6665		break;
6666	default:
6667		version = RTL_VER_UNKNOWN;
6668		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6669		break;
6670	}
6671
6672	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6673
6674	return version;
6675}
6676
6677static int rtl8152_probe(struct usb_interface *intf,
6678			 const struct usb_device_id *id)
6679{
6680	struct usb_device *udev = interface_to_usbdev(intf);
6681	u8 version = rtl_get_version(intf);
6682	struct r8152 *tp;
6683	struct net_device *netdev;
6684	int ret;
6685
6686	if (version == RTL_VER_UNKNOWN)
6687		return -ENODEV;
6688
6689	if (udev->actconfig->desc.bConfigurationValue != 1) {
6690		usb_driver_set_configuration(udev, 1);
6691		return -ENODEV;
6692	}
6693
6694	if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6695		return -ENODEV;
6696
6697	usb_reset_device(udev);
6698	netdev = alloc_etherdev(sizeof(struct r8152));
6699	if (!netdev) {
6700		dev_err(&intf->dev, "Out of memory\n");
6701		return -ENOMEM;
6702	}
6703
6704	SET_NETDEV_DEV(netdev, &intf->dev);
6705	tp = netdev_priv(netdev);
6706	tp->msg_enable = 0x7FFF;
6707
6708	tp->udev = udev;
6709	tp->netdev = netdev;
6710	tp->intf = intf;
6711	tp->version = version;
6712
6713	switch (version) {
6714	case RTL_VER_01:
6715	case RTL_VER_02:
6716	case RTL_VER_07:
6717		tp->mii.supports_gmii = 0;
6718		break;
6719	default:
6720		tp->mii.supports_gmii = 1;
6721		break;
6722	}
6723
6724	ret = rtl_ops_init(tp);
6725	if (ret)
6726		goto out;
6727
6728	rtl_fw_init(tp);
6729
6730	mutex_init(&tp->control);
6731	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6732	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6733	tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6734	tasklet_disable(&tp->tx_tl);
6735
6736	netdev->netdev_ops = &rtl8152_netdev_ops;
6737	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6738
6739	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6740			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6741			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6742			    NETIF_F_HW_VLAN_CTAG_TX;
6743	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6744			      NETIF_F_TSO | NETIF_F_FRAGLIST |
6745			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6746			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6747	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6748				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6749				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6750
6751	if (tp->version == RTL_VER_01) {
6752		netdev->features &= ~NETIF_F_RXCSUM;
6753		netdev->hw_features &= ~NETIF_F_RXCSUM;
6754	}
6755
6756	if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO) {
6757		switch (le16_to_cpu(udev->descriptor.idProduct)) {
6758		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
6759		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
6760			set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6761		}
6762	}
6763
6764	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6765	    (!strcmp(udev->serial, "000001000000") ||
6766	     !strcmp(udev->serial, "000002000000"))) {
6767		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6768		set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6769	}
6770
6771	netdev->ethtool_ops = &ops;
6772	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6773
6774	/* MTU range: 68 - 1500 or 9194 */
6775	netdev->min_mtu = ETH_MIN_MTU;
6776	switch (tp->version) {
6777	case RTL_VER_01:
6778	case RTL_VER_02:
6779		netdev->max_mtu = ETH_DATA_LEN;
6780		break;
6781	default:
6782		netdev->max_mtu = RTL8153_MAX_MTU;
6783		break;
6784	}
6785
6786	tp->mii.dev = netdev;
6787	tp->mii.mdio_read = read_mii_word;
6788	tp->mii.mdio_write = write_mii_word;
6789	tp->mii.phy_id_mask = 0x3f;
6790	tp->mii.reg_num_mask = 0x1f;
6791	tp->mii.phy_id = R8152_PHY_ID;
6792
6793	tp->autoneg = AUTONEG_ENABLE;
6794	tp->speed = SPEED_100;
6795	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6796			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6797	if (tp->mii.supports_gmii) {
6798		tp->speed = SPEED_1000;
6799		tp->advertising |= RTL_ADVERTISED_1000_FULL;
6800	}
6801	tp->duplex = DUPLEX_FULL;
6802
6803	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6804	tp->rx_pending = 10 * RTL8152_MAX_RX;
6805
6806	intf->needs_remote_wakeup = 1;
6807
6808	if (!rtl_can_wakeup(tp))
6809		__rtl_set_wol(tp, 0);
6810	else
6811		tp->saved_wolopts = __rtl_get_wol(tp);
6812
6813	tp->rtl_ops.init(tp);
6814#if IS_BUILTIN(CONFIG_USB_RTL8152)
6815	/* Retry in case request_firmware() is not ready yet. */
6816	tp->rtl_fw.retry = true;
6817#endif
6818	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6819	set_ethernet_addr(tp);
6820
6821	usb_set_intfdata(intf, tp);
6822	netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6823
6824	ret = register_netdev(netdev);
6825	if (ret != 0) {
6826		netif_err(tp, probe, netdev, "couldn't register the device\n");
6827		goto out1;
6828	}
6829
6830	if (tp->saved_wolopts)
6831		device_set_wakeup_enable(&udev->dev, true);
6832	else
6833		device_set_wakeup_enable(&udev->dev, false);
6834
6835	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6836
6837	return 0;
6838
6839out1:
6840	tasklet_kill(&tp->tx_tl);
6841	usb_set_intfdata(intf, NULL);
6842out:
6843	free_netdev(netdev);
6844	return ret;
6845}
6846
6847static void rtl8152_disconnect(struct usb_interface *intf)
6848{
6849	struct r8152 *tp = usb_get_intfdata(intf);
6850
6851	usb_set_intfdata(intf, NULL);
6852	if (tp) {
6853		rtl_set_unplug(tp);
6854
6855		unregister_netdev(tp->netdev);
6856		tasklet_kill(&tp->tx_tl);
6857		cancel_delayed_work_sync(&tp->hw_phy_work);
6858		tp->rtl_ops.unload(tp);
6859		rtl8152_release_firmware(tp);
6860		free_netdev(tp->netdev);
6861	}
6862}
6863
6864#define REALTEK_USB_DEVICE(vend, prod)	\
6865	.match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6866		       USB_DEVICE_ID_MATCH_INT_CLASS, \
6867	.idVendor = (vend), \
6868	.idProduct = (prod), \
6869	.bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6870}, \
6871{ \
6872	.match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6873		       USB_DEVICE_ID_MATCH_DEVICE, \
6874	.idVendor = (vend), \
6875	.idProduct = (prod), \
6876	.bInterfaceClass = USB_CLASS_COMM, \
6877	.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6878	.bInterfaceProtocol = USB_CDC_PROTO_NONE
6879
6880/* table of devices that work with this driver */
6881static const struct usb_device_id rtl8152_table[] = {
6882	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6883	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6884	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6885	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6886	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6887	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6888	{REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6889	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6890	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6891	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6892	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6893	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6894	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6895	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6896	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6897	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6898	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6899	{REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6900	{}
6901};
6902
6903MODULE_DEVICE_TABLE(usb, rtl8152_table);
6904
6905static struct usb_driver rtl8152_driver = {
6906	.name =		MODULENAME,
6907	.id_table =	rtl8152_table,
6908	.probe =	rtl8152_probe,
6909	.disconnect =	rtl8152_disconnect,
6910	.suspend =	rtl8152_suspend,
6911	.resume =	rtl8152_resume,
6912	.reset_resume =	rtl8152_reset_resume,
6913	.pre_reset =	rtl8152_pre_reset,
6914	.post_reset =	rtl8152_post_reset,
6915	.supports_autosuspend = 1,
6916	.disable_hub_initiated_lpm = 1,
6917};
6918
6919module_usb_driver(rtl8152_driver);
6920
6921MODULE_AUTHOR(DRIVER_AUTHOR);
6922MODULE_DESCRIPTION(DRIVER_DESC);
6923MODULE_LICENSE("GPL");
6924MODULE_VERSION(DRIVER_VERSION);