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1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35#include <linux/module.h>
36#include <linux/delay.h>
37#include <linux/errno.h>
38#include <linux/err.h>
39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/nand_bch.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
48#include <linux/leds.h>
49#include <linux/io.h>
50#include <linux/mtd/partitions.h>
51
52/* Define default oob placement schemes for large and small page devices */
53static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61};
62
63static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69};
70
71static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80};
81
82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94};
95
96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102/*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
123 __func__);
124 ret = -EINVAL;
125 }
126
127 /* Do not allow past end of device */
128 if (ofs + len > mtd->size) {
129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
130 __func__);
131 ret = -EINVAL;
132 }
133
134 return ret;
135}
136
137/**
138 * nand_release_device - [GENERIC] release chip
139 * @mtd: MTD device structure
140 *
141 * Deselect, release chip lock and wake up anyone waiting on the device
142 */
143static void nand_release_device(struct mtd_info *mtd)
144{
145 struct nand_chip *chip = mtd->priv;
146
147 /* De-select the NAND device */
148 chip->select_chip(mtd, -1);
149
150 /* Release the controller and the chip */
151 spin_lock(&chip->controller->lock);
152 chip->controller->active = NULL;
153 chip->state = FL_READY;
154 wake_up(&chip->controller->wq);
155 spin_unlock(&chip->controller->lock);
156}
157
158/**
159 * nand_read_byte - [DEFAULT] read one byte from the chip
160 * @mtd: MTD device structure
161 *
162 * Default read function for 8bit buswith
163 */
164static uint8_t nand_read_byte(struct mtd_info *mtd)
165{
166 struct nand_chip *chip = mtd->priv;
167 return readb(chip->IO_ADDR_R);
168}
169
170/**
171 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
172 * @mtd: MTD device structure
173 *
174 * Default read function for 16bit buswith with
175 * endianess conversion
176 */
177static uint8_t nand_read_byte16(struct mtd_info *mtd)
178{
179 struct nand_chip *chip = mtd->priv;
180 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
181}
182
183/**
184 * nand_read_word - [DEFAULT] read one word from the chip
185 * @mtd: MTD device structure
186 *
187 * Default read function for 16bit buswith without
188 * endianess conversion
189 */
190static u16 nand_read_word(struct mtd_info *mtd)
191{
192 struct nand_chip *chip = mtd->priv;
193 return readw(chip->IO_ADDR_R);
194}
195
196/**
197 * nand_select_chip - [DEFAULT] control CE line
198 * @mtd: MTD device structure
199 * @chipnr: chipnumber to select, -1 for deselect
200 *
201 * Default select function for 1 chip devices.
202 */
203static void nand_select_chip(struct mtd_info *mtd, int chipnr)
204{
205 struct nand_chip *chip = mtd->priv;
206
207 switch (chipnr) {
208 case -1:
209 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
210 break;
211 case 0:
212 break;
213
214 default:
215 BUG();
216 }
217}
218
219/**
220 * nand_write_buf - [DEFAULT] write buffer to chip
221 * @mtd: MTD device structure
222 * @buf: data buffer
223 * @len: number of bytes to write
224 *
225 * Default write function for 8bit buswith
226 */
227static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
228{
229 int i;
230 struct nand_chip *chip = mtd->priv;
231
232 for (i = 0; i < len; i++)
233 writeb(buf[i], chip->IO_ADDR_W);
234}
235
236/**
237 * nand_read_buf - [DEFAULT] read chip data into buffer
238 * @mtd: MTD device structure
239 * @buf: buffer to store date
240 * @len: number of bytes to read
241 *
242 * Default read function for 8bit buswith
243 */
244static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
245{
246 int i;
247 struct nand_chip *chip = mtd->priv;
248
249 for (i = 0; i < len; i++)
250 buf[i] = readb(chip->IO_ADDR_R);
251}
252
253/**
254 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
255 * @mtd: MTD device structure
256 * @buf: buffer containing the data to compare
257 * @len: number of bytes to compare
258 *
259 * Default verify function for 8bit buswith
260 */
261static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
262{
263 int i;
264 struct nand_chip *chip = mtd->priv;
265
266 for (i = 0; i < len; i++)
267 if (buf[i] != readb(chip->IO_ADDR_R))
268 return -EFAULT;
269 return 0;
270}
271
272/**
273 * nand_write_buf16 - [DEFAULT] write buffer to chip
274 * @mtd: MTD device structure
275 * @buf: data buffer
276 * @len: number of bytes to write
277 *
278 * Default write function for 16bit buswith
279 */
280static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
281{
282 int i;
283 struct nand_chip *chip = mtd->priv;
284 u16 *p = (u16 *) buf;
285 len >>= 1;
286
287 for (i = 0; i < len; i++)
288 writew(p[i], chip->IO_ADDR_W);
289
290}
291
292/**
293 * nand_read_buf16 - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
297 *
298 * Default read function for 16bit buswith
299 */
300static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
301{
302 int i;
303 struct nand_chip *chip = mtd->priv;
304 u16 *p = (u16 *) buf;
305 len >>= 1;
306
307 for (i = 0; i < len; i++)
308 p[i] = readw(chip->IO_ADDR_R);
309}
310
311/**
312 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
313 * @mtd: MTD device structure
314 * @buf: buffer containing the data to compare
315 * @len: number of bytes to compare
316 *
317 * Default verify function for 16bit buswith
318 */
319static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
320{
321 int i;
322 struct nand_chip *chip = mtd->priv;
323 u16 *p = (u16 *) buf;
324 len >>= 1;
325
326 for (i = 0; i < len; i++)
327 if (p[i] != readw(chip->IO_ADDR_R))
328 return -EFAULT;
329
330 return 0;
331}
332
333/**
334 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
335 * @mtd: MTD device structure
336 * @ofs: offset from device start
337 * @getchip: 0, if the chip is already selected
338 *
339 * Check, if the block is bad.
340 */
341static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
342{
343 int page, chipnr, res = 0;
344 struct nand_chip *chip = mtd->priv;
345 u16 bad;
346
347 if (chip->options & NAND_BBT_SCANLASTPAGE)
348 ofs += mtd->erasesize - mtd->writesize;
349
350 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351
352 if (getchip) {
353 chipnr = (int)(ofs >> chip->chip_shift);
354
355 nand_get_device(chip, mtd, FL_READING);
356
357 /* Select the NAND device */
358 chip->select_chip(mtd, chipnr);
359 }
360
361 if (chip->options & NAND_BUSWIDTH_16) {
362 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
363 page);
364 bad = cpu_to_le16(chip->read_word(mtd));
365 if (chip->badblockpos & 0x1)
366 bad >>= 8;
367 else
368 bad &= 0xFF;
369 } else {
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
371 bad = chip->read_byte(mtd);
372 }
373
374 if (likely(chip->badblockbits == 8))
375 res = bad != 0xFF;
376 else
377 res = hweight8(bad) < chip->badblockbits;
378
379 if (getchip)
380 nand_release_device(mtd);
381
382 return res;
383}
384
385/**
386 * nand_default_block_markbad - [DEFAULT] mark a block bad
387 * @mtd: MTD device structure
388 * @ofs: offset from device start
389 *
390 * This is the default implementation, which can be overridden by
391 * a hardware specific driver.
392*/
393static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394{
395 struct nand_chip *chip = mtd->priv;
396 uint8_t buf[2] = { 0, 0 };
397 int block, ret, i = 0;
398
399 if (chip->options & NAND_BBT_SCANLASTPAGE)
400 ofs += mtd->erasesize - mtd->writesize;
401
402 /* Get block number */
403 block = (int)(ofs >> chip->bbt_erase_shift);
404 if (chip->bbt)
405 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
406
407 /* Do we have a flash based bad block table ? */
408 if (chip->options & NAND_USE_FLASH_BBT)
409 ret = nand_update_bbt(mtd, ofs);
410 else {
411 nand_get_device(chip, mtd, FL_WRITING);
412
413 /* Write to first two pages and to byte 1 and 6 if necessary.
414 * If we write to more than one location, the first error
415 * encountered quits the procedure. We write two bytes per
416 * location, so we dont have to mess with 16 bit access.
417 */
418 do {
419 chip->ops.len = chip->ops.ooblen = 2;
420 chip->ops.datbuf = NULL;
421 chip->ops.oobbuf = buf;
422 chip->ops.ooboffs = chip->badblockpos & ~0x01;
423
424 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
425
426 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
427 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
428 & ~0x01;
429 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
430 }
431 i++;
432 ofs += mtd->writesize;
433 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
434 i < 2);
435
436 nand_release_device(mtd);
437 }
438 if (!ret)
439 mtd->ecc_stats.badblocks++;
440
441 return ret;
442}
443
444/**
445 * nand_check_wp - [GENERIC] check if the chip is write protected
446 * @mtd: MTD device structure
447 * Check, if the device is write protected
448 *
449 * The function expects, that the device is already selected
450 */
451static int nand_check_wp(struct mtd_info *mtd)
452{
453 struct nand_chip *chip = mtd->priv;
454
455 /* broken xD cards report WP despite being writable */
456 if (chip->options & NAND_BROKEN_XD)
457 return 0;
458
459 /* Check the WP bit */
460 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
461 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
462}
463
464/**
465 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
466 * @mtd: MTD device structure
467 * @ofs: offset from device start
468 * @getchip: 0, if the chip is already selected
469 * @allowbbt: 1, if its allowed to access the bbt area
470 *
471 * Check, if the block is bad. Either by reading the bad block table or
472 * calling of the scan function.
473 */
474static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
475 int allowbbt)
476{
477 struct nand_chip *chip = mtd->priv;
478
479 if (!chip->bbt)
480 return chip->block_bad(mtd, ofs, getchip);
481
482 /* Return info from the table */
483 return nand_isbad_bbt(mtd, ofs, allowbbt);
484}
485
486/**
487 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
488 * @mtd: MTD device structure
489 * @timeo: Timeout
490 *
491 * Helper function for nand_wait_ready used when needing to wait in interrupt
492 * context.
493 */
494static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
495{
496 struct nand_chip *chip = mtd->priv;
497 int i;
498
499 /* Wait for the device to get ready */
500 for (i = 0; i < timeo; i++) {
501 if (chip->dev_ready(mtd))
502 break;
503 touch_softlockup_watchdog();
504 mdelay(1);
505 }
506}
507
508/*
509 * Wait for the ready pin, after a command
510 * The timeout is catched later.
511 */
512void nand_wait_ready(struct mtd_info *mtd)
513{
514 struct nand_chip *chip = mtd->priv;
515 unsigned long timeo = jiffies + 2;
516
517 /* 400ms timeout */
518 if (in_interrupt() || oops_in_progress)
519 return panic_nand_wait_ready(mtd, 400);
520
521 led_trigger_event(nand_led_trigger, LED_FULL);
522 /* wait until command is processed or timeout occures */
523 do {
524 if (chip->dev_ready(mtd))
525 break;
526 touch_softlockup_watchdog();
527 } while (time_before(jiffies, timeo));
528 led_trigger_event(nand_led_trigger, LED_OFF);
529}
530EXPORT_SYMBOL_GPL(nand_wait_ready);
531
532/**
533 * nand_command - [DEFAULT] Send command to NAND device
534 * @mtd: MTD device structure
535 * @command: the command to be sent
536 * @column: the column address for this command, -1 if none
537 * @page_addr: the page address for this command, -1 if none
538 *
539 * Send command to NAND device. This function is used for small page
540 * devices (256/512 Bytes per page)
541 */
542static void nand_command(struct mtd_info *mtd, unsigned int command,
543 int column, int page_addr)
544{
545 register struct nand_chip *chip = mtd->priv;
546 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
547
548 /*
549 * Write out the command to the device.
550 */
551 if (command == NAND_CMD_SEQIN) {
552 int readcmd;
553
554 if (column >= mtd->writesize) {
555 /* OOB area */
556 column -= mtd->writesize;
557 readcmd = NAND_CMD_READOOB;
558 } else if (column < 256) {
559 /* First 256 bytes --> READ0 */
560 readcmd = NAND_CMD_READ0;
561 } else {
562 column -= 256;
563 readcmd = NAND_CMD_READ1;
564 }
565 chip->cmd_ctrl(mtd, readcmd, ctrl);
566 ctrl &= ~NAND_CTRL_CHANGE;
567 }
568 chip->cmd_ctrl(mtd, command, ctrl);
569
570 /*
571 * Address cycle, when necessary
572 */
573 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
574 /* Serially input address */
575 if (column != -1) {
576 /* Adjust columns for 16 bit buswidth */
577 if (chip->options & NAND_BUSWIDTH_16)
578 column >>= 1;
579 chip->cmd_ctrl(mtd, column, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 }
582 if (page_addr != -1) {
583 chip->cmd_ctrl(mtd, page_addr, ctrl);
584 ctrl &= ~NAND_CTRL_CHANGE;
585 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
586 /* One more address cycle for devices > 32MiB */
587 if (chip->chipsize > (32 << 20))
588 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
589 }
590 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
591
592 /*
593 * program and erase have their own busy handlers
594 * status and sequential in needs no delay
595 */
596 switch (command) {
597
598 case NAND_CMD_PAGEPROG:
599 case NAND_CMD_ERASE1:
600 case NAND_CMD_ERASE2:
601 case NAND_CMD_SEQIN:
602 case NAND_CMD_STATUS:
603 return;
604
605 case NAND_CMD_RESET:
606 if (chip->dev_ready)
607 break;
608 udelay(chip->chip_delay);
609 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
610 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
611 chip->cmd_ctrl(mtd,
612 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
613 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
614 ;
615 return;
616
617 /* This applies to read commands */
618 default:
619 /*
620 * If we don't have access to the busy pin, we apply the given
621 * command delay
622 */
623 if (!chip->dev_ready) {
624 udelay(chip->chip_delay);
625 return;
626 }
627 }
628 /* Apply this short delay always to ensure that we do wait tWB in
629 * any case on any machine. */
630 ndelay(100);
631
632 nand_wait_ready(mtd);
633}
634
635/**
636 * nand_command_lp - [DEFAULT] Send command to NAND large page device
637 * @mtd: MTD device structure
638 * @command: the command to be sent
639 * @column: the column address for this command, -1 if none
640 * @page_addr: the page address for this command, -1 if none
641 *
642 * Send command to NAND device. This is the version for the new large page
643 * devices We dont have the separate regions as we have in the small page
644 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
645 */
646static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
647 int column, int page_addr)
648{
649 register struct nand_chip *chip = mtd->priv;
650
651 /* Emulate NAND_CMD_READOOB */
652 if (command == NAND_CMD_READOOB) {
653 column += mtd->writesize;
654 command = NAND_CMD_READ0;
655 }
656
657 /* Command latch cycle */
658 chip->cmd_ctrl(mtd, command & 0xff,
659 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
660
661 if (column != -1 || page_addr != -1) {
662 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
663
664 /* Serially input address */
665 if (column != -1) {
666 /* Adjust columns for 16 bit buswidth */
667 if (chip->options & NAND_BUSWIDTH_16)
668 column >>= 1;
669 chip->cmd_ctrl(mtd, column, ctrl);
670 ctrl &= ~NAND_CTRL_CHANGE;
671 chip->cmd_ctrl(mtd, column >> 8, ctrl);
672 }
673 if (page_addr != -1) {
674 chip->cmd_ctrl(mtd, page_addr, ctrl);
675 chip->cmd_ctrl(mtd, page_addr >> 8,
676 NAND_NCE | NAND_ALE);
677 /* One more address cycle for devices > 128MiB */
678 if (chip->chipsize > (128 << 20))
679 chip->cmd_ctrl(mtd, page_addr >> 16,
680 NAND_NCE | NAND_ALE);
681 }
682 }
683 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
684
685 /*
686 * program and erase have their own busy handlers
687 * status, sequential in, and deplete1 need no delay
688 */
689 switch (command) {
690
691 case NAND_CMD_CACHEDPROG:
692 case NAND_CMD_PAGEPROG:
693 case NAND_CMD_ERASE1:
694 case NAND_CMD_ERASE2:
695 case NAND_CMD_SEQIN:
696 case NAND_CMD_RNDIN:
697 case NAND_CMD_STATUS:
698 case NAND_CMD_DEPLETE1:
699 return;
700
701 /*
702 * read error status commands require only a short delay
703 */
704 case NAND_CMD_STATUS_ERROR:
705 case NAND_CMD_STATUS_ERROR0:
706 case NAND_CMD_STATUS_ERROR1:
707 case NAND_CMD_STATUS_ERROR2:
708 case NAND_CMD_STATUS_ERROR3:
709 udelay(chip->chip_delay);
710 return;
711
712 case NAND_CMD_RESET:
713 if (chip->dev_ready)
714 break;
715 udelay(chip->chip_delay);
716 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
717 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
718 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
719 NAND_NCE | NAND_CTRL_CHANGE);
720 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
721 ;
722 return;
723
724 case NAND_CMD_RNDOUT:
725 /* No ready / busy check necessary */
726 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
727 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
728 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
729 NAND_NCE | NAND_CTRL_CHANGE);
730 return;
731
732 case NAND_CMD_READ0:
733 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
737
738 /* This applies to read commands */
739 default:
740 /*
741 * If we don't have access to the busy pin, we apply the given
742 * command delay
743 */
744 if (!chip->dev_ready) {
745 udelay(chip->chip_delay);
746 return;
747 }
748 }
749
750 /* Apply this short delay always to ensure that we do wait tWB in
751 * any case on any machine. */
752 ndelay(100);
753
754 nand_wait_ready(mtd);
755}
756
757/**
758 * panic_nand_get_device - [GENERIC] Get chip for selected access
759 * @chip: the nand chip descriptor
760 * @mtd: MTD device structure
761 * @new_state: the state which is requested
762 *
763 * Used when in panic, no locks are taken.
764 */
765static void panic_nand_get_device(struct nand_chip *chip,
766 struct mtd_info *mtd, int new_state)
767{
768 /* Hardware controller shared among independend devices */
769 chip->controller->active = chip;
770 chip->state = new_state;
771}
772
773/**
774 * nand_get_device - [GENERIC] Get chip for selected access
775 * @chip: the nand chip descriptor
776 * @mtd: MTD device structure
777 * @new_state: the state which is requested
778 *
779 * Get the device and lock it for exclusive access
780 */
781static int
782nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
783{
784 spinlock_t *lock = &chip->controller->lock;
785 wait_queue_head_t *wq = &chip->controller->wq;
786 DECLARE_WAITQUEUE(wait, current);
787retry:
788 spin_lock(lock);
789
790 /* Hardware controller shared among independent devices */
791 if (!chip->controller->active)
792 chip->controller->active = chip;
793
794 if (chip->controller->active == chip && chip->state == FL_READY) {
795 chip->state = new_state;
796 spin_unlock(lock);
797 return 0;
798 }
799 if (new_state == FL_PM_SUSPENDED) {
800 if (chip->controller->active->state == FL_PM_SUSPENDED) {
801 chip->state = FL_PM_SUSPENDED;
802 spin_unlock(lock);
803 return 0;
804 }
805 }
806 set_current_state(TASK_UNINTERRUPTIBLE);
807 add_wait_queue(wq, &wait);
808 spin_unlock(lock);
809 schedule();
810 remove_wait_queue(wq, &wait);
811 goto retry;
812}
813
814/**
815 * panic_nand_wait - [GENERIC] wait until the command is done
816 * @mtd: MTD device structure
817 * @chip: NAND chip structure
818 * @timeo: Timeout
819 *
820 * Wait for command done. This is a helper function for nand_wait used when
821 * we are in interrupt context. May happen when in panic and trying to write
822 * an oops through mtdoops.
823 */
824static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
825 unsigned long timeo)
826{
827 int i;
828 for (i = 0; i < timeo; i++) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
831 break;
832 } else {
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
834 break;
835 }
836 mdelay(1);
837 }
838}
839
840/**
841 * nand_wait - [DEFAULT] wait until the command is done
842 * @mtd: MTD device structure
843 * @chip: NAND chip structure
844 *
845 * Wait for command done. This applies to erase and program only
846 * Erase can take up to 400ms and program up to 20ms according to
847 * general NAND and SmartMedia specs
848 */
849static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
850{
851
852 unsigned long timeo = jiffies;
853 int status, state = chip->state;
854
855 if (state == FL_ERASING)
856 timeo += (HZ * 400) / 1000;
857 else
858 timeo += (HZ * 20) / 1000;
859
860 led_trigger_event(nand_led_trigger, LED_FULL);
861
862 /* Apply this short delay always to ensure that we do wait tWB in
863 * any case on any machine. */
864 ndelay(100);
865
866 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
867 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
868 else
869 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
870
871 if (in_interrupt() || oops_in_progress)
872 panic_nand_wait(mtd, chip, timeo);
873 else {
874 while (time_before(jiffies, timeo)) {
875 if (chip->dev_ready) {
876 if (chip->dev_ready(mtd))
877 break;
878 } else {
879 if (chip->read_byte(mtd) & NAND_STATUS_READY)
880 break;
881 }
882 cond_resched();
883 }
884 }
885 led_trigger_event(nand_led_trigger, LED_OFF);
886
887 status = (int)chip->read_byte(mtd);
888 return status;
889}
890
891/**
892 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
893 *
894 * @mtd: mtd info
895 * @ofs: offset to start unlock from
896 * @len: length to unlock
897 * @invert: when = 0, unlock the range of blocks within the lower and
898 * upper boundary address
899 * when = 1, unlock the range of blocks outside the boundaries
900 * of the lower and upper boundary address
901 *
902 * return - unlock status
903 */
904static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
905 uint64_t len, int invert)
906{
907 int ret = 0;
908 int status, page;
909 struct nand_chip *chip = mtd->priv;
910
911 /* Submit address of first page to unlock */
912 page = ofs >> chip->page_shift;
913 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
914
915 /* Submit address of last page to unlock */
916 page = (ofs + len) >> chip->page_shift;
917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
918 (page | invert) & chip->pagemask);
919
920 /* Call wait ready function */
921 status = chip->waitfunc(mtd, chip);
922 udelay(1000);
923 /* See if device thinks it succeeded */
924 if (status & 0x01) {
925 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
926 __func__, status);
927 ret = -EIO;
928 }
929
930 return ret;
931}
932
933/**
934 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
935 *
936 * @mtd: mtd info
937 * @ofs: offset to start unlock from
938 * @len: length to unlock
939 *
940 * return - unlock status
941 */
942int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
943{
944 int ret = 0;
945 int chipnr;
946 struct nand_chip *chip = mtd->priv;
947
948 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
949 __func__, (unsigned long long)ofs, len);
950
951 if (check_offs_len(mtd, ofs, len))
952 ret = -EINVAL;
953
954 /* Align to last block address if size addresses end of the device */
955 if (ofs + len == mtd->size)
956 len -= mtd->erasesize;
957
958 nand_get_device(chip, mtd, FL_UNLOCKING);
959
960 /* Shift to get chip number */
961 chipnr = ofs >> chip->chip_shift;
962
963 chip->select_chip(mtd, chipnr);
964
965 /* Check, if it is write protected */
966 if (nand_check_wp(mtd)) {
967 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
968 __func__);
969 ret = -EIO;
970 goto out;
971 }
972
973 ret = __nand_unlock(mtd, ofs, len, 0);
974
975out:
976 nand_release_device(mtd);
977
978 return ret;
979}
980EXPORT_SYMBOL(nand_unlock);
981
982/**
983 * nand_lock - [REPLACEABLE] locks all blocks present in the device
984 *
985 * @mtd: mtd info
986 * @ofs: offset to start unlock from
987 * @len: length to unlock
988 *
989 * return - lock status
990 *
991 * This feature is not supported in many NAND parts. 'Micron' NAND parts
992 * do have this feature, but it allows only to lock all blocks, not for
993 * specified range for block.
994 *
995 * Implementing 'lock' feature by making use of 'unlock', for now.
996 */
997int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
998{
999 int ret = 0;
1000 int chipnr, status, page;
1001 struct nand_chip *chip = mtd->priv;
1002
1003 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1004 __func__, (unsigned long long)ofs, len);
1005
1006 if (check_offs_len(mtd, ofs, len))
1007 ret = -EINVAL;
1008
1009 nand_get_device(chip, mtd, FL_LOCKING);
1010
1011 /* Shift to get chip number */
1012 chipnr = ofs >> chip->chip_shift;
1013
1014 chip->select_chip(mtd, chipnr);
1015
1016 /* Check, if it is write protected */
1017 if (nand_check_wp(mtd)) {
1018 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1019 __func__);
1020 status = MTD_ERASE_FAILED;
1021 ret = -EIO;
1022 goto out;
1023 }
1024
1025 /* Submit address of first page to lock */
1026 page = ofs >> chip->page_shift;
1027 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1028
1029 /* Call wait ready function */
1030 status = chip->waitfunc(mtd, chip);
1031 udelay(1000);
1032 /* See if device thinks it succeeded */
1033 if (status & 0x01) {
1034 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1035 __func__, status);
1036 ret = -EIO;
1037 goto out;
1038 }
1039
1040 ret = __nand_unlock(mtd, ofs, len, 0x1);
1041
1042out:
1043 nand_release_device(mtd);
1044
1045 return ret;
1046}
1047EXPORT_SYMBOL(nand_lock);
1048
1049/**
1050 * nand_read_page_raw - [Intern] read raw page data without ecc
1051 * @mtd: mtd info structure
1052 * @chip: nand chip info structure
1053 * @buf: buffer to store read data
1054 * @page: page number to read
1055 *
1056 * Not for syndrome calculating ecc controllers, which use a special oob layout
1057 */
1058static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1059 uint8_t *buf, int page)
1060{
1061 chip->read_buf(mtd, buf, mtd->writesize);
1062 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1063 return 0;
1064}
1065
1066/**
1067 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1068 * @mtd: mtd info structure
1069 * @chip: nand chip info structure
1070 * @buf: buffer to store read data
1071 * @page: page number to read
1072 *
1073 * We need a special oob layout and handling even when OOB isn't used.
1074 */
1075static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1076 struct nand_chip *chip,
1077 uint8_t *buf, int page)
1078{
1079 int eccsize = chip->ecc.size;
1080 int eccbytes = chip->ecc.bytes;
1081 uint8_t *oob = chip->oob_poi;
1082 int steps, size;
1083
1084 for (steps = chip->ecc.steps; steps > 0; steps--) {
1085 chip->read_buf(mtd, buf, eccsize);
1086 buf += eccsize;
1087
1088 if (chip->ecc.prepad) {
1089 chip->read_buf(mtd, oob, chip->ecc.prepad);
1090 oob += chip->ecc.prepad;
1091 }
1092
1093 chip->read_buf(mtd, oob, eccbytes);
1094 oob += eccbytes;
1095
1096 if (chip->ecc.postpad) {
1097 chip->read_buf(mtd, oob, chip->ecc.postpad);
1098 oob += chip->ecc.postpad;
1099 }
1100 }
1101
1102 size = mtd->oobsize - (oob - chip->oob_poi);
1103 if (size)
1104 chip->read_buf(mtd, oob, size);
1105
1106 return 0;
1107}
1108
1109/**
1110 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1111 * @mtd: mtd info structure
1112 * @chip: nand chip info structure
1113 * @buf: buffer to store read data
1114 * @page: page number to read
1115 */
1116static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1117 uint8_t *buf, int page)
1118{
1119 int i, eccsize = chip->ecc.size;
1120 int eccbytes = chip->ecc.bytes;
1121 int eccsteps = chip->ecc.steps;
1122 uint8_t *p = buf;
1123 uint8_t *ecc_calc = chip->buffers->ecccalc;
1124 uint8_t *ecc_code = chip->buffers->ecccode;
1125 uint32_t *eccpos = chip->ecc.layout->eccpos;
1126
1127 chip->ecc.read_page_raw(mtd, chip, buf, page);
1128
1129 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1130 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1131
1132 for (i = 0; i < chip->ecc.total; i++)
1133 ecc_code[i] = chip->oob_poi[eccpos[i]];
1134
1135 eccsteps = chip->ecc.steps;
1136 p = buf;
1137
1138 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1139 int stat;
1140
1141 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1142 if (stat < 0)
1143 mtd->ecc_stats.failed++;
1144 else
1145 mtd->ecc_stats.corrected += stat;
1146 }
1147 return 0;
1148}
1149
1150/**
1151 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1152 * @mtd: mtd info structure
1153 * @chip: nand chip info structure
1154 * @data_offs: offset of requested data within the page
1155 * @readlen: data length
1156 * @bufpoi: buffer to store read data
1157 */
1158static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1159 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1160{
1161 int start_step, end_step, num_steps;
1162 uint32_t *eccpos = chip->ecc.layout->eccpos;
1163 uint8_t *p;
1164 int data_col_addr, i, gaps = 0;
1165 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1166 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1167 int index = 0;
1168
1169 /* Column address wihin the page aligned to ECC size (256bytes). */
1170 start_step = data_offs / chip->ecc.size;
1171 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1172 num_steps = end_step - start_step + 1;
1173
1174 /* Data size aligned to ECC ecc.size*/
1175 datafrag_len = num_steps * chip->ecc.size;
1176 eccfrag_len = num_steps * chip->ecc.bytes;
1177
1178 data_col_addr = start_step * chip->ecc.size;
1179 /* If we read not a page aligned data */
1180 if (data_col_addr != 0)
1181 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1182
1183 p = bufpoi + data_col_addr;
1184 chip->read_buf(mtd, p, datafrag_len);
1185
1186 /* Calculate ECC */
1187 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1188 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1189
1190 /* The performance is faster if to position offsets
1191 according to ecc.pos. Let make sure here that
1192 there are no gaps in ecc positions */
1193 for (i = 0; i < eccfrag_len - 1; i++) {
1194 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1195 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1196 gaps = 1;
1197 break;
1198 }
1199 }
1200 if (gaps) {
1201 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1202 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1203 } else {
1204 /* send the command to read the particular ecc bytes */
1205 /* take care about buswidth alignment in read_buf */
1206 index = start_step * chip->ecc.bytes;
1207
1208 aligned_pos = eccpos[index] & ~(busw - 1);
1209 aligned_len = eccfrag_len;
1210 if (eccpos[index] & (busw - 1))
1211 aligned_len++;
1212 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1213 aligned_len++;
1214
1215 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1216 mtd->writesize + aligned_pos, -1);
1217 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1218 }
1219
1220 for (i = 0; i < eccfrag_len; i++)
1221 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1222
1223 p = bufpoi + data_col_addr;
1224 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1225 int stat;
1226
1227 stat = chip->ecc.correct(mtd, p,
1228 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1229 if (stat < 0)
1230 mtd->ecc_stats.failed++;
1231 else
1232 mtd->ecc_stats.corrected += stat;
1233 }
1234 return 0;
1235}
1236
1237/**
1238 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1239 * @mtd: mtd info structure
1240 * @chip: nand chip info structure
1241 * @buf: buffer to store read data
1242 * @page: page number to read
1243 *
1244 * Not for syndrome calculating ecc controllers which need a special oob layout
1245 */
1246static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1247 uint8_t *buf, int page)
1248{
1249 int i, eccsize = chip->ecc.size;
1250 int eccbytes = chip->ecc.bytes;
1251 int eccsteps = chip->ecc.steps;
1252 uint8_t *p = buf;
1253 uint8_t *ecc_calc = chip->buffers->ecccalc;
1254 uint8_t *ecc_code = chip->buffers->ecccode;
1255 uint32_t *eccpos = chip->ecc.layout->eccpos;
1256
1257 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1258 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1259 chip->read_buf(mtd, p, eccsize);
1260 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1261 }
1262 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1263
1264 for (i = 0; i < chip->ecc.total; i++)
1265 ecc_code[i] = chip->oob_poi[eccpos[i]];
1266
1267 eccsteps = chip->ecc.steps;
1268 p = buf;
1269
1270 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1271 int stat;
1272
1273 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1274 if (stat < 0)
1275 mtd->ecc_stats.failed++;
1276 else
1277 mtd->ecc_stats.corrected += stat;
1278 }
1279 return 0;
1280}
1281
1282/**
1283 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1284 * @mtd: mtd info structure
1285 * @chip: nand chip info structure
1286 * @buf: buffer to store read data
1287 * @page: page number to read
1288 *
1289 * Hardware ECC for large page chips, require OOB to be read first.
1290 * For this ECC mode, the write_page method is re-used from ECC_HW.
1291 * These methods read/write ECC from the OOB area, unlike the
1292 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1293 * "infix ECC" scheme and reads/writes ECC from the data area, by
1294 * overwriting the NAND manufacturer bad block markings.
1295 */
1296static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1297 struct nand_chip *chip, uint8_t *buf, int page)
1298{
1299 int i, eccsize = chip->ecc.size;
1300 int eccbytes = chip->ecc.bytes;
1301 int eccsteps = chip->ecc.steps;
1302 uint8_t *p = buf;
1303 uint8_t *ecc_code = chip->buffers->ecccode;
1304 uint32_t *eccpos = chip->ecc.layout->eccpos;
1305 uint8_t *ecc_calc = chip->buffers->ecccalc;
1306
1307 /* Read the OOB area first */
1308 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1309 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1310 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1311
1312 for (i = 0; i < chip->ecc.total; i++)
1313 ecc_code[i] = chip->oob_poi[eccpos[i]];
1314
1315 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1316 int stat;
1317
1318 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1319 chip->read_buf(mtd, p, eccsize);
1320 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1321
1322 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1323 if (stat < 0)
1324 mtd->ecc_stats.failed++;
1325 else
1326 mtd->ecc_stats.corrected += stat;
1327 }
1328 return 0;
1329}
1330
1331/**
1332 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1333 * @mtd: mtd info structure
1334 * @chip: nand chip info structure
1335 * @buf: buffer to store read data
1336 * @page: page number to read
1337 *
1338 * The hw generator calculates the error syndrome automatically. Therefor
1339 * we need a special oob layout and handling.
1340 */
1341static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1342 uint8_t *buf, int page)
1343{
1344 int i, eccsize = chip->ecc.size;
1345 int eccbytes = chip->ecc.bytes;
1346 int eccsteps = chip->ecc.steps;
1347 uint8_t *p = buf;
1348 uint8_t *oob = chip->oob_poi;
1349
1350 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1351 int stat;
1352
1353 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1354 chip->read_buf(mtd, p, eccsize);
1355
1356 if (chip->ecc.prepad) {
1357 chip->read_buf(mtd, oob, chip->ecc.prepad);
1358 oob += chip->ecc.prepad;
1359 }
1360
1361 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1362 chip->read_buf(mtd, oob, eccbytes);
1363 stat = chip->ecc.correct(mtd, p, oob, NULL);
1364
1365 if (stat < 0)
1366 mtd->ecc_stats.failed++;
1367 else
1368 mtd->ecc_stats.corrected += stat;
1369
1370 oob += eccbytes;
1371
1372 if (chip->ecc.postpad) {
1373 chip->read_buf(mtd, oob, chip->ecc.postpad);
1374 oob += chip->ecc.postpad;
1375 }
1376 }
1377
1378 /* Calculate remaining oob bytes */
1379 i = mtd->oobsize - (oob - chip->oob_poi);
1380 if (i)
1381 chip->read_buf(mtd, oob, i);
1382
1383 return 0;
1384}
1385
1386/**
1387 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1388 * @chip: nand chip structure
1389 * @oob: oob destination address
1390 * @ops: oob ops structure
1391 * @len: size of oob to transfer
1392 */
1393static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1394 struct mtd_oob_ops *ops, size_t len)
1395{
1396 switch (ops->mode) {
1397
1398 case MTD_OOB_PLACE:
1399 case MTD_OOB_RAW:
1400 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1401 return oob + len;
1402
1403 case MTD_OOB_AUTO: {
1404 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1405 uint32_t boffs = 0, roffs = ops->ooboffs;
1406 size_t bytes = 0;
1407
1408 for (; free->length && len; free++, len -= bytes) {
1409 /* Read request not from offset 0 ? */
1410 if (unlikely(roffs)) {
1411 if (roffs >= free->length) {
1412 roffs -= free->length;
1413 continue;
1414 }
1415 boffs = free->offset + roffs;
1416 bytes = min_t(size_t, len,
1417 (free->length - roffs));
1418 roffs = 0;
1419 } else {
1420 bytes = min_t(size_t, len, free->length);
1421 boffs = free->offset;
1422 }
1423 memcpy(oob, chip->oob_poi + boffs, bytes);
1424 oob += bytes;
1425 }
1426 return oob;
1427 }
1428 default:
1429 BUG();
1430 }
1431 return NULL;
1432}
1433
1434/**
1435 * nand_do_read_ops - [Internal] Read data with ECC
1436 *
1437 * @mtd: MTD device structure
1438 * @from: offset to read from
1439 * @ops: oob ops structure
1440 *
1441 * Internal function. Called with chip held.
1442 */
1443static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1444 struct mtd_oob_ops *ops)
1445{
1446 int chipnr, page, realpage, col, bytes, aligned;
1447 struct nand_chip *chip = mtd->priv;
1448 struct mtd_ecc_stats stats;
1449 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1450 int sndcmd = 1;
1451 int ret = 0;
1452 uint32_t readlen = ops->len;
1453 uint32_t oobreadlen = ops->ooblen;
1454 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1455 mtd->oobavail : mtd->oobsize;
1456
1457 uint8_t *bufpoi, *oob, *buf;
1458
1459 stats = mtd->ecc_stats;
1460
1461 chipnr = (int)(from >> chip->chip_shift);
1462 chip->select_chip(mtd, chipnr);
1463
1464 realpage = (int)(from >> chip->page_shift);
1465 page = realpage & chip->pagemask;
1466
1467 col = (int)(from & (mtd->writesize - 1));
1468
1469 buf = ops->datbuf;
1470 oob = ops->oobbuf;
1471
1472 while (1) {
1473 bytes = min(mtd->writesize - col, readlen);
1474 aligned = (bytes == mtd->writesize);
1475
1476 /* Is the current page in the buffer ? */
1477 if (realpage != chip->pagebuf || oob) {
1478 bufpoi = aligned ? buf : chip->buffers->databuf;
1479
1480 if (likely(sndcmd)) {
1481 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1482 sndcmd = 0;
1483 }
1484
1485 /* Now read the page into the buffer */
1486 if (unlikely(ops->mode == MTD_OOB_RAW))
1487 ret = chip->ecc.read_page_raw(mtd, chip,
1488 bufpoi, page);
1489 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1490 ret = chip->ecc.read_subpage(mtd, chip,
1491 col, bytes, bufpoi);
1492 else
1493 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1494 page);
1495 if (ret < 0)
1496 break;
1497
1498 /* Transfer not aligned data */
1499 if (!aligned) {
1500 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1501 !(mtd->ecc_stats.failed - stats.failed))
1502 chip->pagebuf = realpage;
1503 memcpy(buf, chip->buffers->databuf + col, bytes);
1504 }
1505
1506 buf += bytes;
1507
1508 if (unlikely(oob)) {
1509
1510 int toread = min(oobreadlen, max_oobsize);
1511
1512 if (toread) {
1513 oob = nand_transfer_oob(chip,
1514 oob, ops, toread);
1515 oobreadlen -= toread;
1516 }
1517 }
1518
1519 if (!(chip->options & NAND_NO_READRDY)) {
1520 /*
1521 * Apply delay or wait for ready/busy pin. Do
1522 * this before the AUTOINCR check, so no
1523 * problems arise if a chip which does auto
1524 * increment is marked as NOAUTOINCR by the
1525 * board driver.
1526 */
1527 if (!chip->dev_ready)
1528 udelay(chip->chip_delay);
1529 else
1530 nand_wait_ready(mtd);
1531 }
1532 } else {
1533 memcpy(buf, chip->buffers->databuf + col, bytes);
1534 buf += bytes;
1535 }
1536
1537 readlen -= bytes;
1538
1539 if (!readlen)
1540 break;
1541
1542 /* For subsequent reads align to page boundary. */
1543 col = 0;
1544 /* Increment page address */
1545 realpage++;
1546
1547 page = realpage & chip->pagemask;
1548 /* Check, if we cross a chip boundary */
1549 if (!page) {
1550 chipnr++;
1551 chip->select_chip(mtd, -1);
1552 chip->select_chip(mtd, chipnr);
1553 }
1554
1555 /* Check, if the chip supports auto page increment
1556 * or if we have hit a block boundary.
1557 */
1558 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1559 sndcmd = 1;
1560 }
1561
1562 ops->retlen = ops->len - (size_t) readlen;
1563 if (oob)
1564 ops->oobretlen = ops->ooblen - oobreadlen;
1565
1566 if (ret)
1567 return ret;
1568
1569 if (mtd->ecc_stats.failed - stats.failed)
1570 return -EBADMSG;
1571
1572 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1573}
1574
1575/**
1576 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1577 * @mtd: MTD device structure
1578 * @from: offset to read from
1579 * @len: number of bytes to read
1580 * @retlen: pointer to variable to store the number of read bytes
1581 * @buf: the databuffer to put data
1582 *
1583 * Get hold of the chip and call nand_do_read
1584 */
1585static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1586 size_t *retlen, uint8_t *buf)
1587{
1588 struct nand_chip *chip = mtd->priv;
1589 int ret;
1590
1591 /* Do not allow reads past end of device */
1592 if ((from + len) > mtd->size)
1593 return -EINVAL;
1594 if (!len)
1595 return 0;
1596
1597 nand_get_device(chip, mtd, FL_READING);
1598
1599 chip->ops.len = len;
1600 chip->ops.datbuf = buf;
1601 chip->ops.oobbuf = NULL;
1602
1603 ret = nand_do_read_ops(mtd, from, &chip->ops);
1604
1605 *retlen = chip->ops.retlen;
1606
1607 nand_release_device(mtd);
1608
1609 return ret;
1610}
1611
1612/**
1613 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1614 * @mtd: mtd info structure
1615 * @chip: nand chip info structure
1616 * @page: page number to read
1617 * @sndcmd: flag whether to issue read command or not
1618 */
1619static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1620 int page, int sndcmd)
1621{
1622 if (sndcmd) {
1623 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1624 sndcmd = 0;
1625 }
1626 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1627 return sndcmd;
1628}
1629
1630/**
1631 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1632 * with syndromes
1633 * @mtd: mtd info structure
1634 * @chip: nand chip info structure
1635 * @page: page number to read
1636 * @sndcmd: flag whether to issue read command or not
1637 */
1638static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1639 int page, int sndcmd)
1640{
1641 uint8_t *buf = chip->oob_poi;
1642 int length = mtd->oobsize;
1643 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1644 int eccsize = chip->ecc.size;
1645 uint8_t *bufpoi = buf;
1646 int i, toread, sndrnd = 0, pos;
1647
1648 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1649 for (i = 0; i < chip->ecc.steps; i++) {
1650 if (sndrnd) {
1651 pos = eccsize + i * (eccsize + chunk);
1652 if (mtd->writesize > 512)
1653 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1654 else
1655 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1656 } else
1657 sndrnd = 1;
1658 toread = min_t(int, length, chunk);
1659 chip->read_buf(mtd, bufpoi, toread);
1660 bufpoi += toread;
1661 length -= toread;
1662 }
1663 if (length > 0)
1664 chip->read_buf(mtd, bufpoi, length);
1665
1666 return 1;
1667}
1668
1669/**
1670 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1671 * @mtd: mtd info structure
1672 * @chip: nand chip info structure
1673 * @page: page number to write
1674 */
1675static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1676 int page)
1677{
1678 int status = 0;
1679 const uint8_t *buf = chip->oob_poi;
1680 int length = mtd->oobsize;
1681
1682 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1683 chip->write_buf(mtd, buf, length);
1684 /* Send command to program the OOB data */
1685 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1686
1687 status = chip->waitfunc(mtd, chip);
1688
1689 return status & NAND_STATUS_FAIL ? -EIO : 0;
1690}
1691
1692/**
1693 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1694 * with syndrome - only for large page flash !
1695 * @mtd: mtd info structure
1696 * @chip: nand chip info structure
1697 * @page: page number to write
1698 */
1699static int nand_write_oob_syndrome(struct mtd_info *mtd,
1700 struct nand_chip *chip, int page)
1701{
1702 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1703 int eccsize = chip->ecc.size, length = mtd->oobsize;
1704 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1705 const uint8_t *bufpoi = chip->oob_poi;
1706
1707 /*
1708 * data-ecc-data-ecc ... ecc-oob
1709 * or
1710 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1711 */
1712 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1713 pos = steps * (eccsize + chunk);
1714 steps = 0;
1715 } else
1716 pos = eccsize;
1717
1718 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1719 for (i = 0; i < steps; i++) {
1720 if (sndcmd) {
1721 if (mtd->writesize <= 512) {
1722 uint32_t fill = 0xFFFFFFFF;
1723
1724 len = eccsize;
1725 while (len > 0) {
1726 int num = min_t(int, len, 4);
1727 chip->write_buf(mtd, (uint8_t *)&fill,
1728 num);
1729 len -= num;
1730 }
1731 } else {
1732 pos = eccsize + i * (eccsize + chunk);
1733 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1734 }
1735 } else
1736 sndcmd = 1;
1737 len = min_t(int, length, chunk);
1738 chip->write_buf(mtd, bufpoi, len);
1739 bufpoi += len;
1740 length -= len;
1741 }
1742 if (length > 0)
1743 chip->write_buf(mtd, bufpoi, length);
1744
1745 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1746 status = chip->waitfunc(mtd, chip);
1747
1748 return status & NAND_STATUS_FAIL ? -EIO : 0;
1749}
1750
1751/**
1752 * nand_do_read_oob - [Intern] NAND read out-of-band
1753 * @mtd: MTD device structure
1754 * @from: offset to read from
1755 * @ops: oob operations description structure
1756 *
1757 * NAND read out-of-band data from the spare area
1758 */
1759static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1760 struct mtd_oob_ops *ops)
1761{
1762 int page, realpage, chipnr, sndcmd = 1;
1763 struct nand_chip *chip = mtd->priv;
1764 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1765 int readlen = ops->ooblen;
1766 int len;
1767 uint8_t *buf = ops->oobbuf;
1768
1769 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1770 __func__, (unsigned long long)from, readlen);
1771
1772 if (ops->mode == MTD_OOB_AUTO)
1773 len = chip->ecc.layout->oobavail;
1774 else
1775 len = mtd->oobsize;
1776
1777 if (unlikely(ops->ooboffs >= len)) {
1778 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1779 "outside oob\n", __func__);
1780 return -EINVAL;
1781 }
1782
1783 /* Do not allow reads past end of device */
1784 if (unlikely(from >= mtd->size ||
1785 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1786 (from >> chip->page_shift)) * len)) {
1787 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1788 "of device\n", __func__);
1789 return -EINVAL;
1790 }
1791
1792 chipnr = (int)(from >> chip->chip_shift);
1793 chip->select_chip(mtd, chipnr);
1794
1795 /* Shift to get page */
1796 realpage = (int)(from >> chip->page_shift);
1797 page = realpage & chip->pagemask;
1798
1799 while (1) {
1800 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1801
1802 len = min(len, readlen);
1803 buf = nand_transfer_oob(chip, buf, ops, len);
1804
1805 if (!(chip->options & NAND_NO_READRDY)) {
1806 /*
1807 * Apply delay or wait for ready/busy pin. Do this
1808 * before the AUTOINCR check, so no problems arise if a
1809 * chip which does auto increment is marked as
1810 * NOAUTOINCR by the board driver.
1811 */
1812 if (!chip->dev_ready)
1813 udelay(chip->chip_delay);
1814 else
1815 nand_wait_ready(mtd);
1816 }
1817
1818 readlen -= len;
1819 if (!readlen)
1820 break;
1821
1822 /* Increment page address */
1823 realpage++;
1824
1825 page = realpage & chip->pagemask;
1826 /* Check, if we cross a chip boundary */
1827 if (!page) {
1828 chipnr++;
1829 chip->select_chip(mtd, -1);
1830 chip->select_chip(mtd, chipnr);
1831 }
1832
1833 /* Check, if the chip supports auto page increment
1834 * or if we have hit a block boundary.
1835 */
1836 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1837 sndcmd = 1;
1838 }
1839
1840 ops->oobretlen = ops->ooblen;
1841 return 0;
1842}
1843
1844/**
1845 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1846 * @mtd: MTD device structure
1847 * @from: offset to read from
1848 * @ops: oob operation description structure
1849 *
1850 * NAND read data and/or out-of-band data
1851 */
1852static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1853 struct mtd_oob_ops *ops)
1854{
1855 struct nand_chip *chip = mtd->priv;
1856 int ret = -ENOTSUPP;
1857
1858 ops->retlen = 0;
1859
1860 /* Do not allow reads past end of device */
1861 if (ops->datbuf && (from + ops->len) > mtd->size) {
1862 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1863 "beyond end of device\n", __func__);
1864 return -EINVAL;
1865 }
1866
1867 nand_get_device(chip, mtd, FL_READING);
1868
1869 switch (ops->mode) {
1870 case MTD_OOB_PLACE:
1871 case MTD_OOB_AUTO:
1872 case MTD_OOB_RAW:
1873 break;
1874
1875 default:
1876 goto out;
1877 }
1878
1879 if (!ops->datbuf)
1880 ret = nand_do_read_oob(mtd, from, ops);
1881 else
1882 ret = nand_do_read_ops(mtd, from, ops);
1883
1884out:
1885 nand_release_device(mtd);
1886 return ret;
1887}
1888
1889
1890/**
1891 * nand_write_page_raw - [Intern] raw page write function
1892 * @mtd: mtd info structure
1893 * @chip: nand chip info structure
1894 * @buf: data buffer
1895 *
1896 * Not for syndrome calculating ecc controllers, which use a special oob layout
1897 */
1898static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1899 const uint8_t *buf)
1900{
1901 chip->write_buf(mtd, buf, mtd->writesize);
1902 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1903}
1904
1905/**
1906 * nand_write_page_raw_syndrome - [Intern] raw page write function
1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @buf: data buffer
1910 *
1911 * We need a special oob layout and handling even when ECC isn't checked.
1912 */
1913static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1914 struct nand_chip *chip,
1915 const uint8_t *buf)
1916{
1917 int eccsize = chip->ecc.size;
1918 int eccbytes = chip->ecc.bytes;
1919 uint8_t *oob = chip->oob_poi;
1920 int steps, size;
1921
1922 for (steps = chip->ecc.steps; steps > 0; steps--) {
1923 chip->write_buf(mtd, buf, eccsize);
1924 buf += eccsize;
1925
1926 if (chip->ecc.prepad) {
1927 chip->write_buf(mtd, oob, chip->ecc.prepad);
1928 oob += chip->ecc.prepad;
1929 }
1930
1931 chip->read_buf(mtd, oob, eccbytes);
1932 oob += eccbytes;
1933
1934 if (chip->ecc.postpad) {
1935 chip->write_buf(mtd, oob, chip->ecc.postpad);
1936 oob += chip->ecc.postpad;
1937 }
1938 }
1939
1940 size = mtd->oobsize - (oob - chip->oob_poi);
1941 if (size)
1942 chip->write_buf(mtd, oob, size);
1943}
1944/**
1945 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1946 * @mtd: mtd info structure
1947 * @chip: nand chip info structure
1948 * @buf: data buffer
1949 */
1950static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1951 const uint8_t *buf)
1952{
1953 int i, eccsize = chip->ecc.size;
1954 int eccbytes = chip->ecc.bytes;
1955 int eccsteps = chip->ecc.steps;
1956 uint8_t *ecc_calc = chip->buffers->ecccalc;
1957 const uint8_t *p = buf;
1958 uint32_t *eccpos = chip->ecc.layout->eccpos;
1959
1960 /* Software ecc calculation */
1961 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1962 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1963
1964 for (i = 0; i < chip->ecc.total; i++)
1965 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1966
1967 chip->ecc.write_page_raw(mtd, chip, buf);
1968}
1969
1970/**
1971 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1972 * @mtd: mtd info structure
1973 * @chip: nand chip info structure
1974 * @buf: data buffer
1975 */
1976static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1977 const uint8_t *buf)
1978{
1979 int i, eccsize = chip->ecc.size;
1980 int eccbytes = chip->ecc.bytes;
1981 int eccsteps = chip->ecc.steps;
1982 uint8_t *ecc_calc = chip->buffers->ecccalc;
1983 const uint8_t *p = buf;
1984 uint32_t *eccpos = chip->ecc.layout->eccpos;
1985
1986 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1987 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1988 chip->write_buf(mtd, p, eccsize);
1989 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1990 }
1991
1992 for (i = 0; i < chip->ecc.total; i++)
1993 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1994
1995 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1996}
1997
1998/**
1999 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
2000 * @mtd: mtd info structure
2001 * @chip: nand chip info structure
2002 * @buf: data buffer
2003 *
2004 * The hw generator calculates the error syndrome automatically. Therefor
2005 * we need a special oob layout and handling.
2006 */
2007static void nand_write_page_syndrome(struct mtd_info *mtd,
2008 struct nand_chip *chip, const uint8_t *buf)
2009{
2010 int i, eccsize = chip->ecc.size;
2011 int eccbytes = chip->ecc.bytes;
2012 int eccsteps = chip->ecc.steps;
2013 const uint8_t *p = buf;
2014 uint8_t *oob = chip->oob_poi;
2015
2016 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2017
2018 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2019 chip->write_buf(mtd, p, eccsize);
2020
2021 if (chip->ecc.prepad) {
2022 chip->write_buf(mtd, oob, chip->ecc.prepad);
2023 oob += chip->ecc.prepad;
2024 }
2025
2026 chip->ecc.calculate(mtd, p, oob);
2027 chip->write_buf(mtd, oob, eccbytes);
2028 oob += eccbytes;
2029
2030 if (chip->ecc.postpad) {
2031 chip->write_buf(mtd, oob, chip->ecc.postpad);
2032 oob += chip->ecc.postpad;
2033 }
2034 }
2035
2036 /* Calculate remaining oob bytes */
2037 i = mtd->oobsize - (oob - chip->oob_poi);
2038 if (i)
2039 chip->write_buf(mtd, oob, i);
2040}
2041
2042/**
2043 * nand_write_page - [REPLACEABLE] write one page
2044 * @mtd: MTD device structure
2045 * @chip: NAND chip descriptor
2046 * @buf: the data to write
2047 * @page: page number to write
2048 * @cached: cached programming
2049 * @raw: use _raw version of write_page
2050 */
2051static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2052 const uint8_t *buf, int page, int cached, int raw)
2053{
2054 int status;
2055
2056 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2057
2058 if (unlikely(raw))
2059 chip->ecc.write_page_raw(mtd, chip, buf);
2060 else
2061 chip->ecc.write_page(mtd, chip, buf);
2062
2063 /*
2064 * Cached progamming disabled for now, Not sure if its worth the
2065 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2066 */
2067 cached = 0;
2068
2069 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2070
2071 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2072 status = chip->waitfunc(mtd, chip);
2073 /*
2074 * See if operation failed and additional status checks are
2075 * available
2076 */
2077 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2078 status = chip->errstat(mtd, chip, FL_WRITING, status,
2079 page);
2080
2081 if (status & NAND_STATUS_FAIL)
2082 return -EIO;
2083 } else {
2084 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2085 status = chip->waitfunc(mtd, chip);
2086 }
2087
2088#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2089 /* Send command to read back the data */
2090 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2091
2092 if (chip->verify_buf(mtd, buf, mtd->writesize))
2093 return -EIO;
2094#endif
2095 return 0;
2096}
2097
2098/**
2099 * nand_fill_oob - [Internal] Transfer client buffer to oob
2100 * @chip: nand chip structure
2101 * @oob: oob data buffer
2102 * @len: oob data write length
2103 * @ops: oob ops structure
2104 */
2105static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2106 struct mtd_oob_ops *ops)
2107{
2108 switch (ops->mode) {
2109
2110 case MTD_OOB_PLACE:
2111 case MTD_OOB_RAW:
2112 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2113 return oob + len;
2114
2115 case MTD_OOB_AUTO: {
2116 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2117 uint32_t boffs = 0, woffs = ops->ooboffs;
2118 size_t bytes = 0;
2119
2120 for (; free->length && len; free++, len -= bytes) {
2121 /* Write request not from offset 0 ? */
2122 if (unlikely(woffs)) {
2123 if (woffs >= free->length) {
2124 woffs -= free->length;
2125 continue;
2126 }
2127 boffs = free->offset + woffs;
2128 bytes = min_t(size_t, len,
2129 (free->length - woffs));
2130 woffs = 0;
2131 } else {
2132 bytes = min_t(size_t, len, free->length);
2133 boffs = free->offset;
2134 }
2135 memcpy(chip->oob_poi + boffs, oob, bytes);
2136 oob += bytes;
2137 }
2138 return oob;
2139 }
2140 default:
2141 BUG();
2142 }
2143 return NULL;
2144}
2145
2146#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2147
2148/**
2149 * nand_do_write_ops - [Internal] NAND write with ECC
2150 * @mtd: MTD device structure
2151 * @to: offset to write to
2152 * @ops: oob operations description structure
2153 *
2154 * NAND write with ECC
2155 */
2156static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2157 struct mtd_oob_ops *ops)
2158{
2159 int chipnr, realpage, page, blockmask, column;
2160 struct nand_chip *chip = mtd->priv;
2161 uint32_t writelen = ops->len;
2162
2163 uint32_t oobwritelen = ops->ooblen;
2164 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2165 mtd->oobavail : mtd->oobsize;
2166
2167 uint8_t *oob = ops->oobbuf;
2168 uint8_t *buf = ops->datbuf;
2169 int ret, subpage;
2170
2171 ops->retlen = 0;
2172 if (!writelen)
2173 return 0;
2174
2175 /* reject writes, which are not page aligned */
2176 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2177 printk(KERN_NOTICE "%s: Attempt to write not "
2178 "page aligned data\n", __func__);
2179 return -EINVAL;
2180 }
2181
2182 column = to & (mtd->writesize - 1);
2183 subpage = column || (writelen & (mtd->writesize - 1));
2184
2185 if (subpage && oob)
2186 return -EINVAL;
2187
2188 chipnr = (int)(to >> chip->chip_shift);
2189 chip->select_chip(mtd, chipnr);
2190
2191 /* Check, if it is write protected */
2192 if (nand_check_wp(mtd))
2193 return -EIO;
2194
2195 realpage = (int)(to >> chip->page_shift);
2196 page = realpage & chip->pagemask;
2197 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2198
2199 /* Invalidate the page cache, when we write to the cached page */
2200 if (to <= (chip->pagebuf << chip->page_shift) &&
2201 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2202 chip->pagebuf = -1;
2203
2204 /* If we're not given explicit OOB data, let it be 0xFF */
2205 if (likely(!oob))
2206 memset(chip->oob_poi, 0xff, mtd->oobsize);
2207
2208 /* Don't allow multipage oob writes with offset */
2209 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2210 return -EINVAL;
2211
2212 while (1) {
2213 int bytes = mtd->writesize;
2214 int cached = writelen > bytes && page != blockmask;
2215 uint8_t *wbuf = buf;
2216
2217 /* Partial page write ? */
2218 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2219 cached = 0;
2220 bytes = min_t(int, bytes - column, (int) writelen);
2221 chip->pagebuf = -1;
2222 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2223 memcpy(&chip->buffers->databuf[column], buf, bytes);
2224 wbuf = chip->buffers->databuf;
2225 }
2226
2227 if (unlikely(oob)) {
2228 size_t len = min(oobwritelen, oobmaxlen);
2229 oob = nand_fill_oob(chip, oob, len, ops);
2230 oobwritelen -= len;
2231 }
2232
2233 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2234 (ops->mode == MTD_OOB_RAW));
2235 if (ret)
2236 break;
2237
2238 writelen -= bytes;
2239 if (!writelen)
2240 break;
2241
2242 column = 0;
2243 buf += bytes;
2244 realpage++;
2245
2246 page = realpage & chip->pagemask;
2247 /* Check, if we cross a chip boundary */
2248 if (!page) {
2249 chipnr++;
2250 chip->select_chip(mtd, -1);
2251 chip->select_chip(mtd, chipnr);
2252 }
2253 }
2254
2255 ops->retlen = ops->len - writelen;
2256 if (unlikely(oob))
2257 ops->oobretlen = ops->ooblen;
2258 return ret;
2259}
2260
2261/**
2262 * panic_nand_write - [MTD Interface] NAND write with ECC
2263 * @mtd: MTD device structure
2264 * @to: offset to write to
2265 * @len: number of bytes to write
2266 * @retlen: pointer to variable to store the number of written bytes
2267 * @buf: the data to write
2268 *
2269 * NAND write with ECC. Used when performing writes in interrupt context, this
2270 * may for example be called by mtdoops when writing an oops while in panic.
2271 */
2272static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2273 size_t *retlen, const uint8_t *buf)
2274{
2275 struct nand_chip *chip = mtd->priv;
2276 int ret;
2277
2278 /* Do not allow reads past end of device */
2279 if ((to + len) > mtd->size)
2280 return -EINVAL;
2281 if (!len)
2282 return 0;
2283
2284 /* Wait for the device to get ready. */
2285 panic_nand_wait(mtd, chip, 400);
2286
2287 /* Grab the device. */
2288 panic_nand_get_device(chip, mtd, FL_WRITING);
2289
2290 chip->ops.len = len;
2291 chip->ops.datbuf = (uint8_t *)buf;
2292 chip->ops.oobbuf = NULL;
2293
2294 ret = nand_do_write_ops(mtd, to, &chip->ops);
2295
2296 *retlen = chip->ops.retlen;
2297 return ret;
2298}
2299
2300/**
2301 * nand_write - [MTD Interface] NAND write with ECC
2302 * @mtd: MTD device structure
2303 * @to: offset to write to
2304 * @len: number of bytes to write
2305 * @retlen: pointer to variable to store the number of written bytes
2306 * @buf: the data to write
2307 *
2308 * NAND write with ECC
2309 */
2310static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2311 size_t *retlen, const uint8_t *buf)
2312{
2313 struct nand_chip *chip = mtd->priv;
2314 int ret;
2315
2316 /* Do not allow reads past end of device */
2317 if ((to + len) > mtd->size)
2318 return -EINVAL;
2319 if (!len)
2320 return 0;
2321
2322 nand_get_device(chip, mtd, FL_WRITING);
2323
2324 chip->ops.len = len;
2325 chip->ops.datbuf = (uint8_t *)buf;
2326 chip->ops.oobbuf = NULL;
2327
2328 ret = nand_do_write_ops(mtd, to, &chip->ops);
2329
2330 *retlen = chip->ops.retlen;
2331
2332 nand_release_device(mtd);
2333
2334 return ret;
2335}
2336
2337/**
2338 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2339 * @mtd: MTD device structure
2340 * @to: offset to write to
2341 * @ops: oob operation description structure
2342 *
2343 * NAND write out-of-band
2344 */
2345static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2346 struct mtd_oob_ops *ops)
2347{
2348 int chipnr, page, status, len;
2349 struct nand_chip *chip = mtd->priv;
2350
2351 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2352 __func__, (unsigned int)to, (int)ops->ooblen);
2353
2354 if (ops->mode == MTD_OOB_AUTO)
2355 len = chip->ecc.layout->oobavail;
2356 else
2357 len = mtd->oobsize;
2358
2359 /* Do not allow write past end of page */
2360 if ((ops->ooboffs + ops->ooblen) > len) {
2361 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2362 "past end of page\n", __func__);
2363 return -EINVAL;
2364 }
2365
2366 if (unlikely(ops->ooboffs >= len)) {
2367 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2368 "write outside oob\n", __func__);
2369 return -EINVAL;
2370 }
2371
2372 /* Do not allow write past end of device */
2373 if (unlikely(to >= mtd->size ||
2374 ops->ooboffs + ops->ooblen >
2375 ((mtd->size >> chip->page_shift) -
2376 (to >> chip->page_shift)) * len)) {
2377 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2378 "end of device\n", __func__);
2379 return -EINVAL;
2380 }
2381
2382 chipnr = (int)(to >> chip->chip_shift);
2383 chip->select_chip(mtd, chipnr);
2384
2385 /* Shift to get page */
2386 page = (int)(to >> chip->page_shift);
2387
2388 /*
2389 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2390 * of my DiskOnChip 2000 test units) will clear the whole data page too
2391 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2392 * it in the doc2000 driver in August 1999. dwmw2.
2393 */
2394 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2395
2396 /* Check, if it is write protected */
2397 if (nand_check_wp(mtd))
2398 return -EROFS;
2399
2400 /* Invalidate the page cache, if we write to the cached page */
2401 if (page == chip->pagebuf)
2402 chip->pagebuf = -1;
2403
2404 memset(chip->oob_poi, 0xff, mtd->oobsize);
2405 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2406 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2407 memset(chip->oob_poi, 0xff, mtd->oobsize);
2408
2409 if (status)
2410 return status;
2411
2412 ops->oobretlen = ops->ooblen;
2413
2414 return 0;
2415}
2416
2417/**
2418 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2419 * @mtd: MTD device structure
2420 * @to: offset to write to
2421 * @ops: oob operation description structure
2422 */
2423static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2424 struct mtd_oob_ops *ops)
2425{
2426 struct nand_chip *chip = mtd->priv;
2427 int ret = -ENOTSUPP;
2428
2429 ops->retlen = 0;
2430
2431 /* Do not allow writes past end of device */
2432 if (ops->datbuf && (to + ops->len) > mtd->size) {
2433 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2434 "end of device\n", __func__);
2435 return -EINVAL;
2436 }
2437
2438 nand_get_device(chip, mtd, FL_WRITING);
2439
2440 switch (ops->mode) {
2441 case MTD_OOB_PLACE:
2442 case MTD_OOB_AUTO:
2443 case MTD_OOB_RAW:
2444 break;
2445
2446 default:
2447 goto out;
2448 }
2449
2450 if (!ops->datbuf)
2451 ret = nand_do_write_oob(mtd, to, ops);
2452 else
2453 ret = nand_do_write_ops(mtd, to, ops);
2454
2455out:
2456 nand_release_device(mtd);
2457 return ret;
2458}
2459
2460/**
2461 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2462 * @mtd: MTD device structure
2463 * @page: the page address of the block which will be erased
2464 *
2465 * Standard erase command for NAND chips
2466 */
2467static void single_erase_cmd(struct mtd_info *mtd, int page)
2468{
2469 struct nand_chip *chip = mtd->priv;
2470 /* Send commands to erase a block */
2471 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2472 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2473}
2474
2475/**
2476 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2477 * @mtd: MTD device structure
2478 * @page: the page address of the block which will be erased
2479 *
2480 * AND multi block erase command function
2481 * Erase 4 consecutive blocks
2482 */
2483static void multi_erase_cmd(struct mtd_info *mtd, int page)
2484{
2485 struct nand_chip *chip = mtd->priv;
2486 /* Send commands to erase a block */
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2488 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2489 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2490 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2491 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2492}
2493
2494/**
2495 * nand_erase - [MTD Interface] erase block(s)
2496 * @mtd: MTD device structure
2497 * @instr: erase instruction
2498 *
2499 * Erase one ore more blocks
2500 */
2501static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2502{
2503 return nand_erase_nand(mtd, instr, 0);
2504}
2505
2506#define BBT_PAGE_MASK 0xffffff3f
2507/**
2508 * nand_erase_nand - [Internal] erase block(s)
2509 * @mtd: MTD device structure
2510 * @instr: erase instruction
2511 * @allowbbt: allow erasing the bbt area
2512 *
2513 * Erase one ore more blocks
2514 */
2515int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2516 int allowbbt)
2517{
2518 int page, status, pages_per_block, ret, chipnr;
2519 struct nand_chip *chip = mtd->priv;
2520 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2521 unsigned int bbt_masked_page = 0xffffffff;
2522 loff_t len;
2523
2524 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2525 __func__, (unsigned long long)instr->addr,
2526 (unsigned long long)instr->len);
2527
2528 if (check_offs_len(mtd, instr->addr, instr->len))
2529 return -EINVAL;
2530
2531 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2532
2533 /* Grab the lock and see if the device is available */
2534 nand_get_device(chip, mtd, FL_ERASING);
2535
2536 /* Shift to get first page */
2537 page = (int)(instr->addr >> chip->page_shift);
2538 chipnr = (int)(instr->addr >> chip->chip_shift);
2539
2540 /* Calculate pages in each block */
2541 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2542
2543 /* Select the NAND device */
2544 chip->select_chip(mtd, chipnr);
2545
2546 /* Check, if it is write protected */
2547 if (nand_check_wp(mtd)) {
2548 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2549 __func__);
2550 instr->state = MTD_ERASE_FAILED;
2551 goto erase_exit;
2552 }
2553
2554 /*
2555 * If BBT requires refresh, set the BBT page mask to see if the BBT
2556 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2557 * can not be matched. This is also done when the bbt is actually
2558 * erased to avoid recusrsive updates
2559 */
2560 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2561 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2562
2563 /* Loop through the pages */
2564 len = instr->len;
2565
2566 instr->state = MTD_ERASING;
2567
2568 while (len) {
2569 /*
2570 * heck if we have a bad block, we do not erase bad blocks !
2571 */
2572 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2573 chip->page_shift, 0, allowbbt)) {
2574 printk(KERN_WARNING "%s: attempt to erase a bad block "
2575 "at page 0x%08x\n", __func__, page);
2576 instr->state = MTD_ERASE_FAILED;
2577 goto erase_exit;
2578 }
2579
2580 /*
2581 * Invalidate the page cache, if we erase the block which
2582 * contains the current cached page
2583 */
2584 if (page <= chip->pagebuf && chip->pagebuf <
2585 (page + pages_per_block))
2586 chip->pagebuf = -1;
2587
2588 chip->erase_cmd(mtd, page & chip->pagemask);
2589
2590 status = chip->waitfunc(mtd, chip);
2591
2592 /*
2593 * See if operation failed and additional status checks are
2594 * available
2595 */
2596 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2597 status = chip->errstat(mtd, chip, FL_ERASING,
2598 status, page);
2599
2600 /* See if block erase succeeded */
2601 if (status & NAND_STATUS_FAIL) {
2602 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2603 "page 0x%08x\n", __func__, page);
2604 instr->state = MTD_ERASE_FAILED;
2605 instr->fail_addr =
2606 ((loff_t)page << chip->page_shift);
2607 goto erase_exit;
2608 }
2609
2610 /*
2611 * If BBT requires refresh, set the BBT rewrite flag to the
2612 * page being erased
2613 */
2614 if (bbt_masked_page != 0xffffffff &&
2615 (page & BBT_PAGE_MASK) == bbt_masked_page)
2616 rewrite_bbt[chipnr] =
2617 ((loff_t)page << chip->page_shift);
2618
2619 /* Increment page address and decrement length */
2620 len -= (1 << chip->phys_erase_shift);
2621 page += pages_per_block;
2622
2623 /* Check, if we cross a chip boundary */
2624 if (len && !(page & chip->pagemask)) {
2625 chipnr++;
2626 chip->select_chip(mtd, -1);
2627 chip->select_chip(mtd, chipnr);
2628
2629 /*
2630 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2631 * page mask to see if this BBT should be rewritten
2632 */
2633 if (bbt_masked_page != 0xffffffff &&
2634 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2635 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2636 BBT_PAGE_MASK;
2637 }
2638 }
2639 instr->state = MTD_ERASE_DONE;
2640
2641erase_exit:
2642
2643 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2644
2645 /* Deselect and wake up anyone waiting on the device */
2646 nand_release_device(mtd);
2647
2648 /* Do call back function */
2649 if (!ret)
2650 mtd_erase_callback(instr);
2651
2652 /*
2653 * If BBT requires refresh and erase was successful, rewrite any
2654 * selected bad block tables
2655 */
2656 if (bbt_masked_page == 0xffffffff || ret)
2657 return ret;
2658
2659 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2660 if (!rewrite_bbt[chipnr])
2661 continue;
2662 /* update the BBT for chip */
2663 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2664 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2665 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2666 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2667 }
2668
2669 /* Return more or less happy */
2670 return ret;
2671}
2672
2673/**
2674 * nand_sync - [MTD Interface] sync
2675 * @mtd: MTD device structure
2676 *
2677 * Sync is actually a wait for chip ready function
2678 */
2679static void nand_sync(struct mtd_info *mtd)
2680{
2681 struct nand_chip *chip = mtd->priv;
2682
2683 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2684
2685 /* Grab the lock and see if the device is available */
2686 nand_get_device(chip, mtd, FL_SYNCING);
2687 /* Release it and go back */
2688 nand_release_device(mtd);
2689}
2690
2691/**
2692 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2693 * @mtd: MTD device structure
2694 * @offs: offset relative to mtd start
2695 */
2696static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2697{
2698 /* Check for invalid offset */
2699 if (offs > mtd->size)
2700 return -EINVAL;
2701
2702 return nand_block_checkbad(mtd, offs, 1, 0);
2703}
2704
2705/**
2706 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2707 * @mtd: MTD device structure
2708 * @ofs: offset relative to mtd start
2709 */
2710static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2711{
2712 struct nand_chip *chip = mtd->priv;
2713 int ret;
2714
2715 ret = nand_block_isbad(mtd, ofs);
2716 if (ret) {
2717 /* If it was bad already, return success and do nothing. */
2718 if (ret > 0)
2719 return 0;
2720 return ret;
2721 }
2722
2723 return chip->block_markbad(mtd, ofs);
2724}
2725
2726/**
2727 * nand_suspend - [MTD Interface] Suspend the NAND flash
2728 * @mtd: MTD device structure
2729 */
2730static int nand_suspend(struct mtd_info *mtd)
2731{
2732 struct nand_chip *chip = mtd->priv;
2733
2734 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2735}
2736
2737/**
2738 * nand_resume - [MTD Interface] Resume the NAND flash
2739 * @mtd: MTD device structure
2740 */
2741static void nand_resume(struct mtd_info *mtd)
2742{
2743 struct nand_chip *chip = mtd->priv;
2744
2745 if (chip->state == FL_PM_SUSPENDED)
2746 nand_release_device(mtd);
2747 else
2748 printk(KERN_ERR "%s called for a chip which is not "
2749 "in suspended state\n", __func__);
2750}
2751
2752/*
2753 * Set default functions
2754 */
2755static void nand_set_defaults(struct nand_chip *chip, int busw)
2756{
2757 /* check for proper chip_delay setup, set 20us if not */
2758 if (!chip->chip_delay)
2759 chip->chip_delay = 20;
2760
2761 /* check, if a user supplied command function given */
2762 if (chip->cmdfunc == NULL)
2763 chip->cmdfunc = nand_command;
2764
2765 /* check, if a user supplied wait function given */
2766 if (chip->waitfunc == NULL)
2767 chip->waitfunc = nand_wait;
2768
2769 if (!chip->select_chip)
2770 chip->select_chip = nand_select_chip;
2771 if (!chip->read_byte)
2772 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2773 if (!chip->read_word)
2774 chip->read_word = nand_read_word;
2775 if (!chip->block_bad)
2776 chip->block_bad = nand_block_bad;
2777 if (!chip->block_markbad)
2778 chip->block_markbad = nand_default_block_markbad;
2779 if (!chip->write_buf)
2780 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2781 if (!chip->read_buf)
2782 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2783 if (!chip->verify_buf)
2784 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2785 if (!chip->scan_bbt)
2786 chip->scan_bbt = nand_default_bbt;
2787
2788 if (!chip->controller) {
2789 chip->controller = &chip->hwcontrol;
2790 spin_lock_init(&chip->controller->lock);
2791 init_waitqueue_head(&chip->controller->wq);
2792 }
2793
2794}
2795
2796/*
2797 * sanitize ONFI strings so we can safely print them
2798 */
2799static void sanitize_string(uint8_t *s, size_t len)
2800{
2801 ssize_t i;
2802
2803 /* null terminate */
2804 s[len - 1] = 0;
2805
2806 /* remove non printable chars */
2807 for (i = 0; i < len - 1; i++) {
2808 if (s[i] < ' ' || s[i] > 127)
2809 s[i] = '?';
2810 }
2811
2812 /* remove trailing spaces */
2813 strim(s);
2814}
2815
2816static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2817{
2818 int i;
2819 while (len--) {
2820 crc ^= *p++ << 8;
2821 for (i = 0; i < 8; i++)
2822 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2823 }
2824
2825 return crc;
2826}
2827
2828/*
2829 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2830 */
2831static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2832 int busw)
2833{
2834 struct nand_onfi_params *p = &chip->onfi_params;
2835 int i;
2836 int val;
2837
2838 /* try ONFI for unknow chip or LP */
2839 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2840 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2841 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2842 return 0;
2843
2844 printk(KERN_INFO "ONFI flash detected\n");
2845 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2846 for (i = 0; i < 3; i++) {
2847 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2848 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2849 le16_to_cpu(p->crc)) {
2850 printk(KERN_INFO "ONFI param page %d valid\n", i);
2851 break;
2852 }
2853 }
2854
2855 if (i == 3)
2856 return 0;
2857
2858 /* check version */
2859 val = le16_to_cpu(p->revision);
2860 if (val & (1 << 5))
2861 chip->onfi_version = 23;
2862 else if (val & (1 << 4))
2863 chip->onfi_version = 22;
2864 else if (val & (1 << 3))
2865 chip->onfi_version = 21;
2866 else if (val & (1 << 2))
2867 chip->onfi_version = 20;
2868 else if (val & (1 << 1))
2869 chip->onfi_version = 10;
2870 else
2871 chip->onfi_version = 0;
2872
2873 if (!chip->onfi_version) {
2874 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2875 __func__, val);
2876 return 0;
2877 }
2878
2879 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2880 sanitize_string(p->model, sizeof(p->model));
2881 if (!mtd->name)
2882 mtd->name = p->model;
2883 mtd->writesize = le32_to_cpu(p->byte_per_page);
2884 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2885 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2886 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2887 busw = 0;
2888 if (le16_to_cpu(p->features) & 1)
2889 busw = NAND_BUSWIDTH_16;
2890
2891 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2892 chip->options |= (NAND_NO_READRDY |
2893 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2894
2895 return 1;
2896}
2897
2898/*
2899 * Get the flash and manufacturer id and lookup if the type is supported
2900 */
2901static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2902 struct nand_chip *chip,
2903 int busw,
2904 int *maf_id, int *dev_id,
2905 struct nand_flash_dev *type)
2906{
2907 int i, maf_idx;
2908 u8 id_data[8];
2909 int ret;
2910
2911 /* Select the device */
2912 chip->select_chip(mtd, 0);
2913
2914 /*
2915 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2916 * after power-up
2917 */
2918 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2919
2920 /* Send the command for reading device ID */
2921 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2922
2923 /* Read manufacturer and device IDs */
2924 *maf_id = chip->read_byte(mtd);
2925 *dev_id = chip->read_byte(mtd);
2926
2927 /* Try again to make sure, as some systems the bus-hold or other
2928 * interface concerns can cause random data which looks like a
2929 * possibly credible NAND flash to appear. If the two results do
2930 * not match, ignore the device completely.
2931 */
2932
2933 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2934
2935 for (i = 0; i < 2; i++)
2936 id_data[i] = chip->read_byte(mtd);
2937
2938 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2939 printk(KERN_INFO "%s: second ID read did not match "
2940 "%02x,%02x against %02x,%02x\n", __func__,
2941 *maf_id, *dev_id, id_data[0], id_data[1]);
2942 return ERR_PTR(-ENODEV);
2943 }
2944
2945 if (!type)
2946 type = nand_flash_ids;
2947
2948 for (; type->name != NULL; type++)
2949 if (*dev_id == type->id)
2950 break;
2951
2952 chip->onfi_version = 0;
2953 if (!type->name || !type->pagesize) {
2954 /* Check is chip is ONFI compliant */
2955 ret = nand_flash_detect_onfi(mtd, chip, busw);
2956 if (ret)
2957 goto ident_done;
2958 }
2959
2960 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2961
2962 /* Read entire ID string */
2963
2964 for (i = 0; i < 8; i++)
2965 id_data[i] = chip->read_byte(mtd);
2966
2967 if (!type->name)
2968 return ERR_PTR(-ENODEV);
2969
2970 if (!mtd->name)
2971 mtd->name = type->name;
2972
2973 chip->chipsize = (uint64_t)type->chipsize << 20;
2974
2975 if (!type->pagesize && chip->init_size) {
2976 /* set the pagesize, oobsize, erasesize by the driver*/
2977 busw = chip->init_size(mtd, chip, id_data);
2978 } else if (!type->pagesize) {
2979 int extid;
2980 /* The 3rd id byte holds MLC / multichip data */
2981 chip->cellinfo = id_data[2];
2982 /* The 4th id byte is the important one */
2983 extid = id_data[3];
2984
2985 /*
2986 * Field definitions are in the following datasheets:
2987 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2988 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2989 *
2990 * Check for wraparound + Samsung ID + nonzero 6th byte
2991 * to decide what to do.
2992 */
2993 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2994 id_data[0] == NAND_MFR_SAMSUNG &&
2995 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2996 id_data[5] != 0x00) {
2997 /* Calc pagesize */
2998 mtd->writesize = 2048 << (extid & 0x03);
2999 extid >>= 2;
3000 /* Calc oobsize */
3001 switch (extid & 0x03) {
3002 case 1:
3003 mtd->oobsize = 128;
3004 break;
3005 case 2:
3006 mtd->oobsize = 218;
3007 break;
3008 case 3:
3009 mtd->oobsize = 400;
3010 break;
3011 default:
3012 mtd->oobsize = 436;
3013 break;
3014 }
3015 extid >>= 2;
3016 /* Calc blocksize */
3017 mtd->erasesize = (128 * 1024) <<
3018 (((extid >> 1) & 0x04) | (extid & 0x03));
3019 busw = 0;
3020 } else {
3021 /* Calc pagesize */
3022 mtd->writesize = 1024 << (extid & 0x03);
3023 extid >>= 2;
3024 /* Calc oobsize */
3025 mtd->oobsize = (8 << (extid & 0x01)) *
3026 (mtd->writesize >> 9);
3027 extid >>= 2;
3028 /* Calc blocksize. Blocksize is multiples of 64KiB */
3029 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3030 extid >>= 2;
3031 /* Get buswidth information */
3032 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3033 }
3034 } else {
3035 /*
3036 * Old devices have chip data hardcoded in the device id table
3037 */
3038 mtd->erasesize = type->erasesize;
3039 mtd->writesize = type->pagesize;
3040 mtd->oobsize = mtd->writesize / 32;
3041 busw = type->options & NAND_BUSWIDTH_16;
3042
3043 /*
3044 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3045 * some Spansion chips have erasesize that conflicts with size
3046 * listed in nand_ids table
3047 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3048 */
3049 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3050 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3051 id_data[7] == 0x00 && mtd->writesize == 512) {
3052 mtd->erasesize = 128 * 1024;
3053 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3054 }
3055 }
3056 /* Get chip options, preserve non chip based options */
3057 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3058 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3059
3060 /* Check if chip is a not a samsung device. Do not clear the
3061 * options for chips which are not having an extended id.
3062 */
3063 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3064 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3065ident_done:
3066
3067 /*
3068 * Set chip as a default. Board drivers can override it, if necessary
3069 */
3070 chip->options |= NAND_NO_AUTOINCR;
3071
3072 /* Try to identify manufacturer */
3073 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3074 if (nand_manuf_ids[maf_idx].id == *maf_id)
3075 break;
3076 }
3077
3078 /*
3079 * Check, if buswidth is correct. Hardware drivers should set
3080 * chip correct !
3081 */
3082 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3083 printk(KERN_INFO "NAND device: Manufacturer ID:"
3084 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3085 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3086 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3087 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3088 busw ? 16 : 8);
3089 return ERR_PTR(-EINVAL);
3090 }
3091
3092 /* Calculate the address shift from the page size */
3093 chip->page_shift = ffs(mtd->writesize) - 1;
3094 /* Convert chipsize to number of pages per chip -1. */
3095 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3096
3097 chip->bbt_erase_shift = chip->phys_erase_shift =
3098 ffs(mtd->erasesize) - 1;
3099 if (chip->chipsize & 0xffffffff)
3100 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3101 else {
3102 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3103 chip->chip_shift += 32 - 1;
3104 }
3105
3106 chip->badblockbits = 8;
3107
3108 /* Set the bad block position */
3109 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3110 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3111 else
3112 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3113
3114 /*
3115 * Bad block marker is stored in the last page of each block
3116 * on Samsung and Hynix MLC devices; stored in first two pages
3117 * of each block on Micron devices with 2KiB pages and on
3118 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3119 * only the first page.
3120 */
3121 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3122 (*maf_id == NAND_MFR_SAMSUNG ||
3123 *maf_id == NAND_MFR_HYNIX))
3124 chip->options |= NAND_BBT_SCANLASTPAGE;
3125 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3126 (*maf_id == NAND_MFR_SAMSUNG ||
3127 *maf_id == NAND_MFR_HYNIX ||
3128 *maf_id == NAND_MFR_TOSHIBA ||
3129 *maf_id == NAND_MFR_AMD)) ||
3130 (mtd->writesize == 2048 &&
3131 *maf_id == NAND_MFR_MICRON))
3132 chip->options |= NAND_BBT_SCAN2NDPAGE;
3133
3134 /*
3135 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3136 */
3137 if (!(busw & NAND_BUSWIDTH_16) &&
3138 *maf_id == NAND_MFR_STMICRO &&
3139 mtd->writesize == 2048) {
3140 chip->options |= NAND_BBT_SCANBYTE1AND6;
3141 chip->badblockpos = 0;
3142 }
3143
3144 /* Check for AND chips with 4 page planes */
3145 if (chip->options & NAND_4PAGE_ARRAY)
3146 chip->erase_cmd = multi_erase_cmd;
3147 else
3148 chip->erase_cmd = single_erase_cmd;
3149
3150 /* Do not replace user supplied command function ! */
3151 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3152 chip->cmdfunc = nand_command_lp;
3153
3154 /* TODO onfi flash name */
3155 printk(KERN_INFO "NAND device: Manufacturer ID:"
3156 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3157 nand_manuf_ids[maf_idx].name,
3158 chip->onfi_version ? chip->onfi_params.model : type->name);
3159
3160 return type;
3161}
3162
3163/**
3164 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3165 * @mtd: MTD device structure
3166 * @maxchips: Number of chips to scan for
3167 * @table: Alternative NAND ID table
3168 *
3169 * This is the first phase of the normal nand_scan() function. It
3170 * reads the flash ID and sets up MTD fields accordingly.
3171 *
3172 * The mtd->owner field must be set to the module of the caller.
3173 */
3174int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3175 struct nand_flash_dev *table)
3176{
3177 int i, busw, nand_maf_id, nand_dev_id;
3178 struct nand_chip *chip = mtd->priv;
3179 struct nand_flash_dev *type;
3180
3181 /* Get buswidth to select the correct functions */
3182 busw = chip->options & NAND_BUSWIDTH_16;
3183 /* Set the default functions */
3184 nand_set_defaults(chip, busw);
3185
3186 /* Read the flash type */
3187 type = nand_get_flash_type(mtd, chip, busw,
3188 &nand_maf_id, &nand_dev_id, table);
3189
3190 if (IS_ERR(type)) {
3191 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3192 printk(KERN_WARNING "No NAND device found.\n");
3193 chip->select_chip(mtd, -1);
3194 return PTR_ERR(type);
3195 }
3196
3197 /* Check for a chip array */
3198 for (i = 1; i < maxchips; i++) {
3199 chip->select_chip(mtd, i);
3200 /* See comment in nand_get_flash_type for reset */
3201 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3202 /* Send the command for reading device ID */
3203 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3204 /* Read manufacturer and device IDs */
3205 if (nand_maf_id != chip->read_byte(mtd) ||
3206 nand_dev_id != chip->read_byte(mtd))
3207 break;
3208 }
3209 if (i > 1)
3210 printk(KERN_INFO "%d NAND chips detected\n", i);
3211
3212 /* Store the number of chips and calc total size for mtd */
3213 chip->numchips = i;
3214 mtd->size = i * chip->chipsize;
3215
3216 return 0;
3217}
3218EXPORT_SYMBOL(nand_scan_ident);
3219
3220
3221/**
3222 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3223 * @mtd: MTD device structure
3224 *
3225 * This is the second phase of the normal nand_scan() function. It
3226 * fills out all the uninitialized function pointers with the defaults
3227 * and scans for a bad block table if appropriate.
3228 */
3229int nand_scan_tail(struct mtd_info *mtd)
3230{
3231 int i;
3232 struct nand_chip *chip = mtd->priv;
3233
3234 if (!(chip->options & NAND_OWN_BUFFERS))
3235 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3236 if (!chip->buffers)
3237 return -ENOMEM;
3238
3239 /* Set the internal oob buffer location, just after the page data */
3240 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3241
3242 /*
3243 * If no default placement scheme is given, select an appropriate one
3244 */
3245 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3246 switch (mtd->oobsize) {
3247 case 8:
3248 chip->ecc.layout = &nand_oob_8;
3249 break;
3250 case 16:
3251 chip->ecc.layout = &nand_oob_16;
3252 break;
3253 case 64:
3254 chip->ecc.layout = &nand_oob_64;
3255 break;
3256 case 128:
3257 chip->ecc.layout = &nand_oob_128;
3258 break;
3259 default:
3260 printk(KERN_WARNING "No oob scheme defined for "
3261 "oobsize %d\n", mtd->oobsize);
3262 BUG();
3263 }
3264 }
3265
3266 if (!chip->write_page)
3267 chip->write_page = nand_write_page;
3268
3269 /*
3270 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3271 * selected and we have 256 byte pagesize fallback to software ECC
3272 */
3273
3274 switch (chip->ecc.mode) {
3275 case NAND_ECC_HW_OOB_FIRST:
3276 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3277 if (!chip->ecc.calculate || !chip->ecc.correct ||
3278 !chip->ecc.hwctl) {
3279 printk(KERN_WARNING "No ECC functions supplied; "
3280 "Hardware ECC not possible\n");
3281 BUG();
3282 }
3283 if (!chip->ecc.read_page)
3284 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3285
3286 case NAND_ECC_HW:
3287 /* Use standard hwecc read page function ? */
3288 if (!chip->ecc.read_page)
3289 chip->ecc.read_page = nand_read_page_hwecc;
3290 if (!chip->ecc.write_page)
3291 chip->ecc.write_page = nand_write_page_hwecc;
3292 if (!chip->ecc.read_page_raw)
3293 chip->ecc.read_page_raw = nand_read_page_raw;
3294 if (!chip->ecc.write_page_raw)
3295 chip->ecc.write_page_raw = nand_write_page_raw;
3296 if (!chip->ecc.read_oob)
3297 chip->ecc.read_oob = nand_read_oob_std;
3298 if (!chip->ecc.write_oob)
3299 chip->ecc.write_oob = nand_write_oob_std;
3300
3301 case NAND_ECC_HW_SYNDROME:
3302 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3303 !chip->ecc.hwctl) &&
3304 (!chip->ecc.read_page ||
3305 chip->ecc.read_page == nand_read_page_hwecc ||
3306 !chip->ecc.write_page ||
3307 chip->ecc.write_page == nand_write_page_hwecc)) {
3308 printk(KERN_WARNING "No ECC functions supplied; "
3309 "Hardware ECC not possible\n");
3310 BUG();
3311 }
3312 /* Use standard syndrome read/write page function ? */
3313 if (!chip->ecc.read_page)
3314 chip->ecc.read_page = nand_read_page_syndrome;
3315 if (!chip->ecc.write_page)
3316 chip->ecc.write_page = nand_write_page_syndrome;
3317 if (!chip->ecc.read_page_raw)
3318 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3319 if (!chip->ecc.write_page_raw)
3320 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3321 if (!chip->ecc.read_oob)
3322 chip->ecc.read_oob = nand_read_oob_syndrome;
3323 if (!chip->ecc.write_oob)
3324 chip->ecc.write_oob = nand_write_oob_syndrome;
3325
3326 if (mtd->writesize >= chip->ecc.size)
3327 break;
3328 printk(KERN_WARNING "%d byte HW ECC not possible on "
3329 "%d byte page size, fallback to SW ECC\n",
3330 chip->ecc.size, mtd->writesize);
3331 chip->ecc.mode = NAND_ECC_SOFT;
3332
3333 case NAND_ECC_SOFT:
3334 chip->ecc.calculate = nand_calculate_ecc;
3335 chip->ecc.correct = nand_correct_data;
3336 chip->ecc.read_page = nand_read_page_swecc;
3337 chip->ecc.read_subpage = nand_read_subpage;
3338 chip->ecc.write_page = nand_write_page_swecc;
3339 chip->ecc.read_page_raw = nand_read_page_raw;
3340 chip->ecc.write_page_raw = nand_write_page_raw;
3341 chip->ecc.read_oob = nand_read_oob_std;
3342 chip->ecc.write_oob = nand_write_oob_std;
3343 if (!chip->ecc.size)
3344 chip->ecc.size = 256;
3345 chip->ecc.bytes = 3;
3346 break;
3347
3348 case NAND_ECC_SOFT_BCH:
3349 if (!mtd_nand_has_bch()) {
3350 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3351 BUG();
3352 }
3353 chip->ecc.calculate = nand_bch_calculate_ecc;
3354 chip->ecc.correct = nand_bch_correct_data;
3355 chip->ecc.read_page = nand_read_page_swecc;
3356 chip->ecc.read_subpage = nand_read_subpage;
3357 chip->ecc.write_page = nand_write_page_swecc;
3358 chip->ecc.read_page_raw = nand_read_page_raw;
3359 chip->ecc.write_page_raw = nand_write_page_raw;
3360 chip->ecc.read_oob = nand_read_oob_std;
3361 chip->ecc.write_oob = nand_write_oob_std;
3362 /*
3363 * Board driver should supply ecc.size and ecc.bytes values to
3364 * select how many bits are correctable; see nand_bch_init()
3365 * for details.
3366 * Otherwise, default to 4 bits for large page devices
3367 */
3368 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3369 chip->ecc.size = 512;
3370 chip->ecc.bytes = 7;
3371 }
3372 chip->ecc.priv = nand_bch_init(mtd,
3373 chip->ecc.size,
3374 chip->ecc.bytes,
3375 &chip->ecc.layout);
3376 if (!chip->ecc.priv) {
3377 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3378 BUG();
3379 }
3380 break;
3381
3382 case NAND_ECC_NONE:
3383 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3384 "This is not recommended !!\n");
3385 chip->ecc.read_page = nand_read_page_raw;
3386 chip->ecc.write_page = nand_write_page_raw;
3387 chip->ecc.read_oob = nand_read_oob_std;
3388 chip->ecc.read_page_raw = nand_read_page_raw;
3389 chip->ecc.write_page_raw = nand_write_page_raw;
3390 chip->ecc.write_oob = nand_write_oob_std;
3391 chip->ecc.size = mtd->writesize;
3392 chip->ecc.bytes = 0;
3393 break;
3394
3395 default:
3396 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3397 chip->ecc.mode);
3398 BUG();
3399 }
3400
3401 /*
3402 * The number of bytes available for a client to place data into
3403 * the out of band area
3404 */
3405 chip->ecc.layout->oobavail = 0;
3406 for (i = 0; chip->ecc.layout->oobfree[i].length
3407 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3408 chip->ecc.layout->oobavail +=
3409 chip->ecc.layout->oobfree[i].length;
3410 mtd->oobavail = chip->ecc.layout->oobavail;
3411
3412 /*
3413 * Set the number of read / write steps for one page depending on ECC
3414 * mode
3415 */
3416 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3417 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3418 printk(KERN_WARNING "Invalid ecc parameters\n");
3419 BUG();
3420 }
3421 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3422
3423 /*
3424 * Allow subpage writes up to ecc.steps. Not possible for MLC
3425 * FLASH.
3426 */
3427 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3428 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3429 switch (chip->ecc.steps) {
3430 case 2:
3431 mtd->subpage_sft = 1;
3432 break;
3433 case 4:
3434 case 8:
3435 case 16:
3436 mtd->subpage_sft = 2;
3437 break;
3438 }
3439 }
3440 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3441
3442 /* Initialize state */
3443 chip->state = FL_READY;
3444
3445 /* De-select the device */
3446 chip->select_chip(mtd, -1);
3447
3448 /* Invalidate the pagebuffer reference */
3449 chip->pagebuf = -1;
3450
3451 /* Fill in remaining MTD driver data */
3452 mtd->type = MTD_NANDFLASH;
3453 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3454 MTD_CAP_NANDFLASH;
3455 mtd->erase = nand_erase;
3456 mtd->point = NULL;
3457 mtd->unpoint = NULL;
3458 mtd->read = nand_read;
3459 mtd->write = nand_write;
3460 mtd->panic_write = panic_nand_write;
3461 mtd->read_oob = nand_read_oob;
3462 mtd->write_oob = nand_write_oob;
3463 mtd->sync = nand_sync;
3464 mtd->lock = NULL;
3465 mtd->unlock = NULL;
3466 mtd->suspend = nand_suspend;
3467 mtd->resume = nand_resume;
3468 mtd->block_isbad = nand_block_isbad;
3469 mtd->block_markbad = nand_block_markbad;
3470 mtd->writebufsize = mtd->writesize;
3471
3472 /* propagate ecc.layout to mtd_info */
3473 mtd->ecclayout = chip->ecc.layout;
3474
3475 /* Check, if we should skip the bad block table scan */
3476 if (chip->options & NAND_SKIP_BBTSCAN)
3477 return 0;
3478
3479 /* Build bad block table */
3480 return chip->scan_bbt(mtd);
3481}
3482EXPORT_SYMBOL(nand_scan_tail);
3483
3484/* is_module_text_address() isn't exported, and it's mostly a pointless
3485 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3486 * to call us from in-kernel code if the core NAND support is modular. */
3487#ifdef MODULE
3488#define caller_is_module() (1)
3489#else
3490#define caller_is_module() \
3491 is_module_text_address((unsigned long)__builtin_return_address(0))
3492#endif
3493
3494/**
3495 * nand_scan - [NAND Interface] Scan for the NAND device
3496 * @mtd: MTD device structure
3497 * @maxchips: Number of chips to scan for
3498 *
3499 * This fills out all the uninitialized function pointers
3500 * with the defaults.
3501 * The flash ID is read and the mtd/chip structures are
3502 * filled with the appropriate values.
3503 * The mtd->owner field must be set to the module of the caller
3504 *
3505 */
3506int nand_scan(struct mtd_info *mtd, int maxchips)
3507{
3508 int ret;
3509
3510 /* Many callers got this wrong, so check for it for a while... */
3511 if (!mtd->owner && caller_is_module()) {
3512 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3513 __func__);
3514 BUG();
3515 }
3516
3517 ret = nand_scan_ident(mtd, maxchips, NULL);
3518 if (!ret)
3519 ret = nand_scan_tail(mtd);
3520 return ret;
3521}
3522EXPORT_SYMBOL(nand_scan);
3523
3524/**
3525 * nand_release - [NAND Interface] Free resources held by the NAND device
3526 * @mtd: MTD device structure
3527*/
3528void nand_release(struct mtd_info *mtd)
3529{
3530 struct nand_chip *chip = mtd->priv;
3531
3532 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3533 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3534
3535 mtd_device_unregister(mtd);
3536
3537 /* Free bad block table memory */
3538 kfree(chip->bbt);
3539 if (!(chip->options & NAND_OWN_BUFFERS))
3540 kfree(chip->buffers);
3541
3542 /* Free bad block descriptor memory */
3543 if (chip->badblock_pattern && chip->badblock_pattern->options
3544 & NAND_BBT_DYNAMICSTRUCT)
3545 kfree(chip->badblock_pattern);
3546}
3547EXPORT_SYMBOL_GPL(nand_release);
3548
3549static int __init nand_base_init(void)
3550{
3551 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3552 return 0;
3553}
3554
3555static void __exit nand_base_exit(void)
3556{
3557 led_trigger_unregister_simple(nand_led_trigger);
3558}
3559
3560module_init(nand_base_init);
3561module_exit(nand_base_exit);
3562
3563MODULE_LICENSE("GPL");
3564MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3565MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3566MODULE_DESCRIPTION("Generic NAND flash driver code");