Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
4 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
5 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
7 *
8 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
9 */
10
11#include <linux/module.h>
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17#include <linux/ide.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21
22#define DRV_NAME "ns87415"
23
24#ifdef CONFIG_SUPERIO
25/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
26 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
27 * which use the integrated NS87514 cell for CD-ROM support.
28 * i.e we have to support for CD-ROM installs.
29 * See drivers/parisc/superio.c for more gory details.
30 */
31#include <asm/superio.h>
32
33#define SUPERIO_IDE_MAX_RETRIES 25
34
35/* Because of a defect in Super I/O, all reads of the PCI DMA status
36 * registers, IDE status register and the IDE select register need to be
37 * retried
38 */
39static u8 superio_ide_inb (unsigned long port)
40{
41 u8 tmp;
42 int retries = SUPERIO_IDE_MAX_RETRIES;
43
44 /* printk(" [ reading port 0x%x with retry ] ", port); */
45
46 do {
47 tmp = inb(port);
48 if (tmp == 0)
49 udelay(50);
50 } while (tmp == 0 && retries-- > 0);
51
52 return tmp;
53}
54
55static u8 superio_read_status(ide_hwif_t *hwif)
56{
57 return superio_ide_inb(hwif->io_ports.status_addr);
58}
59
60static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
61{
62 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
63}
64
65static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
66 u8 valid)
67{
68 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
69
70 if (valid & IDE_VALID_ERROR)
71 tf->error = inb(io_ports->feature_addr);
72 if (valid & IDE_VALID_NSECT)
73 tf->nsect = inb(io_ports->nsect_addr);
74 if (valid & IDE_VALID_LBAL)
75 tf->lbal = inb(io_ports->lbal_addr);
76 if (valid & IDE_VALID_LBAM)
77 tf->lbam = inb(io_ports->lbam_addr);
78 if (valid & IDE_VALID_LBAH)
79 tf->lbah = inb(io_ports->lbah_addr);
80 if (valid & IDE_VALID_DEVICE)
81 tf->device = superio_ide_inb(io_ports->device_addr);
82}
83
84static void ns87415_dev_select(ide_drive_t *drive);
85
86static const struct ide_tp_ops superio_tp_ops = {
87 .exec_command = ide_exec_command,
88 .read_status = superio_read_status,
89 .read_altstatus = ide_read_altstatus,
90 .write_devctl = ide_write_devctl,
91
92 .dev_select = ns87415_dev_select,
93 .tf_load = ide_tf_load,
94 .tf_read = superio_tf_read,
95
96 .input_data = ide_input_data,
97 .output_data = ide_output_data,
98};
99
100static void superio_init_iops(struct hwif_s *hwif)
101{
102 struct pci_dev *pdev = to_pci_dev(hwif->dev);
103 u32 dma_stat;
104 u8 port = hwif->channel, tmp;
105
106 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
107
108 /* Clear error/interrupt, enable dma */
109 tmp = superio_ide_inb(dma_stat);
110 outb(tmp | 0x66, dma_stat);
111}
112#else
113#define superio_dma_sff_read_status ide_dma_sff_read_status
114#endif
115
116static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
117
118/*
119 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
120 * the IRQ associated with the port,
121 * and selects either PIO or DMA handshaking for the next I/O operation.
122 */
123static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
124{
125 ide_hwif_t *hwif = drive->hwif;
126 struct pci_dev *dev = to_pci_dev(hwif->dev);
127 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
128 unsigned long flags;
129
130 local_irq_save(flags);
131 new = *old;
132
133 /* Adjust IRQ enable bit */
134 bit = 1 << (8 + hwif->channel);
135
136 if (drive->dev_flags & IDE_DFLAG_PRESENT)
137 new &= ~bit;
138 else
139 new |= bit;
140
141 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
142 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
143 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
144 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
145
146 if (new != *old) {
147 unsigned char stat;
148
149 /*
150 * Don't change DMA engine settings while Write Buffers
151 * are busy.
152 */
153 (void) pci_read_config_byte(dev, 0x43, &stat);
154 while (stat & 0x03) {
155 udelay(1);
156 (void) pci_read_config_byte(dev, 0x43, &stat);
157 }
158
159 *old = new;
160 (void) pci_write_config_dword(dev, 0x40, new);
161
162 /*
163 * And let things settle...
164 */
165 udelay(10);
166 }
167
168 local_irq_restore(flags);
169}
170
171static void ns87415_dev_select(ide_drive_t *drive)
172{
173 ns87415_prepare_drive(drive,
174 !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
175
176 outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
177}
178
179static void ns87415_dma_start(ide_drive_t *drive)
180{
181 ns87415_prepare_drive(drive, 1);
182 ide_dma_start(drive);
183}
184
185static int ns87415_dma_end(ide_drive_t *drive)
186{
187 ide_hwif_t *hwif = drive->hwif;
188 u8 dma_stat = 0, dma_cmd = 0;
189
190 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
191 /* get DMA command mode */
192 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
193 /* stop DMA */
194 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
195 /* from ERRATA: clear the INTR & ERROR bits */
196 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
197 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
198
199 ns87415_prepare_drive(drive, 0);
200
201 /* verify good DMA status */
202 return (dma_stat & 7) != 4;
203}
204
205static void init_hwif_ns87415 (ide_hwif_t *hwif)
206{
207 struct pci_dev *dev = to_pci_dev(hwif->dev);
208 unsigned int ctrl, using_inta;
209 u8 progif;
210#ifdef __sparc_v9__
211 int timeout;
212 u8 stat;
213#endif
214
215 /*
216 * We cannot probe for IRQ: both ports share common IRQ on INTA.
217 * Also, leave IRQ masked during drive probing, to prevent infinite
218 * interrupts from a potentially floating INTA..
219 *
220 * IRQs get unmasked in dev_select() when drive is first used.
221 */
222 (void) pci_read_config_dword(dev, 0x40, &ctrl);
223 (void) pci_read_config_byte(dev, 0x09, &progif);
224 /* is irq in "native" mode? */
225 using_inta = progif & (1 << (hwif->channel << 1));
226 if (!using_inta)
227 using_inta = ctrl & (1 << (4 + hwif->channel));
228 if (hwif->mate) {
229 hwif->select_data = hwif->mate->select_data;
230 } else {
231 hwif->select_data = (unsigned long)
232 &ns87415_control[ns87415_count++];
233 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
234 if (using_inta)
235 ctrl &= ~(1 << 6); /* unmask INTA */
236 *((unsigned int *)hwif->select_data) = ctrl;
237 (void) pci_write_config_dword(dev, 0x40, ctrl);
238
239 /*
240 * Set prefetch size to 512 bytes for both ports,
241 * but don't turn on/off prefetching here.
242 */
243 pci_write_config_byte(dev, 0x55, 0xee);
244
245#ifdef __sparc_v9__
246 /*
247 * XXX: Reset the device, if we don't it will not respond to
248 * dev_select() properly during first ide_probe_port().
249 */
250 timeout = 10000;
251 outb(12, hwif->io_ports.ctl_addr);
252 udelay(10);
253 outb(8, hwif->io_ports.ctl_addr);
254 do {
255 udelay(50);
256 stat = hwif->tp_ops->read_status(hwif);
257 if (stat == 0xff)
258 break;
259 } while ((stat & ATA_BUSY) && --timeout);
260#endif
261 }
262
263 if (!using_inta)
264 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
265
266 if (!hwif->dma_base)
267 return;
268
269 outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
270}
271
272static const struct ide_tp_ops ns87415_tp_ops = {
273 .exec_command = ide_exec_command,
274 .read_status = ide_read_status,
275 .read_altstatus = ide_read_altstatus,
276 .write_devctl = ide_write_devctl,
277
278 .dev_select = ns87415_dev_select,
279 .tf_load = ide_tf_load,
280 .tf_read = ide_tf_read,
281
282 .input_data = ide_input_data,
283 .output_data = ide_output_data,
284};
285
286static const struct ide_dma_ops ns87415_dma_ops = {
287 .dma_host_set = ide_dma_host_set,
288 .dma_setup = ide_dma_setup,
289 .dma_start = ns87415_dma_start,
290 .dma_end = ns87415_dma_end,
291 .dma_test_irq = ide_dma_test_irq,
292 .dma_lost_irq = ide_dma_lost_irq,
293 .dma_timer_expiry = ide_dma_sff_timer_expiry,
294 .dma_sff_read_status = superio_dma_sff_read_status,
295};
296
297static const struct ide_port_info ns87415_chipset = {
298 .name = DRV_NAME,
299 .init_hwif = init_hwif_ns87415,
300 .tp_ops = &ns87415_tp_ops,
301 .dma_ops = &ns87415_dma_ops,
302 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
303 IDE_HFLAG_NO_ATAPI_DMA,
304};
305
306static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
307{
308 struct ide_port_info d = ns87415_chipset;
309
310#ifdef CONFIG_SUPERIO
311 if (PCI_SLOT(dev->devfn) == 0xE) {
312 /* Built-in - assume it's under superio. */
313 d.init_iops = superio_init_iops;
314 d.tp_ops = &superio_tp_ops;
315 }
316#endif
317 return ide_pci_init_one(dev, &d, NULL);
318}
319
320static const struct pci_device_id ns87415_pci_tbl[] = {
321 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
322 { 0, },
323};
324MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
325
326static struct pci_driver ns87415_pci_driver = {
327 .name = "NS87415_IDE",
328 .id_table = ns87415_pci_tbl,
329 .probe = ns87415_init_one,
330 .remove = ide_pci_remove,
331 .suspend = ide_pci_suspend,
332 .resume = ide_pci_resume,
333};
334
335static int __init ns87415_ide_init(void)
336{
337 return ide_pci_register_driver(&ns87415_pci_driver);
338}
339
340static void __exit ns87415_ide_exit(void)
341{
342 pci_unregister_driver(&ns87415_pci_driver);
343}
344
345module_init(ns87415_ide_init);
346module_exit(ns87415_ide_exit);
347
348MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
349MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
350MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
6 *
7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
8 */
9
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
21#define DRV_NAME "ns87415"
22
23#ifdef CONFIG_SUPERIO
24/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
26 * which use the integrated NS87514 cell for CD-ROM support.
27 * i.e we have to support for CD-ROM installs.
28 * See drivers/parisc/superio.c for more gory details.
29 */
30#include <asm/superio.h>
31
32#define SUPERIO_IDE_MAX_RETRIES 25
33
34/* Because of a defect in Super I/O, all reads of the PCI DMA status
35 * registers, IDE status register and the IDE select register need to be
36 * retried
37 */
38static u8 superio_ide_inb (unsigned long port)
39{
40 u8 tmp;
41 int retries = SUPERIO_IDE_MAX_RETRIES;
42
43 /* printk(" [ reading port 0x%x with retry ] ", port); */
44
45 do {
46 tmp = inb(port);
47 if (tmp == 0)
48 udelay(50);
49 } while (tmp == 0 && retries-- > 0);
50
51 return tmp;
52}
53
54static u8 superio_read_status(ide_hwif_t *hwif)
55{
56 return superio_ide_inb(hwif->io_ports.status_addr);
57}
58
59static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
60{
61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
62}
63
64static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
65 u8 valid)
66{
67 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
68
69 if (valid & IDE_VALID_ERROR)
70 tf->error = inb(io_ports->feature_addr);
71 if (valid & IDE_VALID_NSECT)
72 tf->nsect = inb(io_ports->nsect_addr);
73 if (valid & IDE_VALID_LBAL)
74 tf->lbal = inb(io_ports->lbal_addr);
75 if (valid & IDE_VALID_LBAM)
76 tf->lbam = inb(io_ports->lbam_addr);
77 if (valid & IDE_VALID_LBAH)
78 tf->lbah = inb(io_ports->lbah_addr);
79 if (valid & IDE_VALID_DEVICE)
80 tf->device = superio_ide_inb(io_ports->device_addr);
81}
82
83static void ns87415_dev_select(ide_drive_t *drive);
84
85static const struct ide_tp_ops superio_tp_ops = {
86 .exec_command = ide_exec_command,
87 .read_status = superio_read_status,
88 .read_altstatus = ide_read_altstatus,
89 .write_devctl = ide_write_devctl,
90
91 .dev_select = ns87415_dev_select,
92 .tf_load = ide_tf_load,
93 .tf_read = superio_tf_read,
94
95 .input_data = ide_input_data,
96 .output_data = ide_output_data,
97};
98
99static void __devinit superio_init_iops(struct hwif_s *hwif)
100{
101 struct pci_dev *pdev = to_pci_dev(hwif->dev);
102 u32 dma_stat;
103 u8 port = hwif->channel, tmp;
104
105 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
106
107 /* Clear error/interrupt, enable dma */
108 tmp = superio_ide_inb(dma_stat);
109 outb(tmp | 0x66, dma_stat);
110}
111#else
112#define superio_dma_sff_read_status ide_dma_sff_read_status
113#endif
114
115static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
116
117/*
118 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
119 * the IRQ associated with the port,
120 * and selects either PIO or DMA handshaking for the next I/O operation.
121 */
122static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
123{
124 ide_hwif_t *hwif = drive->hwif;
125 struct pci_dev *dev = to_pci_dev(hwif->dev);
126 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
127 unsigned long flags;
128
129 local_irq_save(flags);
130 new = *old;
131
132 /* Adjust IRQ enable bit */
133 bit = 1 << (8 + hwif->channel);
134
135 if (drive->dev_flags & IDE_DFLAG_PRESENT)
136 new &= ~bit;
137 else
138 new |= bit;
139
140 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
141 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
142 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
143 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
144
145 if (new != *old) {
146 unsigned char stat;
147
148 /*
149 * Don't change DMA engine settings while Write Buffers
150 * are busy.
151 */
152 (void) pci_read_config_byte(dev, 0x43, &stat);
153 while (stat & 0x03) {
154 udelay(1);
155 (void) pci_read_config_byte(dev, 0x43, &stat);
156 }
157
158 *old = new;
159 (void) pci_write_config_dword(dev, 0x40, new);
160
161 /*
162 * And let things settle...
163 */
164 udelay(10);
165 }
166
167 local_irq_restore(flags);
168}
169
170static void ns87415_dev_select(ide_drive_t *drive)
171{
172 ns87415_prepare_drive(drive,
173 !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
174
175 outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
176}
177
178static void ns87415_dma_start(ide_drive_t *drive)
179{
180 ns87415_prepare_drive(drive, 1);
181 ide_dma_start(drive);
182}
183
184static int ns87415_dma_end(ide_drive_t *drive)
185{
186 ide_hwif_t *hwif = drive->hwif;
187 u8 dma_stat = 0, dma_cmd = 0;
188
189 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
190 /* get DMA command mode */
191 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
192 /* stop DMA */
193 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
194 /* from ERRATA: clear the INTR & ERROR bits */
195 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
196 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
197
198 ns87415_prepare_drive(drive, 0);
199
200 /* verify good DMA status */
201 return (dma_stat & 7) != 4;
202}
203
204static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
205{
206 struct pci_dev *dev = to_pci_dev(hwif->dev);
207 unsigned int ctrl, using_inta;
208 u8 progif;
209#ifdef __sparc_v9__
210 int timeout;
211 u8 stat;
212#endif
213
214 /*
215 * We cannot probe for IRQ: both ports share common IRQ on INTA.
216 * Also, leave IRQ masked during drive probing, to prevent infinite
217 * interrupts from a potentially floating INTA..
218 *
219 * IRQs get unmasked in dev_select() when drive is first used.
220 */
221 (void) pci_read_config_dword(dev, 0x40, &ctrl);
222 (void) pci_read_config_byte(dev, 0x09, &progif);
223 /* is irq in "native" mode? */
224 using_inta = progif & (1 << (hwif->channel << 1));
225 if (!using_inta)
226 using_inta = ctrl & (1 << (4 + hwif->channel));
227 if (hwif->mate) {
228 hwif->select_data = hwif->mate->select_data;
229 } else {
230 hwif->select_data = (unsigned long)
231 &ns87415_control[ns87415_count++];
232 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
233 if (using_inta)
234 ctrl &= ~(1 << 6); /* unmask INTA */
235 *((unsigned int *)hwif->select_data) = ctrl;
236 (void) pci_write_config_dword(dev, 0x40, ctrl);
237
238 /*
239 * Set prefetch size to 512 bytes for both ports,
240 * but don't turn on/off prefetching here.
241 */
242 pci_write_config_byte(dev, 0x55, 0xee);
243
244#ifdef __sparc_v9__
245 /*
246 * XXX: Reset the device, if we don't it will not respond to
247 * dev_select() properly during first ide_probe_port().
248 */
249 timeout = 10000;
250 outb(12, hwif->io_ports.ctl_addr);
251 udelay(10);
252 outb(8, hwif->io_ports.ctl_addr);
253 do {
254 udelay(50);
255 stat = hwif->tp_ops->read_status(hwif);
256 if (stat == 0xff)
257 break;
258 } while ((stat & ATA_BUSY) && --timeout);
259#endif
260 }
261
262 if (!using_inta)
263 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
264
265 if (!hwif->dma_base)
266 return;
267
268 outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
269}
270
271static const struct ide_tp_ops ns87415_tp_ops = {
272 .exec_command = ide_exec_command,
273 .read_status = ide_read_status,
274 .read_altstatus = ide_read_altstatus,
275 .write_devctl = ide_write_devctl,
276
277 .dev_select = ns87415_dev_select,
278 .tf_load = ide_tf_load,
279 .tf_read = ide_tf_read,
280
281 .input_data = ide_input_data,
282 .output_data = ide_output_data,
283};
284
285static const struct ide_dma_ops ns87415_dma_ops = {
286 .dma_host_set = ide_dma_host_set,
287 .dma_setup = ide_dma_setup,
288 .dma_start = ns87415_dma_start,
289 .dma_end = ns87415_dma_end,
290 .dma_test_irq = ide_dma_test_irq,
291 .dma_lost_irq = ide_dma_lost_irq,
292 .dma_timer_expiry = ide_dma_sff_timer_expiry,
293 .dma_sff_read_status = superio_dma_sff_read_status,
294};
295
296static const struct ide_port_info ns87415_chipset __devinitdata = {
297 .name = DRV_NAME,
298 .init_hwif = init_hwif_ns87415,
299 .tp_ops = &ns87415_tp_ops,
300 .dma_ops = &ns87415_dma_ops,
301 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
302 IDE_HFLAG_NO_ATAPI_DMA,
303};
304
305static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
306{
307 struct ide_port_info d = ns87415_chipset;
308
309#ifdef CONFIG_SUPERIO
310 if (PCI_SLOT(dev->devfn) == 0xE) {
311 /* Built-in - assume it's under superio. */
312 d.init_iops = superio_init_iops;
313 d.tp_ops = &superio_tp_ops;
314 }
315#endif
316 return ide_pci_init_one(dev, &d, NULL);
317}
318
319static const struct pci_device_id ns87415_pci_tbl[] = {
320 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
321 { 0, },
322};
323MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
324
325static struct pci_driver ns87415_pci_driver = {
326 .name = "NS87415_IDE",
327 .id_table = ns87415_pci_tbl,
328 .probe = ns87415_init_one,
329 .remove = ide_pci_remove,
330 .suspend = ide_pci_suspend,
331 .resume = ide_pci_resume,
332};
333
334static int __init ns87415_ide_init(void)
335{
336 return ide_pci_register_driver(&ns87415_pci_driver);
337}
338
339static void __exit ns87415_ide_exit(void)
340{
341 pci_unregister_driver(&ns87415_pci_driver);
342}
343
344module_init(ns87415_ide_init);
345module_exit(ns87415_ide_exit);
346
347MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
348MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
349MODULE_LICENSE("GPL");