Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * I2C bus driver for the Cadence I2C controller.
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/i2c.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/pm_runtime.h>
17
18/* Register offsets for the I2C device. */
19#define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
20#define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
21#define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22#define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
23#define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
24#define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
25#define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
26#define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
27#define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
28#define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
29
30/* Control Register Bit mask definitions */
31#define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
32#define CDNS_I2C_CR_ACK_EN BIT(3)
33#define CDNS_I2C_CR_NEA BIT(2)
34#define CDNS_I2C_CR_MS BIT(1)
35/* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
36#define CDNS_I2C_CR_RW BIT(0)
37/* 1 = Auto init FIFO to zeroes */
38#define CDNS_I2C_CR_CLR_FIFO BIT(6)
39#define CDNS_I2C_CR_DIVA_SHIFT 14
40#define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
41#define CDNS_I2C_CR_DIVB_SHIFT 8
42#define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
43
44#define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
45 CDNS_I2C_CR_ACK_EN | \
46 CDNS_I2C_CR_MS)
47
48#define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
49
50/* Status Register Bit mask definitions */
51#define CDNS_I2C_SR_BA BIT(8)
52#define CDNS_I2C_SR_TXDV BIT(6)
53#define CDNS_I2C_SR_RXDV BIT(5)
54#define CDNS_I2C_SR_RXRW BIT(3)
55
56/*
57 * I2C Address Register Bit mask definitions
58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
59 * bits. A write access to this register always initiates a transfer if the I2C
60 * is in master mode.
61 */
62#define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
63
64/*
65 * I2C Interrupt Registers Bit mask definitions
66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
67 * bit definitions.
68 */
69#define CDNS_I2C_IXR_ARB_LOST BIT(9)
70#define CDNS_I2C_IXR_RX_UNF BIT(7)
71#define CDNS_I2C_IXR_TX_OVF BIT(6)
72#define CDNS_I2C_IXR_RX_OVF BIT(5)
73#define CDNS_I2C_IXR_SLV_RDY BIT(4)
74#define CDNS_I2C_IXR_TO BIT(3)
75#define CDNS_I2C_IXR_NACK BIT(2)
76#define CDNS_I2C_IXR_DATA BIT(1)
77#define CDNS_I2C_IXR_COMP BIT(0)
78
79#define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
80 CDNS_I2C_IXR_RX_UNF | \
81 CDNS_I2C_IXR_TX_OVF | \
82 CDNS_I2C_IXR_RX_OVF | \
83 CDNS_I2C_IXR_SLV_RDY | \
84 CDNS_I2C_IXR_TO | \
85 CDNS_I2C_IXR_NACK | \
86 CDNS_I2C_IXR_DATA | \
87 CDNS_I2C_IXR_COMP)
88
89#define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
90 CDNS_I2C_IXR_RX_UNF | \
91 CDNS_I2C_IXR_TX_OVF | \
92 CDNS_I2C_IXR_RX_OVF | \
93 CDNS_I2C_IXR_NACK)
94
95#define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
96 CDNS_I2C_IXR_RX_UNF | \
97 CDNS_I2C_IXR_TX_OVF | \
98 CDNS_I2C_IXR_RX_OVF | \
99 CDNS_I2C_IXR_NACK | \
100 CDNS_I2C_IXR_DATA | \
101 CDNS_I2C_IXR_COMP)
102
103#define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
104 CDNS_I2C_IXR_TX_OVF | \
105 CDNS_I2C_IXR_RX_OVF | \
106 CDNS_I2C_IXR_TO | \
107 CDNS_I2C_IXR_NACK | \
108 CDNS_I2C_IXR_DATA | \
109 CDNS_I2C_IXR_COMP)
110
111#define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
112/* timeout for pm runtime autosuspend */
113#define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
114
115#define CDNS_I2C_FIFO_DEPTH 16
116/* FIFO depth at which the DATA interrupt occurs */
117#define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
118#define CDNS_I2C_MAX_TRANSFER_SIZE 255
119/* Transfer size in multiples of data interrupt depth */
120#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
121
122#define DRIVER_NAME "cdns-i2c"
123
124#define CDNS_I2C_DIVA_MAX 4
125#define CDNS_I2C_DIVB_MAX 64
126
127#define CDNS_I2C_TIMEOUT_MAX 0xFF
128
129#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
130
131#define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
132#define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
133
134#if IS_ENABLED(CONFIG_I2C_SLAVE)
135/**
136 * enum cdns_i2c_mode - I2C Controller current operating mode
137 *
138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
140 */
141enum cdns_i2c_mode {
142 CDNS_I2C_MODE_SLAVE,
143 CDNS_I2C_MODE_MASTER,
144};
145
146/**
147 * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
148 *
149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
152 */
153enum cdns_i2c_slave_state {
154 CDNS_I2C_SLAVE_STATE_IDLE,
155 CDNS_I2C_SLAVE_STATE_SEND,
156 CDNS_I2C_SLAVE_STATE_RECV,
157};
158#endif
159
160/**
161 * struct cdns_i2c - I2C device private data structure
162 *
163 * @dev: Pointer to device structure
164 * @membase: Base address of the I2C device
165 * @adap: I2C adapter instance
166 * @p_msg: Message pointer
167 * @err_status: Error status in Interrupt Status Register
168 * @xfer_done: Transfer complete status
169 * @p_send_buf: Pointer to transmit buffer
170 * @p_recv_buf: Pointer to receive buffer
171 * @send_count: Number of bytes still expected to send
172 * @recv_count: Number of bytes still expected to receive
173 * @curr_recv_count: Number of bytes to be received in current transfer
174 * @irq: IRQ number
175 * @input_clk: Input clock to I2C controller
176 * @i2c_clk: Maximum I2C clock speed
177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
178 * @clk: Pointer to struct clk
179 * @clk_rate_change_nb: Notifier block for clock rate changes
180 * @quirks: flag for broken hold bit usage in r1p10
181 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
182 * @slave: Registered slave instance.
183 * @dev_mode: I2C operating role(master/slave).
184 * @slave_state: I2C Slave state(idle/read/write).
185 */
186struct cdns_i2c {
187 struct device *dev;
188 void __iomem *membase;
189 struct i2c_adapter adap;
190 struct i2c_msg *p_msg;
191 int err_status;
192 struct completion xfer_done;
193 unsigned char *p_send_buf;
194 unsigned char *p_recv_buf;
195 unsigned int send_count;
196 unsigned int recv_count;
197 unsigned int curr_recv_count;
198 int irq;
199 unsigned long input_clk;
200 unsigned int i2c_clk;
201 unsigned int bus_hold_flag;
202 struct clk *clk;
203 struct notifier_block clk_rate_change_nb;
204 u32 quirks;
205#if IS_ENABLED(CONFIG_I2C_SLAVE)
206 u16 ctrl_reg_diva_divb;
207 struct i2c_client *slave;
208 enum cdns_i2c_mode dev_mode;
209 enum cdns_i2c_slave_state slave_state;
210#endif
211};
212
213struct cdns_platform_data {
214 u32 quirks;
215};
216
217#define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
218 clk_rate_change_nb)
219
220/**
221 * cdns_i2c_clear_bus_hold - Clear bus hold bit
222 * @id: Pointer to driver data struct
223 *
224 * Helper to clear the controller's bus hold bit.
225 */
226static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
227{
228 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
229 if (reg & CDNS_I2C_CR_HOLD)
230 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
231}
232
233static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
234{
235 return (hold_wrkaround &&
236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
237}
238
239#if IS_ENABLED(CONFIG_I2C_SLAVE)
240static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
241{
242 /* Disable all interrupts */
243 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
244
245 /* Clear FIFO and transfer size */
246 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
247
248 /* Update device mode and state */
249 id->dev_mode = mode;
250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
251
252 switch (mode) {
253 case CDNS_I2C_MODE_MASTER:
254 /* Enable i2c master */
255 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
256 CDNS_I2C_CR_MASTER_EN_MASK,
257 CDNS_I2C_CR_OFFSET);
258 /*
259 * This delay is needed to give the IP some time to switch to
260 * the master mode. With lower values(like 110 us) i2cdetect
261 * will not detect any slave and without this delay, the IP will
262 * trigger a timeout interrupt.
263 */
264 usleep_range(115, 125);
265 break;
266 case CDNS_I2C_MODE_SLAVE:
267 /* Enable i2c slave */
268 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
269 CDNS_I2C_CR_SLAVE_EN_MASK,
270 CDNS_I2C_CR_OFFSET);
271
272 /* Setting slave address */
273 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
274 CDNS_I2C_ADDR_OFFSET);
275
276 /* Enable slave send/receive interrupts */
277 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
278 CDNS_I2C_IER_OFFSET);
279 break;
280 }
281}
282
283static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
284{
285 u8 bytes;
286 unsigned char data;
287
288 /* Prepare backend for data reception */
289 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
290 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
291 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
292 }
293
294 /* Fetch number of bytes to receive */
295 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
296
297 /* Read data and send to backend */
298 while (bytes--) {
299 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
300 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
301 }
302}
303
304static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
305{
306 u8 data;
307
308 /* Prepare backend for data transmission */
309 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
310 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
311 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
312 } else {
313 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
314 }
315
316 /* Send data over bus */
317 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
318}
319
320/**
321 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
322 * @ptr: Pointer to I2C device private data
323 *
324 * This function handles the data interrupt and transfer complete interrupt of
325 * the I2C device in slave role.
326 *
327 * Return: IRQ_HANDLED always
328 */
329static irqreturn_t cdns_i2c_slave_isr(void *ptr)
330{
331 struct cdns_i2c *id = ptr;
332 unsigned int isr_status, i2c_status;
333
334 /* Fetch the interrupt status */
335 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
336 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
337
338 /* Ignore masked interrupts */
339 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
340
341 /* Fetch transfer mode (send/receive) */
342 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
343
344 /* Handle data send/receive */
345 if (i2c_status & CDNS_I2C_SR_RXRW) {
346 /* Send data to master */
347 if (isr_status & CDNS_I2C_IXR_DATA)
348 cdns_i2c_slave_send_data(id);
349
350 if (isr_status & CDNS_I2C_IXR_COMP) {
351 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
352 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
353 }
354 } else {
355 /* Receive data from master */
356 if (isr_status & CDNS_I2C_IXR_DATA)
357 cdns_i2c_slave_rcv_data(id);
358
359 if (isr_status & CDNS_I2C_IXR_COMP) {
360 cdns_i2c_slave_rcv_data(id);
361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
363 }
364 }
365
366 /* Master indicated xfer stop or fifo underflow/overflow */
367 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
368 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
369 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
370 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
371 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
372 }
373
374 return IRQ_HANDLED;
375}
376#endif
377
378/**
379 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
380 * @ptr: Pointer to I2C device private data
381 *
382 * This function handles the data interrupt, transfer complete interrupt and
383 * the error interrupts of the I2C device in master role.
384 *
385 * Return: IRQ_HANDLED always
386 */
387static irqreturn_t cdns_i2c_master_isr(void *ptr)
388{
389 unsigned int isr_status, avail_bytes, updatetx;
390 unsigned int bytes_to_send;
391 bool hold_quirk;
392 struct cdns_i2c *id = ptr;
393 /* Signal completion only after everything is updated */
394 int done_flag = 0;
395 irqreturn_t status = IRQ_NONE;
396
397 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
398 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
399 id->err_status = 0;
400
401 /* Handling nack and arbitration lost interrupt */
402 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
403 done_flag = 1;
404 status = IRQ_HANDLED;
405 }
406
407 /*
408 * Check if transfer size register needs to be updated again for a
409 * large data receive operation.
410 */
411 updatetx = 0;
412 if (id->recv_count > id->curr_recv_count)
413 updatetx = 1;
414
415 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
416
417 /* When receiving, handle data interrupt and completion interrupt */
418 if (id->p_recv_buf &&
419 ((isr_status & CDNS_I2C_IXR_COMP) ||
420 (isr_status & CDNS_I2C_IXR_DATA))) {
421 /* Read data if receive data valid is set */
422 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
423 CDNS_I2C_SR_RXDV) {
424 if (id->recv_count > 0) {
425 *(id->p_recv_buf)++ =
426 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
427 id->recv_count--;
428 id->curr_recv_count--;
429
430 /*
431 * Clear hold bit that was set for FIFO control
432 * if RX data left is less than or equal to
433 * FIFO DEPTH unless repeated start is selected
434 */
435 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
436 !id->bus_hold_flag)
437 cdns_i2c_clear_bus_hold(id);
438
439 } else {
440 dev_err(id->adap.dev.parent,
441 "xfer_size reg rollover. xfer aborted!\n");
442 id->err_status |= CDNS_I2C_IXR_TO;
443 break;
444 }
445
446 if (cdns_is_holdquirk(id, hold_quirk))
447 break;
448 }
449
450 /*
451 * The controller sends NACK to the slave when transfer size
452 * register reaches zero without considering the HOLD bit.
453 * This workaround is implemented for large data transfers to
454 * maintain transfer size non-zero while performing a large
455 * receive operation.
456 */
457 if (cdns_is_holdquirk(id, hold_quirk)) {
458 /* wait while fifo is full */
459 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
460 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
461 ;
462
463 /*
464 * Check number of bytes to be received against maximum
465 * transfer size and update register accordingly.
466 */
467 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
468 CDNS_I2C_TRANSFER_SIZE) {
469 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
470 CDNS_I2C_XFER_SIZE_OFFSET);
471 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
472 CDNS_I2C_FIFO_DEPTH;
473 } else {
474 cdns_i2c_writereg(id->recv_count -
475 CDNS_I2C_FIFO_DEPTH,
476 CDNS_I2C_XFER_SIZE_OFFSET);
477 id->curr_recv_count = id->recv_count;
478 }
479 } else if (id->recv_count && !hold_quirk &&
480 !id->curr_recv_count) {
481
482 /* Set the slave address in address register*/
483 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
484 CDNS_I2C_ADDR_OFFSET);
485
486 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
487 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
488 CDNS_I2C_XFER_SIZE_OFFSET);
489 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
490 } else {
491 cdns_i2c_writereg(id->recv_count,
492 CDNS_I2C_XFER_SIZE_OFFSET);
493 id->curr_recv_count = id->recv_count;
494 }
495 }
496
497 /* Clear hold (if not repeated start) and signal completion */
498 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
499 if (!id->bus_hold_flag)
500 cdns_i2c_clear_bus_hold(id);
501 done_flag = 1;
502 }
503
504 status = IRQ_HANDLED;
505 }
506
507 /* When sending, handle transfer complete interrupt */
508 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
509 /*
510 * If there is more data to be sent, calculate the
511 * space available in FIFO and fill with that many bytes.
512 */
513 if (id->send_count) {
514 avail_bytes = CDNS_I2C_FIFO_DEPTH -
515 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
516 if (id->send_count > avail_bytes)
517 bytes_to_send = avail_bytes;
518 else
519 bytes_to_send = id->send_count;
520
521 while (bytes_to_send--) {
522 cdns_i2c_writereg(
523 (*(id->p_send_buf)++),
524 CDNS_I2C_DATA_OFFSET);
525 id->send_count--;
526 }
527 } else {
528 /*
529 * Signal the completion of transaction and
530 * clear the hold bus bit if there are no
531 * further messages to be processed.
532 */
533 done_flag = 1;
534 }
535 if (!id->send_count && !id->bus_hold_flag)
536 cdns_i2c_clear_bus_hold(id);
537
538 status = IRQ_HANDLED;
539 }
540
541 /* Update the status for errors */
542 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
543 if (id->err_status)
544 status = IRQ_HANDLED;
545
546 if (done_flag)
547 complete(&id->xfer_done);
548
549 return status;
550}
551
552/**
553 * cdns_i2c_isr - Interrupt handler for the I2C device
554 * @irq: irq number for the I2C device
555 * @ptr: void pointer to cdns_i2c structure
556 *
557 * This function passes the control to slave/master based on current role of
558 * i2c controller.
559 *
560 * Return: IRQ_HANDLED always
561 */
562static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
563{
564#if IS_ENABLED(CONFIG_I2C_SLAVE)
565 struct cdns_i2c *id = ptr;
566
567 if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
568 return cdns_i2c_slave_isr(ptr);
569#endif
570 return cdns_i2c_master_isr(ptr);
571}
572
573/**
574 * cdns_i2c_mrecv - Prepare and start a master receive operation
575 * @id: pointer to the i2c device structure
576 */
577static void cdns_i2c_mrecv(struct cdns_i2c *id)
578{
579 unsigned int ctrl_reg;
580 unsigned int isr_status;
581
582 id->p_recv_buf = id->p_msg->buf;
583 id->recv_count = id->p_msg->len;
584
585 /* Put the controller in master receive mode and clear the FIFO */
586 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
587 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
588
589 if (id->p_msg->flags & I2C_M_RECV_LEN)
590 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1;
591
592 id->curr_recv_count = id->recv_count;
593
594 /*
595 * Check for the message size against FIFO depth and set the
596 * 'hold bus' bit if it is greater than FIFO depth.
597 */
598 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
599 ctrl_reg |= CDNS_I2C_CR_HOLD;
600
601 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
602
603 /* Clear the interrupts in interrupt status register */
604 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
605 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
606
607 /*
608 * The no. of bytes to receive is checked against the limit of
609 * max transfer size. Set transfer size register with no of bytes
610 * receive if it is less than transfer size and transfer size if
611 * it is more. Enable the interrupts.
612 */
613 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
614 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
615 CDNS_I2C_XFER_SIZE_OFFSET);
616 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
617 } else {
618 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
619 }
620
621 /* Set the slave address in address register - triggers operation */
622 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
623 CDNS_I2C_ADDR_OFFSET);
624 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
625 if (!id->bus_hold_flag &&
626 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
627 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
628 cdns_i2c_clear_bus_hold(id);
629 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
630}
631
632/**
633 * cdns_i2c_msend - Prepare and start a master send operation
634 * @id: pointer to the i2c device
635 */
636static void cdns_i2c_msend(struct cdns_i2c *id)
637{
638 unsigned int avail_bytes;
639 unsigned int bytes_to_send;
640 unsigned int ctrl_reg;
641 unsigned int isr_status;
642
643 id->p_recv_buf = NULL;
644 id->p_send_buf = id->p_msg->buf;
645 id->send_count = id->p_msg->len;
646
647 /* Set the controller in Master transmit mode and clear the FIFO. */
648 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
649 ctrl_reg &= ~CDNS_I2C_CR_RW;
650 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
651
652 /*
653 * Check for the message size against FIFO depth and set the
654 * 'hold bus' bit if it is greater than FIFO depth.
655 */
656 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
657 ctrl_reg |= CDNS_I2C_CR_HOLD;
658 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
659
660 /* Clear the interrupts in interrupt status register. */
661 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
662 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
663
664 /*
665 * Calculate the space available in FIFO. Check the message length
666 * against the space available, and fill the FIFO accordingly.
667 * Enable the interrupts.
668 */
669 avail_bytes = CDNS_I2C_FIFO_DEPTH -
670 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
671
672 if (id->send_count > avail_bytes)
673 bytes_to_send = avail_bytes;
674 else
675 bytes_to_send = id->send_count;
676
677 while (bytes_to_send--) {
678 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
679 id->send_count--;
680 }
681
682 /*
683 * Clear the bus hold flag if there is no more data
684 * and if it is the last message.
685 */
686 if (!id->bus_hold_flag && !id->send_count)
687 cdns_i2c_clear_bus_hold(id);
688 /* Set the slave address in address register - triggers operation. */
689 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
690 CDNS_I2C_ADDR_OFFSET);
691
692 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
693}
694
695/**
696 * cdns_i2c_master_reset - Reset the interface
697 * @adap: pointer to the i2c adapter driver instance
698 *
699 * This function cleanup the fifos, clear the hold bit and status
700 * and disable the interrupts.
701 */
702static void cdns_i2c_master_reset(struct i2c_adapter *adap)
703{
704 struct cdns_i2c *id = adap->algo_data;
705 u32 regval;
706
707 /* Disable the interrupts */
708 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
709 /* Clear the hold bit and fifos */
710 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
711 regval &= ~CDNS_I2C_CR_HOLD;
712 regval |= CDNS_I2C_CR_CLR_FIFO;
713 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
714 /* Update the transfercount register to zero */
715 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
716 /* Clear the interrupt status register */
717 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
718 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
719 /* Clear the status register */
720 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
721 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
722}
723
724static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
725 struct i2c_adapter *adap)
726{
727 unsigned long time_left;
728 u32 reg;
729
730 id->p_msg = msg;
731 id->err_status = 0;
732 reinit_completion(&id->xfer_done);
733
734 /* Check for the TEN Bit mode on each msg */
735 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
736 if (msg->flags & I2C_M_TEN) {
737 if (reg & CDNS_I2C_CR_NEA)
738 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
739 CDNS_I2C_CR_OFFSET);
740 } else {
741 if (!(reg & CDNS_I2C_CR_NEA))
742 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
743 CDNS_I2C_CR_OFFSET);
744 }
745
746 /* Check for the R/W flag on each msg */
747 if (msg->flags & I2C_M_RD)
748 cdns_i2c_mrecv(id);
749 else
750 cdns_i2c_msend(id);
751
752 /* Wait for the signal of completion */
753 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout);
754 if (time_left == 0) {
755 cdns_i2c_master_reset(adap);
756 dev_err(id->adap.dev.parent,
757 "timeout waiting on completion\n");
758 return -ETIMEDOUT;
759 }
760
761 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
762 CDNS_I2C_IDR_OFFSET);
763
764 /* If it is bus arbitration error, try again */
765 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
766 return -EAGAIN;
767
768 return 0;
769}
770
771/**
772 * cdns_i2c_master_xfer - The main i2c transfer function
773 * @adap: pointer to the i2c adapter driver instance
774 * @msgs: pointer to the i2c message structure
775 * @num: the number of messages to transfer
776 *
777 * Initiates the send/recv activity based on the transfer message received.
778 *
779 * Return: number of msgs processed on success, negative error otherwise
780 */
781static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
782 int num)
783{
784 int ret, count;
785 u32 reg;
786 struct cdns_i2c *id = adap->algo_data;
787 bool hold_quirk;
788#if IS_ENABLED(CONFIG_I2C_SLAVE)
789 bool change_role = false;
790#endif
791
792 ret = pm_runtime_get_sync(id->dev);
793 if (ret < 0)
794 return ret;
795
796#if IS_ENABLED(CONFIG_I2C_SLAVE)
797 /* Check i2c operating mode and switch if possible */
798 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
799 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
800 return -EAGAIN;
801
802 /* Set mode to master */
803 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
804
805 /* Mark flag to change role once xfer is completed */
806 change_role = true;
807 }
808#endif
809
810 /* Check if the bus is free */
811 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
812 ret = -EAGAIN;
813 goto out;
814 }
815
816 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
817 /*
818 * Set the flag to one when multiple messages are to be
819 * processed with a repeated start.
820 */
821 if (num > 1) {
822 /*
823 * This controller does not give completion interrupt after a
824 * master receive message if HOLD bit is set (repeated start),
825 * resulting in SW timeout. Hence, if a receive message is
826 * followed by any other message, an error is returned
827 * indicating that this sequence is not supported.
828 */
829 for (count = 0; (count < num - 1 && hold_quirk); count++) {
830 if (msgs[count].flags & I2C_M_RD) {
831 dev_warn(adap->dev.parent,
832 "Can't do repeated start after a receive message\n");
833 ret = -EOPNOTSUPP;
834 goto out;
835 }
836 }
837 id->bus_hold_flag = 1;
838 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
839 reg |= CDNS_I2C_CR_HOLD;
840 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
841 } else {
842 id->bus_hold_flag = 0;
843 }
844
845 /* Process the msg one by one */
846 for (count = 0; count < num; count++, msgs++) {
847 if (count == (num - 1))
848 id->bus_hold_flag = 0;
849
850 ret = cdns_i2c_process_msg(id, msgs, adap);
851 if (ret)
852 goto out;
853
854 /* Report the other error interrupts to application */
855 if (id->err_status) {
856 cdns_i2c_master_reset(adap);
857
858 if (id->err_status & CDNS_I2C_IXR_NACK) {
859 ret = -ENXIO;
860 goto out;
861 }
862 ret = -EIO;
863 goto out;
864 }
865 }
866
867 ret = num;
868
869out:
870
871#if IS_ENABLED(CONFIG_I2C_SLAVE)
872 /* Switch i2c mode to slave */
873 if (change_role)
874 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
875#endif
876
877 pm_runtime_mark_last_busy(id->dev);
878 pm_runtime_put_autosuspend(id->dev);
879 return ret;
880}
881
882/**
883 * cdns_i2c_func - Returns the supported features of the I2C driver
884 * @adap: pointer to the i2c adapter structure
885 *
886 * Return: 32 bit value, each bit corresponding to a feature
887 */
888static u32 cdns_i2c_func(struct i2c_adapter *adap)
889{
890 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
891 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
892 I2C_FUNC_SMBUS_BLOCK_DATA;
893
894#if IS_ENABLED(CONFIG_I2C_SLAVE)
895 func |= I2C_FUNC_SLAVE;
896#endif
897
898 return func;
899}
900
901#if IS_ENABLED(CONFIG_I2C_SLAVE)
902static int cdns_reg_slave(struct i2c_client *slave)
903{
904 int ret;
905 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
906 adap);
907
908 if (id->slave)
909 return -EBUSY;
910
911 if (slave->flags & I2C_CLIENT_TEN)
912 return -EAFNOSUPPORT;
913
914 ret = pm_runtime_get_sync(id->dev);
915 if (ret < 0)
916 return ret;
917
918 /* Store slave information */
919 id->slave = slave;
920
921 /* Enable I2C slave */
922 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
923
924 return 0;
925}
926
927static int cdns_unreg_slave(struct i2c_client *slave)
928{
929 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
930 adap);
931
932 pm_runtime_put(id->dev);
933
934 /* Remove slave information */
935 id->slave = NULL;
936
937 /* Enable I2C master */
938 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
939
940 return 0;
941}
942#endif
943
944static const struct i2c_algorithm cdns_i2c_algo = {
945 .master_xfer = cdns_i2c_master_xfer,
946 .functionality = cdns_i2c_func,
947#if IS_ENABLED(CONFIG_I2C_SLAVE)
948 .reg_slave = cdns_reg_slave,
949 .unreg_slave = cdns_unreg_slave,
950#endif
951};
952
953/**
954 * cdns_i2c_calc_divs - Calculate clock dividers
955 * @f: I2C clock frequency
956 * @input_clk: Input clock frequency
957 * @a: First divider (return value)
958 * @b: Second divider (return value)
959 *
960 * f is used as input and output variable. As input it is used as target I2C
961 * frequency. On function exit f holds the actually resulting I2C frequency.
962 *
963 * Return: 0 on success, negative errno otherwise.
964 */
965static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
966 unsigned int *a, unsigned int *b)
967{
968 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
969 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
970 unsigned int last_error, current_error;
971
972 /* calculate (divisor_a+1) x (divisor_b+1) */
973 temp = input_clk / (22 * fscl);
974
975 /*
976 * If the calculated value is negative or 0, the fscl input is out of
977 * range. Return error.
978 */
979 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
980 return -EINVAL;
981
982 last_error = -1;
983 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
984 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
985
986 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
987 continue;
988 div_b--;
989
990 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
991
992 if (actual_fscl > fscl)
993 continue;
994
995 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
996 (fscl - actual_fscl));
997
998 if (last_error > current_error) {
999 calc_div_a = div_a;
1000 calc_div_b = div_b;
1001 best_fscl = actual_fscl;
1002 last_error = current_error;
1003 }
1004 }
1005
1006 *a = calc_div_a;
1007 *b = calc_div_b;
1008 *f = best_fscl;
1009
1010 return 0;
1011}
1012
1013/**
1014 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1015 * @clk_in: I2C clock input frequency in Hz
1016 * @id: Pointer to the I2C device structure
1017 *
1018 * The device must be idle rather than busy transferring data before setting
1019 * these device options.
1020 * The data rate is set by values in the control register.
1021 * The formula for determining the correct register values is
1022 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1023 * See the hardware data sheet for a full explanation of setting the serial
1024 * clock rate. The clock can not be faster than the input clock divide by 22.
1025 * The two most common clock rates are 100KHz and 400KHz.
1026 *
1027 * Return: 0 on success, negative error otherwise
1028 */
1029static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1030{
1031 unsigned int div_a, div_b;
1032 unsigned int ctrl_reg;
1033 int ret = 0;
1034 unsigned long fscl = id->i2c_clk;
1035
1036 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1037 if (ret)
1038 return ret;
1039
1040 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
1041 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1042 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1043 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1044 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1045#if IS_ENABLED(CONFIG_I2C_SLAVE)
1046 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1047 CDNS_I2C_CR_DIVB_MASK);
1048#endif
1049 return 0;
1050}
1051
1052/**
1053 * cdns_i2c_clk_notifier_cb - Clock rate change callback
1054 * @nb: Pointer to notifier block
1055 * @event: Notification reason
1056 * @data: Pointer to notification data object
1057 *
1058 * This function is called when the cdns_i2c input clock frequency changes.
1059 * The callback checks whether a valid bus frequency can be generated after the
1060 * change. If so, the change is acknowledged, otherwise the change is aborted.
1061 * New dividers are written to the HW in the pre- or post change notification
1062 * depending on the scaling direction.
1063 *
1064 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1065 * to acknowledge the change, NOTIFY_DONE if the notification is
1066 * considered irrelevant.
1067 */
1068static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1069 event, void *data)
1070{
1071 struct clk_notifier_data *ndata = data;
1072 struct cdns_i2c *id = to_cdns_i2c(nb);
1073
1074 if (pm_runtime_suspended(id->dev))
1075 return NOTIFY_OK;
1076
1077 switch (event) {
1078 case PRE_RATE_CHANGE:
1079 {
1080 unsigned long input_clk = ndata->new_rate;
1081 unsigned long fscl = id->i2c_clk;
1082 unsigned int div_a, div_b;
1083 int ret;
1084
1085 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1086 if (ret) {
1087 dev_warn(id->adap.dev.parent,
1088 "clock rate change rejected\n");
1089 return NOTIFY_STOP;
1090 }
1091
1092 /* scale up */
1093 if (ndata->new_rate > ndata->old_rate)
1094 cdns_i2c_setclk(ndata->new_rate, id);
1095
1096 return NOTIFY_OK;
1097 }
1098 case POST_RATE_CHANGE:
1099 id->input_clk = ndata->new_rate;
1100 /* scale down */
1101 if (ndata->new_rate < ndata->old_rate)
1102 cdns_i2c_setclk(ndata->new_rate, id);
1103 return NOTIFY_OK;
1104 case ABORT_RATE_CHANGE:
1105 /* scale up */
1106 if (ndata->new_rate > ndata->old_rate)
1107 cdns_i2c_setclk(ndata->old_rate, id);
1108 return NOTIFY_OK;
1109 default:
1110 return NOTIFY_DONE;
1111 }
1112}
1113
1114/**
1115 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
1116 * @dev: Address of the platform_device structure
1117 *
1118 * Put the driver into low power mode.
1119 *
1120 * Return: 0 always
1121 */
1122static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1123{
1124 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1125
1126 clk_disable(xi2c->clk);
1127
1128 return 0;
1129}
1130
1131/**
1132 * cdns_i2c_runtime_resume - Runtime resume
1133 * @dev: Address of the platform_device structure
1134 *
1135 * Runtime resume callback.
1136 *
1137 * Return: 0 on success and error value on error
1138 */
1139static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1140{
1141 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1142 int ret;
1143
1144 ret = clk_enable(xi2c->clk);
1145 if (ret) {
1146 dev_err(dev, "Cannot enable clock.\n");
1147 return ret;
1148 }
1149
1150 return 0;
1151}
1152
1153static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1154 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1155 cdns_i2c_runtime_resume, NULL)
1156};
1157
1158static const struct cdns_platform_data r1p10_i2c_def = {
1159 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1160};
1161
1162static const struct of_device_id cdns_i2c_of_match[] = {
1163 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1164 { .compatible = "cdns,i2c-r1p14",},
1165 { /* end of table */ }
1166};
1167MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1168
1169/**
1170 * cdns_i2c_probe - Platform registration call
1171 * @pdev: Handle to the platform device structure
1172 *
1173 * This function does all the memory allocation and registration for the i2c
1174 * device. User can modify the address mode to 10 bit address mode using the
1175 * ioctl call with option I2C_TENBIT.
1176 *
1177 * Return: 0 on success, negative error otherwise
1178 */
1179static int cdns_i2c_probe(struct platform_device *pdev)
1180{
1181 struct resource *r_mem;
1182 struct cdns_i2c *id;
1183 int ret;
1184 const struct of_device_id *match;
1185
1186 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1187 if (!id)
1188 return -ENOMEM;
1189
1190 id->dev = &pdev->dev;
1191 platform_set_drvdata(pdev, id);
1192
1193 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1194 if (match && match->data) {
1195 const struct cdns_platform_data *data = match->data;
1196 id->quirks = data->quirks;
1197 }
1198
1199 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1200 if (IS_ERR(id->membase))
1201 return PTR_ERR(id->membase);
1202
1203 id->irq = platform_get_irq(pdev, 0);
1204
1205 id->adap.owner = THIS_MODULE;
1206 id->adap.dev.of_node = pdev->dev.of_node;
1207 id->adap.algo = &cdns_i2c_algo;
1208 id->adap.timeout = CDNS_I2C_TIMEOUT;
1209 id->adap.retries = 3; /* Default retry value. */
1210 id->adap.algo_data = id;
1211 id->adap.dev.parent = &pdev->dev;
1212 init_completion(&id->xfer_done);
1213 snprintf(id->adap.name, sizeof(id->adap.name),
1214 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1215
1216 id->clk = devm_clk_get(&pdev->dev, NULL);
1217 if (IS_ERR(id->clk)) {
1218 if (PTR_ERR(id->clk) != -EPROBE_DEFER)
1219 dev_err(&pdev->dev, "input clock not found.\n");
1220 return PTR_ERR(id->clk);
1221 }
1222 ret = clk_prepare_enable(id->clk);
1223 if (ret)
1224 dev_err(&pdev->dev, "Unable to enable clock.\n");
1225
1226 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1227 pm_runtime_use_autosuspend(id->dev);
1228 pm_runtime_set_active(id->dev);
1229 pm_runtime_enable(id->dev);
1230
1231 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1232 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1233 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1234 id->input_clk = clk_get_rate(id->clk);
1235
1236 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1237 &id->i2c_clk);
1238 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1239 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1240
1241#if IS_ENABLED(CONFIG_I2C_SLAVE)
1242 /* Set initial mode to master */
1243 id->dev_mode = CDNS_I2C_MODE_MASTER;
1244 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1245#endif
1246 cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
1247
1248 ret = cdns_i2c_setclk(id->input_clk, id);
1249 if (ret) {
1250 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1251 ret = -EINVAL;
1252 goto err_clk_dis;
1253 }
1254
1255 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
1256 DRIVER_NAME, id);
1257 if (ret) {
1258 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
1259 goto err_clk_dis;
1260 }
1261
1262 /*
1263 * Cadence I2C controller has a bug wherein it generates
1264 * invalid read transaction after HW timeout in master receiver mode.
1265 * HW timeout is not used by this driver and the interrupt is disabled.
1266 * But the feature itself cannot be disabled. Hence maximum value
1267 * is written to this register to reduce the chances of error.
1268 */
1269 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1270
1271 ret = i2c_add_adapter(&id->adap);
1272 if (ret < 0)
1273 goto err_clk_dis;
1274
1275 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1276 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
1277
1278 return 0;
1279
1280err_clk_dis:
1281 clk_disable_unprepare(id->clk);
1282 pm_runtime_disable(&pdev->dev);
1283 pm_runtime_set_suspended(&pdev->dev);
1284 return ret;
1285}
1286
1287/**
1288 * cdns_i2c_remove - Unregister the device after releasing the resources
1289 * @pdev: Handle to the platform device structure
1290 *
1291 * This function frees all the resources allocated to the device.
1292 *
1293 * Return: 0 always
1294 */
1295static int cdns_i2c_remove(struct platform_device *pdev)
1296{
1297 struct cdns_i2c *id = platform_get_drvdata(pdev);
1298
1299 pm_runtime_disable(&pdev->dev);
1300 pm_runtime_set_suspended(&pdev->dev);
1301 pm_runtime_dont_use_autosuspend(&pdev->dev);
1302
1303 i2c_del_adapter(&id->adap);
1304 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1305 clk_disable_unprepare(id->clk);
1306
1307 return 0;
1308}
1309
1310static struct platform_driver cdns_i2c_drv = {
1311 .driver = {
1312 .name = DRIVER_NAME,
1313 .of_match_table = cdns_i2c_of_match,
1314 .pm = &cdns_i2c_dev_pm_ops,
1315 },
1316 .probe = cdns_i2c_probe,
1317 .remove = cdns_i2c_remove,
1318};
1319
1320module_platform_driver(cdns_i2c_drv);
1321
1322MODULE_AUTHOR("Xilinx Inc.");
1323MODULE_DESCRIPTION("Cadence I2C bus driver");
1324MODULE_LICENSE("GPL");