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1/*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _sienna_cichlid_ip_offset_HEADER
22#define _sienna_cichlid_ip_offset_HEADER
23
24#define MAX_INSTANCE 7
25#define MAX_SEGMENT 5
26
27
28struct IP_BASE_INSTANCE
29{
30 unsigned int segment[MAX_SEGMENT];
31};
32
33struct IP_BASE
34{
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36};
37
38
39static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0 } },
49 { { 0x00017200, 0x02402400, 0, 0, 0 } },
50 { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
51 { { 0x0001B200, 0x0242DC00, 0, 0, 0 } },
52 { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } };
53static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } } } };
60static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } } } };
67static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
68 { { 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } } } };
74static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
75 { { 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } } } };
81static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0 } } } };
88static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } } } };
95static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } } } };
102static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } } } };
109static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } } } };
116static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
117 { { 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } } } };
123static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } } } };
130static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0 } } } };
137static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
138 { { 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0 } } } };
144static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
145 { { 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0 } } } };
151static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
152 { { 0, 0, 0, 0, 0 } },
153 { { 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0 } } } };
158static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0 } } } };
165static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
166 { { 0, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0 } } } };
172static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
173 { { 0, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0 } },
175 { { 0, 0, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0 } } } };
179static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } },
180 { { 0x00054000, 0x02425C00, 0, 0, 0 } },
181 { { 0x00094000, 0x02426000, 0, 0, 0 } },
182 { { 0x000D4000, 0x02426400, 0, 0, 0 } },
183 { { 0x00114000, 0x02426800, 0, 0, 0 } },
184 { { 0x00154000, 0x02426C00, 0, 0, 0 } },
185 { { 0x00194000, 0x02427000, 0, 0, 0 } } } };
186static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } },
191 { { 0, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } } } };
193static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
194 { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } },
195 { { 0, 0, 0, 0, 0 } },
196 { { 0, 0, 0, 0, 0 } },
197 { { 0, 0, 0, 0, 0 } },
198 { { 0, 0, 0, 0, 0 } },
199 { { 0, 0, 0, 0, 0 } } } };
200
201
202#define ATHUB_BASE__INST0_SEG0 0x00000C00
203#define ATHUB_BASE__INST0_SEG1 0x02408C00
204#define ATHUB_BASE__INST0_SEG2 0
205#define ATHUB_BASE__INST0_SEG3 0
206#define ATHUB_BASE__INST0_SEG4 0
207
208#define ATHUB_BASE__INST1_SEG0 0
209#define ATHUB_BASE__INST1_SEG1 0
210#define ATHUB_BASE__INST1_SEG2 0
211#define ATHUB_BASE__INST1_SEG3 0
212#define ATHUB_BASE__INST1_SEG4 0
213
214#define ATHUB_BASE__INST2_SEG0 0
215#define ATHUB_BASE__INST2_SEG1 0
216#define ATHUB_BASE__INST2_SEG2 0
217#define ATHUB_BASE__INST2_SEG3 0
218#define ATHUB_BASE__INST2_SEG4 0
219
220#define ATHUB_BASE__INST3_SEG0 0
221#define ATHUB_BASE__INST3_SEG1 0
222#define ATHUB_BASE__INST3_SEG2 0
223#define ATHUB_BASE__INST3_SEG3 0
224#define ATHUB_BASE__INST3_SEG4 0
225
226#define ATHUB_BASE__INST4_SEG0 0
227#define ATHUB_BASE__INST4_SEG1 0
228#define ATHUB_BASE__INST4_SEG2 0
229#define ATHUB_BASE__INST4_SEG3 0
230#define ATHUB_BASE__INST4_SEG4 0
231
232#define ATHUB_BASE__INST5_SEG0 0
233#define ATHUB_BASE__INST5_SEG1 0
234#define ATHUB_BASE__INST5_SEG2 0
235#define ATHUB_BASE__INST5_SEG3 0
236#define ATHUB_BASE__INST5_SEG4 0
237
238#define ATHUB_BASE__INST6_SEG0 0
239#define ATHUB_BASE__INST6_SEG1 0
240#define ATHUB_BASE__INST6_SEG2 0
241#define ATHUB_BASE__INST6_SEG3 0
242#define ATHUB_BASE__INST6_SEG4 0
243
244#define CLK_BASE__INST0_SEG0 0x00016C00
245#define CLK_BASE__INST0_SEG1 0x02401800
246#define CLK_BASE__INST0_SEG2 0
247#define CLK_BASE__INST0_SEG3 0
248#define CLK_BASE__INST0_SEG4 0
249
250#define CLK_BASE__INST1_SEG0 0x00016E00
251#define CLK_BASE__INST1_SEG1 0x02401C00
252#define CLK_BASE__INST1_SEG2 0
253#define CLK_BASE__INST1_SEG3 0
254#define CLK_BASE__INST1_SEG4 0
255
256#define CLK_BASE__INST2_SEG0 0x00017000
257#define CLK_BASE__INST2_SEG1 0x02402000
258#define CLK_BASE__INST2_SEG2 0
259#define CLK_BASE__INST2_SEG3 0
260#define CLK_BASE__INST2_SEG4 0
261
262#define CLK_BASE__INST3_SEG0 0x00017200
263#define CLK_BASE__INST3_SEG1 0x02402400
264#define CLK_BASE__INST3_SEG2 0
265#define CLK_BASE__INST3_SEG3 0
266#define CLK_BASE__INST3_SEG4 0
267
268#define CLK_BASE__INST4_SEG0 0x0001B000
269#define CLK_BASE__INST4_SEG1 0x0242D800
270#define CLK_BASE__INST4_SEG2 0
271#define CLK_BASE__INST4_SEG3 0
272#define CLK_BASE__INST4_SEG4 0
273
274#define CLK_BASE__INST5_SEG0 0x0001B200
275#define CLK_BASE__INST5_SEG1 0x0242DC00
276#define CLK_BASE__INST5_SEG2 0
277#define CLK_BASE__INST5_SEG3 0
278#define CLK_BASE__INST5_SEG4 0
279
280#define CLK_BASE__INST6_SEG0 0x0001B400
281#define CLK_BASE__INST6_SEG1 0x0242E000
282#define CLK_BASE__INST6_SEG2 0
283#define CLK_BASE__INST6_SEG3 0
284#define CLK_BASE__INST6_SEG4 0
285
286#define DF_BASE__INST0_SEG0 0x00007000
287#define DF_BASE__INST0_SEG1 0x0240B800
288#define DF_BASE__INST0_SEG2 0
289#define DF_BASE__INST0_SEG3 0
290#define DF_BASE__INST0_SEG4 0
291
292#define DF_BASE__INST1_SEG0 0
293#define DF_BASE__INST1_SEG1 0
294#define DF_BASE__INST1_SEG2 0
295#define DF_BASE__INST1_SEG3 0
296#define DF_BASE__INST1_SEG4 0
297
298#define DF_BASE__INST2_SEG0 0
299#define DF_BASE__INST2_SEG1 0
300#define DF_BASE__INST2_SEG2 0
301#define DF_BASE__INST2_SEG3 0
302#define DF_BASE__INST2_SEG4 0
303
304#define DF_BASE__INST3_SEG0 0
305#define DF_BASE__INST3_SEG1 0
306#define DF_BASE__INST3_SEG2 0
307#define DF_BASE__INST3_SEG3 0
308#define DF_BASE__INST3_SEG4 0
309
310#define DF_BASE__INST4_SEG0 0
311#define DF_BASE__INST4_SEG1 0
312#define DF_BASE__INST4_SEG2 0
313#define DF_BASE__INST4_SEG3 0
314#define DF_BASE__INST4_SEG4 0
315
316#define DF_BASE__INST5_SEG0 0
317#define DF_BASE__INST5_SEG1 0
318#define DF_BASE__INST5_SEG2 0
319#define DF_BASE__INST5_SEG3 0
320#define DF_BASE__INST5_SEG4 0
321
322#define DF_BASE__INST6_SEG0 0
323#define DF_BASE__INST6_SEG1 0
324#define DF_BASE__INST6_SEG2 0
325#define DF_BASE__INST6_SEG3 0
326#define DF_BASE__INST6_SEG4 0
327
328#define DIO_BASE__INST0_SEG0 0x02404000
329#define DIO_BASE__INST0_SEG1 0
330#define DIO_BASE__INST0_SEG2 0
331#define DIO_BASE__INST0_SEG3 0
332#define DIO_BASE__INST0_SEG4 0
333
334#define DIO_BASE__INST1_SEG0 0
335#define DIO_BASE__INST1_SEG1 0
336#define DIO_BASE__INST1_SEG2 0
337#define DIO_BASE__INST1_SEG3 0
338#define DIO_BASE__INST1_SEG4 0
339
340#define DIO_BASE__INST2_SEG0 0
341#define DIO_BASE__INST2_SEG1 0
342#define DIO_BASE__INST2_SEG2 0
343#define DIO_BASE__INST2_SEG3 0
344#define DIO_BASE__INST2_SEG4 0
345
346#define DIO_BASE__INST3_SEG0 0
347#define DIO_BASE__INST3_SEG1 0
348#define DIO_BASE__INST3_SEG2 0
349#define DIO_BASE__INST3_SEG3 0
350#define DIO_BASE__INST3_SEG4 0
351
352#define DIO_BASE__INST4_SEG0 0
353#define DIO_BASE__INST4_SEG1 0
354#define DIO_BASE__INST4_SEG2 0
355#define DIO_BASE__INST4_SEG3 0
356#define DIO_BASE__INST4_SEG4 0
357
358#define DIO_BASE__INST5_SEG0 0
359#define DIO_BASE__INST5_SEG1 0
360#define DIO_BASE__INST5_SEG2 0
361#define DIO_BASE__INST5_SEG3 0
362#define DIO_BASE__INST5_SEG4 0
363
364#define DIO_BASE__INST6_SEG0 0
365#define DIO_BASE__INST6_SEG1 0
366#define DIO_BASE__INST6_SEG2 0
367#define DIO_BASE__INST6_SEG3 0
368#define DIO_BASE__INST6_SEG4 0
369
370#define DCN_BASE__INST0_SEG0 0x00000012
371#define DCN_BASE__INST0_SEG1 0x000000C0
372#define DCN_BASE__INST0_SEG2 0x000034C0
373#define DCN_BASE__INST0_SEG3 0x00009000
374#define DCN_BASE__INST0_SEG4 0x02403C00
375
376#define DCN_BASE__INST1_SEG0 0
377#define DCN_BASE__INST1_SEG1 0
378#define DCN_BASE__INST1_SEG2 0
379#define DCN_BASE__INST1_SEG3 0
380#define DCN_BASE__INST1_SEG4 0
381
382#define DCN_BASE__INST2_SEG0 0
383#define DCN_BASE__INST2_SEG1 0
384#define DCN_BASE__INST2_SEG2 0
385#define DCN_BASE__INST2_SEG3 0
386#define DCN_BASE__INST2_SEG4 0
387
388#define DCN_BASE__INST3_SEG0 0
389#define DCN_BASE__INST3_SEG1 0
390#define DCN_BASE__INST3_SEG2 0
391#define DCN_BASE__INST3_SEG3 0
392#define DCN_BASE__INST3_SEG4 0
393
394#define DCN_BASE__INST4_SEG0 0
395#define DCN_BASE__INST4_SEG1 0
396#define DCN_BASE__INST4_SEG2 0
397#define DCN_BASE__INST4_SEG3 0
398#define DCN_BASE__INST4_SEG4 0
399
400#define DCN_BASE__INST5_SEG0 0
401#define DCN_BASE__INST5_SEG1 0
402#define DCN_BASE__INST5_SEG2 0
403#define DCN_BASE__INST5_SEG3 0
404#define DCN_BASE__INST5_SEG4 0
405
406#define DCN_BASE__INST6_SEG0 0
407#define DCN_BASE__INST6_SEG1 0
408#define DCN_BASE__INST6_SEG2 0
409#define DCN_BASE__INST6_SEG3 0
410#define DCN_BASE__INST6_SEG4 0
411
412#define DPCS_BASE__INST0_SEG0 0x00000012
413#define DPCS_BASE__INST0_SEG1 0x000000C0
414#define DPCS_BASE__INST0_SEG2 0x000034C0
415#define DPCS_BASE__INST0_SEG3 0x00009000
416#define DPCS_BASE__INST0_SEG4 0x02403C00
417
418#define DPCS_BASE__INST1_SEG0 0
419#define DPCS_BASE__INST1_SEG1 0
420#define DPCS_BASE__INST1_SEG2 0
421#define DPCS_BASE__INST1_SEG3 0
422#define DPCS_BASE__INST1_SEG4 0
423
424#define DPCS_BASE__INST2_SEG0 0
425#define DPCS_BASE__INST2_SEG1 0
426#define DPCS_BASE__INST2_SEG2 0
427#define DPCS_BASE__INST2_SEG3 0
428#define DPCS_BASE__INST2_SEG4 0
429
430#define DPCS_BASE__INST3_SEG0 0
431#define DPCS_BASE__INST3_SEG1 0
432#define DPCS_BASE__INST3_SEG2 0
433#define DPCS_BASE__INST3_SEG3 0
434#define DPCS_BASE__INST3_SEG4 0
435
436#define DPCS_BASE__INST4_SEG0 0
437#define DPCS_BASE__INST4_SEG1 0
438#define DPCS_BASE__INST4_SEG2 0
439#define DPCS_BASE__INST4_SEG3 0
440#define DPCS_BASE__INST4_SEG4 0
441
442#define DPCS_BASE__INST5_SEG0 0
443#define DPCS_BASE__INST5_SEG1 0
444#define DPCS_BASE__INST5_SEG2 0
445#define DPCS_BASE__INST5_SEG3 0
446#define DPCS_BASE__INST5_SEG4 0
447
448#define DPCS_BASE__INST6_SEG0 0
449#define DPCS_BASE__INST6_SEG1 0
450#define DPCS_BASE__INST6_SEG2 0
451#define DPCS_BASE__INST6_SEG3 0
452#define DPCS_BASE__INST6_SEG4 0
453
454#define FUSE_BASE__INST0_SEG0 0x00017400
455#define FUSE_BASE__INST0_SEG1 0x02401400
456#define FUSE_BASE__INST0_SEG2 0
457#define FUSE_BASE__INST0_SEG3 0
458#define FUSE_BASE__INST0_SEG4 0
459
460#define FUSE_BASE__INST1_SEG0 0
461#define FUSE_BASE__INST1_SEG1 0
462#define FUSE_BASE__INST1_SEG2 0
463#define FUSE_BASE__INST1_SEG3 0
464#define FUSE_BASE__INST1_SEG4 0
465
466#define FUSE_BASE__INST2_SEG0 0
467#define FUSE_BASE__INST2_SEG1 0
468#define FUSE_BASE__INST2_SEG2 0
469#define FUSE_BASE__INST2_SEG3 0
470#define FUSE_BASE__INST2_SEG4 0
471
472#define FUSE_BASE__INST3_SEG0 0
473#define FUSE_BASE__INST3_SEG1 0
474#define FUSE_BASE__INST3_SEG2 0
475#define FUSE_BASE__INST3_SEG3 0
476#define FUSE_BASE__INST3_SEG4 0
477
478#define FUSE_BASE__INST4_SEG0 0
479#define FUSE_BASE__INST4_SEG1 0
480#define FUSE_BASE__INST4_SEG2 0
481#define FUSE_BASE__INST4_SEG3 0
482#define FUSE_BASE__INST4_SEG4 0
483
484#define FUSE_BASE__INST5_SEG0 0
485#define FUSE_BASE__INST5_SEG1 0
486#define FUSE_BASE__INST5_SEG2 0
487#define FUSE_BASE__INST5_SEG3 0
488#define FUSE_BASE__INST5_SEG4 0
489
490#define FUSE_BASE__INST6_SEG0 0
491#define FUSE_BASE__INST6_SEG1 0
492#define FUSE_BASE__INST6_SEG2 0
493#define FUSE_BASE__INST6_SEG3 0
494#define FUSE_BASE__INST6_SEG4 0
495
496#define GC_BASE__INST0_SEG0 0x00001260
497#define GC_BASE__INST0_SEG1 0x0000A000
498#define GC_BASE__INST0_SEG2 0x0001C000
499#define GC_BASE__INST0_SEG3 0x02402C00
500#define GC_BASE__INST0_SEG4 0
501
502#define GC_BASE__INST1_SEG0 0
503#define GC_BASE__INST1_SEG1 0
504#define GC_BASE__INST1_SEG2 0
505#define GC_BASE__INST1_SEG3 0
506#define GC_BASE__INST1_SEG4 0
507
508#define GC_BASE__INST2_SEG0 0
509#define GC_BASE__INST2_SEG1 0
510#define GC_BASE__INST2_SEG2 0
511#define GC_BASE__INST2_SEG3 0
512#define GC_BASE__INST2_SEG4 0
513
514#define GC_BASE__INST3_SEG0 0
515#define GC_BASE__INST3_SEG1 0
516#define GC_BASE__INST3_SEG2 0
517#define GC_BASE__INST3_SEG3 0
518#define GC_BASE__INST3_SEG4 0
519
520#define GC_BASE__INST4_SEG0 0
521#define GC_BASE__INST4_SEG1 0
522#define GC_BASE__INST4_SEG2 0
523#define GC_BASE__INST4_SEG3 0
524#define GC_BASE__INST4_SEG4 0
525
526#define GC_BASE__INST5_SEG0 0
527#define GC_BASE__INST5_SEG1 0
528#define GC_BASE__INST5_SEG2 0
529#define GC_BASE__INST5_SEG3 0
530#define GC_BASE__INST5_SEG4 0
531
532#define GC_BASE__INST6_SEG0 0
533#define GC_BASE__INST6_SEG1 0
534#define GC_BASE__INST6_SEG2 0
535#define GC_BASE__INST6_SEG3 0
536#define GC_BASE__INST6_SEG4 0
537
538#define HDA_BASE__INST0_SEG0 0x004C0000
539#define HDA_BASE__INST0_SEG1 0x02404800
540#define HDA_BASE__INST0_SEG2 0
541#define HDA_BASE__INST0_SEG3 0
542#define HDA_BASE__INST0_SEG4 0
543
544#define HDA_BASE__INST1_SEG0 0
545#define HDA_BASE__INST1_SEG1 0
546#define HDA_BASE__INST1_SEG2 0
547#define HDA_BASE__INST1_SEG3 0
548#define HDA_BASE__INST1_SEG4 0
549
550#define HDA_BASE__INST2_SEG0 0
551#define HDA_BASE__INST2_SEG1 0
552#define HDA_BASE__INST2_SEG2 0
553#define HDA_BASE__INST2_SEG3 0
554#define HDA_BASE__INST2_SEG4 0
555
556#define HDA_BASE__INST3_SEG0 0
557#define HDA_BASE__INST3_SEG1 0
558#define HDA_BASE__INST3_SEG2 0
559#define HDA_BASE__INST3_SEG3 0
560#define HDA_BASE__INST3_SEG4 0
561
562#define HDA_BASE__INST4_SEG0 0
563#define HDA_BASE__INST4_SEG1 0
564#define HDA_BASE__INST4_SEG2 0
565#define HDA_BASE__INST4_SEG3 0
566#define HDA_BASE__INST4_SEG4 0
567
568#define HDA_BASE__INST5_SEG0 0
569#define HDA_BASE__INST5_SEG1 0
570#define HDA_BASE__INST5_SEG2 0
571#define HDA_BASE__INST5_SEG3 0
572#define HDA_BASE__INST5_SEG4 0
573
574#define HDA_BASE__INST6_SEG0 0
575#define HDA_BASE__INST6_SEG1 0
576#define HDA_BASE__INST6_SEG2 0
577#define HDA_BASE__INST6_SEG3 0
578#define HDA_BASE__INST6_SEG4 0
579
580#define HDP_BASE__INST0_SEG0 0x00000F20
581#define HDP_BASE__INST0_SEG1 0x0240A400
582#define HDP_BASE__INST0_SEG2 0
583#define HDP_BASE__INST0_SEG3 0
584#define HDP_BASE__INST0_SEG4 0
585
586#define HDP_BASE__INST1_SEG0 0
587#define HDP_BASE__INST1_SEG1 0
588#define HDP_BASE__INST1_SEG2 0
589#define HDP_BASE__INST1_SEG3 0
590#define HDP_BASE__INST1_SEG4 0
591
592#define HDP_BASE__INST2_SEG0 0
593#define HDP_BASE__INST2_SEG1 0
594#define HDP_BASE__INST2_SEG2 0
595#define HDP_BASE__INST2_SEG3 0
596#define HDP_BASE__INST2_SEG4 0
597
598#define HDP_BASE__INST3_SEG0 0
599#define HDP_BASE__INST3_SEG1 0
600#define HDP_BASE__INST3_SEG2 0
601#define HDP_BASE__INST3_SEG3 0
602#define HDP_BASE__INST3_SEG4 0
603
604#define HDP_BASE__INST4_SEG0 0
605#define HDP_BASE__INST4_SEG1 0
606#define HDP_BASE__INST4_SEG2 0
607#define HDP_BASE__INST4_SEG3 0
608#define HDP_BASE__INST4_SEG4 0
609
610#define HDP_BASE__INST5_SEG0 0
611#define HDP_BASE__INST5_SEG1 0
612#define HDP_BASE__INST5_SEG2 0
613#define HDP_BASE__INST5_SEG3 0
614#define HDP_BASE__INST5_SEG4 0
615
616#define HDP_BASE__INST6_SEG0 0
617#define HDP_BASE__INST6_SEG1 0
618#define HDP_BASE__INST6_SEG2 0
619#define HDP_BASE__INST6_SEG3 0
620#define HDP_BASE__INST6_SEG4 0
621
622#define MMHUB_BASE__INST0_SEG0 0x0001A000
623#define MMHUB_BASE__INST0_SEG1 0x02408800
624#define MMHUB_BASE__INST0_SEG2 0
625#define MMHUB_BASE__INST0_SEG3 0
626#define MMHUB_BASE__INST0_SEG4 0
627
628#define MMHUB_BASE__INST1_SEG0 0
629#define MMHUB_BASE__INST1_SEG1 0
630#define MMHUB_BASE__INST1_SEG2 0
631#define MMHUB_BASE__INST1_SEG3 0
632#define MMHUB_BASE__INST1_SEG4 0
633
634#define MMHUB_BASE__INST2_SEG0 0
635#define MMHUB_BASE__INST2_SEG1 0
636#define MMHUB_BASE__INST2_SEG2 0
637#define MMHUB_BASE__INST2_SEG3 0
638#define MMHUB_BASE__INST2_SEG4 0
639
640#define MMHUB_BASE__INST3_SEG0 0
641#define MMHUB_BASE__INST3_SEG1 0
642#define MMHUB_BASE__INST3_SEG2 0
643#define MMHUB_BASE__INST3_SEG3 0
644#define MMHUB_BASE__INST3_SEG4 0
645
646#define MMHUB_BASE__INST4_SEG0 0
647#define MMHUB_BASE__INST4_SEG1 0
648#define MMHUB_BASE__INST4_SEG2 0
649#define MMHUB_BASE__INST4_SEG3 0
650#define MMHUB_BASE__INST4_SEG4 0
651
652#define MMHUB_BASE__INST5_SEG0 0
653#define MMHUB_BASE__INST5_SEG1 0
654#define MMHUB_BASE__INST5_SEG2 0
655#define MMHUB_BASE__INST5_SEG3 0
656#define MMHUB_BASE__INST5_SEG4 0
657
658#define MMHUB_BASE__INST6_SEG0 0
659#define MMHUB_BASE__INST6_SEG1 0
660#define MMHUB_BASE__INST6_SEG2 0
661#define MMHUB_BASE__INST6_SEG3 0
662#define MMHUB_BASE__INST6_SEG4 0
663
664#define MP0_BASE__INST0_SEG0 0x00016000
665#define MP0_BASE__INST0_SEG1 0x00DC0000
666#define MP0_BASE__INST0_SEG2 0x00E00000
667#define MP0_BASE__INST0_SEG3 0x00E40000
668#define MP0_BASE__INST0_SEG4 0x0243FC00
669
670#define MP0_BASE__INST1_SEG0 0
671#define MP0_BASE__INST1_SEG1 0
672#define MP0_BASE__INST1_SEG2 0
673#define MP0_BASE__INST1_SEG3 0
674#define MP0_BASE__INST1_SEG4 0
675
676#define MP0_BASE__INST2_SEG0 0
677#define MP0_BASE__INST2_SEG1 0
678#define MP0_BASE__INST2_SEG2 0
679#define MP0_BASE__INST2_SEG3 0
680#define MP0_BASE__INST2_SEG4 0
681
682#define MP0_BASE__INST3_SEG0 0
683#define MP0_BASE__INST3_SEG1 0
684#define MP0_BASE__INST3_SEG2 0
685#define MP0_BASE__INST3_SEG3 0
686#define MP0_BASE__INST3_SEG4 0
687
688#define MP0_BASE__INST4_SEG0 0
689#define MP0_BASE__INST4_SEG1 0
690#define MP0_BASE__INST4_SEG2 0
691#define MP0_BASE__INST4_SEG3 0
692#define MP0_BASE__INST4_SEG4 0
693
694#define MP0_BASE__INST5_SEG0 0
695#define MP0_BASE__INST5_SEG1 0
696#define MP0_BASE__INST5_SEG2 0
697#define MP0_BASE__INST5_SEG3 0
698#define MP0_BASE__INST5_SEG4 0
699
700#define MP0_BASE__INST6_SEG0 0
701#define MP0_BASE__INST6_SEG1 0
702#define MP0_BASE__INST6_SEG2 0
703#define MP0_BASE__INST6_SEG3 0
704#define MP0_BASE__INST6_SEG4 0
705
706#define MP1_BASE__INST0_SEG0 0x00016000
707#define MP1_BASE__INST0_SEG1 0x00DC0000
708#define MP1_BASE__INST0_SEG2 0x00E00000
709#define MP1_BASE__INST0_SEG3 0x00E40000
710#define MP1_BASE__INST0_SEG4 0x0243FC00
711
712#define MP1_BASE__INST1_SEG0 0
713#define MP1_BASE__INST1_SEG1 0
714#define MP1_BASE__INST1_SEG2 0
715#define MP1_BASE__INST1_SEG3 0
716#define MP1_BASE__INST1_SEG4 0
717
718#define MP1_BASE__INST2_SEG0 0
719#define MP1_BASE__INST2_SEG1 0
720#define MP1_BASE__INST2_SEG2 0
721#define MP1_BASE__INST2_SEG3 0
722#define MP1_BASE__INST2_SEG4 0
723
724#define MP1_BASE__INST3_SEG0 0
725#define MP1_BASE__INST3_SEG1 0
726#define MP1_BASE__INST3_SEG2 0
727#define MP1_BASE__INST3_SEG3 0
728#define MP1_BASE__INST3_SEG4 0
729
730#define MP1_BASE__INST4_SEG0 0
731#define MP1_BASE__INST4_SEG1 0
732#define MP1_BASE__INST4_SEG2 0
733#define MP1_BASE__INST4_SEG3 0
734#define MP1_BASE__INST4_SEG4 0
735
736#define MP1_BASE__INST5_SEG0 0
737#define MP1_BASE__INST5_SEG1 0
738#define MP1_BASE__INST5_SEG2 0
739#define MP1_BASE__INST5_SEG3 0
740#define MP1_BASE__INST5_SEG4 0
741
742#define MP1_BASE__INST6_SEG0 0
743#define MP1_BASE__INST6_SEG1 0
744#define MP1_BASE__INST6_SEG2 0
745#define MP1_BASE__INST6_SEG3 0
746#define MP1_BASE__INST6_SEG4 0
747
748#define NBIO_BASE__INST0_SEG0 0x00000000
749#define NBIO_BASE__INST0_SEG1 0x00000014
750#define NBIO_BASE__INST0_SEG2 0x00000D20
751#define NBIO_BASE__INST0_SEG3 0x00010400
752#define NBIO_BASE__INST0_SEG4 0x0241B000
753
754#define NBIO_BASE__INST1_SEG0 0
755#define NBIO_BASE__INST1_SEG1 0
756#define NBIO_BASE__INST1_SEG2 0
757#define NBIO_BASE__INST1_SEG3 0
758#define NBIO_BASE__INST1_SEG4 0
759
760#define NBIO_BASE__INST2_SEG0 0
761#define NBIO_BASE__INST2_SEG1 0
762#define NBIO_BASE__INST2_SEG2 0
763#define NBIO_BASE__INST2_SEG3 0
764#define NBIO_BASE__INST2_SEG4 0
765
766#define NBIO_BASE__INST3_SEG0 0
767#define NBIO_BASE__INST3_SEG1 0
768#define NBIO_BASE__INST3_SEG2 0
769#define NBIO_BASE__INST3_SEG3 0
770#define NBIO_BASE__INST3_SEG4 0
771
772#define NBIO_BASE__INST4_SEG0 0
773#define NBIO_BASE__INST4_SEG1 0
774#define NBIO_BASE__INST4_SEG2 0
775#define NBIO_BASE__INST4_SEG3 0
776#define NBIO_BASE__INST4_SEG4 0
777
778#define NBIO_BASE__INST5_SEG0 0
779#define NBIO_BASE__INST5_SEG1 0
780#define NBIO_BASE__INST5_SEG2 0
781#define NBIO_BASE__INST5_SEG3 0
782#define NBIO_BASE__INST5_SEG4 0
783
784#define NBIO_BASE__INST6_SEG0 0
785#define NBIO_BASE__INST6_SEG1 0
786#define NBIO_BASE__INST6_SEG2 0
787#define NBIO_BASE__INST6_SEG3 0
788#define NBIO_BASE__INST6_SEG4 0
789
790#define OSSSYS_BASE__INST0_SEG0 0x000010A0
791#define OSSSYS_BASE__INST0_SEG1 0x0240A000
792#define OSSSYS_BASE__INST0_SEG2 0
793#define OSSSYS_BASE__INST0_SEG3 0
794#define OSSSYS_BASE__INST0_SEG4 0
795
796#define OSSSYS_BASE__INST1_SEG0 0
797#define OSSSYS_BASE__INST1_SEG1 0
798#define OSSSYS_BASE__INST1_SEG2 0
799#define OSSSYS_BASE__INST1_SEG3 0
800#define OSSSYS_BASE__INST1_SEG4 0
801
802#define OSSSYS_BASE__INST2_SEG0 0
803#define OSSSYS_BASE__INST2_SEG1 0
804#define OSSSYS_BASE__INST2_SEG2 0
805#define OSSSYS_BASE__INST2_SEG3 0
806#define OSSSYS_BASE__INST2_SEG4 0
807
808#define OSSSYS_BASE__INST3_SEG0 0
809#define OSSSYS_BASE__INST3_SEG1 0
810#define OSSSYS_BASE__INST3_SEG2 0
811#define OSSSYS_BASE__INST3_SEG3 0
812#define OSSSYS_BASE__INST3_SEG4 0
813
814#define OSSSYS_BASE__INST4_SEG0 0
815#define OSSSYS_BASE__INST4_SEG1 0
816#define OSSSYS_BASE__INST4_SEG2 0
817#define OSSSYS_BASE__INST4_SEG3 0
818#define OSSSYS_BASE__INST4_SEG4 0
819
820#define OSSSYS_BASE__INST5_SEG0 0
821#define OSSSYS_BASE__INST5_SEG1 0
822#define OSSSYS_BASE__INST5_SEG2 0
823#define OSSSYS_BASE__INST5_SEG3 0
824#define OSSSYS_BASE__INST5_SEG4 0
825
826#define OSSSYS_BASE__INST6_SEG0 0
827#define OSSSYS_BASE__INST6_SEG1 0
828#define OSSSYS_BASE__INST6_SEG2 0
829#define OSSSYS_BASE__INST6_SEG3 0
830#define OSSSYS_BASE__INST6_SEG4 0
831
832#define PCIE0_BASE__INST0_SEG0 0x00000000
833#define PCIE0_BASE__INST0_SEG1 0x00000014
834#define PCIE0_BASE__INST0_SEG2 0x00000D20
835#define PCIE0_BASE__INST0_SEG3 0x00010400
836#define PCIE0_BASE__INST0_SEG4 0x0241B000
837
838#define PCIE0_BASE__INST1_SEG0 0
839#define PCIE0_BASE__INST1_SEG1 0
840#define PCIE0_BASE__INST1_SEG2 0
841#define PCIE0_BASE__INST1_SEG3 0
842#define PCIE0_BASE__INST1_SEG4 0
843
844#define PCIE0_BASE__INST2_SEG0 0
845#define PCIE0_BASE__INST2_SEG1 0
846#define PCIE0_BASE__INST2_SEG2 0
847#define PCIE0_BASE__INST2_SEG3 0
848#define PCIE0_BASE__INST2_SEG4 0
849
850#define PCIE0_BASE__INST3_SEG0 0
851#define PCIE0_BASE__INST3_SEG1 0
852#define PCIE0_BASE__INST3_SEG2 0
853#define PCIE0_BASE__INST3_SEG3 0
854#define PCIE0_BASE__INST3_SEG4 0
855
856#define PCIE0_BASE__INST4_SEG0 0
857#define PCIE0_BASE__INST4_SEG1 0
858#define PCIE0_BASE__INST4_SEG2 0
859#define PCIE0_BASE__INST4_SEG3 0
860#define PCIE0_BASE__INST4_SEG4 0
861
862#define PCIE0_BASE__INST5_SEG0 0
863#define PCIE0_BASE__INST5_SEG1 0
864#define PCIE0_BASE__INST5_SEG2 0
865#define PCIE0_BASE__INST5_SEG3 0
866#define PCIE0_BASE__INST5_SEG4 0
867
868#define PCIE0_BASE__INST6_SEG0 0
869#define PCIE0_BASE__INST6_SEG1 0
870#define PCIE0_BASE__INST6_SEG2 0
871#define PCIE0_BASE__INST6_SEG3 0
872#define PCIE0_BASE__INST6_SEG4 0
873
874#define SDMA0_BASE__INST0_SEG0 0x00001260
875#define SDMA0_BASE__INST0_SEG1 0x0000A000
876#define SDMA0_BASE__INST0_SEG2 0x0001C000
877#define SDMA0_BASE__INST0_SEG3 0x02402C00
878#define SDMA0_BASE__INST0_SEG4 0
879
880#define SDMA0_BASE__INST1_SEG0 0
881#define SDMA0_BASE__INST1_SEG1 0
882#define SDMA0_BASE__INST1_SEG2 0
883#define SDMA0_BASE__INST1_SEG3 0
884#define SDMA0_BASE__INST1_SEG4 0
885
886#define SDMA0_BASE__INST2_SEG0 0
887#define SDMA0_BASE__INST2_SEG1 0
888#define SDMA0_BASE__INST2_SEG2 0
889#define SDMA0_BASE__INST2_SEG3 0
890#define SDMA0_BASE__INST2_SEG4 0
891
892#define SDMA0_BASE__INST3_SEG0 0
893#define SDMA0_BASE__INST3_SEG1 0
894#define SDMA0_BASE__INST3_SEG2 0
895#define SDMA0_BASE__INST3_SEG3 0
896#define SDMA0_BASE__INST3_SEG4 0
897
898#define SDMA0_BASE__INST4_SEG0 0
899#define SDMA0_BASE__INST4_SEG1 0
900#define SDMA0_BASE__INST4_SEG2 0
901#define SDMA0_BASE__INST4_SEG3 0
902#define SDMA0_BASE__INST4_SEG4 0
903
904#define SDMA0_BASE__INST5_SEG0 0
905#define SDMA0_BASE__INST5_SEG1 0
906#define SDMA0_BASE__INST5_SEG2 0
907#define SDMA0_BASE__INST5_SEG3 0
908#define SDMA0_BASE__INST5_SEG4 0
909
910#define SDMA0_BASE__INST6_SEG0 0
911#define SDMA0_BASE__INST6_SEG1 0
912#define SDMA0_BASE__INST6_SEG2 0
913#define SDMA0_BASE__INST6_SEG3 0
914#define SDMA0_BASE__INST6_SEG4 0
915
916#define SDMA1_BASE__INST0_SEG0 0x00001260
917#define SDMA1_BASE__INST0_SEG1 0x0000A000
918#define SDMA1_BASE__INST0_SEG2 0x0001C000
919#define SDMA1_BASE__INST0_SEG3 0x02402C00
920#define SDMA1_BASE__INST0_SEG4 0
921
922#define SDMA1_BASE__INST1_SEG0 0
923#define SDMA1_BASE__INST1_SEG1 0
924#define SDMA1_BASE__INST1_SEG2 0
925#define SDMA1_BASE__INST1_SEG3 0
926#define SDMA1_BASE__INST1_SEG4 0
927
928#define SDMA1_BASE__INST2_SEG0 0
929#define SDMA1_BASE__INST2_SEG1 0
930#define SDMA1_BASE__INST2_SEG2 0
931#define SDMA1_BASE__INST2_SEG3 0
932#define SDMA1_BASE__INST2_SEG4 0
933
934#define SDMA1_BASE__INST3_SEG0 0
935#define SDMA1_BASE__INST3_SEG1 0
936#define SDMA1_BASE__INST3_SEG2 0
937#define SDMA1_BASE__INST3_SEG3 0
938#define SDMA1_BASE__INST3_SEG4 0
939
940#define SDMA1_BASE__INST4_SEG0 0
941#define SDMA1_BASE__INST4_SEG1 0
942#define SDMA1_BASE__INST4_SEG2 0
943#define SDMA1_BASE__INST4_SEG3 0
944#define SDMA1_BASE__INST4_SEG4 0
945
946#define SDMA1_BASE__INST5_SEG0 0
947#define SDMA1_BASE__INST5_SEG1 0
948#define SDMA1_BASE__INST5_SEG2 0
949#define SDMA1_BASE__INST5_SEG3 0
950#define SDMA1_BASE__INST5_SEG4 0
951
952#define SDMA1_BASE__INST6_SEG0 0
953#define SDMA1_BASE__INST6_SEG1 0
954#define SDMA1_BASE__INST6_SEG2 0
955#define SDMA1_BASE__INST6_SEG3 0
956#define SDMA1_BASE__INST6_SEG4 0
957
958#define SMUIO_BASE__INST0_SEG0 0x00016800
959#define SMUIO_BASE__INST0_SEG1 0x00016A00
960#define SMUIO_BASE__INST0_SEG2 0x00440000
961#define SMUIO_BASE__INST0_SEG3 0x02401000
962#define SMUIO_BASE__INST0_SEG4 0
963
964#define SMUIO_BASE__INST1_SEG0 0
965#define SMUIO_BASE__INST1_SEG1 0
966#define SMUIO_BASE__INST1_SEG2 0
967#define SMUIO_BASE__INST1_SEG3 0
968#define SMUIO_BASE__INST1_SEG4 0
969
970#define SMUIO_BASE__INST2_SEG0 0
971#define SMUIO_BASE__INST2_SEG1 0
972#define SMUIO_BASE__INST2_SEG2 0
973#define SMUIO_BASE__INST2_SEG3 0
974#define SMUIO_BASE__INST2_SEG4 0
975
976#define SMUIO_BASE__INST3_SEG0 0
977#define SMUIO_BASE__INST3_SEG1 0
978#define SMUIO_BASE__INST3_SEG2 0
979#define SMUIO_BASE__INST3_SEG3 0
980#define SMUIO_BASE__INST3_SEG4 0
981
982#define SMUIO_BASE__INST4_SEG0 0
983#define SMUIO_BASE__INST4_SEG1 0
984#define SMUIO_BASE__INST4_SEG2 0
985#define SMUIO_BASE__INST4_SEG3 0
986#define SMUIO_BASE__INST4_SEG4 0
987
988#define SMUIO_BASE__INST5_SEG0 0
989#define SMUIO_BASE__INST5_SEG1 0
990#define SMUIO_BASE__INST5_SEG2 0
991#define SMUIO_BASE__INST5_SEG3 0
992#define SMUIO_BASE__INST5_SEG4 0
993
994#define SMUIO_BASE__INST6_SEG0 0
995#define SMUIO_BASE__INST6_SEG1 0
996#define SMUIO_BASE__INST6_SEG2 0
997#define SMUIO_BASE__INST6_SEG3 0
998#define SMUIO_BASE__INST6_SEG4 0
999
1000#define THM_BASE__INST0_SEG0 0x00016600
1001#define THM_BASE__INST0_SEG1 0x02400C00
1002#define THM_BASE__INST0_SEG2 0
1003#define THM_BASE__INST0_SEG3 0
1004#define THM_BASE__INST0_SEG4 0
1005
1006#define THM_BASE__INST1_SEG0 0
1007#define THM_BASE__INST1_SEG1 0
1008#define THM_BASE__INST1_SEG2 0
1009#define THM_BASE__INST1_SEG3 0
1010#define THM_BASE__INST1_SEG4 0
1011
1012#define THM_BASE__INST2_SEG0 0
1013#define THM_BASE__INST2_SEG1 0
1014#define THM_BASE__INST2_SEG2 0
1015#define THM_BASE__INST2_SEG3 0
1016#define THM_BASE__INST2_SEG4 0
1017
1018#define THM_BASE__INST3_SEG0 0
1019#define THM_BASE__INST3_SEG1 0
1020#define THM_BASE__INST3_SEG2 0
1021#define THM_BASE__INST3_SEG3 0
1022#define THM_BASE__INST3_SEG4 0
1023
1024#define THM_BASE__INST4_SEG0 0
1025#define THM_BASE__INST4_SEG1 0
1026#define THM_BASE__INST4_SEG2 0
1027#define THM_BASE__INST4_SEG3 0
1028#define THM_BASE__INST4_SEG4 0
1029
1030#define THM_BASE__INST5_SEG0 0
1031#define THM_BASE__INST5_SEG1 0
1032#define THM_BASE__INST5_SEG2 0
1033#define THM_BASE__INST5_SEG3 0
1034#define THM_BASE__INST5_SEG4 0
1035
1036#define THM_BASE__INST6_SEG0 0
1037#define THM_BASE__INST6_SEG1 0
1038#define THM_BASE__INST6_SEG2 0
1039#define THM_BASE__INST6_SEG3 0
1040#define THM_BASE__INST6_SEG4 0
1041
1042#define UMC_BASE__INST0_SEG0 0x00014000
1043#define UMC_BASE__INST0_SEG1 0x02425800
1044#define UMC_BASE__INST0_SEG2 0
1045#define UMC_BASE__INST0_SEG3 0
1046#define UMC_BASE__INST0_SEG4 0
1047
1048#define UMC_BASE__INST1_SEG0 0x00054000
1049#define UMC_BASE__INST1_SEG1 0x02425C00
1050#define UMC_BASE__INST1_SEG2 0
1051#define UMC_BASE__INST1_SEG3 0
1052#define UMC_BASE__INST1_SEG4 0
1053
1054#define UMC_BASE__INST2_SEG0 0x00094000
1055#define UMC_BASE__INST2_SEG1 0x02426000
1056#define UMC_BASE__INST2_SEG2 0
1057#define UMC_BASE__INST2_SEG3 0
1058#define UMC_BASE__INST2_SEG4 0
1059
1060#define UMC_BASE__INST3_SEG0 0x000D4000
1061#define UMC_BASE__INST3_SEG1 0x02426400
1062#define UMC_BASE__INST3_SEG2 0
1063#define UMC_BASE__INST3_SEG3 0
1064#define UMC_BASE__INST3_SEG4 0
1065
1066#define UMC_BASE__INST4_SEG0 0x00114000
1067#define UMC_BASE__INST4_SEG1 0x02426800
1068#define UMC_BASE__INST4_SEG2 0
1069#define UMC_BASE__INST4_SEG3 0
1070#define UMC_BASE__INST4_SEG4 0
1071
1072#define UMC_BASE__INST5_SEG0 0x00154000
1073#define UMC_BASE__INST5_SEG1 0x02426C00
1074#define UMC_BASE__INST5_SEG2 0
1075#define UMC_BASE__INST5_SEG3 0
1076#define UMC_BASE__INST5_SEG4 0
1077
1078#define UMC_BASE__INST6_SEG0 0x00194000
1079#define UMC_BASE__INST6_SEG1 0x02427000
1080#define UMC_BASE__INST6_SEG2 0
1081#define UMC_BASE__INST6_SEG3 0
1082#define UMC_BASE__INST6_SEG4 0
1083
1084#define USB0_BASE__INST0_SEG0 0x0242A800
1085#define USB0_BASE__INST0_SEG1 0x05B00000
1086#define USB0_BASE__INST0_SEG2 0
1087#define USB0_BASE__INST0_SEG3 0
1088#define USB0_BASE__INST0_SEG4 0
1089
1090#define USB0_BASE__INST1_SEG0 0
1091#define USB0_BASE__INST1_SEG1 0
1092#define USB0_BASE__INST1_SEG2 0
1093#define USB0_BASE__INST1_SEG3 0
1094#define USB0_BASE__INST1_SEG4 0
1095
1096#define USB0_BASE__INST2_SEG0 0
1097#define USB0_BASE__INST2_SEG1 0
1098#define USB0_BASE__INST2_SEG2 0
1099#define USB0_BASE__INST2_SEG3 0
1100#define USB0_BASE__INST2_SEG4 0
1101
1102#define USB0_BASE__INST3_SEG0 0
1103#define USB0_BASE__INST3_SEG1 0
1104#define USB0_BASE__INST3_SEG2 0
1105#define USB0_BASE__INST3_SEG3 0
1106#define USB0_BASE__INST3_SEG4 0
1107
1108#define USB0_BASE__INST4_SEG0 0
1109#define USB0_BASE__INST4_SEG1 0
1110#define USB0_BASE__INST4_SEG2 0
1111#define USB0_BASE__INST4_SEG3 0
1112#define USB0_BASE__INST4_SEG4 0
1113
1114#define USB0_BASE__INST5_SEG0 0
1115#define USB0_BASE__INST5_SEG1 0
1116#define USB0_BASE__INST5_SEG2 0
1117#define USB0_BASE__INST5_SEG3 0
1118#define USB0_BASE__INST5_SEG4 0
1119
1120#define USB0_BASE__INST6_SEG0 0
1121#define USB0_BASE__INST6_SEG1 0
1122#define USB0_BASE__INST6_SEG2 0
1123#define USB0_BASE__INST6_SEG3 0
1124#define USB0_BASE__INST6_SEG4 0
1125
1126#define VCN_BASE__INST0_SEG0 0x00007800
1127#define VCN_BASE__INST0_SEG1 0x00007E00
1128#define VCN_BASE__INST0_SEG2 0x02403000
1129#define VCN_BASE__INST0_SEG3 0
1130#define VCN_BASE__INST0_SEG4 0
1131
1132#define VCN_BASE__INST1_SEG0 0x00007B00
1133#define VCN_BASE__INST1_SEG1 0x00012000
1134#define VCN_BASE__INST1_SEG2 0x02445000
1135#define VCN_BASE__INST1_SEG3 0
1136#define VCN_BASE__INST1_SEG4 0
1137
1138#define VCN_BASE__INST2_SEG0 0
1139#define VCN_BASE__INST2_SEG1 0
1140#define VCN_BASE__INST2_SEG2 0
1141#define VCN_BASE__INST2_SEG3 0
1142#define VCN_BASE__INST2_SEG4 0
1143
1144#define VCN_BASE__INST3_SEG0 0
1145#define VCN_BASE__INST3_SEG1 0
1146#define VCN_BASE__INST3_SEG2 0
1147#define VCN_BASE__INST3_SEG3 0
1148#define VCN_BASE__INST3_SEG4 0
1149
1150#define VCN_BASE__INST4_SEG0 0
1151#define VCN_BASE__INST4_SEG1 0
1152#define VCN_BASE__INST4_SEG2 0
1153#define VCN_BASE__INST4_SEG3 0
1154#define VCN_BASE__INST4_SEG4 0
1155
1156#define VCN_BASE__INST5_SEG0 0
1157#define VCN_BASE__INST5_SEG1 0
1158#define VCN_BASE__INST5_SEG2 0
1159#define VCN_BASE__INST5_SEG3 0
1160#define VCN_BASE__INST5_SEG4 0
1161
1162#define VCN_BASE__INST6_SEG0 0
1163#define VCN_BASE__INST6_SEG1 0
1164#define VCN_BASE__INST6_SEG2 0
1165#define VCN_BASE__INST6_SEG3 0
1166#define VCN_BASE__INST6_SEG4 0
1167
1168#endif