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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/*
24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
26 */
27
28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32#include <linux/bitmap.h>
33#include <linux/dma-fence.h>
34
35struct pci_dev;
36
37#define KGD_MAX_QUEUES 128
38
39struct kfd_dev;
40struct kgd_dev;
41
42struct kgd_mem;
43
44enum kfd_preempt_type {
45 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
46 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
47};
48
49struct kfd_vm_fault_info {
50 uint64_t page_addr;
51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
54 bool prot_valid;
55 bool prot_read;
56 bool prot_write;
57 bool prot_exec;
58};
59
60struct kfd_cu_info {
61 uint32_t num_shader_engines;
62 uint32_t num_shader_arrays_per_engine;
63 uint32_t num_cu_per_sh;
64 uint32_t cu_active_number;
65 uint32_t cu_ao_mask;
66 uint32_t simd_per_cu;
67 uint32_t max_waves_per_simd;
68 uint32_t wave_front_size;
69 uint32_t max_scratch_slots_per_cu;
70 uint32_t lds_size;
71 uint32_t cu_bitmap[4][4];
72};
73
74/* For getting GPU local memory information from KGD */
75struct kfd_local_mem_info {
76 uint64_t local_mem_size_private;
77 uint64_t local_mem_size_public;
78 uint32_t vram_width;
79 uint32_t mem_clk_max;
80};
81
82enum kgd_memory_pool {
83 KGD_POOL_SYSTEM_CACHEABLE = 1,
84 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
85 KGD_POOL_FRAMEBUFFER = 3,
86};
87
88/**
89 * enum kfd_sched_policy
90 *
91 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
92 * scheduling. In this scheduling mode we're using the firmware code to
93 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
94 * the HIQ queue is used as a special queue that dispatches the configuration
95 * to the cp and the user mode queues list that are currently running.
96 * the DIQ queue is a debugging queue that dispatches debugging commands to the
97 * firmware.
98 * in this scheduling mode user mode queues over subscription feature is
99 * enabled.
100 *
101 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
102 * subscription feature disabled.
103 *
104 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
105 * set the command processor registers and sets the queues "manually". This
106 * mode is used *ONLY* for debugging proposes.
107 *
108 */
109enum kfd_sched_policy {
110 KFD_SCHED_POLICY_HWS = 0,
111 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
112 KFD_SCHED_POLICY_NO_HWS
113};
114
115struct kgd2kfd_shared_resources {
116 /* Bit n == 1 means VMID n is available for KFD. */
117 unsigned int compute_vmid_bitmap;
118
119 /* number of pipes per mec */
120 uint32_t num_pipe_per_mec;
121
122 /* number of queues per pipe */
123 uint32_t num_queue_per_pipe;
124
125 /* Bit n == 1 means Queue n is available for KFD */
126 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
127
128 /* SDMA doorbell assignments (SOC15 and later chips only). Only
129 * specific doorbells are routed to each SDMA engine. Others
130 * are routed to IH and VCN. They are not usable by the CP.
131 */
132 uint32_t *sdma_doorbell_idx;
133
134 /* From SOC15 onward, the doorbell index range not usable for CP
135 * queues.
136 */
137 uint32_t non_cp_doorbells_start;
138 uint32_t non_cp_doorbells_end;
139
140 /* Base address of doorbell aperture. */
141 phys_addr_t doorbell_physical_address;
142
143 /* Size in bytes of doorbell aperture. */
144 size_t doorbell_aperture_size;
145
146 /* Number of bytes at start of aperture reserved for KGD. */
147 size_t doorbell_start_offset;
148
149 /* GPUVM address space size in bytes */
150 uint64_t gpuvm_size;
151
152 /* Minor device number of the render node */
153 int drm_render_minor;
154
155};
156
157struct tile_config {
158 uint32_t *tile_config_ptr;
159 uint32_t *macro_tile_config_ptr;
160 uint32_t num_tile_configs;
161 uint32_t num_macro_tile_configs;
162
163 uint32_t gb_addr_config;
164 uint32_t num_banks;
165 uint32_t num_ranks;
166};
167
168#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
169
170/**
171 * struct kfd2kgd_calls
172 *
173 * @program_sh_mem_settings: A function that should initiate the memory
174 * properties such as main aperture memory type (cache / non cached) and
175 * secondary aperture base address, size and memory type.
176 * This function is used only for no cp scheduling mode.
177 *
178 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
179 * scheduling mode. Only used for no cp scheduling mode.
180 *
181 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
182 * sceduling mode.
183 *
184 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
185 * used only for no HWS mode.
186 *
187 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
188 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
189 *
190 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
191 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
192 *
193 * @hqd_is_occupies: Checks if a hqd slot is occupied.
194 *
195 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
196 *
197 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
198 *
199 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
200 * SDMA hqd slot.
201 *
202 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
203 * Only used for no cp scheduling mode
204 *
205 * @set_vm_context_page_table_base: Program page table base for a VMID
206 *
207 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
208 *
209 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
210 *
211 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
212 * IH ring entry. This function allows the KFD ISR to get the VMID
213 * from the fault status register as early as possible.
214 *
215 * @get_hive_id: Returns hive id of current device, 0 if xgmi is not enabled
216 *
217 * @get_unique_id: Returns uuid id of current device
218 *
219 * This structure contains function pointers to services that the kgd driver
220 * provides to amdkfd driver.
221 *
222 */
223struct kfd2kgd_calls {
224 /* Register access functions */
225 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
226 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
227 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
228
229 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
230 unsigned int vmid);
231
232 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
233
234 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
235 uint32_t queue_id, uint32_t __user *wptr,
236 uint32_t wptr_shift, uint32_t wptr_mask,
237 struct mm_struct *mm);
238
239 int (*hiq_mqd_load)(struct kgd_dev *kgd, void *mqd,
240 uint32_t pipe_id, uint32_t queue_id,
241 uint32_t doorbell_off);
242
243 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
244 uint32_t __user *wptr, struct mm_struct *mm);
245
246 int (*hqd_dump)(struct kgd_dev *kgd,
247 uint32_t pipe_id, uint32_t queue_id,
248 uint32_t (**dump)[2], uint32_t *n_regs);
249
250 int (*hqd_sdma_dump)(struct kgd_dev *kgd,
251 uint32_t engine_id, uint32_t queue_id,
252 uint32_t (**dump)[2], uint32_t *n_regs);
253
254 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
255 uint32_t pipe_id, uint32_t queue_id);
256
257 int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
258 unsigned int timeout, uint32_t pipe_id,
259 uint32_t queue_id);
260
261 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
262
263 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
264 unsigned int timeout);
265
266 int (*address_watch_disable)(struct kgd_dev *kgd);
267 int (*address_watch_execute)(struct kgd_dev *kgd,
268 unsigned int watch_point_id,
269 uint32_t cntl_val,
270 uint32_t addr_hi,
271 uint32_t addr_lo);
272 int (*wave_control_execute)(struct kgd_dev *kgd,
273 uint32_t gfx_index_val,
274 uint32_t sq_cmd);
275 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
276 unsigned int watch_point_id,
277 unsigned int reg_offset);
278 bool (*get_atc_vmid_pasid_mapping_info)(
279 struct kgd_dev *kgd,
280 uint8_t vmid,
281 uint16_t *p_pasid);
282
283 /* No longer needed from GFXv9 onward. The scratch base address is
284 * passed to the shader by the CP. It's the user mode driver's
285 * responsibility.
286 */
287 void (*set_scratch_backing_va)(struct kgd_dev *kgd,
288 uint64_t va, uint32_t vmid);
289
290 void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
291 uint32_t vmid, uint64_t page_table_base);
292 uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
293 uint64_t (*get_hive_id)(struct kgd_dev *kgd);
294 uint64_t (*get_unique_id)(struct kgd_dev *kgd);
295
296};
297
298#endif /* KGD_KFD_INTERFACE_H_INCLUDED */